Low-Power Operation for Flash Memory Systems

Abstract

The present invention relates to a circuit and method for low-power operation in a flash memory system. In the disclosed embodiments of the selection decoding circuit path, a pull-up circuit and a pull-down circuit are used to save values at certain output nodes during a power-saving or off mode, thereby allowing the main power supply to be turned off while still maintaining the values.

Description

[0001] This application is a divisional application. The invention name of its parent application is "Low-Power Operation for Flash Memory Systems", the application date is April 26, 2016, and the application number is 201680031307.5. Technical Field

[0002] The present invention relates to circuits and methods for low-power operation in flash memory systems. In the disclosed embodiments of selecting a decoded circuit path, a pull-up circuit and a pull-down circuit are used during a power-saving or off mode to save values at certain output nodes, thereby allowing the main power supply to be turned off while still maintaining the values. Background Art

[0003] Non-volatile memory cells are well known in the art. Figure 1 A prior art non-volatile split-gate memory cell 10 is shown. The memory cell 10 includes a semiconductor substrate 12 of a first conductivity type, such as P-type. The substrate 12 has a surface on which a first region 14 (also referred to as a source line SL) of a second conductivity type, such as N-type, is formed. A second region 16, also of N-type (also referred to as a drain line), is formed on this surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. A bit line BL 20 is connected to the second region 16. A word line WL 22 is positioned above and insulated from a first portion of the channel region 18. The word line 22 hardly or does not overlap with the second region 16 at all. A floating gate FG 24 is above another portion of the channel region 18. The floating gate 24 is insulated from this other portion and is adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. The floating gate 24 may overlap with the first region 14 to provide coupling of this region 14 to the floating gate 24. A coupling gate CG (also referred to as a control gate) 26 is located above and insulated from the floating gate 24. An erase gate EG 28 is above the first region 14 and is adjacent to the floating gate 24 and the coupling gate 26, and is insulated from the floating gate and the coupling gate. The top corner of the floating gate 24 may point to the inner corner of the T-shaped erase gate 28 to improve erase efficiency. The erase gate 28 is also insulated from the first region 14. The cell 10 is described in more detail in U.S. Patent No. 7,868,375, the disclosure of which is incorporated herein by reference in its entirety.

[0004] An exemplary operation of erasing and programming a non - volatile memory cell 10 of the prior art is as follows. The cell 10 is erased by Fowler - Nordheim tunneling mechanism by applying a high voltage on the erase gate 28 while the other terminals are equal to zero volts. Electrons tunnel from the floating gate 24 into the erase gate 28, making the floating gate 24 positively charged, thus turning on the cell 10 under read conditions. The resulting cell erase state is called the '1' state. The cell 10 is programmed by source - side hot - electron programming mechanism by applying a high voltage on the coupling gate 26, a high voltage on the source line 14, a medium voltage on the erase gate 28, and a programming current on the bit line 20. A portion of the electrons flowing through the gap between the word line 22 and the floating gate 24 acquire sufficient energy to be injected into the floating gate 24, making the floating gate 24 negatively charged, thus turning off the cell 10 under read conditions. The resulting cell programming state is called the '0' state. The memory cell 10 can be read in current - sensing mode as follows: apply a bias voltage on the bit line 20, a bias voltage on the word line 22, a bias voltage on the coupling gate 26, a bias voltage or zero voltage on the erase gate 28, and a ground potential on the source line 14. For the erased state, there is a cell current flowing from the bit line 20 to the source line 14, while for the programmed state, there is a negligible or zero cell current flowing from the bit line 20 to the source line 14. Alternatively, the memory cell can be read in reverse - current - sensing mode, in which the bit line 20 is grounded and a bias voltage is applied on the source line. In this mode, the current reverses direction and flows from the source line 14 to the bit line 20. Alternatively, the memory cell 10 can be read in voltage - sensing mode as follows: apply a bias current (grounded) on the bit line 20, a bias voltage on the word line 22, a bias voltage on the coupling gate 26, a bias voltage on the erase gate 28, and a bias voltage on the source line 14. For the erased state, there is a cell output voltage (significantly > 0v) on the bit line 20, while for the programmed state, there is a negligible or near - zero output voltage on the bit line 20. Alternatively, the memory cell can be read in reverse - voltage - sensing mode, in which the bit line 20 is biased at a bias voltage and a bias current (grounded) is applied on the source line. In this mode, the cell output voltage is on the source line 14 rather than on the bit line 20.

[0005] In the prior art, various combinations of positive or zero voltages are applied to the word line 22, the coupling gate 26, and the floating gate 24 to perform read, program, and erase operations.

[0006] In response to a read, erase, or program command, the logic circuit 270 supplies various voltages to respective parts of both the selected memory cell 10 and the unselected memory cell 10 in a timely and least - interference manner.

[0007] For the selected and unselected memory cells 10, the applied voltages and currents are as follows. As used hereinafter, the following abbreviations are used: source line or first region 14 (SL), bit line 20 (BL), word line 22 (WL), and coupling gate 26 (CG).

[0008] Table 1: PEO (Positive Erase Operation) Table

[0009]

[0010] In a most recent application of the applicant (U.S. Patent Application No. 14 / 602,262 filed on January 21, 2015, incorporated by reference), the applicant disclosed an invention in which a negative voltage can be applied to the word line 22 and / or the coupling gate 26 during read, program, and / or erase operations. In this embodiment, the voltages and currents applied to the selected and unselected memory cells 10 are as follows.

[0011] Table 2: PEO (Positive Erase Operation) Table

[0012]

[0013] In another embodiment of U.S. Patent Application No. 14 / 602,262, when the memory cell 10 is unselected during read, erase, and program operations, a negative voltage can be applied to the word line 22, and a negative voltage can be applied to the coupling gate 26 during the erase operation, such that the following voltages are applied:

[0014] Table 3: PNEO (Positive and Negative Erase Operation) Table

[0015]

[0016] The CGINH signal listed above is a prohibit signal applied to the coupling gate 26 of the unselected cells that share the erase gate 28 with the selected cells.

[0017] Figure 2 An embodiment of the architecture of a flash memory system including die 200 recently developed by the applicant is shown. Die 200 includes: memory arrays 215 and 220 for storing data, and memory arrays 215 and 220 include those previously described in Figure 1Rows and columns of memory cells of the type described as memory cell 10; pads 240 and pads 280 for enabling electrical communication between other components of die 200; typically also including bond wires (not shown) which in turn connect to pins (not shown) for accessing the integrated circuit from outside the packaged chip or package bumps or macro interface pins (not shown) for interconnecting to other macros on a SOC (system on a chip); high voltage circuitry 275 for providing positive and negative voltage sources for the system; control logic 270 for providing various control functions such as redundancy and built-in self-test; analog circuitry 265; sense circuits 260 and 261 for reading data from memory array 215 and memory array 220 respectively; row decoder circuits 245 and row decoder circuits 246 which are respectively used to access the rows to be read or written in memory array 215 and memory array 220; column decoder circuits 255 and column decoder circuits 256 which are respectively used to access the bytes to be read or written in memory array 215 and memory array 220; charge pump circuits 250 and charge pump circuits 251 which are respectively used to provide elevated voltages for programming and erase operations for memory array 215 and memory array 220; negative voltage drive circuitry 230 shared by memory array 215 and memory array 220 for read and write operations; high voltage drive circuitry 225 used by memory array 215 during read and write operations, and high voltage drive circuitry 226 used by memory array 220 during read and write operations.

[0018] As flash memory systems become increasingly prevalent in a wide variety of computing and electronic devices, it is becoming more important to create designs that reduce the amount of power consumed by flash memory systems. What is needed is a novel circuit for reducing power consumption in flash memory systems. Summary of the Invention

[0019] The present invention relates to circuits and methods for low power operation in a flash memory system. In the disclosed embodiments of selecting a decoded circuit path, a pull-up circuit and a pull-down circuit are used to save values at certain output nodes during a power saving or off mode, thereby allowing the main power supply to be turned off while still maintaining the values. Low power read reference generation is described. Address and data encoding, decoding, and scrambling for power saving are described. Brief Description of the Drawings

[0020] Figure 1 is a cross-sectional view of a prior art non-volatile memory cell to which the method of the present invention can be applied.

[0021] Figure 2 is using Figure 1Block diagram of a non-volatile memory device with non-volatile memory cells of the prior art shown therein.

[0022] Figure 3 Is a block diagram of an embodiment of a non-volatile memory device.

[0023] Figure 4A And Figure 4B Shows an embodiment of a pull-down circuit.

[0024] Figure 5A And Figure 5B Shows an embodiment of a pull-up circuit.

[0025] Figure 6A And Figure 6B Shows a first embodiment of a selection decoding circuit path.

[0026] Figure 7A And Figure 7B Shows a second embodiment of a selection decoding circuit path.

[0027] Figure 8A And Figure 8B Shows a third embodiment of a selection decoding circuit path.

[0028] Figure 9 Shows a test mode circuit.

[0029] Figure 10 Shows a global power switch circuit.

[0030] Figure 11A And Figure 11B Shows a local power switch circuit.

[0031] Figure 12 Shows a row decoder circuit.

[0032] Figure 13 Shows a sense circuit.

[0033] Figure 14 Shows a sampling circuit for providing a sampling reference current to the sense circuit.

[0034] Figure 15 Shows another sampling circuit for providing a sampling reference current to the sense circuit.

[0035] Figure 16 Shows an embodiment of a read path for a memory device.

[0036] Figure 17 Shows symbols of different gate configurations. Detailed Description

[0037] Figure 3An embodiment of the architecture of a flash memory system including die 300 is shown. Die 300 includes memory section 390. Memory section 390 includes memory blocks 391 and 392, where memory block 391 includes memory arrays 302 and 322 for storing data, and memory block 392 includes memory arrays 312 and 332 for storing data. Each of memory arrays 302, 312, 322, and 332 includes rows and columns of memory cells of the type previously described as memory cells 10 in Figure 1 ; sense circuits 346 for reading data from memory arrays 302 and 322, and sense circuits 345 for reading data from memory arrays 312 and 332; row decoder circuits 303, 313, 323, and 333 for accessing selected rows to be read or written in memory arrays 302, 312, 322, and 332, respectively; column decoder circuits 304, 314, 324, and 334 for accessing bytes to be read or written in memory arrays 302, 312, 322, and 332, respectively; local power switches 305, 315, 325, and 335 for row decoders 303, 313, 323, and 333; local power switches 347A, 347B for column decoder circuits 304, 314, 324, and 334; local power switches 348A, 348B for sense circuits 346 and 345; and local power switches 342 and 343 for high voltage row decoders WSHDR 341 and 344.

[0038] Die 300 also includes the following functional structures and subsystems: pads (not shown) for enabling electrical connectivity between other components of die 300; bond wires (not shown), which in turn connect to pins (not shown) for accessing the integrated circuit from outside the packaged chip or package bumps (not shown) or macro interface pins (not shown) for interconnecting to other macros on the SOC (system-on-chip); a low voltage generation (including low voltage charge pump circuit) circuit 361 and a high voltage generation (including high voltage charge pump circuit) circuit 362 for providing elevated voltages for programming and erase operations to memory arrays 302, 312, 322, and 332; a non-volatile operation controller circuit 363 shared by memory arrays 302, 312, 322, and 332 for read and write operations; a low voltage generation circuit 361 used by memory arrays 302, 312, 322, and 332; a high voltage generation circuit 362 used by memory arrays 302, 312, 322, and 332; an analog low voltage circuit 359 and an analog high voltage circuit 360 used by the analog circuits on die 300; a global power switch (GPS) circuit 364; a data output circuit 351; a test mode circuit 352; a trim bit active circuit 353; a trim bit circuit 354; a command decoder circuit 355; a data input circuit 356; a power sequence controller 357; and a pin interface 358. Circuit blocks 351-356, 359-363 have local power switches within their blocks.

[0039] Use the trim bit circuit 354 to store the bits used during the trim process, thereby configuring, adjusting, and / or optimizing certain parameters in the flash memory system. These bits can include non-volatile configuration bits such as algorithm parameters and endurance (number of erase / program cycles) data retention specification configuration bits, as well as non-volatile trim bits such as bits for the high voltage ranges applied to the erase gate 28, control gate 26, and source line 14; ranges for Vinh and Iprog (current on the bit line 20 during the programming operation), such as the ranges specified in Table 1-3 above; temperature operating ranges and timing ranges for erase and programming operations.

[0040] Use the trim bit active circuit 353 to store the configuration bits used during the normal operation of the flash memory system. These bits can include read trim bits, which are used to configure certain parameters such as read trim; read bias; voltage ranges applied to the bit line 20, word line 22, erase gate 28, and control gate 26; Icellref trim values for configuring the reference cell current; and redundancy configuration. These bits can also include read configuration parameters such as read low width, write IO width, read speed, and power mode.

[0041] Hard power-off

[0042] When the entire system is shut down by a shutdown command from the user, such as when the user presses the power button to shut down the mobile device containing die 300, a hard power-off operation can be implemented on die 300.

[0043] During the hard power-off of die 300, the following parts are powered down: memory section 390, data output circuit 351; test mode circuit 352; trim bit active circuit 353; trim bit circuit 354; command decoder circuit 355; data input circuit 356; analog low voltage circuit 359; analog high voltage circuit 360; low voltage generation circuit 361; high voltage generation circuit 362; and non-volatile operation controller circuit 363. The circuits for assisting the power-off mode are described below.

[0044] During the hard power-off of die 300, the following parts remain powered on: power sequence controller 357; pin interface 358; and GPS circuit 364.

[0045] Soft power-off

[0046] When the entire system is shut down by a shutdown command from the operating system or a similar device, such as when the operating system of the mobile device containing die 300 commands the system to shut down, a soft power-off operation can be implemented on die 300. The circuits for assisting the power-off mode are described below.

[0047] During the soft power-off of die 300, the following parts are powered down: memory section 390, data output circuit 351; test mode circuit 352; trim bit circuit 354; command decoder circuit 355; data input circuit 356; analog low voltage circuit 359; analog high voltage circuit 360; low voltage generation circuit 361; high voltage generation circuit 362; and non-volatile operation controller circuit 363.

[0048] During the soft power-off of die 300, the following parts remain powered on: trim bit active circuit 353; power sequence controller 357; pin interface 358; and GPS circuit 364.

[0049] Standby

[0050] When the entire system is in the sleep mode, such as when the mobile device containing die 300 is in the sleep mode, a standby operation can be implemented on die 300.

[0051] During the standby operation of die 300, the following parts are powered down: memory section 390, but excluding the active part of array 390 (e.g., array 322), row decoder 323, column decoder 324, high-voltage decoder 344, and power supplies 325 and 343; data output circuit 351; test mode circuit 352; trim bit circuit 354; data input circuit 356; analog high-voltage circuit 360; high-voltage generation circuit 362; and non-volatile operation controller circuit 363. The circuits for assisting the power-down mode are described below.

[0052] During the standby operation of die 300, the following parts remain powered on: array 322; row decoder 323; column decoder 324; high-voltage decoder 344; power supply 343; power supply 325; trim bit active circuit 353; command decoder circuit 355; power sequence controller 357; pin interface 358; analog low-voltage circuit 359; low-voltage generation circuit 361; and GPS circuit 364.

[0053] Active Read

[0054] When the system controller (not shown) needs data from array 390, the active read mode can be implemented on die 300. A read command is executed on pin interface 358 by the system controller.

[0055] During the active read operation of die 300, the following parts are powered down: memory section 390, but excluding array 322 (e.g., the array plane requires data), row decoder 323, column decoder 324, power supplies 325 and 343, high-voltage decoder WSHDR 344; test mode circuit 352; trim bit circuit 354; data input circuit 356; analog high-voltage circuit 360; high-voltage generation circuit 362; and non-volatile operation controller circuit 363. The circuits for assisting the power-down mode are described below.

[0056] During the active read operation of die 300, the following parts remain powered on: array 322; row decoder 323; column decoder 324; power supplies 325 and 343; data output circuit 351; trim bit active circuit 353; command decoder circuit 355; power sequence controller 357; pin interface 358; analog low-voltage circuit 359; low-voltage generation circuit 361; and GPS circuit 364.

[0057] Test Mode

[0058] When the designer, manufacturer, or other person wishes to test die 300, the test mode can be implemented on die 300.

[0059] During the test mode of die 300, the following parts are powered down: memory section 390, data output circuit 351; data input circuit 356; analog low voltage circuit 359; analog high voltage circuit 360; low voltage generation circuit 361; high voltage generation circuit 362; and non-volatile operation controller circuit 363. The circuits for assisting the power-down mode are described below.

[0060] During the test mode of die 300, the following parts remain powered on: test mode circuit 352; trim bit active circuit 353; trim bit circuit 354; command decoder circuit 355; power sequence controller 357; pin interface 358; and GPS circuit 364.

[0061] Non-volatile operation

[0062] Non-volatile operation is the normal operation mode of die 300. In this mode, normal erase, program, and read operations can be performed.

[0063] During the non-volatile operation of die 300, the following parts are powered down: memory section 390, but not including the selected part of array 390 (e.g., array 322), row decoder 323, column decoder 324, power supplies 325 and 343, high voltage decoder WSHDR 344; data output circuit 351; and test mode circuit 352. The circuits for assisting the power-down mode are described below.

[0064] During the non-volatile operation of die 300, the following parts remain powered on: the selected part of array 390 (e.g., array 322); row decoder 323; column decoder 324; high voltage decoder 344; power supplies 325 and 343; trim bit active circuit 353; trim bit circuit 354; command decoder circuit 355; data input circuit 356; power sequence controller 357; pin interface 358; analog low voltage circuit 359; analog high voltage circuit 360; low voltage generation circuit 361; high voltage generation circuit 362; non-volatile operation controller circuit 363; and GPS circuit 364.

[0065] Circuits for power-down

[0066] Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B show NAND and inverter power-saving gate circuits used during the power-down of the various parts of die 300 as discussed above. Figure 4A / Figure 4B and Figure 5A / Figure 5BThe gate circuits in ensure that the outputs are in a known '0' or '1' state, respectively, in the power-down mode. Other circuit implementations for other types of gate circuits such as NOR, XOR, complex gates are similar.

[0067] Figure 4A A pull-down 2-input NAND gate circuit 401 is shown. Pull-down gate circuit 401 pulls output node 441 down to a "0" state (such as ground voltage) during power-down mode. During power-down mode, switch 421 is opened (disconnected), which disconnects node 411 (top power supply) from node 451 (local power supply) of circuit 431. Device 461 (an additional device of the 2-input NAND gate) is turned on by the power-down signal to pull node 441 to a "0" state.

[0068] Figure 4B A pull-down inverter circuit 402 is shown. Pull-down circuit 402 pulls node 442 down to a "0" state (such as ground voltage) during power-down mode. During power-down mode, switch 422 is opened (disconnected), thereby disconnecting node 412 (top power supply) of circuit 432 from node 452 (local power supply). Device 462 (an additional device to the inverter) is turned on by the power-down signal to pull node 442 to a "0" state.

[0069] Figure 5A A pull-up 2-input NAND circuit 501 is shown. Pull-up circuit 501 pulls node 541 to a "1" state (such as a Vdd voltage) during power-down mode. During power-down mode, switch 521 is opened (disconnected), thereby disconnecting node 511 (top ground node) of circuit 531 from node 551 (local ground node). Device 561 is turned on by a power-down signal to pull node 541 up to a "1" state.

[0070] Figure 5B A pull-up inverter circuit 502 is shown. Pull-up circuit 502 pulls node 542 to a "1" state (such as a Vdd voltage) during power-down mode. During power-down mode, switch 522 is opened (disconnected), thereby disconnecting node 512 (top ground node) of circuit 532 from node 552 (local ground node). Device 562 is turned on by the power-down signal to pull node 542 up to a "1" state.

[0071] Select the decoding circuit

[0072] Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B Various implementations of select decode circuits operable in a low power shutdown mode are shown.

[0073] Figure 6A Shows a selection decoding circuit 600, which includes NAND gate 601 and inverters 602, 603, and 604 and is shown symbolically.

[0074] With Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B And Figure 9 Other selection decoding and block circuits that are similar to those in and that use other types of gate circuits (such as NOR and / or complex gates) are implemented in a similar manner.

[0075] Figure 6B Shows the selection decoding circuit 600 at the transistor level. During a power-off event, it is desirable to use power-saving gate circuit techniques as in Figure 4A 、 Figure 4B 、 Figure 5A And Figure 5B To "save" (hold) the output values of NAND gate 601 and inverters 602, 603, and 604 even when the power supply VDD and ground GND are disconnected. NAND gate 601 and inverter 603 are similar to power gate pull-up circuits 501 and pull-up circuit 502. Inverter gates 602 and 604 are similar to power gate pull-down circuits 401 and pull-down circuit 402. Thus, NAND gate 601 is coupled to the top ground node 630 in the manner shown in Figure 6B Through switch 631, which can be in the form of switch 521 or switch 522 in Figure 5A And Figure 5B . Node 630 (top ground wire) coupled to the ground power-saving wire 620 (also labeled GND_PS) corresponds to Figure 5A And Figure 5B Node 511 or node 512 in. When switch 631 is opened (disconnected), the output of NAND 601 will be "1" and will remain in that state when switch 631 is opened. Inverter 603 is also coupled to the ground power-saving wire 620 through switch 631 and will output "1" during the power-off mode. Thus, during a power-off event, the outputs of NAND gate 601 and inverter 603 will be pulled up to the "1" state.

[0076] During a power-off event, inverter 604 is coupled to the top power supply node 640 through switch 641, which can be in the form of switch 421 or switch 422 in Figure 4A And Figure 4B . Node 640 coupled to the VDD power-saving wire 611 (also labeled VDD_PS) corresponds to Figure 4A And Figure 4BNode 411 or node 412 in. Pulling the VDD save wire 611 to the "0" state will cause the output of the inverter 604 to be "saved" as "0". The inverter 602 is also coupled to the VDD save wire 611 and will cause its output to be "saved" as "0". Thus, during a power-off event, the outputs of the inverters 602 and 604 will be pulled down to the "0" state.

[0077] Figure 7A Illustrates a selection decoding circuit 700, which includes NAND gate 701 and inverters 702, 703, and 704 and is shown symbolically. The NAND gate 701 and the inverter 703 are similar to the power gate pull-up circuit 501 and the pull-up circuit 502 (except that there is no device 562 as in Figure 5B ). The inverter gate 702 and the inverter 704 are similar to the power gate pull-down circuit 401 and the pull-down circuit 402, except that there is no device 562 as in Figure 5B . Basically, the circuit 700 only requires the first power gate circuit (NAND 701) and has additional devices ( Figure 5A device 561 in).

[0078] Figure 7B Illustrates the selection decoding circuit 700 at the transistor level. During a power-off event, it is desired to "save" the output values of the NAND gate 701 and the inverters 702, 703, and 704, even when the power supply VDD and the ground GND are disconnected. Thus, the NAND gate 701 is coupled to the top ground wire node 730 through a switch 731 in the manner shown in Figure 7B , and this switch can be in the form of the switch 521 or the switch 522 in Figure 5A and Figure 5B . The node 730 coupled to the ground save wire 720 (also labeled GND_PS) corresponds to the node 511 or the node 512 in Figure 5A and Figure 5B . When the switch 731 is opened (disconnected), the output of the NAND 701 will be "1" and will remain in that state when the switch 731 is closed. The inverter 703 is also coupled to the ground save wire 720 and will output "1" during the power-off mode. Thus, during a power-off event, the outputs of the NAND gate 701 and the inverter 703 will be pulled up to the "1" state.

[0079] During a power-off event, the inverter 704 is coupled to the top power wire node 740 through a switch 741, and this switch can be in the form of the switch 421 or the switch 422 in Figure 4A and Figure 4B . The node 740 coupled to the VDD save wire 711 (also labeled VDD_PS) corresponds to Figure 4A and Figure 4BNode 411 or node 412 in. Pulling the VDD saving wire 711 to the "0" state will cause the output of the inverter 704 to be "saved" as "0". The inverter 702 is also coupled to the VDD saving wire 711 and will cause its output to be "saved" as "0". Therefore, during a power-off event, the outputs of the inverters 702 and 704 will be pulled down to the "0" state.

[0080] Figure 8A The selection decoding circuit 800 is shown, which includes NAND gate 801 and inverters 802, 803, and 804 and is shown symbolically.

[0081] Figure 8B The selection decoding circuit 800 at the transistor level is shown. During a power-off event, it is desired to "save" the output values of the NAND gate 801 and the inverters 802, 803, and 804, even when the power supply VDD and ground GND are disconnected. Therefore, the NAND gate 801 is coupled to the top ground wire node 830 through the switch 831 in the manner shown in Figure 8B and the switch can be in the form of the switch 521 or the switch 522 shown in Figure 5A and Figure 5B The node 830 coupled to the (local) ground saving wire 820 (also labeled GND_PS) corresponds to the node 511 or node 512 in Figure 5A and Figure 5B When the switch 831 is open, the output of the NAND 801 will be "1" and will remain in that state when the switch 831 is open. The inverter 803 is also coupled to the ground saving wire 820 and will output "1" during the power-off mode. Therefore, during a power-off event, the outputs of the NAND gate 801 and the inverter 803 will be pulled up to the "1" state.

[0082] During a power-off event, the inverter 804 is coupled to the top power supply wire node 840 through the switch 841, and the switch can be in the form of the switch 421 or the switch 422 shown in Figure 4A and Figure 4B The node 840 coupled to the (local) VDD saving wire 811 (also labeled VDD_PS) corresponds to the node 411 or node 412 in Figure 4A and Figure 4B When the switch 841 is open (disconnected), the output of the inverter 804 is "saved" as "0". The inverter 802 is also coupled to the VDD saving wire 811 and will cause its output to be "saved" as "0". Therefore, during a power-off event, the outputs of the inverters 802 and 804 will be pulled down to the "0" state.

[0083] Figure 8B The body wire 850 (also labeled NWBULK) is also shown, which is asFigure 8B Some of the transistors in the NAND gate 801 and inverters 802, 803, and 804 shown in Figure 8B provide a common body voltage. An embodiment of body bias modulation for minimizing power consumption and maximizing performance is as follows. The voltage bias on body line 850 is higher than the power supply VDD in the power-off or standby mode to reduce leakage, and lower than or equal to VDD in the active mode to enhance gate current drive.

[0084] Test mode circuit

[0085] Figure 9 A test mode circuit 900 is shown, which includes gates 901, 904, 907, and 908; NAND gates 902 and 905; and inverters 903 and 906 as shown. During a power-off operation, the outputs of NAND gates 902 and 905 are pulled up to "1" using a ground power-saving line 920 (also labeled GND_PS), a power-saving gate pull-up circuit 501 or pull-up circuit 502 ( Figure 4A ," Figure 4B ," Figure 5A ," Figure 5B ," Figure 6A ," Figure 6B ," Figure 7A ," Figure 7B ," Figure 8A ," Figure 8B ," Figure 4A ," Figure 4B ," Figure 5A ," Figure 5B ," Figure 6A ," Figure 6B ," Figure 7A ," Figure 7B ," Figure 8A ," Figure 8B ,"

[0086] GPS circuit

[0087] Figure 10 A global power switch circuit 1000 is shown, which includes a PMOS transistor 1010 and an NMOS transistor 1020 connected as shown. When the signal ENB_VDD_IP is low, the output VDD_IP will be the same as the input VDD_SYS. When the signal DIS_VDD_IP is high, the output VDD_IP will be pulled down to VDD_IP_LOW.

[0088] Local power switch circuit

[0089] Figure 11A The local power switch 1101 is shown, which includes a PMOS transistor as shown. When the signal ENB_VDD_PS is low, the output VDD_PS will be the same as the input VDD_SYS.

[0090] Figure 11B The local power switch 1102 is shown, which includes an NMOS transistor as shown. When the signal EN_GND_PS is high, the output GND_PS will be pulled low (e.g., to ground).

[0091] Row decoder

[0092] Figure 12 The power-saving row decoder 1200 is shown. The row decoder 1200 includes NAND gate 1201, inverter 1202, and circuit blocks 1203, 1204, 1213, and 1214. Circuit block 1203 includes PMOS 1203A, PMOS 1203C, and NMOS 1203B. Circuit block 1204 includes PMOS 1204A and NMOS 1204B. Circuit blocks 1213 and 1214 are similar to circuit blocks 1203 and 1204, respectively. During the power-down operation, the outputs of NAND gate 1201 and circuit blocks 1203 and 1213 are pulled up to '1' using the power-saving pull-up circuit 501 or pull-up circuit 502 and Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A and / or Figure 8B 's technology, and the outputs of inverter 1202 and circuit blocks 1204 and 1214 are pulled down to '0' using the power-saving pull-down circuit 401 or pull-down circuit 402 and Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A and / or Figure 8B 's technology. During the power-down operation, the power supply ZVDD 1230 can be turned off, thus causing overall power savings. During the power-down operation, nodes 1240 and 1241 are biased at the high voltage '1' so that the voltage between the source and drain of transistors 1203C and 1203B is the same, thus causing overall power savings. During the power-down operation, node n-well 1250 can be biased at a high voltage > ZVDD2 1220 and ZVDD 1230 to increase the reverse body-source voltage, resulting in an increase in the threshold voltages of PMOS1203A and 1204A, thus causing overall power savings.

[0093] Sense circuit

[0094] Figure 13Shown is a sensing circuit 1300, which includes a comparator 1301, a PMOS transistor 1302, an NMOS transistor 1303, and a selected memory cell 1304. The NMOS 1303 is coupled between the memory cell 1304 and the comparator 1301. The positive input of the comparator 1301 is the node between the PMOS transistor 1302 and the NMOS transistor 1303, and the negative input of the comparator 1301 is a reference voltage bias signal. The PMOS 1302 coupled to the high power supply is biased by a leakage current, such as to compensate for array bit line leakage and / or leakage caused by the decoding path (such as from transistor direct gate tunneling current or junction). Thus, data is read from the selected memory cell 1304 without using a reference memory cell. In this mode, the effective reference for the sense is substantially a ground reference level (zero current level), meaning that the memory cell current window (the difference between the high (erased) and low (programmed) current levels) has been shifted towards the ground level. Meaning the low current level is shifted below the ground level. This can be achieved, for example, by biasing the memory cell coupling gate at zero or negative voltage, and / or by performing very deep programming with a higher programming voltage and / or with a larger programming current and / or with a longer programming time, and / or by biasing the read bit line voltage at a low level.

[0095] Figure 14 Shown is a circuit 1400 for a method of sampling a reference current (or reference cell voltage) for a sensing operation, whereby a sampled current mirror (or voltage) is used instead of a continuous current mirror (or voltage), thus causing power savings. The circuit 1400 includes a sampled PMOS transistor 1401, sampled switches 1402 and 1405, an enabling NMOS transistor 1403, a reference element 1404 (which can be a resistor, a memory cell, a transistor, or other element), a reference holding capacitor 1406 (which can be optional), a floating holding node 1410 VREFBIAS (at the terminals of the capacitor), and a sense pull-up PMOS transistor 1407 (as part of the sensing circuit for each selected bit line). The sampling interval is, for example, from 0.2 ms to 0.2 us per cycle, thus effectively reducing the effective power consumption from the reference current 1404 by a ratio of about 2 / 2000. The transistors 1401, 1402, 1403, 1404, 1405 are turned off during the reference holding period (no sampling), and turned on during the sampling period to sample the bias on the reference element 1404 into the floating holding node 1410. The reference 1504 can be generated by a switched-capacitor circuit (Req = 1 / R*Freq).

[0096] Figure 15Circuit 1500 for sampling a reference current (or reference cell voltage) for sensing operations is shown, whereby a sampled current mirror (or voltage) rather than a continuous current mirror (or voltage) will be used, thereby causing power savings. Circuit 1500 includes a sampled PMOS transistor 1501, sampling switches 1502 and 1505, an enable NMOS transistor 1503, a reference element 1504 (which can be a resistor, memory cell, transistor, or other element), a reference holding capacitor 1506, a floating holding node 1510 (at the terminals of capacitor 1506), an operational amplifier 1507, and a sense pull-up PMOS transistor 1508 (as part of the sense circuit for each selected bit line). The sampling interval is, for example, up to 2 us every 0.2 ms, thus effectively reducing the effective power consumption from reference current 1504 by a ratio of about 2 / 200. Transistors 1501, 1502, 1503, 1504, 1505 are turned off during the reference holding period (no sampling) and are turned on during the sampling period to sample the bias on reference element 1504 into floating holding node 1510. The operational amplifier 1507 is used to drive the held reference bias (voltage on capacitor 1506) into the gates of a plurality of sense transistors 1508.

[0097] Read path

[0098] Figure 16 An embodiment of read decode path modulation for a flash memory system 1600 during a read operation for power savings is shown. The flash memory system 1600 implements features that cause overall power savings. Specifically, if the address being read is the same as the address read during the previous cycle, no sensing operation is performed.

[0099] The read address of the current read operation is placed in buffer 1602. The address of the previous read operation is placed in buffer 1601. Comparator 1603 compares the address stored in buffer 1601 with the address stored in buffer 1601. If they are the same address, an enable signal is sent to buffer 1608, which outputs the same output data as during the previous operation. If they are different addresses, a read enable signal is sent to row decoder 1605 and column decoder 1606, and a normal read operation will be performed in array 1604 using sense circuit 1607. In another embodiment, if the data output by sense circuit 1607 is the same as the data held in data output circuit 1608, DOUT is not switched, thereby saving power when DOUT switching is not performed.

[0100] Address / data encoding / decoding / scrambling

[0101] In a method for power saving by encoding / decoding / scrambling addresses and / or data, a specific addressing and / or data access method is used for power saving. In an embodiment for address encoding / decoding / scrambling, for N number of words starting from a selected row and a selected column, in the column (bit line) direction, consecutive addressing (address increment) is utilized to continuously read a sequence of consecutive words. Such as the following: Words 1-4 are consecutively located on rows 1-4, the next words 2-8 are consecutively located on rows 1-4 of the next selected column, and so on and so forth. For this example, the array unit sector includes four rows. In another embodiment for data encoding / decoding / scrambling, a state mainly of '0' is used, meaning that most of the '1' data in the word will be converted to data mainly of '0' in the word before storage. Other address scrambling is embodied such as by scrambling the column address. Other address scrambling is possible, such as by switching the high-order row address order.

[0102] Power gate type

[0103] Figure 17 Various gate symbols and various configurations are shown.

[0104] The first row shows NOR gate 1701, NAND gate 1702, and inverter 1703 as standard gates.

[0105] The second row shows NOR gate 1701, NAND gate 1702, and inverter 1703 with VDDin voltage source and GNDin ground potential.

[0106] The third row shows NOR gate 1701, NAND gate 1702, and inverter 1703 with VDDin voltage source.

[0107] The fourth row shows NOR gate 1701, NAND gate 1702, and inverter 1703 with GNDin ground potential.

[0108] The fifth row shows NOR gate 1701, NAND gate 1702, and inverter 1703 with VDDin voltage source, which are connected to pull-down circuit 401 or pull-down circuit 402 to drive the output of the device to '0'.

[0109] The sixth row shows NOR gate 1701, NAND gate 1702, and inverter 1703 with VDDin voltage source, which are connected to pull-up circuit 501 or pull-up circuit 502 to drive the output of the device to '1'.

Claims

1. A method for generating a reference current, comprising: During a sampling period, turning on a first switch (1402, 1502), a second switch (1405, 1505), an NMOS transistor (1403, 1503), a first PMOS transistor (1401, 1501) and a second PMOS transistor (1407, 1508) to sample a bias voltage generated by a reference element (1404, 1504) into a node (1410, 1510) coupled to a capacitor (1406, 1506), wherein the first PMOS transistor includes a first terminal coupled to a power supply, a gate, and a second terminal coupled to the gate; the NMOS transistor includes a first terminal coupled to the second terminal of the first PMOS transistor through the first switch, a gate, and a second terminal coupled to the reference element; the capacitor includes a first terminal coupled to the power supply and a second terminal coupled to the second terminal of the first PMOS transistor through the second switch; and the second PMOS transistor includes a first terminal coupled to the power supply, a gate coupled to the node, and a second terminal; During a reference holding period, turning off the first switch and the second switch, wherein the second terminal of the second PMOS transistor provides a reference current (iref) in response to the bias voltage held by the capacitor at the node, wherein the reference element is a memory cell.

2. The method according to claim 1, wherein the gate of the second PMOS transistor is coupled to the node through an operational amplifier (1507), the operational amplifier including a non-inverting input coupled to the node, an inverting input, and an output coupled to the inverting input and the gate of the second PMOS transistor.

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