A GaO-based x Fabrication method of GaN CMOS inverter

Abstract

This invention discloses a method based on GaO x A method for fabricating a GaN CMOS inverter includes: sequentially growing a carbon-doped GaN buffer layer on a single-crystal Si substrate or a GaN substrate, and growing a GaN channel layer on the surface of the carbon-doped or silicon-doped GaN buffer layer; photolithographically etching the GaN channel layer and the carbon-doped GaN buffer layer in a direction perpendicular to the surface of the GaN channel layer to form an isolation region, and growing a high thermal conductivity material in the isolation region; fabricating grooves on the GaN layer surfaces on both sides of the isolation region, and depositing GaO in the grooves. x and in the deposition of GaO x Mg ions are injected into one side to form Mg-GaO x A metal film and a dielectric layer are deposited on the device surface, followed by annealing. The drain is obtained in the barrier layer region, and the source is obtained at both ends of the GaN layer. GaO is deposited on both sides... x Layers and Mg-GaO x A metal film and a dielectric layer are deposited on the surface of the layer, then peeled off and annealed to obtain the gate. This invention forms a GaO layer. x —GaN heterojunction can improve the performance of inverters, with a simpler structure and better heat dissipation.

Description

Technical Field

[0001] This invention relates to the field of materials technology, and in particular to a GaO-based... x - Fabrication method of GaN CMOS inverter. Background Technology

[0002] In recent years, GaN and Ga2O3 have been identified as among the most important semiconductors for power applications. They both have relatively large band gaps and breakdown electric fields, enabling high-voltage, high-current, and stable device operation. Inverters with GaN / AlGaN heterojunctions have attracted much attention and widespread application due to their excellent performance. The main characteristics of this type of inverter are: (1) high switching speed and low parasitic inductance; (2) suitability for high-frequency, high-voltage, and other applications.

[0003] However, existing inverters have high power consumption, complex manufacturing processes and circuits, poor heat dissipation, and the maximum on-current density is limited to tens of mA / mm. The devices are also relatively large, and the manufacturing process usually requires plasma etching, which has a significant impact on device performance. Summary of the Invention

[0004] This invention provides a GaO-based x Methods for fabricating GaN CMOS inverters include:

[0005] A carbon-doped GaN buffer layer is sequentially grown on a single-crystal Si substrate or a GaN substrate, and a GaN channel layer is grown on the surface of the carbon-doped or silicon-doped GaN buffer layer.

[0006] Photolithography is performed on the GaN channel layer and carbon-doped GaN buffer layer in the direction perpendicular to the surface of the GaN channel layer to form an isolation region, and a material with high thermal conductivity is grown in the isolation region.

[0007] Grooves are fabricated on the GaN layer surface on both sides of the isolation region, and GaO is deposited in the grooves. x and in the deposition of GaO x Mg ions are injected into one side to form Mg-GaOx;

[0008] A metal film and a dielectric layer are deposited on the device surface, followed by annealing. The drain is formed in the barrier layer region, and the source is formed at both ends of the GaN layer. GaO is deposited on both sides... x Layers and Mg-GaO x A metal film and a dielectric layer are deposited on the surface of the layer, then stripped and annealed to obtain the gate.

[0009] Furthermore, the thickness of the carbon-doped or silicon-doped GaN buffer layer is 3-6 μm, and the concentration of carbon or silicon doping is 1-3 × 10⁻⁶. 18 cm -3 .

[0010] Furthermore, the thickness of the GaN channel layer is 150-250 nm.

[0011] Furthermore, GaO x Layers and Mg-GaO x The thickness of the layer is 40–60 nm.

[0012] Furthermore, Mg-GaO x The Mg doping concentration in the layer is 1–3 × 10⁻⁶. 18 cm -3 .

[0013] Furthermore, the length of the high thermal conductivity material is 4–10 μm.

[0014] Furthermore, in the deposition of GaO x After coating the surface with photoresist, peeling off the photoresist from one side of the groove allows GaO to... x Expose and inject Mg ions.

[0015] Furthermore, Al2O3 is used as the gate dielectric layer with a thickness of 20–30 nm, and silicon is used as the dopant with a doping concentration of 2 × 10⁻⁶. 18 cm -3 .

[0016] Furthermore, the drain and source metal films are made of Ti, Al, Ni, or Au, and are annealed at 650°C in an N2 environment.

[0017] Furthermore, the gate metal film uses Ni or Au.

[0018] This invention proposes a method based on GaO x -GaN CMOS inverter, which forms GaO x —GaN heterojunction has the following advantages: (1) Ga2O3’s high bandgap and support for higher frequencies can improve the performance of inverters, thus making them better suited for high-voltage, high-temperature and high-power power devices; (2) The structure is simpler. Ga2O3 presents an n-type structure due to self-compensation, eliminating the need for a doping step; (3) Diamond isolation is used, which provides good heat dissipation. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1An embodiment of the present invention provides a GaO-based x - Fabrication method of GaN CMOS inverter;

[0021] Figure 2 Another GaO-based embodiment of the present invention is provided. x - Fabrication method of GaN CMOS inverter;

[0022] Figure 3 Another GaO-based embodiment provided for embodiments of the present invention x - Fabrication method of GaN CMOS inverter;

[0023] Figure 4 The fourth GaO-based embodiment provided for the present invention x - Fabrication method of GaN CMOS inverter;

[0024] Figure 5 The GaO-based materials prepared for embodiments of the present invention x -A schematic diagram of the structure of a GaN CMOS inverter;

[0025] Figure 6 The GaO-based materials prepared for embodiments of the present invention x -A schematic diagram of the circuit structure of a GaN CMOS inverter. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0027] One embodiment of the present invention provides a GaO-based x The fabrication method of GaN CMOS inverter includes the following steps:

[0028] Step 1: Grow a carbon-doped GaN buffer layer sequentially on a single-crystal Si substrate or GaN substrate, and grow a GaN channel layer on the surface of the carbon-doped or silicon-doped GaN buffer layer.

[0029] In this embodiment, as Figure 1 As shown, preferably, a 4 μm carbon-doped GaN buffer layer is grown on a Si or GaN substrate by organic chemical vapor deposition (MOCVD). Gallium nitride (GaN) of preferably 200 nm is grown on the substrate above the buffer layer by MOCVD. Preferably, the concentration of carbon or silicon doping is 2 × 10⁻⁶. 18 cm -3 The thickness of the substrate is 1 to 1.5 mm, preferably 1.15 mm.

[0030] Step 2: Photolithography is performed on the GaN channel layer and carbon-doped GaN buffer layer in the direction perpendicular to the surface of the GaN channel layer to form an isolation region, and a high thermal conductivity material is grown in the isolation region;

[0031] Embodiments of the present invention, such as Figure 2 As shown, diamond or aluminum nitride ceramics are vertically grown in the buffer layer of the intermediate isolation region using metal-organic chemical vapor deposition (MOCVD). The length of the high thermal conductivity material is 4–10 μm, preferably 5 μm. The thickness of the GaN channel layer is 150–250 nm, preferably 200 nm.

[0032] Step 3: Create grooves on the GaN layer surface on both sides of the isolation region, and deposit GaO in the grooves. x and in the deposition of GaO x Mg ions are injected into one side to form Mg-GaO x ;

[0033] Embodiments of the present invention, such as Figure 3 As shown, during the fabrication of the grooves, photolithography is used to simultaneously create grooves on the gallium nitride (GaN) layers on both sides of the isolation region, with a depth of 10–100 nm, preferably 50 nm. GaO is then deposited on the groove sides using methods such as hydride vapor phase epitaxy (HVPE) and molecular organic vapor deposition (MBE). x The depth is the same as the groove depth. (This refers to the deposition of GaO.) x After coating the surface with photoresist, peeling off the photoresist from one side of the groove allows GaO to... x Exposure, injection of Mg ions, Mg-GaO x The Mg doping concentration in the layer is 1–3 × 10⁻⁶. 18 cm -3 Preferably 2×10 18 cm -3 In other embodiments, Mg ions can be replaced with other metal ions. GaO x Layers and Mg-GaO x The thickness of the layer is 40–60 nm, preferably 50 nm.

[0034] Step 4: Deposit a metal film and a dielectric layer on the device surface, anneal, obtain the drain in the barrier layer region, obtain the source at both ends of the GaN layer, and obtain the GaO on both sides. x Layers and Mg-GaO x A metal film and a dielectric layer are deposited on the surface of the layer, then stripped and annealed to obtain the gate.

[0035] Embodiments of the present invention, such as Figure 4As shown, in the fabrication of the drain and source electrodes: metal films (such as Ti (25nm) / Al (75nm) / Ni (25nm) / Au (75nm)) are deposited using methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation. After forming the electrodes using a lift-off process, they are annealed at 650℃ in an N2 environment. In the fabrication of the gate electrode, methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation are used to deposit metal films on GaO. x and Mg-GaO x A metal film (such as Ni (25nm) / Au (25nm)) is deposited on the layer, and after forming electrodes using a lift-off process, it is annealed at 650°C in an N2 environment.

[0036] In this embodiment of the invention, Al2O3 is used as the gate dielectric layer with a thickness of 20–30 nm, and silicon is used as the dopant with a doping concentration of 2 × 10⁻⁶. 18 cm -3 .

[0037] like Figure 5 To prepare the GaO-based x - A schematic diagram of a GaN CMOS inverter, where 1 and 9 are gate electrodes, 2 and 10 are source electrodes, and 3 is a GaO electrode. x Layers 4 and 12 are GaN channel layers, layers 5 and 13 are GaN buffer layers, layer 6 is a silicon single crystal substrate, layer 7 is the drain, layer 8 is the gate dielectric layer, and layer 11 is Mg-GaO. x Layer 14 is a diamond layer. Figure 6 For GaO x -Circuit diagram of a GaN CMOS inverter.

[0038] This invention proposes a GaO x -GaN CMOS inverter, which forms a GaO x —GaN heterojunction has the following advantages: (1) Ga2O3’s high bandgap and support for higher frequencies can improve the performance of inverters, thus making them better suited for high-voltage, high-temperature and high-power power devices; (2) The structure is simpler. Ga2O3 presents an n-type structure due to self-compensation, eliminating the need for a doping step; (3) Diamond isolation is used, which provides good heat dissipation.

[0039] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0040] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A CMOS inverter based on GaO x -GaN, characterized in that Comprise: Sequentially growing carbon-doped or silicon-doped GaN buffer layer on single crystal Si substrate or GaN substrate, and growing GaN channel layer on the surface of carbon-doped or silicon-doped GaN buffer layer; Photoetching GaN channel layer and carbon-doped or silicon-doped GaN buffer layer in the direction of vertical GaN channel layer surface to form isolation area, and growing high-thermal-conductivity substance in the isolation area; Grooves are made on the surface of the GaN layer on both sides of the isolation region, and GaO is deposited in the grooves x Mg ions are injected into GaOx on one side of the isolation region to form Mg-GaOx A metal film and dielectric layer are deposited on the device surface, followed by annealing. The drain is formed in the isolation region, and the source is formed at both ends of the GaN channel layer. GaO is deposited on both sides... x Layers and Mg-GaO x A metal film and a dielectric layer are deposited on the surface of the layer, and the GaO on both sides is stripped away. x Layers and Mg-GaO x The metal outside the layer surface is annealed to obtain the gate.

2. The production method according to claim 1, characterized by, The thickness of the carbon or silicon doped GaN buffer layer is 3-6 μm, and the carbon or silicon doping concentration is 1-3 x 1018 cm-3. 18 cm -3 .

3. The preparation method according to claim 1, characterized in that, The thickness of GaN channel layer is 150-250nm.

4. The preparation method according to claim 1, characterized in that, GaO x layer and Mg-GaO x The thickness of the layer is 40-60 nm.

5. The preparation method according to claim 4, characterized in that, Mg-GaO x The doping concentration of Mg in the layer is 1-3 x 10 18 cm -3 .

6. The preparation method according to claim 1, characterized in that, The length of high-thermal-conductivity substance is 4-10μm.

7. The preparation method according to claim 1, characterized in that, After depositing GaO x the surface is coated with photoresist, the photoresist is removed from the side of the groove, exposing the GaO x and Mg ions are implanted.

8. The method of claim 1, wherein, Al2O3 is used as the gate dielectric layer, the thickness of Al2O3 is 20-30 nm, silicon is used as the dopant, and the doping concentration is 2x10 18 cm -3 .

9. The method of claim 1, wherein, The metal film of drain and source uses Ti, Al, Ni or Au, and is annealed at 650℃ in N2 environment.

10. The method of claim 1, wherein, The metal film of gate uses Ni or Au.

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