A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The present disclosure provides a semiconductor device manufacturing method and a semiconductor device. The method comprises forming a first stack layer on a substrate, the first stack layer comprising first connection region stack layers at both ends of the first stack layer and second connection region stack layers between the first connection region stack layers. A protective layer is then formed to cover the first connection region stack layers and the second connection region stack layers. Finally, the first stack layer not covered by the protective layer is etched. The width of the first connection region stack layers in the second direction is greater than the width of the second connection region stack layers in the second direction, so that the protective layer on the first connection region stack layers and the second connection region stack layers near the first connection region stack layers is not too thin, thereby reducing the side etching of the protective layer on the first connection region stack layers and the second connection region stack layers near the first connection region stack layers, and enabling the protective layer to effectively protect the first connection region stack layers and the second connection region stack layers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to electronic devices, and more particularly to a semiconductor device manufacturing method and semiconductor device. BACKGROUND

[0002] Three-dimensional memory has been increasingly widely used in electronic products due to its low power consumption, light weight, and excellent performance as a non-volatile storage product. However, users have increasingly high expectations and requirements for three-dimensional memory. As the number of layers increases, semiconductor processes and manufacturing techniques become challenging. SUMMARY

[0003] The present disclosure aims to provide a semiconductor device manufacturing method and semiconductor device, which aims to effectively protect the connection structure by increasing the width of the first connection region stack layer.

[0004] In one aspect, the present disclosure provides a semiconductor device manufacturing method, comprising:

[0005] providing a substrate;

[0006] forming a first stack layer on the substrate, the first stack layer comprising first connection region stack layers located at both ends of the first stack layer in a second direction, and second connection region stack layers located between the first connection region stack layers, wherein the width of the first connection region stack layers in the second direction is greater than the width of the second connection region stack layers in the second direction;

[0007] forming a protection layer covering the first connection region stack layers and the second connection region stack layers;

[0008] forming a connection structure located below the protection layer.

[0009] Further preferably, the first stack layer further comprises a staircase region stack layer, and the staircase region stack layer and the second connection region stack layer are alternately arranged in the second direction.

[0010] Further preferably, before the step of forming a protection layer covering the first connection region stack layers and the second connection region stack layers, the manufacturing method further comprises:

[0011] forming a shielding layer on the first connection region stack layers;

[0012] forming a mask layer on the second connection region stack layers;

[0013] etching the staircase region stack layer based on the mask layer and the shielding layer to form a staircase structure in the staircase region stack layer;

[0014] removing the blocking layer and the mask layer.

[0015] Further preferably, the step of forming the protective layer covering the first connection region stack layer and the second connection region stack layer comprises:

[0016] forming a photoresist layer on the first stack layer;

[0017] exposing and developing the photoresist to form a patterned photoresist layer on the first connection region stack layer and the second connection region stack layer as the protective layer.

[0018] Further preferably, the step of forming the connection structure under the protective layer comprises:

[0019] continuing to etch down the staircase structure, the protective layer protecting the first connection region stack layer and the second connection region stack layer from being etched to form the connection structure.

[0020] Further preferably, the method further comprises:

[0021] in the step of forming the first stack layer, forming a second stack layer on the substrate adjacent to the first stack layer in a first direction, the first direction being perpendicular to the second direction;

[0022] forming a memory structure through the second stack layer in a third direction perpendicular to the substrate.

[0023] Further preferably, the step of forming a second stack layer on the substrate adjacent to the first stack layer in a first direction in the step of forming the first stack layer comprises:

[0024] alternately stacking layers of conductive material and layers of dielectric material in a third direction perpendicular to the substrate.

[0025] In another aspect, the disclosure provides a semiconductor device comprising:

[0026] a substrate;

[0027] a first stack layer on the substrate;

[0028] wherein the first stack layer comprises a first connection structure at each end of the first stack layer in a second direction, and a plurality of second connection structures between the first connection structures; the first connection structure having a width in the second direction that is greater than a width of the second connection structures in the second direction.

[0029] Further preferably, the first stack layer further comprises a plurality of stepped structures, the stepped structures being arranged alternately with the second connection structures in the second direction.

[0030] Further preferably, the semiconductor device further comprises: a second stack layer arranged adjacent to the first stack layer in a first direction perpendicular to the second direction.

[0031] Further preferably, the first stack layer and the second stack layer respectively comprise a plurality of dielectric material layers and a plurality of conductive material layers alternately stacked in a third direction perpendicular to the substrate.

[0032] Further preferably, the semiconductor device further comprises: a storage structure penetrating through the second stack layer in the third direction perpendicular to the substrate.

[0033] The beneficial effects of the present disclosure can include: providing a semiconductor device and a preparation method thereof, comprising forming a stack structure on a substrate, the stack structure comprising a first stack layer and a second stack layer arranged adjacent to the first stack layer in a first direction, the first stack layer comprising a first connection region stack layer and a second connection region stack layer arranged between the first connection region stack layer, the first connection region stack layer being located at both ends of the first stack layer in a second direction. Then a protective layer covering the first connection region stack layer and the second connection region stack layer is formed, and finally the first stack layer not covered by the protective layer is etched. Wherein the width of the first connection region stack layer in the second direction is greater than the width of the second connection region stack layer in the second direction, so as to prevent the protective layer on the first connection region stack layer and the second connection region stack layer near the first connection region stack layer from being too thin, thereby reducing the side etching of the protective layer on the first connection region stack layer and the second connection region stack layer near the first connection region stack layer, and enabling the protective layer to effectively protect the first connection region stack layer and the second connection region stack layer. BRIEF DESCRIPTION OF DRAWINGS

[0034] The technical solutions and other beneficial effects of the present disclosure will become apparent through the following detailed description of specific embodiments of the present disclosure in conjunction with the accompanying drawings.

[0035] Figure 1 is a flowchart of a preparation method of a semiconductor device provided by an embodiment of the present disclosure;

[0036] Figure 2a is a cross-sectional structure schematic diagram of forming a stack layer in the preparation process of a semiconductor device provided by an embodiment of the present disclosure;

[0037] Figure 2b is a top view structure schematic diagram of forming a stack layer in the preparation process of a semiconductor device provided by an embodiment of the present disclosure;

[0038] Figure 2c is a schematic view of a first stack layer in the embodiment of the present disclosure Figure 2b

[0039] Figure 3a is a schematic view of a first stack layer in the process of forming a step structure in the embodiment of the present disclosure

[0040] Figure 3b is a schematic view of a first stack layer in the process of forming a step structure in the embodiment of the present disclosure Figure 3a

[0041] Figure 3c is a schematic view of a first stack layer in the process of forming a step structure in the embodiment of the present disclosure Figure 3b

[0042] Figures 4a-4b is a schematic view of a first stack layer in the process of forming a step structure in the embodiment of the present disclosure

[0043] Figure 5a is a schematic view of a first stack layer in the process of forming a step structure in the embodiment of the present disclosure

[0044] Figure 5b is a schematic view of a first stack layer in the process of forming a step structure in the embodiment of the present disclosure Figure 5a DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present disclosure.

[0046] It should be understood that although the terms first, second, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the present disclosure.

[0047] It should be understood that when one component is said to be “on” or “connected” to another component, it can be directly on or connected to the other component, or there can be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0048] ​​​​As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively close to a substrate and the top side is relatively far from the substrate. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes that are between and at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, where it can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more electrically conductive layers and contact layers (where contacts, interconnect lines, and one or more dielectric layers are formed).

[0049] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

[0050] It should be noted that the diagrams in the embodiments of the present disclosure only schematically illustrate the basic concepts of the present disclosure, and although only the components related to the present disclosure are shown in the diagrams, the actual implementation is not drawn according to the number, shape and size of the components, and the actual implementation of each component can be arbitrarily changed, and the component layout pattern can be more complex.

[0051] One storage plane of a 3D NAND can generally include two storage (GB) and a staircase region between the two storage regions, the staircase region including a plurality of spaced-apart staircase structures to lead out a word line contact from a step, so that the conductive material layer of the two storage regions can be connected with the word line through the staircase structure. The staircase region further includes a connection structure located between two adjacent staircase structures.

[0052] Please refer to Figure 1 , Figure 1 is a flowchart of a preparation method of a semiconductor device provided by the embodiments of the present disclosure. The preparation method includes the following steps S1-S5.

[0053] Please refer to Figure 1 steps S1-S2 and Figures 2a-2b , Figure 2a is a cross-sectional structure schematic diagram of forming a stack layer in the preparation process of a semiconductor device provided by the embodiments of the present disclosure, Figure 2b is a top view structure schematic diagram of forming a stack layer in the preparation process of a semiconductor device provided by the embodiments of the present disclosure.

[0054] Step S1: providing a substrate 10.

[0055] In this embodiment, the substrate 10 is a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). In other embodiments, the semiconductor substrate may also be a substrate including semiconductors of other elements or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0056] Step S2: A stacked structure 20 is formed on the substrate 10. The stacked structure 20 includes a first stacked layer 21 and a second stacked layer 22 disposed adjacent to the first stacked layer 21 in a first direction (Y). The first stacked layer 21 includes a connection region stacked layer 211 and a step region stacked layer 212 disposed alternately along a second direction (X).

[0057] Specifically, dielectric material layers and conductive material layers are alternately stacked on the substrate 10 along a third direction (Z) perpendicular to the substrate 10 to form a stacked structure 20. The stacked structure 20 may include a first stacked layer 21 and two second stacked layers 22 disposed adjacent to the first stacked layer 21 in a first direction (Y). The dielectric material layer may be silicon oxide, and the conductive material layer may be tungsten. In this embodiment, the first stacked layer 21 may be used to form a stepped structure and an interconnect structure, and the second stacked layers 22 may be used to form a storage structure. It is understood that the first stacked layer 21 is disposed along the second direction (X), meaning that the length direction of the first stacked layer 21 is along the second direction (X).

[0058] Please see Figure 2c , Figure 2c This is provided by the embodiments of this disclosure. Figure 2b A magnified structural diagram of the first stacked layer 21. Figure 2b The stacked structure 20 extends over a storage plane, therefore the edge of the first stacked layer 21 in the second direction (X) is the edge of the storage plane. The first stacked layer 21 includes alternating connection area stacked layers 211 and stepped area stacked layers 212 along the second direction (X), with the connection area stacked layers 211 and the stepped area stacked layers 212 respectively arranged along the first direction (Y). In this embodiment, the connection area stacked layer 211 may include two first connection area stacked layers 2111 located at both ends of the first stacked layer 21 in the second direction (X), and a plurality of second connection area stacked layers 2112 located between the two first connection area stacked layers 2111. The first connection area stacked layers 2111 are located at both ends of the first stacked layer 21 in the second direction (X), i.e., at the edge of the storage plane.

[0059] In the embodiment, the first connection region stack layer 2111 has a width in the second direction (X) that is greater than the width of the second connection region stack layer 2112 in the second direction (X).

[0060] Please refer to Figure 1 step S3 and Figures 3a-3c , Figure 3a is a top view structural schematic diagram of a first stack layer in a process of forming a stepped structure provided by the embodiment of the present disclosure, Figure 3b is a YZ cross-sectional structural schematic diagram of a stepped region stack layer after forming a stepped structure in the embodiment of the present disclosure, Figure 3a is a YZ cross-sectional structural schematic diagram of a stepped region stack layer in the embodiment, Figure 3c is a cross-sectional structural schematic diagram at B-B1 in the embodiment. Figure 3b Step S3: forming a stepped structure 30 in the stepped region stack layer 212.

[0061] In the embodiment, step S3 can include the following steps. 1) As shown in

[0062] , forming a shielding layer 40 on the two first connection region stack layers 2111. 2) Forming a mask layer 41 on the second connection region stack layer 2112 and part of the first connection region stack layer 2111, the mask layer 41 has an overlapping part with the shielding layer 40, and the material of the mask layer 41 can be the same as that of the shielding layer 40, for example, polysilicon, high dielectric constant dielectric, titanium nitride or any other appropriate hard mask material. 3) Based on the mask layer 41 and the shielding layer 40, etching the stepped region stack layer 212 to form a stepped structure 30 in each of the stepped region stack layers 212 (as shown in Figure 3a ), and the structure of the first stack layer 21 after forming the stepped structure 30 is as shown in Figure 3b . Among them, the shielding layer 40 is used to protect the first connection region stack layer 2111 from forming a stepped structure, and the mask layer 41 can protect the second connection region stack layer 2112 from forming a stepped structure, so the top surface of the connection region stack layer 211 is still horizontal after step S3. Since the mask layer is square, if there is no shielding layer 40, the first connection region stack layer 2111 will be etched to form a stepped structure. After forming the stepped structure 30, the preparation method further includes removing the shielding layer 40 and the mask layer 41. Figure 3c In some embodiments, the width of the first connection region stack layer 2111 is equal to the width of the second connection region stack layer 2112 (for example, both equal to the width of the second connection region stack layer 2112 in

[0063] Figure 3a , then the stepped structure 30 is formed Figure 3a ​The mask layer 41 shown can just cover the first connection region stack layer 2111 and the second connection region stack layer 2112, so that the first connection region stack layer 2111 and the second connection region stack layer 2112 can be reserved to form the first connection structure and the second connection structure respectively when the subsequent etching of the stepped structure 30 is performed. Figure 3a In the embodiment (the first connection region stack layer 2111 has a width greater than that of the second connection region stack layer 2112), the mask layer used is the same as that of some embodiments (meaning that the pattern of the mask plate used is the same). Therefore, compared with some embodiments, even if the first connection region stack layer 2111 has a width greater than that of the second connection region stack layer 2112 in the embodiment, the same mask plate as that of some embodiments can be used, and there is no need to spend cost to change the pattern design of the mask plate.

[0064] In the embodiment, the mask layer 41 can cover the first connection region stack layer 2111 and the second connection region stack layer 2112. Figure 3a In a variant of the embodiment, the mask layer 41 can only cover the second connection region stack layer 2112, and the cover layer 40 covers the first connection region stack layer 2111, so that the first connection region stack layer 2111 and the second connection region stack layer 2112 can also be guaranteed not to be etched in the subsequent process.

[0065] Further, the stepped structure 30 can include a plurality of sub-stepped structures 31 connected in a head-to-tail manner, and the inclination directions of two adjacent sub-stepped structures 31 are opposite. Each sub-stepped structure 31 includes a plurality of small steps (not shown in the figure).

[0066] Please refer to steps S4 and Figure 1 in the embodiment. Figures 4a-4b , Figures 4a-4b is a cross-sectional structure schematic diagram in the process of forming the protective layer provided by the embodiment of the disclosure.

[0067] Step S4: forming a protective layer 51 covering the connection region stack layer 211.

[0068] In the embodiment, step S4 can include: 1) as shown in Figure 4a , forming a photoresist layer 50 on the first stack layer 21; 2) as shown in Figure 4bAs shown, the photoresist layer 50 is exposed and developed to form a patterned photoresist layer, which is used as the protective layer 51 on the connection region stack layer 211. The blank area on both sides of the first connection region stack layer 2111 is a cutting path area, which is used to divide the semiconductor device to form multiple storage planes. In some embodiments, if the width of the first connection region stack layer 2111 is as narrow as the second connection region stack layer 2112, the photoresist layer 50 formed by spin coating will be thin at the first connection region stack layer 2111 and the second connection region stack layer 2112 close to the first connection region 2111. When exposed and developed, the side of the photoresist layer 50 at the thin part will also be removed (which can be referred to as "side etching"), so the photoresist layer 50 at this position is prone to collapse, which cannot effectively protect the stack layer below in step S5, affecting the morphology.

[0069] In this embodiment, the morphology of the photoresist layer 50 is not flat at the edge of the first connection region stack layer 2111, but forms an arc line as shown. Figure 4a Since the width of the first connection region stack layer 2111 in the second direction (X) is greater than the width of the second connection region stack layer 2112 in the second direction (X), the photoresist layer 50 formed is only thin at the edge of the first connection region stack layer 2111, and the photoresist layer 50 above the second connection region stack layer 2112 in the middle is uniform in thickness, so the patterned photoresist layer will not be side etched, so the protective layer 51 formed can effectively protect the connection region stack layer 211, and then a complete connection structure can be formed in the subsequent process. Since the width of the first connection region stack layer 2111 is wide, the risk of failure of the first connection region stack layer 2111 can be reduced. That is, even if the first connection region stack layer 2111 at the edge is damaged a little, the overall structure will not fail.

[0070] Please refer to step S5 in Figure 1 and Figures 5a-5b , Figure 5a is a cross-sectional structure schematic diagram in the process of forming a connection structure provided by the embodiment of the present disclosure, Figure 5b is a cross-sectional structure schematic diagram at C-C1 in Figure 5a provided by the embodiment of the present disclosure.

[0071] Step S5: etching the first stack layer 21 not covered by the protective layer 51.

[0072] Based on Figure 3b , the step structure 30 is etched downward to reduce the height of the step structure 30 to form a step structure 30', and the height of each sub-step structure 31 is reduced to form a sub-step structure 31', and the height of each sub-step structure 31' can be different. As shown inFigure 5b As shown in Figure 4b In the protection of the protective layer 51, the first connection region stack layer 2111 and the second connection region stack layer 2112 are not etched to form the first connection structure 61 and the second connection structure 62, respectively, and the first connection structure 61 and the second connection structure 62 constitute the connection structure 60. After forming the connection structure 60, the protective layer 51 is removed. The difference between the first connection region stack layer 2111 and the second connection region stack layer 2112 and the first connection structure 61 and the second connection structure 62 can be compared with Figure 3c and Figure 5b In Figure 3c , the first connection region stack layer 2111 and the second connection region stack layer 2112 are integrated with the stepped region stack layer 212; in Figure 5b , after the formation of the stepped structure 30', the first connection structure 61 and the second connection structure 62 become independent structures.

[0073] Please refer to Figure 5a and Figure 5b , the stepped structure 30' is formed between two adjacent connection structures 60, and a word line contact is formed on each sub-stepped structure 31' of the stepped structure 30' (regarding a sub-stepped structure 31' as a step), and then the word line (or gate layer) of each step is driven through the word line contact. Since the stepped structure 30' separates the two second stack layers on both sides in the Y direction, that is, each step is connected to only one of the second stack layers, for example Figure 5a , the left step is connected to the second stack layer on its left side, but not connected to the second stack layer on its right side. Since the stepped structure 30' is adjacent to and in contact with the connection structure 60, the left step can be electrically connected to the right second stack layer through the gate layer in the connection structure 60, so that a bidirectional word line driving scheme can be realized, which is the main function of the connection structure 60.

[0074] It can be understood that, since Figure 5a , the C-C1 in Figure 5b is located at the bottom of the stepped structure 30', therefore, the stepped structure 30' in Figure 5a is not shown. The connection structure 60 includes two first connection structures 61 respectively located at both ends of the first stack layer 21 in the second direction (X), and a plurality of second connection structures 62 located between the two first connection structures 61. Since the width of the first connection region stack layer 2111 in the second direction (X) is greater than the width of the second connection region stack layer 2112 in the second direction (X), the width of the first connection structure 61 in the second direction (X) is greater than the width of the second connection structure 62 in the second direction (X).

[0075] The preparation method can further include forming a storage structure along a third direction (Z) perpendicular to the substrate 10 and penetrating the second stack layer 22, the storage structure including a channel structure penetrating the second stack layer 22 along the third direction (Z).

[0076] The preparation method of the semiconductor device provided in the embodiments of the present disclosure can prevent the first connection region stack layer 2111 from being etched to form a staircase in the process of forming the staircase structure 30 by shielding the first connection region stack layer 2111 with the shielding layer 40. Since the first connection region stack layer 2111 has a large width, the topography of the photoresist layer 50 (the thickness is uniform above several connection region stack layers 211 at the edge) can be improved, and side etching does not occur when the patterned photoresist layer (the protection layer 51) is formed, so the protection layer 51 can effectively protect the connection region stack layer 211 to form the connection structure 60.

[0077] The embodiments of the present disclosure further provide a semiconductor device, which can be prepared by the preparation method of the semiconductor device described above, and thus can refer to the description of the preparation method of the semiconductor device for details. Figures 2a-2b and Figure 5a and Figure 5b The semiconductor device includes a substrate 10, a stack structure 20 on the substrate 10, the stack structure 20 including a first stack layer 21 and two second stack layers 22 adjacent to the first stack layer 21 in a first direction (Y), the first stack layer 21 including connection structures 60 and staircase structures 30' alternately arranged in a second direction (X), and the connection structures 60 and the staircase structures 30' being arranged in a first direction (Y) parallel to the substrate 10 and perpendicular to the second direction (X), respectively.

[0078] The connection structures 60 include two first connection structures 61 respectively at both ends of the first stack layer 21 in the second direction (X), and a plurality of second connection structures 62 between the two first connection structures 61. The width of the first connection structure 61 in the second direction (X) is greater than the width of the second connection structure 62 in the second direction (X).

[0079] The semiconductor device can further include a storage structure penetrating the two second stack layers 22 along a third direction perpendicular to the substrate 10.

[0080] The stack structure 20 includes alternately stacked dielectric material layers and conductive material layers in a third direction (Z) perpendicular to the substrate 10, respectively.

[0081] The above descriptions of the embodiments are only used to help understand the technical solutions of the present disclosure and the core ideas thereof; it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A stacked structure is formed on the substrate. The stacked structure includes a first stacked layer and a second stacked layer disposed adjacent to the first stacked layer in a first direction. The first stacked layer includes a first connection region stacked layer located at both ends of the first stacked layer in a second direction and a second connection region stacked layer located between the first connection region stacked layers. The width of the first connection region stacked layer in the second direction is greater than the width of the second connection region stacked layer in the second direction. The first direction is perpendicular to the second direction. A protective layer is formed covering the first connection region stack layer and the second connection region stack layer; The first stacked layer not covered by the protective layer is etched.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first stacking layer further includes a stepped area stacking layer, which is alternately arranged with the second connection area stacking layer in the second direction.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, Before the step of forming a protective layer covering the first connection region stack layer and the second connection region stack layer, the preparation method further includes: A shielding layer is formed on the stacked layer of the first connection region; A mask layer is formed on the stacked layer of the second connection region; The stepped region stack layer is etched based on the mask layer and the shielding layer to form a stepped structure in the stepped region stack layer; Remove the masking layer and the mask layer.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming a protective layer covering the first connection region stack layer and the second connection region stack layer includes: A photoresist layer is formed on the first stacked layer; The photoresist is exposed and developed to form a patterned photoresist layer, which is located on the first connection region stack layer and the second connection region stack layer as the protective layer.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The step of etching the first stacked layer not covered by the protective layer includes: The stepped structure is etched downwards to reduce its height.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The preparation method further includes: A storage structure is formed that extends through the second stacked layer in a third direction perpendicular to the substrate.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The step of forming a stacked structure on the substrate includes: Conductive material layers and dielectric material layers are alternately stacked in a direction perpendicular to the substrate.

8. A semiconductor device, characterized in that, include: Substrate; A stacked structure located on the substrate, the stacked structure including a first stacked layer and a second stacked layer disposed adjacent to the first stacked layer in a first direction; The first stacked layer includes first connecting structures located at both ends of the first stacked layer in a second direction, and a plurality of second connecting structures located between the first connecting structures; the width of the first connecting structure in the second direction is greater than the width of the second connecting structure in the second direction, and the first direction is perpendicular to the second direction; Both the first connection structure and the second connection structure include alternating layers of dielectric material and conductive material.

9. The semiconductor device according to claim 8, characterized in that, The first stacked layer further includes multiple stepped structures, which are alternately arranged with the second connecting structure in the second direction.

10. The semiconductor device according to claim 8, characterized in that, The stacked structure, along a third direction perpendicular to the substrate, comprises alternating layers of dielectric material and conductive material.

11. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a memory structure that extends through the second stacked layer in a third direction perpendicular to the substrate.

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