Epitaxial structure of compound semiconductor device and method for manufacturing the same

Abstract

The application discloses an epitaxial structure of a compound semiconductor device and a preparation method thereof, and the method comprises the following steps: forming a collector layer of n-type doped gallium nitride (GaN) material on a silicon (Si) substrate by epitaxy; forming a p-type doped gallium arsenide (GaAs) base layer on the collector layer by epitaxy; and forming an n-type doped aluminum gallium arsenide (AlGaAs) emitter layer on the base layer by epitaxy. Since the epitaxial structure of the HBT is made of material epitaxial layers on the Si substrate, a large-size silicon wafer can be used to reduce the manufacturing cost of the chip. Meanwhile, since the HBT device with the epitaxial structure of the HBT uses GaN material as the collector layer, a higher working voltage can be used, thereby being beneficial to increasing the output power of the HBT device, overcoming the power limitation of the GaAs HBT device, and better meeting the high-frequency and high-power requirements of 5G communication.

Description

Technical Field

[0001] This application relates to the field of semiconductor device process technology, specifically to an epitaxial structure of a compound semiconductor device and its preparation method. Background Technology

[0002] The development of wireless communication technology has placed higher demands on the performance of radio frequency (RF) devices, such as higher frequency range, higher power, higher efficiency, and higher operating voltage. Therefore, RF devices based on compound semiconductor materials are finding increasingly widespread applications in the field of wireless communication.

[0003] Gallium arsenide (GaAs) compound semiconductors are one of the main materials for radio frequency power amplifiers in wireless communication systems, and are widely used in the fabrication of radio frequency and microwave devices and high-speed digital circuits due to their high electron mobility. Semiconductor devices made of GaAs have advantages such as high frequency, good temperature performance, low noise, and strong radiation resistance.

[0004] Currently, GaAs-based semiconductor devices mainly include heterojunction bipolar transistors (GaAs HBTs) and high electron mobility transistors (GaAs HEMTs). Among them, GaAs HBTs are widely used in mobile phones, optical communication systems, radar systems, and other equipment systems due to their advantages such as high power density, high gain, low phase noise, good linearity, small chip area, and low manufacturing cost. Summary of the Invention

[0005] In a first aspect, a method for fabricating the epitaxial structure of a compound semiconductor device according to this application includes:

[0006] An n-type doped gallium nitride (GaN) collector layer is epitaxially formed on a silicon (Si) substrate;

[0007] A p-type doped gallium arsenide (GaAs) base layer is epitaxially formed on the current collector layer;

[0008] An n-type doped aluminum gallium arsenide (AlGaAs) emitter layer is epitaxially formed on the base layer.

[0009] Secondly, the present application discloses an epitaxial structure for a compound semiconductor device, comprising: a silicon (Si) substrate, an n-type doped gallium nitride (GaN)-based collector layer, a p-type doped gallium arsenide (GaAs) base layer, and an n-type doped aluminum gallium arsenide (AlGaAs) emitter layer; wherein...

[0010] The current collector layer, the base layer, and the emitter layer are placed sequentially from bottom to top on the upper surface of the substrate.

[0011] As can be seen, this application proposes an epitaxial structure for a compound semiconductor device, a novel epitaxial structure for HBTs, which fabricates the material epitaxial layer on a Si substrate. This allows the use of large-size silicon wafers to reduce chip manufacturing costs. Furthermore, the use of Si substrates will significantly reduce the consumption of GaAs substrate material, greatly mitigating the environmental pollution risks posed by As.

[0012] Meanwhile, in practical applications of HBT devices with new epitaxial structures, the use of GaN-based materials as the collector layer allows for the use of higher operating voltages, which in turn helps to increase the output power of the HBT device, overcome the power limitations of GaAs HBT devices, and better meet the high-frequency and high-power requirements of 5G communication. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the epitaxial structure of a GaAs HBT according to an embodiment of this application;

[0015] Figure 2 This is a schematic diagram of the epitaxial structure of a compound semiconductor device according to an embodiment of this application;

[0016] Figure 3 This is a schematic flowchart of a method for fabricating the epitaxial structure of a compound semiconductor device according to an embodiment of this application;

[0017] Figure 4 This is a schematic diagram of the structure after fabrication of the current collector layer according to an embodiment of this application;

[0018] Figure 5 This is a schematic diagram of the structure after the base layer is fabricated according to an embodiment of this application;

[0019] Figure 6 This is a schematic diagram of the structure after the emission layer is fabricated according to an embodiment of this application;

[0020] Figure 7 This is a schematic diagram of the process for fabricating the emitter of an HBT device according to an embodiment of this application;

[0021] Figure 8This is a schematic diagram of the base fabrication process of an HBT device according to an embodiment of this application;

[0022] Figure 9 This is a schematic diagram of the collector fabrication process of an HBT device according to an embodiment of this application;

[0023] Figure 10 This is a schematic diagram of the structure of an HBT device according to an embodiment of this application;

[0024] Figure 11 This is a schematic diagram of the structure of another HBT device according to an embodiment of this application;

[0025] Figure 12 This is a schematic diagram of the structure of another HBT device according to an embodiment of this application;

[0026] Figure 13 This is a schematic diagram of a power amplifier circuit based on an HBT device according to an embodiment of this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0028] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. The reference to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments. Furthermore, the terms "placed on," "placed," or "placed in" in the embodiments of this application are equivalent to "deposited," referring to a layer structure deposited using thin-film deposition techniques in semiconductor manufacturing processes.

[0029] In the accompanying drawings provided in this application, the cross-sectional views of the device structure shown may not be scaled up, and the schematic diagrams are merely illustrative and should not limit the scope of protection claimed in this application. Furthermore, the thickness of each layer in the cross-sectional views of the device structure is only schematic and needs to be determined based on the specific semiconductor process, and does not constitute a limitation on the embodiments of this application. Additionally, the radio frequency semiconductor device fabricated in the actual fabrication process should include three-dimensional spatial dimensions of length, width, and depth.

[0030] In the embodiments of this application, "at least one item" or its similar expression refers to any combination of these items, including any combination of a single item or a plurality of items. "One or more" means one or more, while "multiple" means two or more. For example, "at least one item" of a, b, or c can represent the following seven cases: a, b, c; a and b; a and c; b and c; a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.

[0031] In this embodiment, the epitaxial structure of GaAs HBT can be prepared using the following method:

[0032] On a GaAs substrate, an n-type doped GaAs (n-GaAs) collector layer, a p-type doped GaAs (p-GaAs) base layer, and an n-type doped AlGaAs (n-AlGaAs) emitter layer are epitaxially grown sequentially. Figure 1 As shown.

[0033] The current collector layer material is GaAs, with a band gap of 1.4 eV and a breakdown electric field strength of 0.4 MV / cm.

[0034] In addition, unlike the GaAs HBT epitaxial structure described above, this application proposes an epitaxial structure for a compound semiconductor device. This epitaxial structure can be a novel HBT epitaxial structure, and can be fabricated using the following methods:

[0035] On a silicon (Si) substrate, an n-type doped gallium nitride (n-GaN) current collector layer, a p-type doped GaAs (p-GaAs) base layer, and an n-type doped aluminum gallium arsenide (n-AlGaAs) emitter layer are sequentially epitaxially formed, such as... Figure 2 As shown.

[0036] Specifically, GaN-based materials may include at least one of GaN, aluminum gallium nitride (AlGaN), and indium gallium nitride (InGaN).

[0037] It should be noted that using GaN-based materials as the current collector layer of GaAs HBTs has the following advantages:

[0038] 1) The bandgap of GaN-based materials can be 3.4 eV;

[0039] Therefore, GaN-based materials have a larger bandgap compared to GaAs.

[0040] 2) The breakdown electric field strength of GaN-based materials can be 3.3 MV / cm.

[0041] Therefore, GaN-based materials have a larger breakdown voltage compared to GaAs.

[0042] Combining the above advantages, this application proposes an epitaxial structure for a compound semiconductor device, specifically a novel epitaxial structure for high-temperature bismuth (HBT). This structure involves fabricating the epitaxial layer of the material on a Si substrate, allowing the use of large-size silicon wafers to reduce chip manufacturing costs. Furthermore, the application of Si substrates will significantly reduce the consumption of GaAs substrate material, greatly mitigating the environmental pollution risks posed by As.

[0043] Meanwhile, in practical applications of HBT devices with the new epitaxial structure of HBT, the use of GaN-based materials as the collector layer allows for the use of higher operating voltages, which in turn helps to increase the output power of the HBT device, overcome the power limitations of GaAs HBT devices, and better meet the high frequency and high power requirements of 5G communication.

[0044] In some possible implementations, the epitaxial structure of the novel HBT of this application, in addition to the above... Figure 2 As shown, there may also be several variant structures, where the various epitaxially grown thin film layers (such as the emitter layer, base layer, and current collector layer) are made of different materials than those described above, as follows:

[0045] 1) In addition to AlGaAs, other single materials such as InGaAs and InGaP can also be used when preparing the emitter layer.

[0046] For example, on a GaAs substrate, an n-type doped InGaAs (or n-type doped InGaP) emitter layer, a p-type doped GaAs base layer, and an n-type doped GaN-based current collector layer are epitaxially grown sequentially.

[0047] 2) Two or more materials can be used when preparing the emitter layer.

[0048] For example, at least two of AlGaAs, InGaAs, and InGaP are used to prepare the emitter layer.

[0049] In some possible implementations, the epitaxial structure of the novel HBT of this application, in addition to the above... Figure 2 As shown, there may be other structures used to enhance device performance, yield and reliability, such as buffer layers, sub-collectors, grading layers, spacers, cap layers, etc.

[0050] For simplicity, the following introduction to the fabrication of the epitaxial structure of the new HBT and the fabrication method of the new HBT device will use [the following text is incomplete and likely refers to a different topic] as the main text. Figure 2 Taking the shown epitaxial structure as an example, the other various variant structures can be understood in the same way, and all of them are within the scope of protection claimed in this application, so they will not be described in detail here.

[0051] I. Epitaxial Structure Fabrication Methods for Compound Semiconductor Devices

[0052] It should be noted that the epitaxial structure of a compound semiconductor device can be a new type of HBT epitaxial structure.

[0053] Please see Figure 3 , Figure 3 This is a schematic flowchart of the method for fabricating the epitaxial structure of a compound semiconductor device according to an embodiment of this application. The specific steps are as follows:

[0054] S310. An n-type doped gallium nitride (GaN) collector layer is epitaxially formed on a silicon (Si) substrate.

[0055] It should be noted that this current collector layer can be prepared by various methods, such as MBE (molecular beam epitaxy), HVPE (hydride vapor phase epitaxy), and MOCVD (metal-organic chemical vapor deposition).

[0056] MOCVD utilizes H2 or N2 as the carrier gas, which carries MO source (such as Ga(CH3)3) and hydride (such as NH3) and other reactants into the mixing chamber through multiple channels, diffuses to the substrate surface, and reacts to generate a single-crystal GaN thin film.

[0057] Specifically, the thickness of the current collector layer can be 500nm-2000nm.

[0058] In addition, in order to form n-type doping, the doping element used can be at least one of Si, C, Ge, etc.

[0059] The most common method is Si doping, which is usually done by adding silane (SiH4) during the MOCVD process to participate in the reaction and complete the doping. The doping concentration can be between 1E17 cm-3 and 1E19 cm-3.

[0060] In some possible implementations, a transition layer and an n-type doped gallium nitride (GaN)-based collector layer are sequentially epitaxially formed on a silicon (Si) substrate.

[0061] It should be noted that when fabricating a GaN-based current collector layer on a Si substrate, the difference in lattice constant and thermal expansion coefficient between GaN and the Si substrate causes attraction during epitaxial growth, leading to defects such as lattice dislocations, wafer warping, and cracking. Therefore, before fabricating this current collector layer, it is usually necessary to prepare some transition layers to absorb stress and achieve lattice matching.

[0062] Specifically, the transition layer may include various structures such as nucleation layers, buffer layers, transition layers, and superlattice layers, or combinations thereof.

[0063] Specifically, the material of the transition layer can be AlN, AlGaN, or other nitrides.

[0064] Specifically, the thickness of this transition layer can range from 0.5 to 2 μm, without any specific limitation. For example, such as... Figure 4 As shown, a transition layer and an n-type doped gallium nitride (GaN) (n-GaN)-based current collector layer are sequentially epitaxially formed on a Si substrate.

[0065] S320. A p-type doped gallium arsenide (GaAs) base layer is epitaxially formed on the collector layer.

[0066] It should be noted that growing GaAs thin films on GaN-based materials, i.e. preparing p-type doped GaAs (p-GaAs) base layers, can be achieved using Gas-Source Molecular Beam Epitaxy (GSMBE). A diethyl arsine (DEA) molecular beam is injected into a vacuum reaction chamber, and solid potassium (Ga) is produced from an evaporation source. GaAs is generated through reaction in a chamber at a reaction temperature of 600℃-800℃, thus forming the base layer.

[0067] Alternatively, the base layer can be prepared in two steps: first, a GaAs thin film is grown on the upper surface of the current collector layer using the GSMBE method as a seed layer, and then the GaAs thin film is grown to the designed base layer thickness using MOCVD (organic metal chemical vapor deposition).

[0068] Specifically, the thickness of the base layer can be 50-150nm.

[0069] In addition, in order to form p-type doping, the doping element used can be at least one of Be, Mg, Zn, Cd, Hg, etc., or at least one of C, Si, Ge, Sn, etc., and the doping concentration can be between 1E18 cm-3 and 1E20 cm-3.

[0070] In some possible implementations, a transition layer, an n-type doped gallium nitride (GaN) current collector layer, and a p-type doped GaAs (p-GaAs) base layer are sequentially epitaxially formed on a Si substrate, such as... Figure 5 As shown.

[0071] S330, an n-type doped aluminum gallium arsenide (n-AlGaAs) emitter layer is epitaxially formed on the base layer.

[0072] It should be noted that there are various methods for growing an n-type doped aluminum gallium arsenide (n-AlGaAs) emitter layer on the upper surface of the p-GaAs base layer, such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), and hydride vapor phase epitaxy (HVPE).

[0073] Trimethylgallium (TMG) can be the source of Ga, trimethylaluminium (TMA) can be the source of Al, and arsenic (AsH3) can be the source of As. The reaction temperature can be between 600℃ and 800℃, and the growth rate can be between 400A / min and 1000A / min.

[0074] Specifically, the thickness of the AlGaAs emitter layer can be 50-500 nm.

[0075] In addition, in order to form n-type doping, the doping element used can be at least one of O, S, Se, Te, etc., or at least one of C, Si, Ge, Sn, etc., and the doping concentration can be between 1E17 cm⁻³ and 1E20 cm⁻³.

[0076] In some possible implementations, a transition layer, an n-type doped gallium nitride (GaN) current collector layer, a p-type doped GaAs (p-GaAs) base layer, and an n-type doped aluminum gallium arsenide (AlGaAs) emitter layer are sequentially epitaxially formed on a Si substrate, such as... Figure 6 As shown.

[0077] II. The novel HBT device fabrication method of this application

[0078] 1. Fabrication of the emitter:

[0079] a) Photolithography process

[0080] It should be noted that the photolithography process can include coating, alignment, and development. For example... Figure 7 As shown in (a), photoresist is prepared on the upper surface of the n-AlGaAs emitter layer.

[0081] Additionally, it should be noted that, Figure 7 In (a), no transition layer is deposited. Examples of embodiments of this application, in conjunction with the above description, can be obtained corresponding to the deposition of a transition layer, and all are within the scope of protection claimed in this application; further details will not be provided.

[0082] b) Fabrication of emitter metal layer

[0083] It should be noted that the emitter metal layer can be prepared by sputtering or evaporation.

[0084] For example, such as Figure 7 As shown in (b), the emitter metal layer is prepared in the photoresist by sputtering and evaporation.

[0085] Specifically, the emitter metal layer can be composed of two or more metals, such as Ni / Au, AuGe / Ti / Au, Ti / Pt / Au, and the thickness can be 10-40nm for Ti, 50-200nm for Pt, and 100-300nm for Au.

[0086] It should be noted that, Figure 7 In (b), no transition layer is deposited. Examples of transition layers can be obtained by referring to the above description in the embodiments of this application, which will not be elaborated further.

[0087] c) Degumming and Cleaning

[0088] For example, such as Figure 7 As shown in (c), an emitter is prepared on the upper surface of the n-AlGaAs emitter layer by desizing and cleaning.

[0089] It should be noted that, Figure 7 In (c), no transition layer is deposited. Examples of transition layer deposits can be obtained by referring to the above description in the embodiments of this application, which will not be elaborated further.

[0090] d) Optionally, a first passivation layer is prepared.

[0091] It should be noted that a first passivation layer can also be fabricated to protect the emitter. This first passivation layer is essentially a passivation layer used to protect the emitter; other terms can also be used to describe it, and no specific restrictions are placed on this.

[0092] For example, such as Figure 7 As shown in (d), a first passivation layer is deposited on the upper surface of the n-AlGaAs emitter layer and on the emitter.

[0093] It should be noted that, Figure 7 In (d), no transition layer is deposited. Examples of transition layers can be obtained by referring to the above description in the embodiments of this application, which will not be elaborated further.

[0094] Specifically, the first passivation layer can be SiN. x , SiO2, Al2O3, AlN, AlON, SiO x N y A single-layer or multi-layer structure composed of at least one of the following materials: HfO2 and Ga2O3.

[0095] Specifically, the thickness of the first passivation layer can be 100-200 nm.

[0096] 2. Base fabrication

[0097] a) Photolithography process

[0098] It should be noted that the photolithography process can include coating, alignment, and development.

[0099] For example, such as Figure 8 As shown in (a), photoresist is prepared on the upper surface of the first passivation layer.

[0100] Additionally, it should be noted that, Figure 8 In (a), no transition layer is deposited. Examples of this application with a deposited transition layer can be obtained by referring to the above description; further details are omitted here.

[0101] b) Etching process

[0102] It should be noted that the etching process can be performed on both the first passivation layer and the n-AlGaAs emitter layer.

[0103] For example, such as Figure 8 As shown in (b), the first passivation layer and the n-AlGaAs emission layer are etched using photoresist as a mask.

[0104] Additionally, it should be noted that, Figure 8 In (b), no transition layer is deposited. Examples of transition layers can be obtained by referring to the above description in the embodiments of this application, which will not be elaborated further.

[0105] Specifically, the first passivation layer can be etched using a dry etching method. Various gases can be used to etch the first passivation layer, such as CF4, CHF3, and SF6.

[0106] Specifically, the etcher layer can be etched using either wet or dry etching processes. Wet etching is performed in an aqueous solution of phosphoric acid (H3PO4) and acidic oxygen water (H2O2). Dry etching employs plasma etching, commonly using gases such as Cl2, BCl3, SiCl4, CF4, and CCl2F2. The desired etching result is achieved by controlling the microwave power, intracavitary pressure, gas type, and flow rate within the reaction chamber.

[0107] In addition, to reduce damage to the emitter layer, atomic layer etching (ALE) can be used when etching the emitter layer, or the etching rate can be reduced by adjusting the process parameters.

[0108] After etching is complete, resist removal and wafer cleaning can be performed.

[0109] c) Base metal layer fabrication

[0110] It should be noted that the base metal layer can be prepared by sputtering and evaporation.

[0111] For example, such as Figure 8 As shown in (c), the base metal layer is prepared by sputtering and evaporation.

[0112] Specifically, the base metal layer can be composed of two or more metals, such as Ti / Au, Ti / Pt / Ti / Au, and the thickness can be 10-40nm for Ti, 50-200nm for Pt, and 100-300nm for Au.

[0113] It should be noted that, Figure 8 In (c), no transition layer is deposited. Examples of transition layer deposits can be obtained by referring to the above description in the embodiments of this application, which will not be elaborated further.

[0114] d) De-adhesive removal and cleaning.

[0115] e) Optionally, a second passivation layer is prepared.

[0116] It should be noted that a second passivation layer can also be fabricated to protect the base. This second passivation layer is essentially a passivation layer used to protect the base, but other terms can be used to describe it; no specific restrictions are placed on this.

[0117] For example, such as Figure 8 As shown in (d), a second passivation layer is deposited on the upper surface of the base, the upper surface of the first passivation layer, and the upper surface of the p-GaAs base layer.

[0118] Additionally, it should be noted that, Figure 8 In (d), no transition layer is deposited. Examples of transition layers can be obtained by referring to the above description in the embodiments of this application, which will not be elaborated further.

[0119] Specifically, the second passivation layer can be SiN. x , SiO2, Al2O3, AlN, AlON, SiO x N y A single-layer or multi-layer structure composed of at least one of the following materials: HfO2 and Ga2O3.

[0120] Specifically, the thickness of the second passivation layer can be 100-200 nm.

[0121] 3. Fabrication of the collector

[0122] a) Photolithography process

[0123] It should be noted that the photolithography process can include coating, alignment, and development.

[0124] For example, such as Figure 9 As shown in (a), photoresist is prepared on the upper surface of the second passivation layer.

[0125] Additionally, it should be noted that, Figure 9 In (a), no transition layer is deposited. Examples of this application with a deposited transition layer can be obtained by referring to the above description; further details are omitted here.

[0126] b) Etching process

[0127] It should be noted that the etching process can be used to etch the second passivation layer and the p-GaAs base layer.

[0128] For example, such as Figure 9 As shown in (b), the second passivation layer and the p-GaAs base layer are etched using photoresist as a mask.

[0129] Additionally, it should be noted that, Figure 9 In (b), no transition layer is deposited. Examples of transition layers can be obtained by referring to the above description in the embodiments of this application, which will not be elaborated further.

[0130] Specifically, the second passivation layer is etched using a dry etching method. Various gases can be used to etch the second passivation layer, such as CF4, CHF3, and SF6.

[0131] Specifically, the etching of the p-GaAs base layer can be performed using either wet or dry etching processes. Wet etching is carried out in an aqueous solution of phosphoric acid (H3PO4) and acidic oxygen water (H2O2). Dry etching employs plasma etching technology, commonly using gases such as Cl2, BCl3, SiCl4, CF4, and CCl2F2. The desired etching result is achieved by controlling the microwave power, intracavitary pressure, gas type, and flow rate within the reaction chamber.

[0132] In addition, to reduce damage to the base layer, atomic layer etching (ALE) can be used when dry etching the base layer, or the etching rate can be reduced by adjusting the process parameters.

[0133] After etching is complete, resist removal and wafer cleaning can be performed.

[0134] c) Fabrication of the current collector metal layer

[0135] It should be noted that the collector metal layer can be prepared by sputtering and evaporation.

[0136] Specifically, the collector metal layer can be composed of two or more metals, such as Ti / Al / Ti / Au, and the thickness can be 10-40nm for Ti, 100-300nm for Al, and 100-300nm for Au.

[0137] d) Degumming and cleaning

[0138] e) Optionally, prepare a third passivation layer.

[0139] It should be noted that a third passivation layer can also be fabricated to protect the collector. This third passivation layer is essentially a passivation layer used to protect the collector, and other terms can be used to describe it; no specific limitation is made.

[0140] For example, such as Figure 9 As shown in (c), a third passivation layer is deposited on the upper surface of the collector and the upper surface of the second passivation layer.

[0141] Specifically, the third passivation layer can be SiN. x , SiO2, Al2O3, AlN, AlON, SiO x N y A single-layer or multi-layer structure composed of at least one of the following materials: HfO2 and Ga2O3.

[0142] Specifically, the thickness of the third passivation layer can be 100-200 nm.

[0143] 4. Other frontside processes

[0144] For the front-side fabrication of new HBT devices, in addition to the fabrication of the emitter, base, and collector, other processes may also be included, such as intermetallic dielectric layers, via etching, and metal interconnects. Figure 10 As shown.

[0145] Specifically, the intermetallic dielectric layer can be silicon oxide, silicon nitride, or polyimide, etc.

[0146] Specifically, the metal interconnects can be Au, Cu, Al, etc.

[0147] Finally, a passivation layer (Final Passivation), also known as the fourth passivation layer, is created. While the fourth passivation layer is essentially a passivation layer, other terms can also be used to describe it; no specific restrictions are placed on this.

[0148] Specifically, the fourth passivation layer can be silicon oxide, silicon nitride, polyimide, benzocyclobutene (BCB), etc.

[0149] For example, a schematic diagram of an HBT device after the front-side process is completed, such as... Figure 10 As shown.

[0150] It should be noted that, Figure 10 No transition layer was deposited in the middle. The embodiments of this application can be combined with the above description to obtain illustrations corresponding to the deposition of a transition layer, which will not be elaborated further.

[0151] 5. Optionally, capacitors, resistors, and inductors can be fabricated.

[0152] It should be noted that, in the embodiments of this application, while fabricating the new HBT device, capacitors, resistors, and inductors can also be fabricated to form a monolithic microwave integrated circuit (MMIC) circuit, which can be used as an internal matching circuit, an input / output matching circuit, or an LC filter, such as... Figure 11 As shown.

[0153] In addition, Figure 11 In the devices shown, the number of capacitors, resistors, and inductors in this application embodiment is not limited.

[0154] It should be noted that, Figure 11 In the middle, no transition layer is deposited. The embodiments of this application can be combined with the above description to obtain the corresponding illustrations where a transition layer is deposited, which will not be elaborated further.

[0155] Specifically, an inductor can be made by winding a metal coil, which can be square, round, or other shapes. The metal electrode material of the inductor can be made of Au, Al, Cu, Fe, Ni, or alloys.

[0156] Specifically, capacitors can employ a MIM (metal-dielectric-metal) structure. The shapes of these capacitors are also diverse, such as square and rectangular. The capacitor dielectric can be silicon nitride, silicon oxide, or other dielectric materials. The metal electrode materials of the capacitor can be Au, Al, Cu, or other metals or alloys. The thickness of the dielectric and metal, as well as the size and shape of the capacitor, can be determined by the specific application and design.

[0157] Specifically, the resistor can be a thin film resistor (TFR). There are various methods for its fabrication, such as etching and metal stripping. The etching method is explained below:

[0158] 1) Fabrication of thin film resistive layer

[0159] It should be noted that the embodiments of this application can be prepared by vacuum evaporation, sputtering or chemical deposition.

[0160] 2) Perform adhesive application, alignment, exposure, and development.

[0161] 3) Thin-film resistive etching

[0162] It should be noted that the materials used for thin-film resistors include Ni-Co, Ta, Si, cermet, and Au-Cr and Ni-P resistive films. For example, NiCr and TaN are also possible materials.

[0163] 4) Remove glue and clean

[0164] 6. Backside Process:

[0165] It should be noted that after the front-side process of the new HBT device is completed, the back-side process can be performed in this embodiment. The back-side process may include the following steps:

[0166] 1) Bond the wafer to a carrier, such as a sapphire or silicon wafer.

[0167] It should be noted that wafer bonding technology refers to the physical bonding of a device wafer onto a carrier for the implementation of back-side wafer processing.

[0168] 2) Thinning and polishing

[0169] It should be noted that the thickness of the thinned wafer can be 50-150um.

[0170] 3) Backside via photolithography

[0171] It should be noted that back-hole photolithography can include processes such as coating, alignment, exposure, and development.

[0172] 4) Back hole etching

[0173] It should be noted that back hole etching can be performed using plasma etching technology, and commonly used gases include Cl2, BCl3, SiCl4, CF4, CCl2F2, etc.

[0174] To obtain vias with good morphology, the Bosch etching method can be used, in which the entire etching process involves alternating etching and deposition steps. The etching step uses SF6 as the etching gas, and the deposition step uses C4F8 as the deposition gas, which deposits a polymer protective film on the silicon via sidewalls to protect them from etching.

[0175] 5) Back hole metallization

[0176] It should be noted that the metallization process may include the sputtering of a seed layer, typically Ti or TiW, with a thickness of 5-50 nm.

[0177] When making metallic conductors, metals such as Al, Cu, and Au can be used, and processes such as vapor deposition or electroplating can be employed, with a thickness ranging from 2 to 10 μm.

[0178] 6) Wafer debonding, cleaning, and testing.

[0179] For example, HBT devices after back-side processing, such as Figure 12 As shown. The Si substrate needs to be thinned, and back vias are made on the thinned Si substrate and the emitter layer, as well as a back metal layer is deposited.

[0180] It should be noted that, Figure 12 No transition layer was deposited in the middle. The embodiments of this application can be combined with the above description to obtain illustrations corresponding to the deposition of a transition layer, which will not be elaborated further.

[0181] In addition, the novel HBT device of this application embodiment can be used to design and fabricate a radio frequency power amplifier (PA). In addition to having excellent frequency performance, the radio frequency power amplifier can be used at higher operating voltages to meet higher power requirements and will greatly reduce the consumption of gallium arsenide substrate material, thus greatly reducing the risk of arsenic pollution to the environment.

[0182] For example, such as Figure 13 As shown, the RF power amplifier may include an input matching module for the input signal, an HBT transistor module, a bias and stabilization circuit module, and an output matching module for the output signal. The input matching module, HBT transistor module, and output matching module are connected in sequence, and the stabilization circuit module is connected to the HBT transistor module.

[0183] Furthermore, it should be noted that, for the sake of simplicity, the above-described method embodiments are all presented as a series of actions. Those skilled in the art should understand that this application is not limited to the described order of actions, as some steps in the embodiments of this application can be performed in other orders or simultaneously. In addition, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of this application.

[0184] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0185] The embodiments of this application have been described in detail above. The descriptions in the embodiments of this application are only for the purpose of helping to understand the method and core ideas of this application. Those skilled in the art should know that there may be changes in the specific implementation methods and application scope of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating the epitaxial structure of a compound semiconductor device, characterized in that, include: An n-type doped gallium nitride (GaN) collector layer is epitaxially formed on a silicon (Si) substrate; A p-type doped gallium arsenide (GaAs) base layer is epitaxially formed on the current collector layer; An n-type doped aluminum gallium arsenide (AlGaAs) emitter layer is epitaxially formed on the base layer; A first photoresist is prepared on the upper surface of the emission layer, an emission electrode metal layer is prepared in the first photoresist, the first photoresist is removed to obtain an emission electrode, the emission electrode is located on the upper surface of the emission layer, and a first passivation layer is deposited on the upper surface of the emission layer and the emission electrode. A second photoresist is prepared on the upper surface of the first passivation layer, and the second photoresist covers the emitter. Using the second photoresist as a mask, the first passivation layer and the emitter layer are etched to expose the base layer. The second photoresist is removed, and a third photoresist is prepared on the upper surface of the exposed base layer. A base metal layer is prepared in the third photoresist, and the third photoresist is removed to obtain the base. The base is located on the upper surface of the exposed base layer. A second passivation layer is deposited on the upper surface of the base, the upper surface of the first passivation layer, and the upper surface of the base layer. A fourth photoresist is prepared on the upper surface of the second passivation layer, the fourth photoresist covering the base electrode. Using the fourth photoresist as a mask, the second passivation layer and the base electrode layer are etched to expose the current collector layer. The fourth photoresist is removed, and a fifth photoresist is prepared on the upper surface of the exposed current collector layer. A current collector metal layer is prepared in the fifth photoresist, and the fifth photoresist is removed to obtain the current collector. A third passivation layer is deposited on the upper surface of the current collector and the upper surface of the second passivation layer. An intermetallic dielectric layer is prepared on the upper surface of the third passivation layer, and a fourth passivation layer is prepared on the upper surface of the intermetallic dielectric layer to obtain a heterojunction bipolar transistor device.

2. The method according to claim 1, characterized in that, The bandgap of the GaN-based material is 3.4e; the electric field strength of the GaN-based material is 3.3 MV / cm.

3. The method according to claim 1, characterized in that, The GaN-based material includes at least one of GaN, aluminum gallium nitride (AlGaN), and indium gallium nitride (InGaN).

4. The method according to claim 1, characterized in that, The doping element used to epitaxially form the current collector layer is at least one of Si, C, and Ge; The doping concentration used to epitaxially form the current collector layer is between 1E17 cm⁻³ and 1E19 cm⁻³.

5. The method according to claim 1, characterized in that, The Al in the AlGaAs used to epitaxially form the emitter layer is provided by trimethylaluminum; The Ga in the AlGaAs used to epitaxially form the emitter layer is provided by trimethylgallium; The As in the AlGaAs used to epitaxially form the emitter layer is provided by arsine; The reaction temperature used to epitaxially form the emitter layer is between 600°C and 800°C; The growth rate used to epitaxially form the emitter layer is between 400 A / min and 1000 A / min; The doping element used to epitaxially form the emitter layer is at least one of O, S, Se, and Te, or the doping element used to epitaxially form the emitter layer is at least one of C, Si, Ge, and Sn; The doping concentration used to epitaxially form the emitter layer is between 1E17 cm⁻³ and 1E20 cm⁻³.

6. The method according to claim 1, characterized in that, The Al in the GaAs used to epitaxially form the base layer is provided by trimethylaluminum; The doping element used to epitaxially form the base layer is at least one of Be, Mg, Zn, Cd, and Hg, or the doping element used to epitaxially form the base layer is at least one of C, Si, Ge, and Sn. The doping concentration used to epitaxially form the base layer is between 1E18 cm⁻³ and 1E20 cm⁻³.

7. The method according to claim 1, characterized in that, The thickness of the current collector layer is 500nm-2000nm; The thickness of the base layer is 50-150 nm; The thickness of the emission layer is 50-500 nm.

8. The method according to claim 1, characterized in that, Also includes: The heterojunction bipolar transistor device is subjected to back-side processing.

9. An epitaxial structure for a compound semiconductor device, characterized in that, include: The structure comprises a silicon (Si) substrate, an n-type doped gallium nitride (GaN) current collector layer, a p-type doped gallium arsenide (GaAs) base layer, and an n-type doped aluminum gallium arsenide (AlGaAs) emitter layer; among which, The current collector layer, the base layer, and the emitter layer are arranged sequentially from bottom to top on the upper surface of the substrate; The epitaxial structure is used to fabricate a heterojunction bipolar transistor device, and the fabrication method of the heterojunction bipolar transistor device includes: A first photoresist is prepared on the upper surface of the emission layer, an emission electrode metal layer is prepared in the first photoresist, the first photoresist is removed to obtain an emission electrode, the emission electrode is located on the upper surface of the emission layer, and a first passivation layer is deposited on the upper surface of the emission layer and the emission electrode. A second photoresist is prepared on the upper surface of the first passivation layer, and the second photoresist covers the emitter. Using the second photoresist as a mask, the first passivation layer and the emitter layer are etched to expose the base layer. The second photoresist is removed, and a third photoresist is prepared on the upper surface of the exposed base layer. A base metal layer is prepared in the third photoresist, and the third photoresist is removed to obtain the base. The base is located on the upper surface of the exposed base layer. A second passivation layer is deposited on the upper surface of the base, the upper surface of the first passivation layer, and the upper surface of the base layer. A fourth photoresist is prepared on the upper surface of the second passivation layer, the fourth photoresist covering the base electrode. Using the fourth photoresist as a mask, the second passivation layer and the base electrode layer are etched to expose the current collector layer. The fourth photoresist is removed, and a fifth photoresist is prepared on the upper surface of the exposed current collector layer. A current collector metal layer is prepared in the fifth photoresist, and the fifth photoresist is removed to obtain the current collector. A third passivation layer is deposited on the upper surface of the current collector and the upper surface of the second passivation layer. An intermetallic dielectric layer is prepared on the upper surface of the third passivation layer, and a fourth passivation layer is prepared on the upper surface of the intermetallic dielectric layer to obtain a heterojunction bipolar transistor device.

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