Charge pump circuit

Abstract

The present invention provides a charge pump circuit. This charge pump circuit includes: a switch module that receives an input voltage and a switching signal and outputs an output voltage; a linear frequency adjustment module that receives and detects the output voltage of the switch module, performs frequency adjustment and duty cycle fixation according to the output voltage, and has a maximum and minimum frequency limit; and a control module that receives the signal output by the linear frequency adjustment module and generates a switching signal.

Description

Technical Field

[0001] The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit that adjusts the fixed duty cycle and frequency according to the output voltage, and is provided with the highest and lowest frequencies to avoid generating noise or interfering with other signals, and can improve the execution efficiency at light load and maintain the execution efficiency at heavy load. Background Art

[0002] The source driver of a conventional organic light emitting diode display panel (e.g., an AMOLED display panel) usually has a built-in charge pump. A charge pump is a DC-DC converter that uses a capacitor as an energy storage element, and is mostly used to generate an output voltage larger than the input voltage or to generate a negative output voltage. The charge pump in the prior art determines the number of pulses of the fixed clock to be skipped according to the sensed output current and voltage to improve the light load efficiency and maintain the heavy load performance, but it will encounter large ripples due to the back-and-forth oscillation at the boundary of the pulse skip number, which will cause uneven brightness and color on the display screen. Summary of the Invention

[0003] Therefore, the present invention provides a charge pump circuit that mainly adjusts the fixed duty cycle and frequency according to the output voltage to improve the execution efficiency at light load and maintain the execution efficiency at heavy load of the charge pump circuit. In addition, the charge pump circuit of the present invention is a linear frequency adjustment without using the pulses of a fixed clock, so there will be no problem of large output ripple caused by back-and-forth oscillation at the boundary.

[0004] An embodiment of the present invention provides a charge pump circuit, including: a switch module that receives an input voltage and a switch signal and outputs an output voltage; a linear frequency adjustment module that receives and detects the output voltage of the switch module, adjusts the frequency according to the output voltage and fixes the duty cycle, and is provided with the highest and lowest frequency limits; and a control module that receives the signal output by the linear frequency adjustment module and generates a switch signal.

[0005] In an embodiment, the linear frequency adjustment module further includes: a frequency generation circuit coupled to the control module for generating a frequency; a frequency adjustment circuit coupled to the control module for determining the maximum and minimum frequencies; and a duty cycle fixing circuit coupled to the control module for generating a fixed duty cycle.

[0006] In one embodiment, the frequency generation circuit further includes: a first resistor for receiving an output voltage; a second resistor connected to the first resistor, wherein a voltage division voltage exists between the first and second resistors; and a first comparator having a first input terminal, a second input terminal, and a first output terminal. The first input terminal is connected between the first resistor and the second resistor, the second input terminal has a first input comparison signal, and the first output terminal is connected to a control module. The first input terminal receives the voltage division voltage, and the second input terminal receives the first input comparison signal to output a first output signal. When the voltage division voltage rises to be the same as the first input comparison signal, the first output signal changes state.

[0007] In one embodiment, the frequency adjustment circuit further includes: a first current source; a third resistor connected to the first current source; a first capacitor, one end of which is connected between the first current source and the third resistor; a second comparator having a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is coupled to the first capacitor, and its output terminal is connected to the control module. The third input terminal receives a first charge and discharge signal, and the fourth input terminal receives a second input comparison signal to output a second output signal. When the voltage signal of the first capacitor is the same as the second input comparison signal, the second output signal changes state to determine the maximum frequency; and a third comparator having a fifth input terminal, a sixth input terminal, and a third output terminal. The fifth input terminal is coupled to the first capacitor, and the third output terminal is connected to the control module. The fifth input terminal receives the voltage signal of the first capacitor, and the sixth input terminal receives a third input comparison signal to output a third output signal. When the voltage signal of the first capacitor is the same as the third input comparison signal, the third output signal changes state to determine the minimum frequency.

[0008] In one embodiment, the duty cycle fixed circuit further includes: a second current source; a third current source connected to the second current source; a second capacitor, one end of which is connected between the second current source and the third current source; and a fourth comparator having a seventh input terminal, an eighth input terminal, and a fourth output terminal. The seventh input terminal is connected to this end of the second capacitor, and its fourth output terminal is connected to the control module. The seventh input terminal receives the voltage signal of the second capacitor, and the eighth input terminal receives a fourth input comparison signal to output a fourth output signal; wherein the fixed duty cycle is determined by the second current source and the third current source.

[0009] In one embodiment, the switching module further includes: a first switch, a second switch, a third switch, and a fourth switch. The first switch and the fourth switch are connected in series with each other, and the second switch and the third switch are connected in series with each other. The first switch is coupled to an input voltage, and the second switch is coupled to a ground voltage. The third switch is coupled to an output voltage, and the fourth switch is coupled to a ground voltage; and a third capacitor, one end of which is coupled between the first switch and the fourth switch, and the other end of which is coupled between the second switch and the third switch.

[0010] For a further understanding of the features and technical content of the present invention, please refer to the following detailed description of the present invention and the attached drawings. However, the attached drawings are only for reference and illustration, and are not intended to limit the present invention. Description of the Drawings

[0011] Figure 1 Shows a charge pump circuit according to an embodiment of the present invention.

[0012] Figure 2 Shows Figure 1 a schematic internal structure diagram of the linear frequency adjustment circuit in

[0013] Figure 3 Shows Figure 1 a schematic internal structure diagram of the switch module in

[0014] Figure 4A Shows an operation waveform diagram of the charge pump circuit according to the present invention.

[0015] Figure 4B Shows Figure 4A a schematic diagram of the relationship between frequency and load in

[0016] Description of the Main Component Symbols:

[0017] 11 Switch module

[0018] 12 Linear frequency adjustment module

[0019] 13 Control module

[0020] 121 Frequency generation circuit

[0021] 122 Frequency adjustment circuit

[0022] 123 Duty cycle fixed circuit

[0023] COM1, COM2, COM3, COM4 Comparators

[0024] SW1, SW2, SW3, SW4 Switches

[0025] Vin, Vout, Vdiv1, Vref0 Voltages

[0026] Vref1, Vref2, Vref3, Vref4, Vsaw1, Vsaw2, Vcom1, Vcom2, Vcom3, Vcom4 Signals

[0027] C1, C2, C3 Capacitors Detailed Embodiments

[0028] Figure 1Displays a charge pump circuit according to an embodiment of the present invention. As Figure 1 shown, the charge pump circuit 1 includes: a switch module 11, a linear frequency adjustment module 12, and a control module 13. The switch module 11 receives an input voltage Vin and outputs an output voltage Vout. The linear frequency adjustment module 12 is connected to the switch module 11, receives and detects the output voltage Vout, adjusts the frequency and fixes the duty cycle according to the output voltage Vout, thereby determining the maximum frequency and the minimum frequency, and has the highest and lowest frequency limits, and the control module 13 is connected to the linear frequency adjustment module 12, receives the signal output by the linear frequency adjustment module 12 and generates a switching signal, thereby controlling the switch module 11.

[0029] Figure 2 Displays Figure 1 the internal structure schematic diagram of the linear frequency adjustment circuit in Figure 2 shown. As

[0030] shown, the linear frequency adjustment module 12 further includes: a frequency generation circuit 121, a frequency adjustment circuit 122, and a duty cycle fixing circuit 123. The frequency generation circuit 121 is coupled to the control module 13 for generating a frequency. The frequency adjustment circuit 122 is coupled to the control module 13 for determining the maximum and minimum frequencies, and the duty cycle fixing circuit 123 is coupled to the control module 13 for generating a fixed duty cycle. Figure 2 shown, the frequency generation circuit 121 further includes: a first resistor R1 receives the output voltage Vout, one end of a second resistor R2 is connected to the first resistor R1, and the other end is connected to a reference voltage Vref0. There is a voltage division voltage Vdiv1 between the first and second resistors, and a first comparator COM1 has a first input terminal a, a second input terminal b, and a first output terminal c. The first input terminal a is connected between the first resistor R1 and the second resistor R2. The second input terminal b has a first input comparison signal Vref1. The first output terminal c is connected to the control module 13. The first input terminal a receives the voltage division voltage Vdiv1, and the second input terminal b receives the first input comparison signal Vref1 to output a first output signal Vcom1. Among them, the voltage division voltage Vdiv1 rises to be the same as the first input comparison signal Vref1 and causes the first output signal Vcom1 to change state.

[0031] As Figure 2As shown, the frequency adjustment circuit 122 further includes: a first current I1; a third resistor R3 connected to the first current source I1; a first capacitor C1, one end of which is connected between the first current I1 and the third resistor R3; a second comparator COM2 having a third input terminal d, a fourth input terminal e, and a second output terminal f, the third input terminal d being coupled to the first capacitor C1, its second output terminal f being connected to the control module 13, the third input terminal d receiving a first capacitor voltage signal Vsaw1, the fourth input terminal e receiving a second input comparison signal Vref2 to output a second output signal Vcom2, wherein when the first capacitor voltage signal Vsaw1 is the same as the second input comparison signal Vref2, the second output signal Vcom2 will change state to determine the maximum frequency; and a third comparator COM3 having a fifth input terminal g, a sixth input terminal h, and a third output terminal i, the fifth input terminal g being coupled to the first capacitor C1, the third output terminal i being connected to the control module 13, wherein the fifth input terminal g receives the first capacitor voltage signal Vsaw1, the sixth input terminal h receives a third input comparison signal Vref3 to output a third output signal Vcom3, wherein when the first capacitor voltage signal Vsaw1 is the same as the third input comparison signal Vref3, the third output signal Vcom3 will change state to determine the minimum frequency.

[0032] As Figure 2 shown, the duty cycle fixed circuit 123 further includes: a second current I2; a third current I3 connected to the second current I2; a second capacitor C2, one end of which is connected between the second current I2 and the third current I3; and a fourth comparator COM4 having a seventh input terminal j, an eighth input terminal k, and a fourth output terminal l, the seventh input terminal j being connected to this end of the second capacitor C2, its fourth output terminal l being connected to the control module 13, wherein the seventh input terminal j receives a second capacitor voltage signal Vsaw2, the eighth input terminal k receives a fourth input comparison signal Vref4 to output a fourth output signal Vcom4. In particular, the fixed duty cycle is determined by the second current I2 and the third current I3.

[0033] Figure 3 Show Figure 1 the internal structure schematic diagram of the switch module 11 in. As Figure 3As shown, the switch module 11 further includes: a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4. Among them, the first switch SW1 and the fourth switch SW4 are connected in series with each other, and the second switch SW2 and the third switch SW3 are connected in series with each other. The first switch SW1 is coupled to the input voltage Vin, and the second switch SW2 is coupled to the ground voltage GND. The third switch SW3 is coupled to the output voltage Vout, and the fourth switch SW4 is coupled to the ground voltage GND; and a third capacitor C3, one end of the third capacitor C3 is coupled between the first switch SW1 and the fourth switch SW4, and the other end is coupled between the second switch SW2 and the third switch SW3.

[0034] Figure 4A Show the operation waveform diagram of the charge pump circuit according to the present invention. As Figure 4A shown, when the charge pump circuit enters the heavy load period, the divided voltage Vdiv1 of the frequency generation circuit 121 rises to be the same as the first input comparison signal Vref2 and causes the first output signal Vcom1 to transition; while the divided voltage Vdiv1 of the frequency generation circuit 121 is rising, the first current I1 of the frequency adjustment circuit 122 charges the first capacitor C1. When the voltage Vsaw1 at the third input terminal d of the frequency adjustment circuit 122 is the same as the second input comparison signal Vref2 at the fourth input terminal e of the frequency adjustment circuit 122, it will cause the second output signal Vcom2 to transition; the voltage Vsaw1 at the fifth input terminal g of the frequency adjustment circuit 122 has not been boosted to the third input comparison signal Vref3 at the sixth input terminal h of the frequency adjustment circuit, and the third output signal Vcom3 has not transitioned: the first output signal Vcom1 transitions before the second output signal Vcom2 and the third output signal Vcom3 transition, and the maximum frequency is determined by the transition point of the second output signal Vcom2 of the frequency adjustment circuit 122.

[0035] When the charge pump circuit enters the medium load period, the first current I1 of the frequency adjustment circuit 122 charges the first capacitor C1. When the voltage Vsaw1 at the third input terminal d of the frequency adjustment circuit 122 is the same as the second input comparison signal Vref2 at the fourth input terminal e of the frequency adjustment circuit 122, it will cause the second output signal Vcom2 to transition; the voltage Vsaw1 at the fifth input terminal g of the frequency adjustment circuit 122 has not been boosted to the third input comparison signal Vref3 at the sixth input terminal h of the frequency adjustment circuit, and the third output signal Vcom3 has not transitioned; during this period, the divided voltage Vdiv1 of the frequency generation circuit 121 rises to be the same as the first input comparison signal Vref1 and causes the first output signal Vcom1 to transition: when the first output signal Vcom1 transitions after the second output signal Vcom2 transitions and the third output signal Vcom3 has not transitioned, the frequency is determined by the transition point of the first output signal Vcom1 of the frequency generation circuit 121.

[0036] When the charge pump circuit enters the light load period, the first current I1 of the frequency adjustment circuit 122 charges the first capacitor C1. When the voltage Vsaw1 of the third input terminal d of the frequency adjustment circuit 122 is the same as the second input comparison signal Vref2 of the fourth input terminal e of the frequency adjustment circuit, the second output signal Vcom2 will be changed. When the capacitor voltage signal Vsaw1 of the fifth input terminal g of the frequency adjustment circuit 122 is the same as the third input comparison signal Vref3 of the sixth input terminal h of the frequency adjustment circuit 122, the third output signal Vcom3 will be changed. At this time, the divided voltage Vdiv1 of the frequency generating circuit 121 has not yet been boosted to the same as the first input comparison signal Vref2, and the first output signal Vcom1 has not changed. When the second output signal Vcom2 and the third output signal Vcom3 have changed, and the first output signal Vcom1 has not yet changed, the minimum frequency is determined by the change point of the third output signal Vcom3 of the frequency adjustment circuit 122.

[0037] At the beginning of a complete charge and discharge cycle of the charge pump circuit, the second current I2 of the duty cycle fixed circuit 123 charges the second capacitor C2, so that the second capacitor voltage signal Vsaw2 of the seventh input terminal j of the duty cycle fixed circuit 123 starts to increase from the level of the fourth input comparison signal Vref4 of the eighth input terminal k of the duty cycle fixed circuit 123, and when the voltage is increased to the transition point of the first output signal Vcom1 of the frequency generating circuit 121 or the transition point of the second output signal Vcom2 or the transition point of the third output signal Vcom3 of the frequency adjusting circuit 122, the duty cycle fixed circuit 123 is increased. The third current I3 of the duty cycle fixing circuit 123 discharges and reduces the voltage of the second capacitor C2. When the second capacitor voltage signal Vsaw2 at the seventh input terminal j of the duty cycle fixing circuit 123 is equal to the fourth input comparison signal Vref4 at the eighth input terminal k of the duty cycle fixing circuit 123, the fourth output signal Vcom4 will be switched, and a complete cycle of the charge pump circuit will be ended at this time. The duty cycle fixing circuit 123 in the linear frequency adjustment module 12 will fix the duty cycle of the charge pump circuit, wherein the duty cycle is determined and fixed by the second current I2 and the third current I3.

[0038] Figure 4B show Figure 4A Schematic diagram of the relationship between medium frequency and load. Figure 4B and Figure 4A As shown, the frequency FSW between the maximum frequency FMAX and the minimum frequency FMIN increases linearly, and when the load is light, it corresponds to the minimum frequency FMIN to improve the execution performance of the charge pump circuit when the load is light, and when the load is heavy, it corresponds to the maximum frequency FMAX to maintain the execution performance of the charge pump.

[0039] Compared with the prior art, the charge pump circuit of the present invention applies a linear adjustment circuit to perform fixed duty cycle and frequency adjustment according to the output voltage and is provided with the highest and lowest frequency limits, thereby improving the execution efficiency of the charge pump circuit under light load and maintaining the execution efficiency of the charge pump circuit under heavy load. At the same time, it avoids the situation where the charge pump circuit oscillates back and forth at the boundary of the pulse jump number of the pulse number skipped by the fixed clock, resulting in a large ripple, so that the charge pump circuit has a lower output ripple.

[0040] The content disclosed above is only the preferred feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention fall within the scope of the patent application of the present invention.

Claims

1. A charge pump circuit, characterized in that, Comprising: A switching module that receives an input voltage and outputs an output voltage; A linear frequency adjustment module connected to the switching module, receiving and detecting the output voltage, and performing frequency adjustment and duty cycle fixing according to the output voltage, thereby determining a maximum frequency and a minimum frequency; And A control module connected to the linear frequency adjustment module, generating a switching signal, wherein, the linear frequency adjustment module further includes: A frequency generation circuit coupled to the control module for generating a frequency; A frequency adjustment circuit coupled to the control module for determining the maximum and minimum frequencies; and A duty cycle fixing circuit coupled to the control module for generating a fixed duty cycle, and the duty cycle fixing circuit further includes: A second current; A third current connected to the second current; A second capacitor, one end of which is connected between the second current and the third current; and A fourth comparator having a seventh input terminal, an eighth input terminal and a fourth output terminal, the seventh input terminal being connected to that end of the second capacitor, and its fourth output terminal being connected to the control module, wherein the seventh input terminal receives a second capacitor voltage signal, and the eighth input terminal receives a fourth input comparison signal to output a fourth output signal; wherein, the fixed duty cycle is determined by the second current and the third current.

2. The charge pump circuit according to claim 1, wherein The frequency generation circuit further includes: A first resistor that receives the output voltage; A second resistor connected to the first resistor, wherein there is a divided voltage between the first and the second resistors; and A first comparator having a first input terminal, a second input terminal and a first output terminal, the first input terminal being connected between the first resistor and the second resistor, the second input terminal having a first input comparison signal, the first output terminal being connected to the control module, the first input terminal receiving the divided voltage, and the second input terminal receiving a first comparison input signal to output a first output signal, wherein when the divided voltage rises to be the same as the first input comparison signal and causes the first output signal to change state.

3. The charge pump circuit according to claim 1, characterized in that, The frequency adjustment circuit further includes: A first current; A third resistor connected to the first current source; A first capacitor, one end of which is connected between the first current and the third resistor; A second comparator having a third input terminal, a fourth input terminal and a second output terminal, the third input terminal being coupled to the first capacitor, and its output terminal being connected to the control module, the third input terminal receiving a first charge and discharge signal, the fourth input terminal receiving a second input comparison signal to output a second output signal, wherein when the first capacitor voltage signal is the same as the second input comparison signal, it will cause the second output signal to change state to determine a maximum frequency; and A third comparator having a fifth input terminal, a sixth input terminal and a third output terminal, the fifth input terminal being coupled to the first capacitor, the third output terminal being connected to the control module, wherein the fifth input terminal receives the first capacitor voltage signal, the sixth input terminal receives a third input comparison signal to output a third output signal, wherein when the first capacitor voltage signal is the same as the third input comparison signal, the third output signal is toggled to determine a minimum frequency.

4. The charge pump circuit according to claim 1, wherein The switching module further includes: a first switch, a second switch, a third switch and a fourth switch, wherein the first switch and the fourth switch are connected in series with each other and the second switch and the third switch are connected in series with each other, the first switch being coupled to the input voltage and the second switch being coupled to a ground voltage, the third switch being coupled to the output voltage and the fourth switch being coupled to the ground voltage; and a third capacitor having one end coupled between the first switch and the fourth switch and the other end coupled between the second switch and the third switch.

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