Systems, devices, and methods for conveyor belt handling

Abstract

The reconfigurable hardware platform uses chains of reconfigurable hardware operator blocks in place of some software to manipulate data as it moves down the chain. This conveyor belt architecture, or chain of operator blocks, moves data between operator blocks. This conveyor belt architecture processor can be combined with a traditional front-end processor to process complex information or critical loops in hardware while processing the rest of the program as software.

Description

[0001] Related Applications

[0002] This application claims priority and the benefit of U.S. Provisional Patent Application No. 62 / 896,682, filed on Sep. 6, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] This application relates to computers and, more particularly, to computer processors. Background Art

[0004] Digital computers designed for general-purpose computing may use a standard architecture, such as the von Neumann architecture. The von Neumann architecture machine, designed by physicist and mathematician John von Neumann around 1945, may serve as a theoretical design for a stored-program digital computer. Summary of the Invention

[0005] Embodiments of the present application provide a system, apparatus, and method for conveyor belt processing, which can improve the computing efficiency of a system equipped with a conveyor belt processor.

[0006] In a first aspect, embodiments of the present application provide a method for configuring a processor. The method includes: receiving a program configured to run as software; determining a first part of the program to be run in hardware and a second part of the program to be run as software; determining, based on the first part, a plurality of interconnected reprogrammable operator blocks, the plurality of interconnected reprogrammable operator blocks including one or more transformation functions, the one or more transformation functions obtaining input data from a previous data bus, performing one or more transformations on the input data, and outputting the transformed input data via an output data bus; configuring the plurality of interconnected reprogrammable operator blocks to execute on one or more reprogrammable processors; executing the second part via one or more front-end processors; sending first data from the one or more front-end processors to the one or more reprogrammable processors; executing the first part via the one or more reprogrammable processors; sending second data from the one or more reprogrammable processors to the one or more front-end processors; and determining result data based on the first data and the second data.

[0007] Second aspect, an embodiment of the present application provides a conveyor belt processor, including: an input data bus, a plurality of interconnected reprogrammable operator blocks, and an output data bus. The plurality of interconnected reprogrammable operator blocks include: an input data bus of a first reprogrammable operator block, and the input data bus of the first reprogrammable operator block is coupled to an output data bus or the input data bus of a second reprogrammable operator block; an output data bus of the first reprogrammable operator block, and the output data bus of the first reprogrammable operator block is coupled to an input data bus or an output data bus of a third reprogrammable operator block; one or more transformation functions, which obtain input data from a previous data bus, perform one or more transformations on the input data, and output the transformed input data via the output data bus; the conveyor belt processor is configured to perform the following steps: determine the plurality of interconnected reprogrammable operator blocks according to a first part of a program that runs as software and is to be run in hardware; configure the plurality of interconnected reprogrammable operator blocks; and execute the first part via the one or more reprogrammable processors.

[0008] Third aspect, an embodiment of the present application provides a system for processing data. The system includes: a plurality of processors and a management function. Each processor includes an input data bus, a plurality of interconnected reprogrammable operator blocks, and an output data bus. The plurality of interconnected reprogrammable operator blocks include: an input data bus of a first reprogrammable operator block, and the input data bus of the first reprogrammable operator block is coupled to an output data bus or the input data bus of a second reprogrammable operator block; an output data bus of the first reprogrammable operator block, and the output data bus of the first reprogrammable operator block is coupled to an input data bus or an output data bus of a third reprogrammable operator block; and one or more transformation functions, which obtain input data from a previous data bus, perform one or more transformations on the input data, and output the transformed input data via the output data bus; and the output data bus; the management function is configured to allocate data to each processor; each processor is configured to perform the following steps: determine the plurality of interconnected reprogrammable operator blocks according to a first part of a program that runs as software and is to be run in hardware; configure the plurality of interconnected reprogrammable operator blocks; and execute the first part via the one or more reprogrammable processors.

[0009] Depending on the application, a conveyor belt architecture computing system may be much faster than a standard architecture computing system. For example, a conveyor belt architecture computing system may be faster in applications that process large amounts of data. The performance advantage of a conveyor belt architecture computing system over a standard architecture computing system may depend on the program being executed. It has been noted through testing that in some applications, an advantage of 100% to 2,000% is possible. Description of the Drawings

[0010] Figure 1 Schematic diagram of the framework of a traditional computing system.

[0011] Figure 2 Schematic diagram of the framework of the conveyor belt architecture computing system in an embodiment of the present invention.

[0012] Figure 3 Shows the program source code for printing Fibonacci numbers.

[0013] Figure 4 Shows the program machine code for printing Fibonacci numbers executed on a standard architecture system.

[0014] Figure 5 Shows the flowchart of the operator block for printing Fibonacci numbers executed on a conveyor belt architecture system.

[0015] Figure 6 Shows the source code for calculating and printing the sum of numbers.

[0016] Figure 7 Shows the first quarter of the machine code for calculating and printing the sum of numbers executed on a standard architecture system.

[0017] Figure 8 Shows the second quarter of the machine code for calculating and printing the sum of numbers executed on a standard architecture system.

[0018] Figure 9 Shows the third quarter of the machine code for calculating and printing the sum of numbers executed on a standard architecture system.

[0019] Figure 10 Shows the fourth quarter of the machine code for calculating and printing the sum of numbers executed on a standard architecture system.

[0020] Figure 11 Shows the flowchart of the operator block for calculating and printing the sum of numbers executed on a conveyor belt architecture system.

[0021] Figure 12 Shows the block diagram illustrating the conveyor belt architecture computing system used in conjunction with a standard architecture computing system.

[0022] Figure 13 Shows the block diagram illustrating how a program can be executed across a conveyor belt architecture computing system and a standard architecture computing system.

[0023] Figure 14 Shows the flowchart of the method for preparing the conveyor belt architecture.

[0024] Figure 15A block diagram showing a computing system and components. Detailed Description

[0025] A detailed description of systems and methods consistent with embodiments of the present disclosure is provided below. Although several embodiments are described, it should be understood that the present disclosure is not limited to any one embodiment, but encompasses many alternatives, modifications, and equivalents. Additionally, although many specific details are set forth in the following description to provide a thorough understanding of the embodiments disclosed herein, some embodiments may be practiced without some or all of these details. Moreover, certain technical materials known in the prior art are not described in detail to avoid unnecessarily obscuring the present disclosure.

[0026] Techniques, apparatus, and methods are disclosed for using a reconfigurable hardware platform to interconnect a chain of reconfigurable hardware operator blocks to manipulate data as the data moves down the chain. This conveyor belt architecture or chain of operator blocks moves data between the operator blocks. Instead of some software, the chain of reconfigurable hardware operator blocks manipulates the data as the data moves down the chain.

[0027] In some embodiments, the conveyor belt architecture computing system can be used alone to perform computing tasks.

[0028] Multiple conveyor belt architecture computing systems can be used in series or in parallel, such as to share the workload between computing systems.

[0029] The conveyor belt architecture computing system can be used in combination with a standard architecture computing system, such as to share the workload between computing systems.

[0030] Multiple conveyor belt architecture computing systems can be used in series or in parallel and in combination with a standard architecture computing system, such as to share the workload between computing systems.

[0031] For example, the conveyor belt architecture computing system can be used in combination with multiple standard architecture computing systems and share the workload between the computing systems.

[0032] Figure 1A diagram is shown that illustrates an example of a computing system similar to or including a von Neumann architecture computing system. The computing system includes an input 102, a computing system 104, and an output 106. The input 102 (e.g., via a bus, etc.) is received into the computing system 104, and the input 102 is processed at the computing system 104 before being sent as an output 106 from the computing system 104 (e.g., via a bus, etc.). A random access memory (RAM) 108 is included within the computing system 104, which is coupled to a central processing unit (CPU) 112 via a common bus 110. In addition, the CPU 112 includes an arithmetic logic unit (ALU) 116, a control unit 114, and registers 118 as well as a stack 120.

[0033] A program executed on a standard architecture computing system can include a set of instructions that are executed in a specific order to manipulate data.

[0034] Once the program is loaded into the RAM 108, the CPU 112 can execute a series of "fetch - decode - execute" loops, whereby the contents of a RAM 108 location are read, decoded, and then executed in a specific order as specified by the program. Since the locations in the RAM 108 contain both instructions and data, the CPU 112 reads and decodes the instructions to determine how to process the information and then executes based on the results. Some instructions tell the CPU 112 to write the operation result back to a RAM 108 location, while other instructions tell the CPU 112 to jump to a specific location in the RAM 108 based on the result of the previous instruction.

[0035] A problem with this architecture can be that program instructions and data are contained in the same RAM 108. The information in the RAM 108 can be read one at a time and decoded, resulting in inefficiencies in the architecture and performance limitations. In addition, the common bus 110 may not allow the CPU 112 to read and write information simultaneously.

[0036] This is referred to as a bottleneck and can further limit the performance of the system.

[0037] Figure 2 A diagram is shown that illustrates a conveyor belt architecture computing system including an input 202, a computing system 204, and an output 206. The input 202 is received by the computing system 204 (e.g., via a bus, etc.), and the input 202 is processed at the computing system 204 before being sent as an output 206 from the computing system 204 (e.g., via a bus, etc.). A reconfigurable hardware platform 208 (e.g., a field programmable gate array (FPGA)) is included within the computing system 204, which includes a large number of reconfigurable operator blocks 210, 212, 214, 216, and 218 interconnected by data paths 220, 222, 224, and 226 in one direction and a data path 228 in the opposite direction.

[0038] Instead of a CPU coupled to a RAM via a bus, a conveyor belt architecture can use a reconfigurable hardware platform (such as FPGA 208) to interconnect a chain of reconfigurable operator blocks 210, 212, 214, 216, and 218 to manipulate data as the data moves between operator blocks along data paths 220, 222, 224, and 226 in one direction and along data path 228 in the opposite direction.

[0039] In this embodiment, at each operator block 210, 212, 214, 216, and 218, one operation or a set of operations is performed to manipulate the data before the data is carried to the next operator block in the chain along data paths 220, 222, 224, and 226 in one direction and along data path 228 in the opposite direction.

[0040] The program is translated and then copied into the reconfigurable hardware platform 208 (e.g., FPGA, etc.). Each instruction or set of instructions is assigned to operator blocks 210, 212, 214, 216, and 218, and the program flow is determined by the interconnection of these operator blocks.

[0041] As the data flows between operator blocks along the chain on data paths 220, 222, 224, and 226, the data is manipulated at each operator block 210, 212, 214, 216, and 218.

[0042] In the case of a "jump" instruction, the data flow can be changed / redirected by the operator block in the opposite direction or through a separate data path 228 to some other operator block. In this example, a jump based on a condition is shown where operator block 4 (216) returns to operator block 2 (212).

[0043] In addition, operator blocks 210, 212, 214, 216, and 218 can be autonomous and capable of processing data asynchronously or synchronously when they receive data from the previous operator block in the chain.

[0044] In one embodiment of autonomous operation, the conveyor belt architecture allows multiple instructions to be executed in a single processor cycle.

[0045] The conveyor belt architecture can be more efficient than a standard architecture because it does not need to read the program from the RAM and decrypt it.

[0046] The conveyor belt architecture can avoid the bottlenecks associated with traditional computer architectures because it does not rely on a common bus path and each set of operator blocks has its own data path.

[0047] The conveyor belt architecture can allow for higher throughput and processing capabilities. Another advantage of this architecture is that when operating in synchronous mode, the conveyor belt architecture can pack data more densely into the reconfigurable hardware platform by queuing data at the input of each operator block, ready to be loaded into subsequent operator blocks as it becomes more available.

[0048] Program instructions can be included in operator blocks in the form of hardware logic gates rather than software, which makes instruction execution much faster than its software counterpart.

[0049] Another benefit of the conveyor belt architecture is that the program may be more difficult to crack. The program can be stored as hardware, and any modification of the program by a hacker may break the chain of the conveyor belt and cause the system to reset. The system reset may cause the system to automatically reload the original (unchanged) program into the reconfigurable hardware platform.

[0050] Figure 3-11 Shows the differences between the two architectures. For two different programs, the C source code and the compiled output from a more traditional computing system and a conveyor belt computing system were tested.

[0051] Figure 3 Shows the source code for printing Fibonacci numbers. Displays the C source code for a program that prints Fibonacci numbers in the range from 0 to 255.

[0052] Figure 4 Shows the machine code for printing Fibonacci numbers. Figure 3 The C source code in can be compiled to execute on a traditional computing system. The resulting machine language may look similar to the list shown in Figure 4 A traditional computing system can use at least 85 CPU clock cycles to complete the first iteration of the calculation and print loop. Thereafter, a traditional computing system can use at least 56 CPU cycles to complete subsequent iterations of the calculation and print loop.

[0053] Figure 5 Shows the flowchart of the operator block for printing Fibonacci numbers. Compared with Figure 4 Figure 3 The C source code shown in can be compiled to execute on a conveyor belt computing system. The resulting operator blocks for executing the program can be similar to those shown in Figure 5

[0054] ​​Operator block 1 (OB#1) 502 assigns the values "x = 0" and "y = 1". Operator block 2 (OB#2) 504 lines the "printf" function. Operator block 3 (OB#3) 506 adds the contents of x and y and assigns it to variable z. It also assigns y to x and z to y. If the result of "x < 255" is true, operator block 4 (OB#4) 508 performs a conditional jump back to the start of operator block 2 504, and if the result of "x < 255" is false, operator block 4 performs a conditional jump back to the start of operator block 1 502.

[0055] In this embodiment, multiple instructions can be combined together in a single operator block 502, 504, 506, and 508, thereby allowing multiple operations to be performed on the data before the data is passed to the next operator block. When operating in synchronous mode, the conveyor belt architecture can use four processor clock cycles to complete the first iteration and subsequent iterations of the calculation and print loop. This can allow the conveyor belt architecture machine in this example to operate 14 times faster than a traditional machine with a similar clock cycle (i.e., 56 cycles versus 4 cycles).

[0056] Figure 6 The source code for finding the sum of digits is shown. In Figure 6 the C source code of the program for finding the sum of digits of a number using recursion is shown.

[0057] Figure 7-10 The source code for finding the sum of digits is shown. Figure 6 The C source code in can be compiled to execute on a von Neumann computing system. The resulting machine language may look similar to the list shown in Figure 7-10 The "main" loop calls a separate "sum" loop 802 to calculate and return the result 1002. Inside the sum loop, an "if" statement 902 is included. Depending on the result of the if statement, the digital computer can use 113 CPU clock cycles or 191 clock cycles to process a single iteration.

[0058] Figure 9 The flowchart of the operator block for finding the sum of digits is shown. Compared with Figure 7-10 the C source code shown in Figure 6 can be compiled to execute on a conveyor belt architecture computing system. The resulting operator blocks for executing the program can be similar to those shown in Figure 11 .

[0059] Operator block 1 (OB#1) 1102 executes the "printf" function to print "Enter the number" on the output device. Operator block 2 (OB#2) 1104 executes the "scanf" function to input a number from the input device. Operator block 3 (OB#3) 1106 executes an "if" statement that compares the input number with 0, and then redirects the program to operator block 4 (OB#4) 1108 if the result is positive, and to operator block 5 (OB#5) 1110 if the result is negative. Operator block 4 (OB#4) 1108 performs calculations. Operator block 5 (OB#5) 1110 returns 0. Operator block 6 (OB#6) 1112 assigns the number returned by OB#4 (1108) or OB#5 (1110) to the variable "sum". Operator block 7 (OB#7) 1114 executes the "printf" function to print sum on the output device. Additionally, the output of this operator block 1114 is coupled to the input of OB#1 (1102) to allow the program to loop infinitely.

[0060] In this embodiment, the operator blocks can redirect the program chain based on the result of a condition. When operating in synchronous mode, the conveyor belt architecture computing system can use six processor clock cycles to complete an iteration of the program, regardless of the result of the "if" instruction. The conveyor belt architecture computing system in this example can be 18 times faster than a standard architecture computing system with respect to similar clock cycles (i.e., 113 cycles versus 6 cycles).

[0061] Depending on the application, the conveyor belt architecture computing system can be much faster than a standard architecture computing system. For example, the conveyor belt architecture computing system may be faster in applications that process large amounts of data. The performance advantage of the conveyor belt architecture computing system over the standard architecture computing system may depend on the program being executed. It has been noted through testing that in some applications, an advantage of 100% to 2,000% is possible.

[0062] Figure 12 A block diagram illustrating a conveyor belt architecture computing system used in conjunction with a standard architecture computing system is shown. In this embodiment, the standard architecture computing system front end 1202 is coupled to the conveyor belt architecture computing system back end 1204 via a common bus 1206.

[0063] The standard architecture computing system front end includes the following components coupled together via a common bus arrangement 1206: a central processing unit (CPU) 1208, a dynamic random access memory (DRAM) 1210, a local area network (LAN) adapter 1212, a basic input and output system (BIOS) 1214, and a hard disk drive (HDD) 1216. In the case of the HDD 1216, this is implemented via an interface (I / F) 1218.

[0064] Also shown in this embodiment is a graphics processing unit (GPU) 1220 and another expansion processor 1222.

[0065] The conveyor belt architecture computing system conveyor belt backend includes an FPGA 1224, which is coupled to the rest of the components in the system via a common bus 1206.

[0066] Since some programs may be idle for most of their operating time, it hardly makes sense to execute such idle code in a conveyor belt architecture computing system. Instead, only specific parts of a program (e.g., critical loops, critical paths) can be translated and executed in the conveyor belt architecture computing system to perform "heavy work". The remaining parts of the program that do not have specific parts can still be executed in the front-end standard architecture computing system. Using these two architectures together can avoid the need to translate the entire program to operate on the conveyor belt architecture computing system. This can prevent the use of valuable conveyor belt architecture computing system real estate (e.g., program space) that may not provide any tangible benefits. In addition, the use of these two architectures ensures compatibility with existing programs designed to execute on a standard architecture computing system.

[0067] In some embodiments, a conveyor belt architecture computing system can be used in combination with a standard architecture computing system. Figure 13 A block diagram is shown illustrating how a program can be executed across a conveyor belt architecture computing system and a standard architecture computing system. The standard architecture computing system front end 1302 is coupled to the conveyor belt architecture computing system backend 1304 via a bus 1306. The body of the program 1308 then calls routines A 1312 and B 1314 in the conveyor belt architecture computing system via call functions 1316 and 1320, and returns the results at 1318 and 1322, respectively.

[0068] Figure 14 A flowchart of a method for preparing a conveyor belt architecture is shown. The method can be performed by the systems and / or components described herein, including Figure 2204 in. In block 1402, the conveyor belt system may receive a program configured to run as software. In block 1404, the conveyor belt system may determine that a first part of the program runs in hardware and a second part of the program runs as software. In block 1406, the conveyor belt system may determine, based on the first part, a plurality of interconnected reprogrammable operator blocks, including one or more transformation functions that obtain input data from a previous data bus, perform one or more transformations on the input data, and output the transformed input data via an output data bus. In block 1408, the conveyor belt system may configure the plurality of interconnected reprogrammable operator blocks to execute on one or more reprogrammable processors. In block 1410, the conveyor belt system may execute the second part via one or more front-end processors. In block 1412, the conveyor belt system may send first data from one or more front-end processors to one or more reprogrammable processors. In block 1414, the conveyor belt system may execute the first part via one or more reprogrammable processors. In block 1416, the conveyor belt system may send second data from one or more reprogrammable processors to one or more front-end processors. In block 1418, the conveyor belt system may determine result data based on the first data and the second data.

[0069] The conveyor belt system may determine that a first part of the program runs in hardware based on computational complexity. The result data may be the result of program execution. The second data may be derived from the first data based on one or more transformations. The result data may be derived from the second data, and the second data may be derived from the first data. One or more reprogrammable processors may be field programmable gate arrays. Sending the first data from one or more front-end processors to one or more reprogrammable processors may further include sending the first data from one or more front-end processors to one or more reprogrammable processors via an expansion bus. Receiving a program configured to run as software may further include compiling the program into executable software code, a hardware configuration, and communication code for transferring data between the executable software code and the hardware configuration.

[0070] The conveyor belt processor may include an input data bus, a plurality of interconnected reprogrammable operator blocks, and an output data bus. The plurality of interconnected reprogrammable operator blocks may include: an input data bus of a first reprogrammable operator block, the input data bus of the first reprogrammable operator block being coupled to an output data bus of a second reprogrammable operator block or the input data bus; an output data bus of the first reprogrammable operator block, the output data bus of the first reprogrammable operator block being coupled to an input data bus or an output data bus of a third reprogrammable operator block; and one or more transformation functions that obtain input data from a previous data bus, perform one or more transformations on the input data, and output the transformed input data via the output data bus.

[0071] The bus widths of multiple interconnected reprogrammable operator blocks may be different. The output of a subsequent block may be the input of a previous block. The second reprogrammable operator block and the third reprogrammable operator block may be the same. The third reprogrammable operator block may be before the first reprogrammable operator block in the execution order. The conveyor processor may further include a programming interface configured to receive instructions for creating multiple interconnected reprogrammable operator blocks.

[0072] A system for processing data may include multiple processors and a management function, where the management function is configured to allocate data to each processor. Each processor may include an input data bus, multiple interconnected reprogrammable operator blocks, and an output data bus. The interconnected reprogrammable operator blocks may include: an input data bus of a first reprogrammable operator block, the input data bus of the first reprogrammable operator block being coupled to an output data bus of a second reprogrammable operator block or the input data bus; an output data bus of the first reprogrammable operator block, the output data bus of the first reprogrammable operator block being coupled to an input data bus or an output data bus of a third reprogrammable operator block; and one or more transformation functions that obtain input data from a previous data bus, perform one or more transformations on the input data, and output the transformed input data via the output data bus.

[0073] The management function may also be configured to reconfigure multiple interconnected reprogrammable operator blocks. The management function may include memory storage instructions for creating multiple interconnected reprogrammable operator blocks of multiple processors. The claimed system may further include at least one front-end processor having an architecture different from that of the multiple processors. The at least one front-end processor may include a general-purpose processor. The management function may include: a security interface configured to receive configuration changes; and a non-security interface configured to allocate data to one or more of the multiple processors.

[0074] Figure 15 is a block diagram showing components that can read instructions from a machine-readable or computer-readable medium (e.g., a machine-readable storage medium) and perform any one or more of the methods discussed herein. Specifically, Figure 15 shows a graphical representation of hardware resources 1500, including one or more processors (or processor cores) 1510, one or more memory / storage devices 1520, and one or more communication resources 1530, each of which is communicatively coupled via a bus 1540.

[0075] The processor 1510 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a radio frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, processor 1512 and processor 1514. The memory / storage device 1520 may include a main memory, a disk storage, or any suitable combination thereof.

[0076] The communication resources 1530 may include an interconnect and / or network interface component or other suitable devices to communicate with one or more peripheral devices 1504 and / or one or more databases 1506 via the network 1508. For example, the communication resources 1530 may include a wired communication component (e.g., for coupling via a universal serial bus (USB)), a cellular communication component, a near field communication (NFC) component, a Bluetooth component (e.g., low energy Bluetooth), components, and other communication components.

[0077] The instructions 1550 may include software, programs, applications, applets, apps, or other executable code to cause at least any of the processors 1510 to perform any one or more of the methods discussed herein. The instructions 1550 may reside, in whole or in part, in at least one of the following: the processor 1510 (e.g., within the cache memory of the processor), the memory / storage device 1520, or any suitable combination thereof. Additionally, any part of the instructions 1550 may be transferred from any combination of the peripheral devices 1504 and / or the database 1506 to the hardware resources 1500. Accordingly, the memory of the processor 1510, the memory / storage device 1520, the peripheral devices 1504, and the database 1506 are examples of computer-readable and machine-readable media.

[0078] As used herein, the term "circuit" may refer to, belong to, or include an application specific integrated circuit (ASIC), an electronic circuit, a (shared, dedicated, or combined) processor and / or a (shared, dedicated, or combined) memory that executes one or more software or firmware programs, combinational logic circuitry, and / or other suitable hardware components that provide the described functionality. In some embodiments, the circuit may be implemented in one or more software or firmware modules, or the functionality associated with the circuit may be implemented by one or more software or firmware modules. In some embodiments, the circuit may include logic that is at least partially operable in hardware.

[0079] Embodiments and implementations of the systems and methods described herein may include various operations that may be embodied in machine-executable instructions to be executed by a computer system. The computer system may include one or more general-purpose or special-purpose computers (or other electronic devices). The computer system may include hardware components that include specific logic for performing the operations, or may include a combination of hardware, software, and / or firmware.

[0080] The computer system and the computers in the computer system may be connected via a network. Suitable networks for configuration and / or use as described herein include one or more local area networks, wide area networks, metropolitan area networks, and / or the Internet or IP networks, such as the World Wide Web, a private Internet, a secure Internet, a value-added network, a virtual private network, an extranet, an intranet, or even a stand-alone machine communicating with other machines via physical transmission over a medium. In particular, a suitable network may be formed by portions or all of two or more other networks, including networks using different hardware and network communication technologies.

[0081] A suitable network includes a server and one or more clients; other suitable networks may contain other combinations of servers, clients, and / or peer nodes, and a given computer system may be used as a client and as a server. Each network includes at least two computers or computer systems, such as a server and / or a client. The computer system may include workstations, laptop computers, disconnectable mobile computers, servers, mainframes, clusters, so-called "network computers" or "thin clients", tablet computers, smart phones, personal digital assistants or other handheld computing devices, "smart" consumer electronic devices or appliances, medical devices, or combinations thereof.

[0082] Suitable networks may include communication or network software, such as software available from and other vendors, and may operate over twisted pair, coaxial cable, or fiber optic cable, telephone lines, radio waves, satellites, microwave repeaters, modulated AC power lines, physical media transmission, and / or other data transmission "lines" known to those skilled in the art using TCP / IP, SPX, IPX, and other protocols. The network may include smaller networks and / or may be connectable to other networks via gateways or similar mechanisms.

[0083] Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) contained in a tangible medium, such as a floppy disk, CD-ROM, hard disk drive, magnetic or optical card, solid state memory device, non-transitory computer-readable storage medium, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine such as a computer, the machine becomes an apparatus for practicing the various techniques. In the case of executing program code on a programmable computer, the computing device may include a processor, a processor-readable storage medium (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The volatile and non-volatile memory and / or storage elements may be RAM, EPROM, flash drive, optical drive, magnetic hard drive, or other media for storing electronic data. One or more programs that can implement or utilize the various techniques described herein may use application programming interfaces (APIs), reusable controls, etc. Such programs may be implemented in a high-level procedural programming language or an object-oriented programming language to communicate with a computer system. However, if desired, the program may be implemented in assembly or machine language. In any case, the language may be a compiled or interpreted language and combined with a hardware implementation.

[0084] Each computer system includes one or more processors and / or memories; the computer system may also include various input devices and / or output devices. The processor may include general-purpose devices, such as or other "off-the-shelf" microprocessors. The processor may include dedicated processing devices, such as ASICs, SoCs, SiPs, FPGAs, PALs, PLAs, FPLAs, PLDs, or other custom or programmable devices. The memory may include static RAM, dynamic RAM, flash memory, one or more flip-flops, ROM, CD-ROM, DVD, disk, tape, or magnetic, optical, or other computer storage media. The input devices may include a keyboard, mouse, touch screen, light pen, tablet computer, microphone, sensor, or other hardware with firmware and / or software. The output devices may include a monitor or other display, printer, voice or text synthesizer, switch, signal line, or other hardware with firmware and / or software.

[0085] It should be understood that many of the functional units described in this specification may be implemented as one or more components, and these terms are used to more specifically emphasize the independence of their implementation. For example, a component may be implemented as a hardware circuit that includes custom very large scale integration (VLSI) circuits or gate arrays or off-the-shelf semiconductors (such as logic chips, transistors), or other discrete components. A component may also be implemented in a programmable hardware device (such as a field programmable gate array, programmable array logic, programmable logic device, etc.).

[0086] The components can also be implemented by software executed by various types of processors. The executable code identifying a component can include, for example, one or more physical or logical blocks of computer instructions, which can be organized, for example, as objects, procedures, or functions. However, the executable files of the identifying components need not be physically located together, but may include different instructions stored in different locations, which, when logically combined, constitute the component and achieve the stated purpose of the component.

[0087] In fact, the components of executable code can be a single instruction, or many instructions, and can even be distributed over several different code segments, distributed among different programs, and distributed over several memory devices. Similarly, the operating data may be identified and illustrated in the components herein and can be embodied in any suitable form and organized in any suitable type of data structure. The operating data can be collected as a single data set or can be distributed over different locations, including distributed over different storage devices, and can exist at least partially only as electronic signals in a system or network. A component can be passive or active, including an agent operable to perform the required functions.

[0088] Several aspects of the described embodiments will be illustrated as software modules or components. As used herein, a software module or component can include any type of computer instructions or computer-executable code located within a memory device. For example, a software module can include one or more physical or logical blocks of computer instructions, which can be organized as routines, programs, objects, components, data structures, etc., to perform one or more tasks or implement a particular data type. It will be understood that instead of software or in addition to software, a software module can be implemented in hardware and / or firmware. One or more of the functional modules described herein can be separated into sub-modules and / or combined into a single or fewer number of modules.

[0089] In certain embodiments, a particular software module can include different instructions stored in different locations in a memory device, different memory devices, or different computers, which together implement the described functionality of the module. In fact, a module can include a single instruction or many instructions and can be distributed over several different code segments, distributed among different programs, and distributed across several memory devices. Some embodiments can be practiced in a distributed computing environment where tasks are performed by remote processing devices linked by a communication network. In a distributed computing environment, software modules can be located in local memory storage devices and / or remote memory storage devices. Additionally, data bound or presented together in database records can reside in the same memory device or across several memory devices and can be linked together in record fields in a database across a network.

[0090] References to "examples" throughout this specification mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment of the invention. Thus, the phrase "in an example" appearing throughout the specification does not necessarily refer to the same embodiment.

[0091] As used herein, for convenience, a plurality of items, structural elements, components, and / or materials may be presented in a common list. However, these lists should be interpreted as each member of the list being individually identified as a separate and unique member. Thus, unless indicated to the contrary, no individual member of such a list should be construed as a de facto equivalent of any other member of the same list merely based on its presentation in the common group. Additionally, various embodiments and examples of the invention may be referred to herein along with alternatives for their various components. It should be understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but rather as separate and autonomous manifestations of the invention.

[0092] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of materials, frequencies, dimensions, lengths, widths, shapes, etc., to provide a thorough understanding of the embodiments of the invention. However, those skilled in the relevant art will recognize that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the invention.

[0093] It should be recognized that the systems described herein include descriptions of particular embodiments. These embodiments may be combined into a single system, partially combined into other systems, split into multiple systems, or otherwise partitioned or combined. Additionally, it is contemplated that the parameters / attributes / aspects / etc. of one embodiment may be used in another embodiment. The parameters / attributes / aspects / etc. are described in only one or more embodiments for clarity, and it should be recognized that the parameters / attributes / aspects / etc. may be combined with or substituted for the parameters / attributes / aspects / etc. of another embodiment, unless expressly stated otherwise herein.

[0094] Although the foregoing has been described in detail for purposes of clarity, it will be apparent that certain changes and modifications may be made without departing from its principles. It should be noted that there are many alternative ways of implementing the processes and apparatus described herein. Accordingly, this embodiment may be considered illustrative rather than restrictive, and the present invention is not limited to the details given herein, but may be modified within the scope of the appended claims and their equivalents.

[0095] Those skilled in the art will appreciate that many variations of the details of the above-described embodiments may be made without departing from the basic principles of the present invention. Accordingly, the scope of the present invention should be defined solely by the appended claims.

Claims

1. A method of configuring a processor, the method comprising: Receiving a program configured to run as software; Determining a first portion of the program to be run in hardware and a second portion of the program to run as software; Determining, based on the first portion, a plurality of interconnected reprogrammable operator blocks, the plurality of interconnected reprogrammable operator blocks including one or more transformation functions that obtain input data from a previous data bus, perform one or more transformations on the input data, and output the transformed input data via an output data bus; Configuring the plurality of interconnected reprogrammable operator blocks to execute on one or more reprogrammable processors; Executing the second portion via one or more front-end processors; Sending first data from the one or more front-end processors to the one or more reprogrammable processors; Executing the first portion via the one or more reprogrammable processors; Sending second data from the one or more reprogrammable processors to the one or more front-end processors; and Determining result data based on the first data and the second data.

2. The method according to claim 1, wherein Determining the first portion further includes determining the first portion of the program to be run in hardware based on computational complexity.

3. The method according to claim 1, wherein The result data is the result of the execution of the program.

4. The method according to claim 1, wherein The second data is derived from the first data based on the one or more transformations.

5. The method according to claim 1, wherein The result data is derived from the second data, and the second data is derived from the first data.

6. The method according to claim 1, wherein, The one or more reprogrammable processors are field programmable gate arrays.

7. The method according to claim 1, wherein, Sending the first data from the one or more front-end processors to the one or more reprogrammable processors further includes sending the first data from the one or more front-end processors to the one or more reprogrammable processors via an expansion bus.

8. The method according to claim 1, wherein, Receiving a program configured to run as software further includes compiling the program into executable software code, a hardware configuration, and communication code for transferring data between the executable software code and the hardware configuration.

9. A conveyor processor, comprising: An input data bus; A plurality of interconnected reprogrammable operator blocks, including: An input data bus of a first reprogrammable operator block, the input data bus of the first reprogrammable operator block being coupled to an output data bus of a second reprogrammable operator block or the input data bus; An output data bus of the first reprogrammable operator block, the output data bus of the first reprogrammable operator block being coupled to an input data bus or an output data bus of a third reprogrammable operator block; One or more transformation functions that obtain input data from a previous data bus, perform one or more transformations on the input data, and output the transformed input data via an output data bus; and The output data bus; The conveyor processor is configured to perform the following steps: Determining the plurality of interconnected reprogrammable operator blocks according to a first portion of a program to be run in hardware while the program runs as software; Configuring the plurality of interconnected reprogrammable operator blocks; The first part is executed via one or more reprogrammable processors.

10. The conveyor processor according to claim 9, wherein, The bus widths of the plurality of interconnected reprogrammable operator blocks are different.

11. The conveyor processor according to claim 9, wherein, The output of a subsequent block is the input of a previous block.

12. The conveyor processor according to claim 9, wherein, The second reprogrammable operator block and the third reprogrammable operator block are the same.

13. The conveyor processor according to claim 9, wherein, The third reprogrammable operator block is before the first reprogrammable operator block in the execution order.

14. The conveyor processor according to claim 9, further comprising a programming interface configured to receive instructions for creating the plurality of interconnected reprogrammable operator blocks.

15. A system for processing data, the system comprising: a plurality of processors, each processor comprising: an input data bus; a plurality of interconnected reprogrammable operator blocks, the plurality of interconnected reprogrammable operator blocks comprising: an input data bus of a first reprogrammable operator block, the input data bus of the first reprogrammable operator block being coupled to an output data bus of a second reprogrammable operator block or the input data bus; an output data bus of the first reprogrammable operator block, the output data bus of the first reprogrammable operator block being coupled to an input data bus or an output data bus of a third reprogrammable operator block; and one or more transformation functions that obtain input data from a previous data bus, perform one or more transformations on the input data, and output the transformed input data via the output data bus; and the output data bus; and a management function, wherein the management function is configured to allocate data to each processor; each of the processors is used to perform the following steps: determine the plurality of interconnected reprogrammable operator blocks according to a first part of a program to be run in hardware as software; configure the plurality of interconnected reprogrammable operator blocks; execute the first part via one or more reprogrammable processors.

16. The system according to claim 15, wherein The management function is further configured to reconfigure the plurality of interconnected reprogrammable operator blocks.

17. The system according to claim 15, wherein The management function includes memory storage instructions for creating the plurality of interconnected reprogrammable operator blocks of the plurality of processors.

18. The system according to claim 15, further comprising at least one front-end processor having an architecture different from that of the plurality of processors.

19. The system according to claim 18, wherein, The at least one front-end processor includes a general-purpose processor.

20. The system according to claim 15, wherein The management function includes: a security interface configured to receive configuration changes; and a non-security interface configured to allocate data to one or more of the plurality of processors.

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