Semiconductor devices

Abstract

The present disclosure relates to a semiconductor device. It has a high withstand voltage characteristic and can suppress damage caused by transient large current. A semiconductor device has a super junction structure formed by a first column region of a first conductivity type and a second column region of a second conductivity type arranged adjacent to the first column region, and has: a first semiconductor layer of the second conductivity type arranged on the first column region and the second column region; a second semiconductor layer of the first conductivity type arranged on the first semiconductor layer; a first semiconductor region of the first conductivity type electrically connected to a first electrode and arranged at a surface portion of the second semiconductor layer separated from the first semiconductor layer; and a second semiconductor region of the second conductivity type electrically connected to a second electrode, arranged at least at a surface portion of the second semiconductor layer separated from the first semiconductor region, and electrically connected to the first semiconductor layer.

Description

[0001] The present application is an application of international application PCT / JP2020 / 041633 (international filing date: November 6, 2020) entering the Chinese national phase, and the above-mentioned international application is incorporated in this specification by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device. Background Art

[0003] There are power semiconductor devices suitable for high voltage and large current. As power semiconductor devices, there are known semiconductor devices that utilize the phenomenon that the drift layer or collector layer is reduced in resistance by the conductivity modulation effect in the on state (for example, refer to L. Theolier, C. Benboujema, A. Schellmanns, N. Batut, Y. Raingeaud, JB Quoirin, "BJT Application Expansion by Insertion of Superjunction", 22nd ISPSD, pp 157-160, 2010).

[0004] Semiconductor devices that utilize the conductivity modulation effect include, for example, thyristors, insulated gate bipolar transistors (IGBT: Insulated Gate Bipolar Transistor), and bipolar transistors (BJT: Bipolar Junction Transistor).

[0005] Among them, thyristors and IGBTs can flow a large current in a large current region, whereas BJTs can flow a large current in a region below the diffusion potential. Summary of the invention

[0006] However, although the BJT has excellent current characteristics during rising, it has the following disadvantages: the withstand voltage between the base and the emitter is low, and it is easy to be destroyed when a large current flows instantaneously, such as when it is turned off.

[0007] An object of an embodiment of the present invention is to provide a semiconductor device having high withstand voltage characteristics and capable of suppressing destruction due to transient large current.

[0008] A semiconductor device of an embodiment has a super junction structure formed by a first column region of a first conductivity type and a second column region of a second conductivity type arranged adjacent to the first column region, and the semiconductor device also has: first and second electrodes arranged on one side of the super junction structure, constituting a transistor and controlling a current flowing through the transistor; and a third electrode arranged on the opposite side of the first electrode and the second electrode across the super junction structure, constituting the transistor, the semiconductor device comprising: a first semiconductor layer of the second conductivity type arranged on the first column region and the second column region; a second semiconductor layer of the first conductivity type arranged on the first semiconductor layer; a first semiconductor region of the first conductivity type electrically connected to the first electrode and arranged on a surface portion of the second semiconductor layer separately from the first semiconductor layer; and a second semiconductor region of the second conductivity type electrically connected to the second electrode, arranged on at least a surface portion of the second semiconductor layer separately from the first semiconductor region, and electrically connected to the first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a diagram schematically showing a state of a depletion layer when the semiconductor device according to the first embodiment is in an off state.

[0011] Figure 3 It is a cross-sectional view showing the structure of a semiconductor device according to a comparative example.

[0012] Figure 4 This is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment.

[0013] Figure 5 This is a diagram showing an example of the structure of a semiconductor device according to the third embodiment.

[0014] Figure 6 This is a cross-sectional view showing an example of the structure of a semiconductor device according to Modification 1 of Embodiment 3.

[0015] Figure 7 This is a diagram showing an example of the structure of a semiconductor device according to Modification 2 of Embodiment 3.

[0016] Figure 8 This is a diagram depicting current vectors in the semiconductor device according to the first embodiment.

[0017] Fig. 9 It is an electron density contour map and a current line plot of the semiconductor device involved in Example 2.

[0018] Fig.10 This is a graph showing the concentration of donor impurities, the concentration of acceptor impurities, and the electron density of the semiconductor device according to Example 2.

[0019] Fig.11 This is a graph showing the electrical characteristics of the semiconductor device according to the third embodiment.

[0020] Fig.12 This is a graph showing the withstand voltage characteristics of the semiconductor devices according to Example 4 and the comparative example.

[0021] Fig.13 This is a graph showing the dependency of the on-resistance on the transistor pitch in the semiconductor device according to the fifth embodiment.

[0022] Fig.14 This is a graph showing the dependence of the on-resistance and the current amplification factor on the distance from the end of the n source region to the source contact in the semiconductor device according to the sixth embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In addition, the present invention is not limited to the following embodiments. In addition, the structural elements in the following embodiments include elements that can be easily thought of by those skilled in the art or substantially the same elements.

[0024] [Implementation Method 1]

[0025] Hereinafter, Embodiment 1 will be described in detail with reference to the drawings.

[0026] (Structural Example of Semiconductor Device)

[0027] Figure 1 FIG. 1 is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the first embodiment. Figure 1 As shown, the semiconductor device 1 of the first embodiment includes a semiconductor substrate 10, an n-type semiconductor layer 15, a p-type gate region 16, an n-type source region 17, a source electrode 21, a gate electrode 22, and a drain electrode 23, wherein the semiconductor substrate 10 includes an n-type semiconductor layer 11, an n-type column region 12, a p-type column region 13, and a p-type channel layer 14. In addition, the source electrode 21, the gate electrode 22, and the drain electrode 23 are referred to for convenience, and these functions are not necessarily specified.

[0028] The semiconductor substrate 10 has an n-type semiconductor layer, i.e., an n-type semiconductor layer 11, at the bottom layer. On the n-type semiconductor layer 11, n-type column regions 12 as first column regions and p-type column regions 13 as second column regions are alternately arranged adjacent to each other. The first column regions are n-type semiconductor regions, and the second column regions are p-type semiconductor regions. These n-type column regions 12 and p-type column regions 13 form a super junction structure. A p-type channel layer 14 as a first semiconductor layer is arranged on the n-type column regions 12 and the p-type column regions 13. The first semiconductor layer is a p-type semiconductor layer.

[0029] An n-type semiconductor layer 15 as a second semiconductor layer is arranged on the p-type channel layer 14, and the second semiconductor layer is an n-type semiconductor layer formed by, for example, epitaxial growth. In the n-type semiconductor layer 15, a p-type gate region 16 as a second semiconductor region is arranged, and the second semiconductor region is a p-type diffusion region that reaches the p-type channel layer 14 from the surface of the n-type semiconductor layer 15. In addition, an n-type source region 17 as a first semiconductor region is arranged on the surface of the n-type semiconductor layer 15 sandwiched by the p-type gate region 16, and the first semiconductor region is an n-type diffusion region. The n-type source region 17 is isolated from the p-type channel layer 14 and the p-type gate region 16 by the n-type semiconductor layer 15. At this time, it is preferable to make the distance between the n-type source region 17 and the p-type gate region 16, for example, 3 μm or more.

[0030] The total amount of impurities in the n-type column region 12 is set to be substantially the same as the total amount of impurities in the p-type column region 13. The impurity concentration of the n-type semiconductor layer 15 is set to be lower than the impurity concentration of the n-type column region 12, for example, to 1×10 15 cm -3 The impurity concentration of the p-type gate region 16 is set higher than the impurity concentration of the p-type channel layer 14 .

[0031] The gate electrode 22 as the second electrode is arranged on the p-type gate region 16 and is connected to the p-type gate region 16 via the gate contact 22c. The source electrode 21 as the first electrode is arranged to cover the entirety and is connected to the n-type source region 17 via the source contact 21c. An insulating layer 31 is arranged between the gate electrode 22 and the source electrode 21, and the gate electrode 22 and the source electrode 21 are insulated. The drain electrode 23 as the third electrode is arranged to cover the entire lower surface of the semiconductor substrate 10 on the n-type semiconductor layer 11 side.

[0032] Next, the operation of the semiconductor device 1 configured as above will be described.

[0033] When semiconductor device 1 is turned on, a positive voltage is applied to drain electrode 23 and a positive voltage is applied to gate electrode 22 so that the drain side has a positive potential relative to the source side. Thus, holes are injected from p-type gate region 16 into n-type source region 17 .

[0034] Furthermore, holes are injected from the p-type gate region 16 into the p-type channel layer 14. The holes injected into the p-type channel layer 14 pass through the p-type channel layer 14 and flow into the p-type column region 13 and the n-type column region 12. Thus, at least the upper structure of the superjunction structure has low resistance due to conductivity modulation.

[0035] On the other hand, electrons are injected from the n-type source region 17 into the p-type channel layer 14. The electrons injected into the p-type channel layer 14 pass through the p-type channel layer 14 and flow into the p-type column region 13 and the n-type column region 12 with low resistance, and finally reach the drain electrode 23. As a result, current flows between the source electrode 21 and the drain electrode 23.

[0036] When the semiconductor device 1 is in the off state, no gate voltage is applied to the gate electrode 22. In this state, when a positive voltage is applied to the drain electrode 23, a depletion layer expands from a plurality of pn junctions between the p-type column region 13 and the n-type column region 12 to both sides of the p-type column region 13 and the n-type column region 12. Thus, the super junction structure is depleted at a low electric field strength, and the semiconductor device 1 can have a high withstand voltage.

[0037] In the semiconductor device 1 of the first embodiment, an n-type semiconductor layer 15 having a low impurity concentration is disposed between the n-type source region 17 and the p-type channel layer 14. In addition, the n-type source region 17 and the p-type gate region 16 are also separated by the n-type semiconductor layer 15. As described above, by setting the impurity concentration of the n-type semiconductor layer 15 to, for example, 1×10 15 cm -3 Hereinafter, the distance between the n-type source region 17 and the p-type gate region 16 is set to, for example, 3 μm or more, so that the withstand voltage of the n-type source region 17 and the p-type gate region 16 is, for example, 50 V or more.

[0038] (Transistor pitch)

[0039] Next, use Figure 1 , a preferred structure of the semiconductor device 1 according to the first embodiment is described.

[0040] In the semiconductor device 1 of the first embodiment, as the pitch W2 of the super junction structure is reduced, the impurity concentration of the n-type column region 12 can be increased, and thus the on-resistance can be reduced.

[0041] On the other hand, the transistor pitch W1 depends on the width of the n-type source region 17, and there is an optimal value for the width of the n-type source region 17. This is because, if the width of the n-type source region 17 increases, the electrons injected from the n-type source region 17 to the p-type channel layer 14 increase, and the moving distance of the holes in the n-type source region 17 and the p-type channel layer 14 becomes longer, and the source resistance and the channel resistance increase.

[0042] Therefore, in the semiconductor device 1 , it is preferred to set the width of the n-type source region 17 while fixing the pitch W2 of the super junction structure so that the on-resistance of the semiconductor device 1 becomes extremely small, and set the pitch W1 of the transistors based on the width of the n-type source region 17 .

[0043] (Thickness of channel layer)

[0044] Next, use Figure 1 as well as Figure 2 , a preferred structure of the semiconductor device 1 according to the first embodiment is described. Figure 2 This is a diagram schematically showing the state of the depletion layer D when the semiconductor device 1 according to the first embodiment is in the off state.

[0045] In the on state, as the thickness WP of the p-type channel layer 14 decreases, the transport efficiency of multiple carriers (electrons) injected from the n-type source region 17 into the p-type channel layer 14 approaches 1, and the current driving capability of the semiconductor device 1 increases.

[0046] On the other hand, when the thickness WP of the p-type channel layer 14 is reduced, the p-type channel layer 14 is easily completely depleted in the off state.

[0047] Therefore, it is preferred to increase the impurity concentration Ich of the p-type channel layer 14 while reducing the thickness WP of the p-type channel layer 14 as much as possible. As a goal, the thickness WP of the p-type channel layer 14 can be made thinner than, for example, the width W3 of the p-type column region 13, and the impurity concentration Ich can be made higher than, for example, the impurity concentration Ico of the p-type column region 13.

[0048] like Figure 2 As shown, by configuring as described above, it is possible to suppress the depletion layer D of the super junction structure from connecting between the source and the drain in the off state, and to maintain a high breakdown voltage.

[0049] (Distance between source region and source contact)

[0050] Next, use Figure 1 , a preferred structure of the semiconductor device 1 according to the first embodiment is described.

[0051] In the semiconductor device 1 of the first embodiment, it is preferable that the distance W4 from the end of the n-type source region 17 to the end of the source contact 21c is greater than a given distance. As a result, the current formed by the minority carriers (holes) injected from the p-type gate region 16 into the n-type source region 17 can be reduced, the gate current is reduced, and the current amplification factor of the semiconductor device 1 can be improved. Here, the current amplification factor of the semiconductor device 1 is drain current / gate current.

[0052] The current value based on the holes injected from the above-mentioned p-type gate region 16 into the n-type source region 17 depends on the diffusion length of the holes in the n-type source region 17. Therefore, the distance W4 from the end of the n-type source region 17 to the end of the source contact 21c is preferably greater than the diffusion length of the holes in the n-type source region 17, and the distance W4 is more preferably greater than 3 times the diffusion length of the holes.

[0053] (Comparative Example)

[0054] Next, use Figure 3 , a semiconductor device of a comparative example is described, and the effect of the semiconductor device 1 of the first embodiment with respect to the semiconductor device of the comparative example is described.

[0055] Figure 3 FIG. 4 is a cross-sectional view showing the structure of a semiconductor device according to a comparative example. Figure 3 As shown, the semiconductor device of the comparative example is configured as a super junction bipolar transistor (SJ-BJT) using a super junction structure in the collector region.

[0056] The semiconductor substrate 50 of the semiconductor device of the comparative example includes, from the bottom layer, an n-type collector layer 51, an n-type buffer layer 52b, an n-type column region 52, a p-type column region 53, and a p-type base layer 56. An n-type emitter region 57 is selectively formed on the surface of the p-type base layer 56 on the n-type column region 52. An emitter electrode 61 connected to the n-type emitter region 57 is arranged on the n-type emitter region 57. A base electrode 62 connected to the p-type base layer 56 is arranged on the p-type base layer 56. The emitter electrode 61 and the base electrode 62 are isolated from each other by an insulating layer 71. A collector electrode 63 is arranged on the lower surface of the semiconductor substrate 50 on the n-type collector layer 51 side.

[0057] In the semiconductor device of the comparative example, in the off state, the depletion layer expands from the multiple pn junctions between the p-type column region 53 and the n-type column region 52 to both sides of the p-type column region 53 and the n-type column region 52, respectively, and a high withstand voltage is achieved by depleting the p-type column region 53 and the n-type column region 52 at a lower electric field strength through the super junction structure. In addition, in the off state, the reverse bias is maintained by the super junction structure, so the depletion layer expands less to the p-type base layer 56, and the p-type base layer 56 can be made thinner. Therefore, in the on state, the injection efficiency of electrons from the emitter region to the collector region can be increased.

[0058] When the semiconductor device of the comparative example is turned on, a positive voltage is applied to the base electrode 62. As a result, holes are injected from the p-type base layer 56 into the n-type emitter region 57, and a collector current flows between the collector and the emitter. In the semiconductor device of the comparative example of SJ-BJT, the impurity concentration of the n-type column region 52 can be made higher than the impurity concentration of the collector layer of the conventional high-breakdown voltage vertical bipolar transistor. Therefore, in the region of high collector current density, the reduction of the current amplification factor caused by the collector resistance can be suppressed.

[0059] A portion of the holes from the p-type base layer 56 flows into the p-type column region 53 and the n-type column region 52, and the resistance of the super junction structure and the n-type buffer layer 52b is reduced by conductivity modulation. Therefore, in the semiconductor device of the comparative example, it is not necessary to apply a voltage greater than the diffusion potential difference like an IGBT, and the collector current flows with the application of the collector voltage.

[0060] As described above, the semiconductor device as a comparative example is configured as an SJ-BJT, and has excellent current rise characteristics. However, in the semiconductor device of the comparative example, the high-concentration p-type base layer 56 is in contact with the high-concentration n-type emitter region 57, and the base / emitter withstand voltage is as low as about 10V to 20V. In addition, in the semiconductor device of the comparative example, when a large current flows instantaneously, such as when the device is turned off, the p-type base layer 56 may be destroyed.

[0061] According to the semiconductor device 1 of the first embodiment, the n-type source region 17 is arranged on the surface of the n-type semiconductor layer 15, separated from the p-type channel layer 14. In addition, the p-type gate region 16 is separated from the n-type source region 17, and reaches the p-type channel layer 14 from the surface of the n-type semiconductor layer 15. As a result, the reverse withstand voltage between the gate and the source is increased, and it is difficult to cause destruction.

[0062] According to the semiconductor device 1 of the first embodiment, the p-type gate region 16 is in contact with the p-type channel layer 14. This reduces the resistance of the current path of a large current that is instantaneously generated at the time of turn-off, and can increase the damage resistance.

[0063] According to the semiconductor device 1 of the first embodiment, the pitch W1 of the transistors is set based on the width of the n-type source region 17 while the pitch W2 of the super junction structure is fixed.

[0064] For example, in the semiconductor device of the comparative example, an n-type emitter region 57 is selectively formed on the n-type column region 52, a p-type base layer 56 is formed on the p-type column region 53, and a base electrode 62 is formed on the p-type base layer 56. In other words, as in the semiconductor device of the comparative example, in the case of SJ-BJT, the pitch of the transistor is the same as the pitch of the super junction.

[0065] On the other hand, in the semiconductor device 1 according to the first embodiment, the width of the n-type source region 17 can be optimized regardless of the pitch W2 of the super junction structure, and thus the on-resistance of the semiconductor device 1 can be suppressed.

[0066] According to the semiconductor device 1 of the first embodiment, the thickness WP of the p-type channel layer 14 is made thinner than the width W3 of the p-type column region 13, and the impurity concentration Ich is made higher than the impurity concentration Ico of the p-type column region 13. Thus, in the on state, the transport efficiency of electrons injected from the n-type source region 17 to the p-type channel layer 14 can be made close to 1. In addition, in the off state, the p-type channel layer 14 can be prevented from being completely depleted, the penetration between the drain and the source can be prevented, and a high withstand voltage can be maintained.

[0067] According to the semiconductor device 1 of the first embodiment, the distance W4 from the end of the n-type source region 17 to the end of the source contact 21c is at least three times the diffusion length of holes. This can reduce holes injected from the p-type gate region 16 into the n-type source region 17 and increase the current amplification factor.

[0068] [Implementation Method 2]

[0069] Next, use Figure 4 , a semiconductor device 2 according to a second embodiment will be described. The semiconductor device 2 according to the second embodiment is different from the above-described first embodiment in that the p-type gate region 18 and the p-type channel layer 14 are not in physical contact.

[0070] Figure 4 2 is a cross-sectional view showing an example of the structure of the semiconductor device 2 according to the second embodiment. Figure 4 In the present invention, the same structures as those in the above-mentioned first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0071] like Figure 4As shown, in the semiconductor device 2 of the second embodiment, the p-type gate region 18 does not reach the p-type channel layer 14. Among them, the p-type gate region 18 is electrostatically connected to the p-type channel layer 14. There is a pnp junction structure between the p-type gate region 18 and the p-type channel layer 14. The state in which the p-type gate region 18 is electrostatically connected to the p-type channel layer 14 means that even if the n-type semiconductor layer 15 is interposed, holes can be injected from the p-type gate region 18 to the p-type channel layer 14. In other words, by adjusting the gradient of the impurity concentration in the pnp junction structure between the p-type gate region 18 and the p-type channel layer 14, even if the p-type gate region 18 and the p-type channel layer 14 are separated, it is possible to operate as the semiconductor device 2.

[0072] Therefore, the on / off operation and on / off characteristics of the semiconductor device 2 according to the second embodiment are the same as those of the semiconductor device 1 according to the first embodiment described above.

[0073] On the other hand, in the semiconductor device 2, since the p-type gate region 18 is not diffused to reach the p-type channel layer 14, a high-temperature and long-term heat treatment is not required in the manufacturing process. As a result, the mutual diffusion of impurities between the n-type column region 12 and the p-type column region 13 is suppressed, and the effective impurity amount in the n-type column region 12 is maintained. The effective impurity amount in the n-type column region 12 contributes to the characteristics in the on state.

[0074] According to the semiconductor device 2 of the second embodiment, the p-type gate region 18 and the p-type channel layer 14 are not physically in contact but are electrically connected. This eliminates the need for high-temperature and long-term heat treatment, and can suppress degradation of the performance of the semiconductor device 2 .

[0075] [Implementation method 3]

[0076] Next, use Figure 5 A semiconductor device 3 according to a third embodiment will be described. The semiconductor device 3 according to the third embodiment is different from the first and second embodiments described above in that it includes a p-type embedded gate region 19 .

[0077] Figure 5 This is a diagram showing an example of the structure of a semiconductor device 3 according to the third embodiment. Figure 5 (a) is a longitudinal sectional view of the semiconductor device 3 . Figure 5 (b) is Figure 5 (a) is a cross-sectional view of the semiconductor device 3 taken along line AA. Figure 5 In the present invention, the same structures as those in the above-mentioned embodiments 1 and 2 are denoted by the same reference numerals, and their descriptions are omitted.

[0078] like Figure 5As shown in (a), the semiconductor device 3 of the third embodiment has a p-type embedded gate region 19 as a third semiconductor region in the p-type channel layer 14 below the p-type gate region 18, and the third semiconductor region is a p-type diffusion region. The semiconductor device 3 may also have a p-type gate region 16 reaching the p-type embedded gate region 19 as in the first embodiment described above.

[0079] For example, after forming a p-type channel layer 14 on a semiconductor substrate 10, a p-type impurity is further diffused into a given area at a high concentration, thereby forming a p-type embedded gate region 19. After forming an n-type semiconductor layer 15 as an epitaxial layer, a portion of the p-type impurity that has been diffused at a high concentration is also diffused into the n-type semiconductor layer 15 to form a p-type embedded gate region 19 that is thicker than the p-type channel layer 14.

[0080] The region where the p-type embedded gate region 19 is configured is in an area where the p-type gate region 18 is electrostatically connected to the p-type channel layer 14, and becomes a current path for a large current generated instantly at shutdown. The p-type embedded gate region 19 having a high concentration of p-type impurities reduces the resistance of the current path.

[0081] like Figure 5 As shown in (b), the n-type source region 17, the p-type gate region 18, and the p-type embedded gate region 19 of the semiconductor device 3 extend in a direction along the p-type channel layer 14. The direction along the p-type channel layer 14 includes a direction parallel to the p-type channel layer 14 and a direction substantially parallel to the p-type channel layer 14.

[0082] In addition, a plurality of n-type source regions 17, p-type gate regions 18, and p-type embedded gate regions 19 are arranged in a direction intersecting the extension direction. In other words, the n-type source regions 17, p-type gate regions 18, and p-type embedded gate regions 19 are arranged in a periodic pattern in a direction intersecting the extension direction. The direction intersecting the extension direction includes a direction orthogonal to the extension direction and a direction substantially orthogonal to the extension direction.

[0083] In addition, the n-type column region 12 and the p-type column region 13 of the semiconductor device 3 extend in a direction along the extension direction of the n-type source region 17, the p-type gate region 18, and the p-type embedded gate region 19. The direction along the extension direction includes a direction parallel to the extension direction and a direction substantially parallel to the extension direction. In addition, a plurality of n-type column regions 12 and p-type column regions 13 are arranged in a direction intersecting with their own extension directions. In other words, the n-type column regions 12 and p-type column regions 13 are arranged in a periodic pattern in a direction intersecting with the extension direction.

[0084] In addition, Figure 5The region indicated by oblique lines in (b) is a region where the p-type embedded gate region 19 and the p-type column region 13 overlap in a plan view.

[0085] According to the semiconductor device 3 of the third embodiment, the p-type embedded gate region 19 is disposed in the region of the p-type channel layer 14 electrically connected to the p-type gate region 18. This reduces the resistance of the current path of the large current generated instantaneously at the time of shutdown, and can suppress the operation of parasitic elements and improve the anti-destructive performance.

[0086] (Variant 1)

[0087] Next, use Figure 6 A semiconductor device according to a first variation of the third embodiment will be described. In the semiconductor device according to the first variation, the extending directions of the n-type column region 12 a and the p-type column region 13 a are different from those in the first to third embodiments described above.

[0088] Figure 6 1 is a cross-sectional view showing an example of the structure of a semiconductor device according to a first variation of the third embodiment. More specifically, Figure 6 is with Figure 5 A cross-sectional view of the semiconductor device of Modification 1 taken at the same position as line AA in (a).

[0089] like Figure 6 As shown, the n-type column region 12a and the p-type column region 13a of the semiconductor device of Modification Example 1 extend in a direction intersecting with the extending direction of the n-type source region 17, the p-type gate region 18, and the p-type embedded gate region 19. In addition, a plurality of n-type column regions 12a and p-type column regions 13a are arranged in a direction intersecting with their own extending directions. Figure 6 In FIG. 1 , the region indicated by oblique lines is a region where the p-type embedded gate region 19 and the p-type column region 13 a overlap in a plan view.

[0090] The region where the p-type embedded gate region 19 overlaps with the p-type column region 13a becomes a region that blocks the flow of electrons injected from the n-type source region 17 toward the drain side in the on state. In the semiconductor device of the first variant, the region where the p-type embedded gate region 19 overlaps with the p-type column region 13a is approximately halved compared to the region where the p-type embedded gate region 19 overlaps with the p-type column region 13 in the semiconductor device 3 of the third embodiment described above.

[0091] According to the semiconductor device of Modification 1, the p-type embedded gate region 19 extends in a direction along the p-type channel layer 14, and the p-type column region 13a extends in a direction intersecting the extending direction of the p-type embedded gate region 19. Thus, the ratio of the area where the p-type embedded gate region 19 and the p-type column region 13a overlap can be reduced, and the drain current can be increased in the on state.

[0092] (Variant 2)

[0093] Next, use Figure 7 Next, a semiconductor device 4 according to a second modification of the third embodiment will be described. The semiconductor device 4 according to the second modification is different from the first to third embodiments described above in that a source contact 21ca is arranged in an island shape.

[0094] Figure 7 This is a diagram showing an example of the structure of a semiconductor device 4 according to a second modification of the third embodiment. Figure 7 (a) is a longitudinal cross-sectional view of the semiconductor device 4 . Figure 7 (b) is Figure 7 FIG. 1 is a cross-sectional view of the semiconductor device 4 taken along line BB in FIG.

[0095] like Figure 7 As shown in (b), the source contacts 21ca are separated into islands and are arranged in a dispersed manner in the extending direction of the n-type source region 17 .

[0096] Figure 7 (a) is Figure 7 The longitudinal cross-sectional view of the semiconductor device 4 taken along the CC line in (b) is a longitudinal cross-sectional view at a position where the source contact 21ca does not exist.

[0097] According to the semiconductor device 4 of the second modification, the source contacts 21ca are arranged in a dispersed manner in the extending direction of the n-type source region 17. Thus, the effective distance (equivalent to 100 m) from the end of the n-type source region 17 to the end of the source contact 21ca can be further increased. Figure 1 By increasing the distance W4 in the p-type gate region 16, it is possible to reduce the minority carriers injected from the p-type gate region 16 into the n-type source region 17. Therefore, the current amplification factor in the semiconductor device 4 can be further increased.

[0098] The structure of the semiconductor device 4 according to the second modification is applicable not only to the semiconductor device 3 according to the third embodiment but also to the semiconductor devices 1 and 2 according to the first and second embodiments described above.

[0099] Furthermore, in the above-mentioned Embodiments 1 to 3 and Modifications 1 and 2 thereof, an n-channel transistor is described as an example, but these structures can also be applied to a p-channel transistor in which the conductivity type of each component is inverted.

[0100] [Example]

[0101] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0102] (Example 1)

[0103] Figure 8 This is a diagram depicting current vectors in the semiconductor device according to the first embodiment. Figure 8 (a) is a diagram depicting the hole current vector, Figure 8 (b) is a diagram depicting the electron current vector.

[0104] exist Figure 8 In the embodiment 1, the semiconductor device has the same structure as the semiconductor device 2 of the embodiment 2, and the device simulation result of the semiconductor device of the embodiment 1 in the on state is enlarged and displayed in the vicinity of the n-type source region 17, the p-type gate region 18, and the p-type channel layer 14. Figure 8 In the drawings, for convenience, the same reference numerals are used to denote structures corresponding to those of the semiconductor device 2 according to the second embodiment.

[0105] exist Figure 8 In the vector display of hole current (a), the direction of the vector is the direction of hole movement. Figure 8 As shown in (a), in the on state, holes are injected from the p-type gate region 18 toward the n-type source region 17 and the p-type channel layer 14. The holes injected into the p-type channel layer 14 flow into the p-type column region 13 and the n-type column region 12.

[0106] exist Figure 8 In the vector display of the electron current (b), the opposite direction of the vector is the direction of electron movement. Figure 8 As shown in (b), in the on state, electrons are injected from the n-type source region 17 toward the p-type channel layer 14. The electrons injected into the p-type channel layer 14 flow into the p-type column region 13 and the n-type column region 12. Thereafter, the electrons reach the drain electrode 23, and current flows between the source electrode 21 and the drain electrode 23.

[0107] according to Figure 8 The simulation results can understand the behavior of holes and electrons in the n-type source region 17, the p-type gate region 18 and the vicinity of the p-type channel layer 14, and confirm the operation of the semiconductor devices 1 to 3, 4, etc. of the above-mentioned embodiments 1 to 3 and their modified examples 1 and 2.

[0108] (Example 2)

[0109] Next, use Fig. 9 as well as Fig.10 , the semiconductor device of Example 2 is described.

[0110] Fig. 9 2 is an electron density contour map and a current line map of the semiconductor device involved in Example 2. Fig. 9 In , the electron density contour plot and the current line plot are superimposed. Fig. 9 The lighter the color, the higher the electron density.

[0111] exist Fig. 9 In the figure, the semiconductor device of Example 2 is assumed to have the same structure as the semiconductor device 2 of Embodiment 2, and the device simulation result of the semiconductor device of Example 2 in the on state is enlarged and displayed in the vicinity of the n-type column region 12 and the p-type column region 13. Fig. 9 In the drawings, for convenience, the same reference numerals are used to denote structures corresponding to those of the semiconductor device 2 according to the second embodiment.

[0112] Fig.10 This is a graph showing the concentration of donor impurities, the concentration of acceptor impurities, and the electron density of the semiconductor device according to Example 2. Fig.10 (a) is Fig. 9 The DD line shows the depth position of the graph, Fig.10 (b) is Fig. 9 The EE line is shown in the graph at the depth position. Fig.10 The concentrations of donor impurities, acceptor impurities, and electron density shown are also based on simulations.

[0113] like Fig. 9 as well as Fig.10 As shown in FIG. 1 , the electron density increases in the upper part of the superjunction structure. This is because, as described above, holes are injected from the p-type gate region 16 into the n-type column region 12 and the p-type column region 13 via the p-type channel layer 14, so the charge neutrality condition is maintained. Fig. 9 As shown in the current line drawing of , the electron current spreads to both the n-type column region 12 and the p-type column region 13 .

[0114] like Fig. 9 as well as Fig.10 As shown in FIG. 1 , the electron density decreases in the lower part of the super junction structure. The electron density is the same as the donor impurity concentration in the n-type column region 12, and is lower than the acceptor impurity concentration in the p-type column region 13. This is because the number of holes injected into the n-type column region 12 and the p-type column region 13 gradually decreases as they go down the super junction structure. As a result, the conductivity modulation effect is weakened in the lower part of the super junction structure, as shown in FIG. Fig. 9 As shown in the current line drawing of , it seems that the electron current flows exclusively in the n-type column region 12 .

[0115] As described above, in the semiconductor device of the second embodiment, in the on-state, the resistance is mainly reduced in the upper portion of the super junction structure due to conductivity modulation.

[0116] (Example 3)

[0117] Next, use Fig.11 The semiconductor device according to the third embodiment will be described. Fig.11 This is a graph showing the electrical characteristics of the semiconductor device according to the third embodiment.

[0118] Fig.11 It is a diagram showing device simulation results of the semiconductor device of Example 3, assuming that the semiconductor device of Example 3 has the same structure as the semiconductor device 2 of the second embodiment.

[0119] like Fig.11 As shown, it is predicted that the semiconductor device of Example 3 has a steep rise in drain current in the saturation region and has good electrical characteristics.

[0120] (Example 4)

[0121] Next, use Fig.12 A semiconductor device according to a fourth embodiment will be described. Fig.12 This is a graph showing the withstand voltage characteristics of the semiconductor devices according to Example 4 and the comparative example.

[0122] The semiconductor device of Example 4 is assumed to have the same structure as the semiconductor device 2 of Embodiment 2. The semiconductor device of the comparative example is the above-mentioned Figure 3 The breakdown voltage when a reverse bias is applied to the gate electrode and source electrode of these semiconductor devices was simulated.

[0123] like Fig.12 As shown, the withstand voltage of the semiconductor device of the comparative example is less than 20V, whereas the withstand voltage of the semiconductor device of Example 4 is 50V or more.

[0124] (Example 5)

[0125] Next, use Fig.13 , the semiconductor device of Example 5 is described.

[0126] Fig.13 This is a graph showing the dependency of the on-resistance Ron on the transistor pitch in the semiconductor device according to the fifth embodiment. Fig.13 The horizontal axis of the graph of shows the transistor spacing in terms of the number of p-type column regions included between transistors. In other words, if Figure 1 In the example of the semiconductor device 1 according to the first embodiment shown, the number of p-type column regions 13 included between transistors is two, and the transistor pitch is two.

[0127] Fig.13 In the embodiment, the semiconductor device of the fifth embodiment is assumed to have the same structure as the semiconductor device 2 of the second embodiment, and the transistor pitch of the semiconductor device of the fifth embodiment is changed to plot the device simulation results. More specifically, in Fig.13 In the embodiment of the present invention, the width of the n-type source region is changed, and the transistor pitch is changed accordingly. In addition, the pitch of the super junction structure is set to be fixed at this time.

[0128] like Fig.13 As shown, in the semiconductor device of Example 5, as the transistor pitch increases, the on-resistance Ron temporarily decreases. This is because, as described above, by increasing the width of the n-type source region, the number of electrons injected from the n-type source region into the p-type channel layer increases.

[0129] In addition, in the semiconductor device of Example 5, as the transistor pitch increases, the on-resistance Ron that has been temporarily reduced increases again. This is because, as described above, the width of the n-type source region increases, thereby increasing the moving distance of holes in the n-type source region and the p-type channel layer, and the source resistance and the channel resistance increase.

[0130] As can be seen from the above, the transistor pitch has an optimal value, and the on-resistance can be reduced by making the width of the n-type source region appropriate.

[0131] (Example 6)

[0132] Next, use Fig.14 , the semiconductor device of Example 6 is described. Fig.14 This is a graph showing the dependence of the on-resistance Ron and the current amplification factor hFE in the semiconductor device according to Example 6 on the distance from the end of the n-type source region to the source contact.

[0133] Fig.14 In the embodiment, the semiconductor device of the sixth embodiment has the same structure as the semiconductor device 2 of the second embodiment, and the distance from the end of the n-type source region to the end of the source contact of the semiconductor device of the sixth embodiment is set to be equal to Figure 1 The device simulation results are plotted as the distance W4) changes.

[0134] like Fig.14As shown in FIG. 1 , in the semiconductor device of Example 6, as the distance from the end of the n-type source region to the end of the source contact increases, the current amplification factor hFE (= drain current / gate current) increases. This is because as the distance from the end of the n-type source region to the end of the source contact increases, the current caused by the holes injected from the p-type gate region into the n-type source region decreases, so the gate current decreases. On the other hand, even if the distance from the end of the n-type source region to the end of the source contact is changed, the influence on the on-resistance Ron is small.

[0135] As can be seen from the above, by lengthening the distance from the end of the n-type source region to the end of the source contact, the current amplification factor can be increased without increasing the on-resistance.

[0136] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the claims and their equivalents.

[0137] According to the present invention, it is possible to obtain a semiconductor device which has high withstand voltage characteristics and can suppress destruction due to transient large current.

[0138] -Explanation of symbols-

[0139] 1-3 Semiconductor devices

[0140] 11 n-type semiconductor layer

[0141] 12 n-type column area

[0142] 13 p-type column region

[0143] 14 p-type channel layer

[0144] 15 n-type semiconductor layer

[0145] 16, 18 p-type gate region

[0146] 17 n-type source region

[0147] 19 p-type embedded gate region

[0148] 21 Source electrode

[0149] 21c source contact

[0150] 22. Gate electrode

[0151] 22c Gate contact

[0152] 23 Drain electrode

[0153] 31 Insulation layer.

Claims

1. A semiconductor device having a super junction structure formed by a first row region of a first conductivity type and a second row region of a second conductivity type arranged adjacent to the first row region, The semiconductor device further comprises: A first electrode and a second electrode are disposed on one side of the superjunction structure, forming a transistor and controlling a current flowing through the transistor; and A third electrode is arranged on the opposite side of the first electrode and the second electrode across the super junction structure to constitute the transistor. The semiconductor device comprises: A first semiconductor layer, which is of the second conductivity type and is disposed on the first column region and the second column region; A second semiconductor layer, of the first conductivity type, disposed on the first semiconductor layer; A first semiconductor region, which is of the first conductivity type and is electrically connected to the first electrode and is disposed on a surface portion of the second semiconductor layer so as to be separated from the first semiconductor layer; as well as The second semiconductor region is of the second conductivity type, is electrically connected to the second electrode, is disposed at least on the surface of the second semiconductor layer so as to be separated from the first semiconductor region, and is electrically connected to the first semiconductor layer.

2. The semiconductor device according to claim 1, wherein The second semiconductor region is not in contact with the first semiconductor layer.

3. The semiconductor device according to claim 1, wherein A third semiconductor region of the second conductivity type is arranged in a region of the first semiconductor layer electrically connected to the second semiconductor region.

4. The semiconductor device according to claim 3, wherein: The third semiconductor region extends in a first direction along the first semiconductor layer, The first row of regions and the second row of regions are arranged in the first direction and extend in a second direction intersecting the first direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein A contact connecting the first semiconductor region and the first electrode is provided on the first semiconductor region. The first semiconductor region extends in a third direction along the first semiconductor layer, The contacts are arranged in a dispersed manner in the third direction.

Images