Method for manufacturing semiconductor structure
By forming a sacrificial layer and a semiconductor active layer on the substrate and removing the sacrificial layer by using an annular trench, the problems of high cost and poor quality of GaN devices are solved, and low-cost and high-quality semiconductor structure production is achieved.
Patent Information
- Application Number
- CN201980102369.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-12-13
- Publication Date
- 2025-08-26
- Estimated Expiration
- 2039-12-13
AI Technical Summary
In the prior art, the laser peeling cost of GaN devices is high and the quality is poor, which easily leads to device damage.
The sacrificial layer and the semiconductor active layer are formed on the substrate, and the annular trench is patterned and the sacrificial layer is removed, so that the semiconductor active layer is separated from the substrate, and the sacrificial layer is etched or removed by dry or wet method to avoid thermal process damage.
It realizes the production of semiconductor structures in a low-cost and large-scale manner, with good peeling quality and no damage to the semiconductor active layer, and is suitable for the preparation of LED components of different sizes.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art
[0002] Group III nitride semiconductor substrates represented by GaN are receiving more and more attention because group III nitride semiconductor substrates can be widely used as light emitting diodes (LEDs) for semiconductor lighting, high-power power electronics and radio frequency devices.
[0003] In the industry, GaN devices are commonly fabricated on foreign substrates, such as sapphire, silicon carbide, and silicon, and then the foreign substrate is removed by laser lift-off. Laser lift-off technology uses a laser of a specific wavelength to irradiate the interface between the GaN device and the foreign substrate. The GaN material at the interface absorbs the laser energy and decomposes into Ga metal and nitrogen, thus separating the GaN device from the foreign substrate.
[0004] However, laser lift-off technology is expensive. Furthermore, the easy oxidation of Ga metal to form easily adherent gallium-based oxides results in poor lift-off quality. Heat exposure to GaN material generates thermal stress, which degrades quality and can damage devices.
[0005] In view of this, it is necessary to provide a new method for manufacturing a semiconductor structure to solve the above technical problems. Summary of the Invention
[0006] The purpose of the present invention is to provide a method for manufacturing a semiconductor structure, which can improve the peeling quality, avoid damaging the device and reduce the cost.
[0007] To achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, comprising:
[0008] Providing a substrate, the substrate comprising a plurality of device regions and a peripheral region surrounding each of the device regions;
[0009] forming a sacrificial layer on the substrate, and patterning the sacrificial layer to at least retain the sacrificial layer in the device area;
[0010] forming a semiconductor active layer on the sacrificial layer and the substrate; patterning the semiconductor active layer to remove the semiconductor active layer in the peripheral region to form a plurality of annular grooves, thereby separating the semiconductor active layers in each device region;
[0011] The sacrificial layer of each device region is removed through the annular trench, so that the discrete semiconductor active layer is separated from the substrate, and each separated semiconductor active layer forms a semiconductor structure.
[0012] Optionally, when patterning the sacrificial layer, the retained sacrificial layer extends from the device area to the peripheral area; when patterning the semiconductor active layer, the sacrificial layer in the peripheral area is also removed or the annular trench exposes the sacrificial layer in the peripheral area.
[0013] Optionally, dry etching or wet etching is used to remove the sacrificial layer in the peripheral area.
[0014] Optionally, dry etching or wet etching is used to remove the sacrificial layer in each device region.
[0015] Optionally, the peripheral regions are connected together.
[0016] Optionally, forming a semiconductor active layer on the sacrificial layer and the substrate includes: forming a transition layer on the sacrificial layer and the substrate, and forming a semiconductor active layer on the transition layer; and patterning the transition layer when patterning the semiconductor active layer.
[0017] Optionally, before forming the semiconductor active layer, the transition layer is subjected to high-temperature annealing to form the transition layer into a single crystal material.
[0018] Optionally, before, during, or after the sacrificial layer of each of the device regions is removed, a carrier is provided on the semiconductor active layer of at least a portion of the device regions.
[0019] Optionally, the cross-sectional shape of the semiconductor active layer in the device area is polygonal, and the cross-sectional shape of the semiconductor active layer in the peripheral area is a polygonal ring; or the cross-sectional shape of the semiconductor active layer in the device area is circular or elliptical, and the cross-sectional shape of the semiconductor active layer in the peripheral area is a circular ring or an elliptical ring accordingly.
[0020] Optionally, the semiconductor active layer includes a GaN-based material.
[0021] Optionally, the GaN-based material includes at least one of GaN, AlGaN, and AlInGaN.
[0022] Optionally, the material of the transition layer includes at least one of AlN, SiAlN, and AlGaN.
[0023] Optionally, the material of the sacrificial layer includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride.
[0024] Optionally, the semiconductor active layer includes a P-type semiconductor layer, an N-type semiconductor layer, and a light-emitting material layer located between the P-type semiconductor layer and the N-type semiconductor layer.
[0025] Compared with the prior art, the present invention has the following beneficial effects:
[0026] 1) In the semiconductor structure manufacturing method of the present invention, a substrate is first provided, the substrate including a plurality of device regions and a peripheral region surrounding each device region; a sacrificial layer is then formed on each device region, and a semiconductor active layer is formed on the sacrificial layer and the substrate not covered by the sacrificial layer; the semiconductor active layer is then patterned to remove the semiconductor active layer in the peripheral region to form a plurality of annular grooves, the annular grooves exposing the sacrificial layer and also separating the semiconductor active layers in each device region; the sacrificial layer in each device region is then removed through the annular grooves, thereby separating the separated semiconductor active layers from the substrate, with each separated semiconductor active layer forming a semiconductor structure. The above method can simultaneously manufacture multiple semiconductor structures by removing the sacrificial layer, that is, it can realize the simultaneous manufacture of semiconductor structures in large quantities at a low cost; in addition, the material of the sacrificial layer is different from the material of the semiconductor active layer, and the substrate can be peeled off by removing the sacrificial layer, with good peeling quality. At the same time, the peeling process does not require a thermal process and will not cause damage to the semiconductor active layer.
[0027] 2) In an alternative solution, when patterning the sacrificial layer, the remaining sacrificial layer extends from the device area to the peripheral area; when patterning the semiconductor active layer, either a) the sacrificial layer in the peripheral area is also removed, or b) the sacrificial layer in the peripheral area is exposed by forming an annular trench. In another alternative solution, c) when patterning the sacrificial layer, only the sacrificial layer in the device area is retained, and when patterning the semiconductor active layer to form an annular trench, the sidewalls of the sacrificial layer in the device area are exposed within the annular trench. All three of the above solutions can achieve the removal of the sacrificial layer in the device area.
[0028] 3) In an optional solution, dry etching or wet etching is used to remove the sacrificial layer in the peripheral area. The present invention does not limit the method for removing the sacrificial layer in the peripheral area.
[0029] 4) In an optional solution, dry etching or wet etching is used to remove the sacrificial layer in each device area. Using a dry etching gas or wet etching solution with a high selectivity for the sacrificial layer can ensure that the semiconductor active layer in the device area is not damaged while removing the sacrificial layer.
[0030] 5) In an optional solution, forming the semiconductor active layer on the sacrificial layer and the substrate includes forming a transition layer on the sacrificial layer and the substrate, and forming the semiconductor active layer on the transition layer; and patterning the transition layer when patterning the semiconductor active layer. The transition layer can improve the quality of the grown semiconductor active layer.
[0031] 6) In an optional solution, before forming the semiconductor active layer, the transition layer is subjected to high temperature annealing to form a single crystal material for the transition layer. Single crystal material is beneficial to improving the quality of the semiconductor active layer formed thereon.
[0032] 7) In an alternative embodiment, the semiconductor active layer includes a P-type semiconductor layer, an N-type semiconductor layer, and a light-emitting material layer located between the P-type semiconductor layer and the N-type semiconductor layer. The semiconductor active layer forms an LED device. In other alternative embodiments, the semiconductor active layer can also form other semiconductor structures, which are not limited by the present invention.
[0033] The manufacturing method disclosed in this application is simple and low-cost, and can be applied to the preparation of components with different size requirements, for example, it can be used to prepare LED components above 200 μm, and can also be used to prepare LED components below 50 μm, including 2-15 μm level. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention;
[0035] Figures 2 to 8 yes Figure 1 Schematic diagram of the intermediate structure corresponding to the process in;
[0036] Figures 9 to 11 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a second embodiment of the present invention;
[0037] Figure 12 It is a schematic diagram of an intermediate structure corresponding to the method for manufacturing a semiconductor structure according to the third embodiment of the present invention.
[0038] To facilitate understanding of the present invention, all reference numerals appearing in the present invention are listed below:
[0039] Substrate 10 Device region 10a
[0040] Peripheral region 10b Sacrificial layer 11
[0041] Transition layer 12 Semiconductor active layer 13
[0042] Annular trench 14 P-type semiconductor layer 131
[0043] N-type semiconductor layer 132 Light emitting material layer 133
[0044] Carrier 20 Semiconductor structures 1, 2, 3 DETAILED DESCRIPTION
[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0046] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention; Figures 2 to 8 yes Figure 1Schematic diagram of the intermediate structure corresponding to the process in .
[0047] First, refer to Figure 1 Step S1, Figure 2 and Figure 3 As shown, a substrate 10 is provided. The substrate 10 includes a plurality of device regions 10 a and a peripheral region 10 b surrounding each device region 10 a.
[0048] The material of the substrate 10 can be sapphire, silicon carbide, silicon, etc.
[0049] Reference Figure 2 and Figure 3 As shown, the six adjacent device regions 10a of each device region 10a are arranged in a regular hexagon. In other embodiments, the device regions 10a may also be arranged in other ways.
[0050] like Figure 2 As shown in FIG, the device region 10a may be rectangular, and the corresponding peripheral region 10b may be a rectangular ring; or Figure 3 As shown in FIG, the device region 10a is circular, and the corresponding peripheral region 10b is annular. In other embodiments, the device region 10a can also be other polygons besides a rectangle, or even an ellipse. The present invention does not limit the shapes of the device region 10a and the peripheral region 10b.
[0051] like Figure 2 and Figure 3 As shown in FIG, the peripheral region 10b of each device region 10a may be connected together.
[0052] Figure 5 It is along Figure 4 Next, refer to the AA line in the figure. Figure 1 Step S2 in Figure 5 As shown, a sacrificial layer 11 is formed on a substrate 10 and patterned, and at least the sacrificial layer 11 in the device region 10 a is retained.
[0053] The material of the sacrificial layer 11 may include at least one of silicon dioxide, silicon nitride, and silicon oxynitride, and may be formed by physical vapor deposition or chemical vapor deposition. The patterning of the sacrificial layer 11 may be achieved by dry etching or wet etching.
[0054] Figure 5 In the illustrated embodiment, when the sacrificial layer 11 is patterned, only the sacrificial layer 11 in the device region 10 a is retained.
[0055] Afterwards, refer to Figure 1 Step S3 in Figure 5 As shown, a semiconductor active layer 13 is formed on the sacrificial layer 11 and the substrate 10; Figure 6 and Figure 7As shown, the semiconductor active layer 13 is patterned to remove the semiconductor active layer 13 in the peripheral region 10b to form a plurality of annular grooves 14, so that the semiconductor active layer 13 in each device region 10a is separated. Figure 7 It is along Figure 6 Cross-sectional view of line BB in.
[0056] In an optional solution, forming the semiconductor active layer 13 on the sacrificial layer 11 and the substrate 10 includes: first forming the transition layer 12 on the sacrificial layer 11 and the substrate 10 , and then forming the semiconductor active layer 13 on the transition layer 12 .
[0057] The material of the transition layer 12 can include at least one of AlN, SiAlN, and AlGaN. The transition layer 12 helps improve the crystal quality of the subsequent semiconductor active layer 13. For example, the transition layer 12 can be formed first using physical vapor deposition (PVD) and then metal-organic chemical vapor deposition (MOCVD); or it can be formed using lateral epitaxial growth.
[0058] In an optional solution, the transition layer 12 can be subjected to high-temperature annealing to form a single-crystalline material, thereby further improving the crystal quality of the semiconductor active layer 13. Specifically, the transition layer 12 can be prepared in a PVD device, and then subjected to high-temperature annealing in an MOCVD device, thereby obtaining a high-quality single-crystalline transition layer 12.
[0059] The semiconductor active layer 13 may include a GaN-based material, and the GaN-based material may include at least one of GaN, AlGaN, and AlInGaN.
[0060] The formation process of GaN-based materials may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition, or a combination thereof.
[0061] Figure 5In the illustrated embodiment, the semiconductor active layer 13 includes a P-type semiconductor layer 131, an N-type semiconductor layer 132, and a light-emitting material layer 133 located between the P-type semiconductor layer 131 and the N-type semiconductor layer 132. In other words, the semiconductor active layer 13 forms an LED device. In other alternatives, the semiconductor active layer 13 can also form other semiconductor structures, which are not limited by the present invention.
[0062] When the semiconductor active layer 13 is patterned, the transition layer 12 is also patterned. The patterning of the semiconductor active layer 13 and the transition layer 12 can be achieved by dry etching or wet etching. Figure 6 and Figure 7 As shown, one of the purposes of patterning the semiconductor active layer 13 and the transition layer 12 is to expose the sidewall of the sacrificial layer 11 of the device region 10 a in the annular trench 14 .
[0063] Afterwards, refer to Figure 1 Step S4 in Figure 7 and Figure 8 As shown, the sacrificial layer 11 of each device region 10 a is removed through the annular trench 14 , so that the discrete semiconductor active layer 13 is separated from the substrate 10 . Each separated semiconductor active layer 13 forms a semiconductor structure 1 .
[0064] Removal of the sacrificial layer 11 in each device region 10 a may be achieved by dry etching or wet etching.
[0065] When the material of the sacrificial layer 11 is silicon dioxide, silicon nitride, or silicon oxynitride, the dry etching gas may be CF4, C3F8, or the like. Since the material of the sacrificial layer 11 is different from that of the semiconductor active layer 13, a dry etching gas with a high etching selectivity for the sacrificial layer 11 is used to ensure that the semiconductor active layer 13 in the device region 10a is not damaged while the sacrificial layer 11 is removed.
[0066] A separate semiconductor active layer 13 is used to form a semiconductor structure 1 .
[0067] For the solution with the transition layer 12 , the transition layer 12 and the semiconductor active layer 13 may form a semiconductor structure 1 .
[0068] In one option, Figure 8 As shown, at the end of the dry etching process to remove the sacrificial layer 11, a carrier 20 is placed on at least a portion of the semiconductor active layer 13 in the device area 10a. Then, as needed, a portion or all of the semiconductor structures 1 are transferred to the carrier 20 by mechanical breaking. In other optional solutions, after the sacrificial layer 11 is removed by dry etching, a carrier 20 may be placed on each separate semiconductor active layer 13.
[0069] When the material of the sacrificial layer 11 is silicon dioxide or silicon oxynitride, the wet etching solution may be HF acid; when the material of the sacrificial layer 11 is silicon nitride, the wet etching solution may be hot phosphoric acid.
[0070] In one option, Figure 2 and Figure 3 As shown, when the peripheral regions 10b are connected and at least one peripheral region 10b is located on the sidewall of the substrate 10, that is, exposed to the outside world, a carrier 20 is placed on the semiconductor active layer 13 of at least a portion of the device regions 10a before wet etching to remove the sacrificial layer 11 of each device region 10a. In this optional solution, the semiconductor structure with the carrier 20 is placed in a wet etching solution, and the solution can begin to etch the sacrificial layer 11 of each device region 10a through the sidewall of the substrate 10 until each discrete semiconductor active layer 13 (and the transition layer 12) is separated from the substrate 10.
[0071] It can be seen that the above-mentioned method of removing the sacrificial layer 11 can simultaneously produce multiple semiconductor structures 1, that is, a large number of semiconductor structures 1 can be produced simultaneously at a low cost; in addition, the material of the sacrificial layer 11 is different from the material of the semiconductor active layer 13. The substrate 10 can be peeled off by removing the sacrificial layer 11, and the peeling quality is good. At the same time, the peeling process does not require a thermal process and will not cause damage to the semiconductor active layer 13.
[0072] Figures 9 to 11 FIG. 1 is a schematic diagram of an intermediate structure corresponding to the method for manufacturing a semiconductor structure according to the second embodiment of the present invention. Figures 9 to 11 As shown, the manufacturing method of the semiconductor structure 2 of the second embodiment is substantially the same as the manufacturing method of the semiconductor structure 1 of the first embodiment, with the only difference being that: in step S1, the peripheral regions 10b of each device region 10a are not connected to each other; and in step S5, regardless of whether dry etching or wet etching is used to remove the sacrificial layer 11 of each device region 10a, the carrier 20 can only be disposed on the semiconductor active layer 13 of each device region 10a at the end of the process of removing the sacrificial layer 11 or after the removal.
[0073] In other embodiments, the peripheral regions 10b of a portion of the device regions 10a may be connected together; and the peripheral regions 10b of another portion of the device regions 10a may not be connected to each other.
[0074] Figure 12 FIG. 1 is a schematic diagram of an intermediate structure corresponding to the method for manufacturing a semiconductor structure according to the third embodiment of the present invention. Figure 12As shown, the manufacturing method of the semiconductor structure 3 of the present embodiment 3 is substantially the same as the manufacturing method of the semiconductor structures 1 and 2 of the embodiments 1 and 2, with the only difference being that: in step S2, when patterning the sacrificial layer 11, the retained sacrificial layer 11 extends from the device area 10a to the peripheral area 10b; and in step S4, when patterning the semiconductor active layer 13 (and the transition layer 12), the sacrificial layer 11 in the peripheral area 10b is also removed or the annular trench 14 is removed to expose the sacrificial layer 11 in the peripheral area 10b.
[0075] The manufacturing method disclosed in this application is simple and low-cost, and can be applied to the preparation of components with different size requirements, for example, it can be used to prepare LED components above 200 μm, and can also be used to prepare LED components below 50 μm, including 2-15 μm level.
[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: A substrate (10) is provided, wherein the substrate (10) includes a plurality of device regions (10a) and a peripheral region (10b) surrounding each of the device regions (10a); the peripheral regions (10b) are connected, and at least one of the peripheral regions (10b) is located on a sidewall of the substrate (10); forming a sacrificial layer (11) on the substrate (10), patterning the sacrificial layer (11), and retaining at least the sacrificial layer (11) in the device region (10a); forming a semiconductor active layer (13) on the sacrificial layer (11) and the substrate (10); patterning the semiconductor active layer (13) to remove the semiconductor active layer (13) in the peripheral region (10b) to form a plurality of annular grooves (14), thereby separating the semiconductor active layers (13) in each device region (10a); The sacrificial layer (11) of each device region (10a) is removed through the annular groove (14), so that the discrete semiconductor active layer (13) is separated from the substrate (10), and each separated semiconductor active layer (13) forms a semiconductor structure (1).
2. The method for manufacturing a semiconductor structure according to claim 1, wherein: When the sacrificial layer (11) is patterned, the retained sacrificial layer (11) extends from the device area (10a) to the peripheral area (10b); and when the semiconductor active layer (13) is patterned, the sacrificial layer (11) in the peripheral area (10b) is also removed or the annular groove (14) is removed to expose the sacrificial layer (11) in the peripheral area (10b).
3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The sacrificial layer (11) in the peripheral area (10b) is removed by dry etching or wet etching.
4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The sacrificial layer (11) of each device region (10a) is removed by dry etching or wet etching.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The peripheral areas (10b) are connected together.
6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Forming a semiconductor active layer (13) on the sacrificial layer (11) and the substrate (10) comprises: forming a transition layer (12) on the sacrificial layer (11) and the substrate (10), and forming a semiconductor active layer (13) on the transition layer (12); and patterning the transition layer (12) when patterning the semiconductor active layer (13).
7. The method for manufacturing a semiconductor structure according to claim 6, wherein: Before forming the semiconductor active layer (13), the transition layer (12) is subjected to high-temperature annealing to form the transition layer (12) into a single crystal material.
8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 7, wherein: Before, during or after the sacrificial layer (11) of each device area (10a) is removed, a carrier (20) is arranged on the semiconductor active layer (13) of at least a portion of the device areas (10a).
9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 7, wherein: The cross-section of the semiconductor active layer (13) in the device area (10a) is polygonal, and the cross-section of the semiconductor active layer (13) in the peripheral area (10b) is polygonal; or the cross-section of the semiconductor active layer (13) in the device area (10a) is circular or elliptical, and the cross-section of the semiconductor active layer (13) in the peripheral area (10b) is a circular ring or an elliptical ring.
10. The method for manufacturing a semiconductor structure according to any one of claims 1 to 7, wherein: The semiconductor active layer (13) comprises GaN-based materials.
11. The method for manufacturing a semiconductor structure according to any one of claims 1 to 7, wherein: The material of the sacrificial layer (11) includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride.
12. The method for manufacturing a semiconductor structure according to any one of claims 1 to 7, wherein: The semiconductor active layer (13) comprises a P-type semiconductor layer (131), an N-type semiconductor layer (132), and a light-emitting material layer (133) located between the P-type semiconductor layer (131) and the N-type semiconductor layer (132).
Citation Information
Patent Citations
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