DC / DC converter

Abstract

DC / DC converter (100) has N converters (DCk) each having an inductor (Lk), a switching element (Qk), and an anti-flow element (Dk) and being connected in parallel, each converter (DCk) being controlled in a manner that the phase is different from each other so that the total of the switching frequency (F) is outside the range of the first non-selective band (B1). The inductor (Lk) is constituted by an inductance that is smaller as the switching frequency (F) is higher. The switching element (Qk) is controlled by the switching frequency (F) that is set higher than the second non-selective band (B2), the gate total charge amount (Qg) is constituted to be small so that the total loss (PSUM) is reduced compared to the case where the switching frequency (F) is set lower than the second non-selective band (B2), the second non-selective band (B2) having the upper limit and lower limit of 1 / N of the upper limit frequency and lower limit frequency of the first non-selective band (B1).

Description

TECHNICAL FIELD

[0001] The present application relates to a DC / DC converter. BACKGROUND

[0002] In order to reduce noise caused by high-order harmonic currents, a conventional DC / DC converter shown below has been proposed.

[0003] A conventional power supply device as a DC / DC converter has: a plurality of current paths branched from an alternating current power supply after full-wave rectification; a plurality of inductors provided in the respective current paths; a direct current voltage generation section that generates a direct current voltage by supplying output currents of the plurality of inductors to a common capacitor element; and a switching section that controls currents flowing to the plurality of inductors. The switching section performs switching control using different phases for each of the plurality of inductors. With this configuration, the current paths are branched into a plurality of paths, the current value of each current path is reduced, and the current of each switching transistor can be reduced. Further, since the phases of the switching are staggered, the ripple component of the total value of the currents flowing to the plurality of inductors can be reduced, and high-order harmonic currents that become noise can be reduced (for example, refer to Patent Literature 1).

[0004] PRIOR ART DOCUMENTS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2007-195282 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] The conventional DC / DC converter is an interleaved type DC / DC converter in which a plurality of converters each having a current path composed of an inductor and a switching transistor are connected in parallel, and switching control is performed using different phases for each converter. In this case, the total of the switching frequencies increases in accordance with the number of converters, and it is possible that noise interference occurs in a broadcast band, such as AM (Amplitude Modulation) radio broadcasting, and in particular, in a DC / DC converter for a vehicle use, it is required to avoid noise interference with a vehicle-mounted radio device (AM radio).

[0009] However, from the viewpoint of circuit loss and heat generation of the DC / DC converter, the total of the switching frequencies is set to be lower than the broadcast band, and thus there is a problem that peripheral components, in particular, inductors, are upsized.

[0010] Disclosed is a technology for solving the above-described problem, and an object thereof is to provide a DC-DC converter that can reduce noise caused by high-order harmonic currents, avoid specific frequency bands, suppress circuit loss and heat generation, and promote miniaturization.

[0011] Solution to the problem

[0012] A DC / DC converter disclosed in the present application includes N converters each having an inductor, a switching element, and an anti-backflow element, and connected in parallel, and a control unit that controls the N converters by switching control of the switching element of each of the converters at a set switching frequency. The control unit controls each of the converters in a manner that the phases are different from each other, so that the total of the switching frequencies is outside a range of a first non-selection frequency band set in advance. In each of the converters, the inductor is configured with an inductance that is smaller as the switching frequency is higher, and a total loss of a loss of the inductor and a loss of the switching element varies in accordance with the switching frequency. In at least one of the N converters, the switching element is controlled at a higher switching frequency than a second non-selection frequency band, and a total gate charge amount is configured to be smaller, so that the total loss is reduced as compared with a case where the switching frequency is set lower than the second non-selection frequency band, the second non-selection frequency band having a frequency of 1 / N of each of an upper limit frequency and a lower limit frequency of the first non-selection frequency band as an upper limit and a lower limit.

[0013] Effects of the invention

[0014] According to the DC / DC converter disclosed in the present application, reduction of noise caused by high-order harmonic currents can be achieved. Furthermore, the first non-selection frequency band can be avoided, and circuit loss and heat generation can be suppressed, and miniaturization can be promoted. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a diagram showing a schematic configuration of a DC / DC converter of Embodiment 1.

[0016] Figure 2 is a waveform diagram explaining each part of the operation of the DC / DC converter of Embodiment 1.

[0017] Figure 3 is a diagram showing a range of a total frequency of Embodiment 1.

[0018] Figure 4 is a diagram showing characteristics of circuit loss corresponding to a switching frequency of Embodiment 1 together with a comparative example.

[0019] Figure 5 is a diagram explaining a region of a switching frequency of Embodiment 1.

[0020] Figure 6 This is a diagram illustrating the region of the switching frequency in another example of Embodiment 1.

[0021] Figure 7 This is a diagram illustrating the region of the switching frequency in another example of Embodiment 1.

[0022] Figure 8 This is a diagram illustrating the characteristics of circuit loss in another example of Implementation 1.

[0023] Figure 9 This is a diagram showing the schematic structure of the DC / DC converter in Embodiment 2.

[0024] Figure 10 This is a diagram showing the schematic structure of the DC / DC converter in Embodiment 3.

[0025] Figure 11 These are waveform diagrams illustrating the various parts of the operation of the DC / DC converter in Embodiment 4.

[0026] Figure 12 This is a diagram illustrating the variation range of the switching frequency in another example of Embodiment 4.

[0027] Figure 13 This is a diagram illustrating the variation range of the switching frequency in another example of Embodiment 4.

[0028] Figure 14 This is a diagram illustrating the variation range of the switching frequency in another example of Embodiment 4.

[0029] Figure 15 This is a diagram illustrating the switching frequency of the DC / DC converter in Embodiment 5. Detailed Implementation

[0030] Implementation method 1.

[0031] Figure 1 This is a diagram showing the schematic structure of the DC / DC converter in Embodiment 1.

[0032] like Figure 1 As shown, the DC / DC converter 100 includes N converters DCk (k = 1 to N) connected in parallel to the input and output sides respectively. Each converter DCk is composed of a boost relay switch circuit having an inductor Lk, a switching element Qk, and a diode Dk as an anti-reverse current element.

[0033] It should be noted that N is a complex number, which is 3 in this example. That is, the three converters DC1, DC2, and DC3, each equipped with inductors L1, L2, and L3, switching elements Q1, Q2, and Q3, and diodes D1, D2, and D3, are connected in parallel.

[0034] In addition, the DC / DC converter 100 is provided with an input voltage generation source (hereinafter, referred to as a power supply 11) that generates an input voltage Vin, and a controller 12 that controls each converter DCk as a control section by performing switching control of each switching element Qk at mutually different phases. Further, the input voltage Vin is boosted, and direct current power as an output voltage Vo is supplied to a load 101 via an output capacitor Co.

[0035] Note that the output capacitor Co is provided as a filter for avoiding a large variation of the output voltage Vo in a short time. The output capacitor Co can be connected to the output side of each converter DCk, respectively.

[0036] Thus, the DC / DC converter 100 is an interleaved type DC / DC converter in which a plurality of converters DCk are connected in parallel and switching control is performed at different phases for each converter DCk.

[0037] Each switching element Qk uses a self-turn-off type switching element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), for example.

[0038] The controller 12 is constituted by an arithmetic processing circuit such as a CPU (Central Processing Unit) or an FPGA (Field Programmable Gate Array), for example, and generates a control signal for PWM (Pulse Width Modulation) control of each switching element Qk, in which case, a gate signal Gk (G1, G2, G3) is generated and output.

[0039] Figure 2 is a waveform chart that explains each part of the operation of the DC / DC converter 100.

[0040] Figure 2 The gate signals G1, G2, G3 of each switching element Q1, Q2, Q3, the inductor currents IL1, IL2, IL3 flowing to each inductor L1, L2, L3, and the input current IA input from the power supply 11 are shown. The input current IA is equal to the sum of the inductor currents IL1, IL2, IL3.

[0041] In this case, the switching elements Qk of the respective converters DCk are controlled at an equal switching frequency F, and the gate signals Gk are PWM signals that are equal in period T (=1 / F) and whose phases are each shifted by (2π / N). That is, the phases of the gate signals Gl, G2, G3 are each shifted by T / 3.

[0042] The inductor currents ILk (ILl, IL2, IL3) are triangular current waveforms that increase when the switching element Qk is in the on state and decrease when the switching element Qk is in the off state, and the average currents ILav and the amplitudes ΔILk (ΔILl, ΔIL2, ΔIL3) of the respective inductor currents ILk are each approximately equal.

[0043] The sum of the inductor currents ILl, IL2, IL3, that is, the input current IA, is a triangular current waveform that varies at a total frequency FA that is the sum of the respective switching frequencies F. In this case, the respective switching elements Qk are controlled at an equal switching frequency F with their phases each shifted by (2π / 3), and therefore the total frequency FA is approximately three times the switching frequency F, and the period TA (=1 / FA) is approximately (1 / 3) times the switching period T.

[0044] The average current IAav of the input current IA is approximately three times the average currents ILav of the respective inductor currents ILk, and the amplitude ΔIA of the input current IA is approximately (1 / 3) times the amplitudes ΔILk of the respective inductor currents ILk.

[0045] In this way, the amplitude ΔIA of the input current IA, which is the sum of the inductor currents ILl, IL2, IL3, is reduced, and therefore the amplitude of the high-order harmonic current that accompanies switching of the DC / DC converter 100 can be reduced, and the noise caused by the high-order harmonic current can be reduced. Furthermore, the average current IAav of the input current IA is dispersed into the average currents ILav of the respective inductors Lk, and particularly in the case of a large output power, the conversion efficiency of the DC / DC converter 100 can be improved.

[0046] When the DC / DC converter 100 thus configured and controlled is used for, for example, a vehicle-mounted application, as described above, it is required to avoid noise interference on a vehicle-mounted wireless device (AM radio). The broadcast band of the AM radio is approximately 526.5 kHz to 1606.5 kHz, which is close to the band of the switching frequency that is generally used in a DC / DC converter.

[0047] Figure 3 is a graph showing the range of the total frequency FA of the DC / DC converter 100.

[0048] In the DC / DC converter 100, the switching frequency F of each switching element Qk is set so that the total frequency FA is outside the range of the broadcast band of the AM radio broadcast (hereinafter, referred to as the AM band B1) which is the first non-selection band. That is, the total frequency FA is used in a low frequency band Al lower than the AM band B1 or a high frequency band C1 higher than the AM band B1 outside the range of the AM band B1 set as the upper limit frequency FH and the lower limit frequency FL.

[0049] Note that, in this embodiment, the total frequency FA is set to be within the high frequency band C1, and each switching element Qk is controlled at the same switching frequency F.

[0050] Figure 4 is a graph showing the characteristics of the circuit loss corresponding to the switching frequency together with the comparative example. Here, a case where a storage battery for a vehicle is used in the power supply 11 is shown.

[0051] The circuit loss of each converter DCk is represented by the total loss PSUM of the loss PL of each inductor Lk and the loss PQ of the switching element Qk.

[0052] In this embodiment, a switching element Qk having a gate total charge amount Qg of, for example, 25 nC or less is used, which is smaller than the switching element normally used. In contrast, in the comparative example, a case where a switching element widely used in the past, for example, having a gate total charge amount Qg of 50 nC or more is used is shown, and the loss PQ-A of the switching element and the total loss PSUM-A of the loss PQ-A and the loss PL of the inductor Lk are shown.

[0053] In each converter DCk, the switching frequency F of the switching element Qk is set to be within a frequency band C2 higher than the non-selection band B2 which is the second non-selection band, and the second non-selection band has 1 / N (in this case, 1 / 3) of each of the upper limit frequency FH and the lower limit frequency FL of the AM band B1 as the upper limit FH / 3 (about 535.5 kHz) and the lower limit FL / 3 (about 175.5 kHz).

[0054] The inductor Lk in each converter DCk is constituted by a small inductance which does not become less than the lower limit value, and the higher the switching frequency F, the smaller the inductance becomes.

[0055] Note that the inductance of the inductor Lk is described as the inductance Lk for simplicity.

[0056] The lower limit value infLk of the inductor Lk is determined by the voltage VLk applied to both ends of the inductor Lk, the maximum ripple width ΔILmax determined by the average value (average current) ILav of the inductor current ILk and the limit value ILlim, the switching frequency F, and the duty ratio D, and is represented by the following formula (1).

[0057] infLk = (VLk / ILlim) · D · (1 / F)... (1)

[0058] Note that the voltage VLk applied to both ends of the inductor Lk is equal to the input voltage Vin. Also, the limit value ILlim of the inductor current ILk is, for example, a specification value determined so that the noise level caused by the high-order harmonic current component converges to a standard value or a saturation current value of the inductor Lk, etc. In this case, the limit value ILlim is equal in each inductor Lk, but can also be different for each inductor Lk.

[0059] In Figure 4 , the characteristics when the inductance Lk is set to the lower limit value infLk are shown.

[0060] As Figure 4 shown, in the switching element Qk, when the switching frequency F is raised, the switching loss increases, so the loss PQ increases. In this case, since the gate total charge amount Qg is small, the loss PQ is small compared to the loss PQ-A of the comparative example, and the slope at which the loss PQ increases as the switching frequency F increases can be further reduced.

[0061] In the inductor Lk, the loss PL caused by the combination of the copper loss caused by the resistance component, the iron loss generated in the core, and the skin effect, etc. is generated. As described above, since the inductance Lk is constituted so as to be smaller as the switching frequency F is higher, in the low frequency region, the copper loss is dominant, and when the switching frequency F is raised, the copper loss decreases and the loss PL also decreases. When the frequency is raised, the iron loss increases, and further, the loss caused by the skin effect is sometimes added, and the loss PL changes from decreasing to increasing.

[0062] When the switching frequency F is higher than the frequency band A2, the total loss PSUM (= PQ+PL) is reduced from the minimum value Pα in the frequency band A2, and in the frequency band C2 higher than the non-selection band B2, there is an interval Fw in which the total loss PSUM is reduced from Pα.

[0063] In this embodiment, the switching frequency F is set in the frequency band C2 higher than the non-selection band B2, and in particular, the total loss PSUM (= PQ+PL) is set to an interval Fw in which the total loss PSUM is reduced from the minimum value Pα in the frequency band A2 lower than the non-selection band B2. In the frequency band C2 higher than the non-selection band B2, if the switching frequency at which the total loss PSUM = Pα is set to Fα, then the interval Fw becomes (FH / 3) ~ Fα.

[0064] For example, when the switching frequency F is set to X within the interval Fw, the total loss PSUM (=P3) of the inductor Lk loss PL (=P1) and the switching element Qk loss PQ (=P2) is smaller than Pα. That is, the total loss PSUM is smaller compared to the case where the switching frequency F is set lower than the non-selective band B2.

[0065] In the comparative example, the switching element loss PQ-A is large, and the rate of increase of loss PQ-A with the increase of switching frequency F is also large, resulting in a similar increase in total loss PSUM-A. Therefore, in the comparative example, it is impossible to set a range within frequency band C2 that is smaller than the minimum value of total loss PSUM-A; that is, there is no range equivalent to range Fw.

[0066] As described above, in this embodiment, by using a switching element Qk with a small total gate charge Qg for the converter DCk, the interval Fw is set within the frequency band C2. Using the switching frequency F within the interval Fw, the total loss PSUM (=PQ+PL) in the interval Fw is reduced compared to the minimum value Pα in the frequency band A2, which is lower than the non-selected band domain B2.

[0067] Figure 5 This is a diagram illustrating the region of the switching frequency F.

[0068] like Figure 5 As shown, the interval Fw is a region contained within the AM band B1 and including the central part of the AM band B1. Utilizing this characteristic, the switching frequency F can be preset to the central part of the AM band B1, making it easy to set the switching frequency F within the interval Fw.

[0069] The relationship between the interval Fw and the AM band domain B1 varies depending on the number of converters N in the DCk converter. Figure 6 , Figure 7 The cases of N=2 and N=4 are shown respectively. In either case, the interval Fw becomes the interval containing the central part of the AM band B1, so the switching frequency F can be preset in the central part of the AM band B1.

[0070] It should be noted that the total gate charge Qg is not limited to the value mentioned above. As long as the total loss PSUM can be reduced within the interval Fw in the frequency band C2 by the minimum value Pα in the frequency band A2, the switching frequency F can be set within the interval Fw.

[0071] That is, in each converter DCk, the inductor Lk is composed of an inductor that is smaller as the switching frequency increases, and is controlled by a switching frequency F set within the frequency band C2. The total gate charge Qg of the switching element Qk is made small, so that the total loss PSUM is reduced compared to the case where the switching frequency F is assumed to be set within the frequency band A2.

[0072] Thus, in each converter DCk, the total loss PSUM can be reduced using the switching frequency F in the frequency band C2 higher than the non-selected band B2, and both the miniaturization of the inductor Lk and the reduction of the total loss PSUM can be achieved. Therefore, the DC / DC converter 100 is suppressed in circuit loss and heat generation, and can contribute to miniaturization.

[0073] In addition, since each converter DCk is controlled using the switching frequency F in the frequency band C2 higher than the non-selected band B2, in the DC / DC converter 100, the total frequency FA can be easily and reliably avoided from the AM band B1, in which the non-selected band B2 has the frequency of 1 / N of each of the upper limit frequency FH and the lower limit frequency FL as the upper limit and the lower limit.

[0074] In addition, in the case where the on-vehicle storage battery is used in the power supply 11, the typical value is about 12V, but if the instantaneous variation is included, the variation of about 6V to 19V needs to be considered. In the case where the input voltage Vin has such a large variation range, as the input voltage Vin decreases, the average current IAav of the input current IA increases, and the average current ILav of each inductor current ILk also increases. In this case, if the switching frequency F is high and the inductance Lk is small, the copper loss further decreases, and thus the effect of reducing the total loss PSUM increases.

[0075] In addition, since each converter DCk is constituted by the step-up break-chopper circuit as the step-up converter, when the average current ILav of each inductor current ILk increases, if the switching frequency F is high and the inductance Lk is small, the copper loss further decreases, and thus the effect of reducing the total loss PSUM increases.

[0076] In addition, since the inductance Lk is determined based on the lower limit value infLk described above, the inductance Lk that is smaller as the switching frequency F is higher can be easily and reliably determined.

[0077] Note that the switching element Qk can be constituted by a wide band gap semiconductor such as GaN or SiC, in addition to Si semiconductor. The switching element Qk using the wide band gap semiconductor can effectively achieve the reduction of the total loss PSUM in the region where the switching frequency F is high, since the gate total charge amount Qg is small and the loss PQ of the switching element Qk is small.

[0078] Furthermore, in the above embodiment, N converters DCk are similarly configured and controlled with equal switching frequencies F, but this is not a limitation. That is, for at least one converter DCk, a switching element Qk with a small total gate charge Qg is used, and within frequency band C2, the switching frequency F is controlled such that the total loss PSUM is reduced compared to the minimum value Pα within frequency band A2. This suppresses the total loss PSUM of the converter DCk and enables miniaturization of the inductor Lk, thus contributing to the suppression of circuit losses and heat generation in the DC / DC converter 100 and its miniaturization.

[0079] In this case, the total frequency FA of the DC / DC converter 100 only needs to be outside the range of the AM band B1, but can be within the low frequency band A1.

[0080] Furthermore, the above implementation determines the total frequency FA by avoiding the AM band B1, but it is also applicable when the frequency bands other than the AM band B1 are set as the first non-selected frequency bands to avoid them.

[0081] In addition, in the above embodiment, the inductance Lk is set to a limit value infLk corresponding to the switching frequency F, but a ready-made inductor product with a known inductance can also be used.

[0082] Inductors come in a wide variety of sizes, such as 1μH, 1.5μH, 2.2μH, 3.3μH, 4.7μH, 6.8μH, 10μH, 15μH, 22μH, and so on. From these inductor products, an inductor Lk can be constructed using a small inductance that is not less than the lower limit value infLk.

[0083] Figure 8 The characteristics of circuit losses corresponding to the switching frequency in a converter DCk using pre-existing inductors are shown. The circuit losses of each converter DCk are represented by the total loss PSUMa of the inductor Lk loss PLA and the switching element Qk loss PQ. It should be noted that the use of... Figure 4 The same switching element Qk is shown in the example.

[0084] In this case, since the inductance decreases in a stepwise manner corresponding to the increase in switching frequency, the inductor loss PLa and the total loss PSUMA also change stepwise, but with the... Figure 4The same tendency is shown in this case. That is, when the switching frequency F is higher than the frequency band A2, the total loss PSUMa is reduced from the minimum value Pa in the frequency band A2, and has a range Fw in which the total loss PSUMa is reduced from Pa in the frequency band C2 which is higher than the non-selection band B2. Also, the switching frequency F used for control is set in the range Fw. When the switching frequency F is set to Fa in the frequency band C2 which is higher than the non-selection band B2, the range Fw becomes (FH / 3) ~ Fa.

[0085] For example, when the switching frequency F is set to Xa in the range Fw, the total loss PSUMa (= P3a) of the loss PLa (= Pla) of the inductor Lk and the loss PQ (= P2a) of the switching element Qk is smaller than Pa. That is, the total loss PSUMa is smaller than in the case where the switching frequency F is set to be lower than the non-selection band B2.

[0086] In this case, too, the total loss PSUMa of each converter DCk can be reduced and the inductor Lk can be downsized, so as in the above embodiment, the circuit loss and heat generation of the DC / DC converter 100 can be reduced and downsizing can be promoted. Also, each converter DCk can be easily constructed using an off-the-shelf inductor product.

[0087] Note that a plurality of off-the-shelf inductor products can be combined in series and in parallel to construct an inductor Lk having a desired inductance.

[0088] Embodiment 2

[0089] Figure 9 is a diagram showing the schematic structure of a DC / DC converter according to Embodiment 2.

[0090] As shown in Figure 9 , the DC / DC converter 100A has N converters DCak (k = 1 ~ N) connected in parallel on the input side and the output side, respectively. Each converter DCak is constructed of a boost chopper circuit having an inductor Lk, a switching element Qk, and a switching element Sk as an anti-backflow element. Note that N is plural, and in this example, is 3, and three converters DCal, DCa2, and DCa3 are connected in parallel.

[0091] In this Embodiment 2, the anti-backflow element in each converter DCak uses a switching element Sk, and the controller 12A as a control unit performs switching control on each switching element Qk and each switching element Sk. The other structures are the same as in the above Embodiment 1.

[0092] Each switching element Sk, like the switching element Qk, uses a self- turn-off type switching element such as a MOSFET or an IGBT.

[0093] The controller 12A generates the gate signal Gk to switch control each switching element Qk at mutually different phases, and generates the PWM signal, i.e., the gate signal Gak (Ga1, Ga2, Ga3) opposite to the gate signal Gk to switch control each switching element Sk. Note that the gate signals Gk, Gak are provided with dead times to avoid simultaneous turn-on of the switching element Qk and the switching element Sk.

[0094] In this embodiment, each converter DCak also uses the same inductor Lk and switching element Qk as in Embodiment 1, and is controlled at the same switching frequency F.

[0095] That is, the inductance of the inductor Lk is set small based on the lower limit value infLk in correspondence with the switching frequency F, and the switching element Qk with a small total gate charge amount Qg is used. Also, the switching frequency F is set in the frequency band C2 higher than the non-selection band B2, and in particular, in the interval Fw in which the total loss PSUM (= PQ+ PL) is reduced from the minimum value Pα in the frequency band A2 lower than the non-selection band B2.

[0096] Therefore, as in Embodiment 1, in each converter DCak, the switching frequency F in the frequency band C2 higher than the non-selection band B2 is used, the total loss PSUM can be reduced, and both the miniaturization of the inductor Lk and the reduction of the total loss PSUM can be achieved. Thus, in the DC / DC converter 100A, the total frequency FA can be easily and reliably avoided from the AM band B1, and the circuit loss and heat generation can be suppressed, and the miniaturization can be promoted.

[0097] Note that in this embodiment, the switching element Sk is also controlled at the same switching frequency F as the switching element Qk, and the loss of the switching element Sk varies in correspondence with the switching frequency F. Therefore, as to the switching element Sk, an element with a small total gate charge amount Qg is also used, and the total loss PSUM used in the basis for determining the switching frequency F is preferably used with the addition of the loss of the switching element Sk.

[0098] Embodiment 3.

[0099] Figure 10 is a diagram showing the schematic structure of the DC / DC converter of Embodiment 3.

[0100] As shown in Figure 10 , the DC / DC converter 100B has N converters DCbk (k = 1 to N) connected in parallel on the input side and the output side, respectively. Each converter DCbk is composed of a step-down breakable switching circuit having an inductor Lk, a switching element Qk, and a diode Dk as an anti-backflow element. Note that N is plural, and in this example, is 3, and three converters DCb1, DCb2, DCb3 are connected in parallel.

[0101] The controller 12B as the control section controls each converter DCbk by switching control of each switching element Qk at mutually different phases, steps down the input voltage Vin, and supplies direct-current power as an output voltage Vo to the load 101 via the output capacitor Co.

[0102] The other configuration is the same as that of the above-described embodiment 1.

[0103] In this embodiment, each converter DCbk is configured of a step-down breakable switching circuit as a step-down converter, the inductor current ILk flowing to each inductor Lk is an output current of each converter DCbk, and the sum of the inductor currents IL1, IL2, IL3 is output as an output current IA from the DC / DC converter 100B.

[0104] The inductor Lk in each converter DCbk is configured of an inductance that does not become small to a degree less than the lower limit value, and becomes an inductance that is smaller as the switching frequency F is higher.

[0105] In this case, the lower limit value infLk of the inductor Lk is also represented by the formula (1) shown in the above-described embodiment 1. However, the voltage VLk applied to both ends of the inductor Lk is a difference voltage (Vin-Vo) of the input voltage Vin and the output voltage Vo.

[0106] In this embodiment, each converter DCbk also uses the inductor Lk and the switching element Qk that are the same as those of the above-described embodiment 1, and is controlled at the same switching frequency F.

[0107] That is, the inductance of the inductor Lk corresponds to the switching frequency F, is set to be small based on the lower limit value infLk, and the switching element Qk having a small total gate charge amount Qg is used. Also, the switching frequency F is set in the frequency band C2 higher than the non-selection band B2, and in particular, in the interval Fw in which the total loss PSUM (=PQ+PL) is reduced from the minimum value Pα in the frequency band A2 lower than the non-selection band B2.

[0108] Therefore, as in the above-described embodiment 1, in each converter DCak, the switching frequency F in the frequency band C2 higher than the non-selection band B2 is used, the total loss PSUM can be reduced, and both the miniaturization of the inductor Lk and the reduction of the total loss PSUM can be achieved. Thus, in the DC / DC converter 100B, the total frequency FA can be easily and reliably avoided from the AM band B1, and the circuit loss and the heat generation can be suppressed, and the miniaturization can be promoted.

[0109] Note that, in this embodiment, the above-described embodiment 2 can also be applied, and the switching element Sk can be used as the anti-inrush element.

[0110] In addition, the converters are not limited to the structures shown in Embodiments 1 and 2, and can be a step-up / down converter, a Cuk converter, a Zeta converter, or a Sepic converter, etc.

[0111] Embodiment 4

[0112] In the above-described Embodiment 1, the converters DCk are controlled to be fixed at the set switching frequency F, but in this Embodiment 4, the switching frequency F is used so as to vary in time.

[0113] Figure 11 is an operation waveform diagram illustrating the operation of the DC / DC converter of Embodiment 4. Here, an example of the DC / DC converter 100 in which the number of converters DCk used is 2 is shown.

[0114] As shown in Figure 11 , the switching elements Qk (Q1, Q2) are switched from Fa to Fb in the switching frequency F at time t1, i.e., from Ta (=1 / Fa) to Tb (=1 / Fb) in the switching period T. The two switching elements Qk are controlled so as to be each shifted by π in phase, and thus are switched with a shift of (Ta / 2) in the interval in which the switching period T is Ta, and are switched with a shift of (Tb / 2) in the interval in which the switching period T is Tb.

[0115] The sum of the inductor currents IL1, IL2, i.e., the input current IA, becomes a triangular current waveform that varies at a total frequency FA that is the total of the switching frequencies F. That is, the input current IA varies at a period TAa that is approximately 1 / 2 times Ta in the interval in which the switching period T is Ta, and varies at a period TAb that is approximately 1 / 2 times Tb in the interval in which the switching period T is Tb.

[0116] Note that in this case, the state when the switching frequency F is changed at time t1 is described, but the three or more kinds of switching frequencies F can be changed at a predetermined time interval.

[0117] In addition, the inductors Lk are used in a manner that satisfies the lower limit value infLk of the inductance calculated corresponding to the lowest switching frequency within the plurality of switching frequencies F, i.e., in a manner that the inductors Lk are not used to be smaller than the lower limit value infLk. Further, in an interval Fw in which the total loss PSUM (=PQ+PL) is reduced compared to the minimum value Pα within the frequency band A2, the plurality of switching frequencies F are selected so as to vary in time.

[0118] In this embodiment, as with Embodiment 1 described above, the inductance of the inductor Lk corresponding to the switching frequency F is set to be small based on the lower limit value infLk, and a switching element Qk having a small total gate charge amount Qg is used. Also, the switching frequency F is set in the frequency band C2 higher than the non-selection band B2, and in particular, in the interval Fw in which the total loss PSUM (= PQ+PL) is reduced from the minimum value Pα in the frequency band A2 lower than the non-selection band B2.

[0119] Therefore, as with Embodiment 1 described above, in each converter DCk, the total loss PSUM can be reduced using the switching frequency F in the frequency band C2 higher than the non-selection band B2, and both the miniaturization of the inductor Lk and the reduction of the total loss PSUM can be achieved. Thus, in the DC / DC converter 100, the total frequency FA can be easily and reliably avoided from the AM band B1, and the circuit loss and the heat generation can be suppressed, and the miniaturization can be promoted.

[0120] In addition, since the plurality of switching frequencies F are used while being varied in time, the amplitude ΔIA of the sum of the inductor currents ILk, that is, the current IA is further reduced, and the noise component caused by the switching frequency F is dispersed, and thus, the noise caused by the high-order harmonic current accompanying the switching of the DC / DC converter 100 can be further reduced.

[0121] Note that the region in which the plurality of switching frequencies F are varied in time is preferably the interval Fw in which the total loss PSUM is reduced from the minimum value Pα, but as long as the average value is in the interval Fw, the effects of the miniaturization of the inductor Lk and the reduction of the total loss PSUM can be obtained. Based on Figure 12 , the following description is made.

[0122] As shown in Figure 12 , since the interval Fw is an interval included in the AM band B1 and including the central portion of the AM band B1, the switching frequency F is varied in the frequency band C2 higher than the non-selection band B2 and in the interval FFw within the AM band B1. Note that the switching frequency F is varied so that the average value Fav of the switching frequency F is in the interval Fw.

[0123] Since the interval FFw is set in advance to be (FH / 2) to FH, the switching frequency F can be easily set.

[0124] The relationship of the interval FFw to the AM band B1 varies depending on the number N of the converters DCk, Figure 13 , Figure 14The case where N = 3 and the case where N = 4 are shown separately. In either case, the interval Fw becomes an interval including the central portion of the AM band B1, and the switching frequency F is varied within the interval Fw to become within the AM band B1 in a frequency band C2 higher than the non-selection band B2. In particular, in the case where N = 4, the interval Fw coincides with the AM band B1. Further, the average value Fav of the switching frequency F becomes within the interval Fw.

[0125] In either case, the switching frequency F can be easily set.

[0126] Embodiment 5

[0127] In Embodiment 4, the switching frequency F is varied in time to be used in the plurality of converters DCk in the same manner, but in this Embodiment 5, different switching frequencies F are used in at least one converter DCk.

[0128] Figure 15 is a diagram illustrating the switching frequency of the DC / DC converter of this Embodiment 5. In this case, a DC / DC converter 100 in which the number of parallel connection of the converters DCk is four is used.

[0129] As shown in Figure 15 , the gate signals Gk (Gl, G2, G3, G4) of the four converters DCk are switched in the period A, the period B, the period C, the period D, the period E, and the period F.

[0130] In this case, as shown in the above-described Embodiment 4, a plurality of switching frequencies F are selected within the interval Fw in which the total loss PSUM (= PQ+PL) is reduced within the frequency band A2. Further, the difference frequency of the switching frequencies F before and after the switching, that is, the frequency interval is limited, and for example, the switching is performed with a frequency interval of 100 kHz or less.

[0131] In this case, five switching frequencies Fa, Fb, Fc, Fd, Fe, Ff (Fa Figure 15 are used, and the switching is performed as shown in . In the period A to the period F, when the gate signal G3 in which the switching is sequentially performed to be Fa, Fb, Fc, Fd, Fe, Ff is taken as a reference, the switching frequency F is different in the period E of the gate signal Gl, the period D of the gate signal G2, and the period B to the period E of the gate signal G4.

[0132] In this embodiment, the plurality of switching frequencies F are also used so as to vary in time, and thus the amplitude ΔIA of the sum of the inductor currents ILk, i.e., the current IA, is further reduced, and the noise component due to the switching frequency F can be further dispersed. Further, since different switching frequencies F are used in at least one of the converters DCk, the noise component can be further dispersed over a wide range, and the noise due to the high-order harmonic current accompanying the switching can be further reduced.

[0133] Note that, Figure 15 The switching pattern shown is merely an example, and as long as the plurality of converters DCk are not caused to vary in time at the same switching frequency F, and as long as the optimum switching frequency F is appropriately set in correspondence with the generated noise level, the same effect can be obtained.

[0134] In the above-described embodiments 1 to 5, the DC / DC converter for vehicle use is described, but is not limited thereto. The same effect can be obtained in the case where the device, such as a home-use audio player or a medical device, which is used in a frequency band close to the switching frequency F used in the DC / DC converter and needs to avoid noise interference, is disposed in the vicinity of the DC / DC converter. In this case, the frequency band of the above-described device is set as the first non-selected band.

[0135] Various features, modes, and functions described in one or more embodiments are not limited to the application of the specific embodiment, and can be applied to the embodiments alone or in various combinations.

[0136] Therefore, a large number of modifications not exemplified can be conceived within the technical scope disclosed in the present application. For example, a case where at least one component is modified, a case where at least one component is added or at least one component is omitted, and a case where at least one component is extracted and combined with the components of the other embodiments are included.

[0137] Explanation of Reference Numerals

[0138] 12, 12A, 12B controller, 100, 100A, 100B DC / DC converter, B1 AM band, B2 non-selected band, Dk diode, DCk, DCak, DCbk converter, F switching frequency, ILk inductor current, Lk inductor, PL, PLa loss of inductor, PQ loss of switching element, PSUM, PSUMa total loss, Qk switching element, Qg total gate charge, Sk switching element.

Claims

1. A DC / DC converter, wherein the DC / DC converter is provided with N converters each having an inductor, a switching element, and an anti-inrush element, and connected in parallel, and a control section that controls the N converters by switching control of the switching element of each of the converters at a switching frequency set in advance, the control section controls each of the converters in a manner that the phases are different from each other so that the total of the switching frequencies becomes outside a range of a first non-selection band set in advance, in each of the converters, the inductor is constituted by an inductance that is smaller the higher the switching frequency, and a total loss of a loss of the inductor and a loss of the switching element varies in correspondence with the switching frequency, each of the switching elements of the N converters is controlled by the switching frequency set higher than a second non-selection band that has as upper and lower limits, respectively, frequencies that are 1 / N of upper and lower limits of the first non-selection band, and a gate total charge amount is constituted to be small so that the total loss is reduced compared to a case where the switching frequency is set lower than the second non-selection band, the switching frequency of each of the converters is within the first non-selection band.

2. The DC / DC converter according to claim 1, wherein the inductor of each of the converters is decided with a lower limit value of an inductance value decided by an applied voltage to the inductor, a maximum ripple width decided by an average value and a limit value of an inductor current, the switching frequency, and a duty ratio.

3. The DC / DC converter according to claim 1, wherein the control section controls each of the converters by varying each of the switching frequencies in time.

4. The DC / DC converter according to claim 1, wherein the control section controls each of the converters in a manner that each of the switching frequencies is the same and the phases each differ by 2π / N.

5. The DC / DC converter according to claim 3, wherein the control section controls each of the converters in a manner that each of the switching frequencies is the same and the phases each differ by 2π / N.

6. The DC / DC converter according to claim 3, wherein the control section uses a different frequency from the others for at least one of the switching frequencies.

7. The DC / DC converter according to claim 1, wherein the N converters are step-up converters that each step up an input direct-current voltage and output.

8. The DC / DC converter according to any one of claims 1 to 7, wherein the first non-selection band is a band of amplitude modulation broadcasting of radio broadcasting.

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