Layout of pads and wires of memory devices and related devices, systems, and methods

Abstract

The present application generally relates to a layout of pads and conductors for a memory device and related devices, systems, and methods. A memory device may include a memory cell and a conductor arranged above the memory cell. The conductor may extend from substantially a first side of the memory device to substantially a second side of the memory device. Each of the conductors may be electrically coupled to a bonding pad, a first probe pad, and a second probe pad. The bonding pad may be located at or near the first side and configured to receive power. The first probe pad may be located at or near the first side and configured to be electrically coupled to a probe. The second probe pad may be located at or near the second side.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 134,906, filed January 7, 2021, entitled “Layouts for pads and wires of memory devices, and associated means, systems, and methods,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to memory devices. More specifically, various embodiments relate to one or more layouts of pads and wires for memory devices, and to related methods, apparatus, and systems. Background Technology

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low-power double data rate memory (LPDDR), phase-change memory (PCM), and flash memory.

[0005] A memory device may include multiple memory cells and multiple metal layers, the metal layers including conductors disposed above the memory cells. The conductors may be configured to supply power to the multiple memory cells. The conductors may be electrically coupled to bonding pads for receiving power from an external source. Additionally, the conductors may be electrically coupled to probe pads, and probes may be electrically coupled to the probe pads to test the memory device. Summary of the Invention

[0006] Some embodiments of this disclosure include a memory device comprising a plurality of memory cells and a plurality of wires disposed above the plurality of memory cells. The plurality of wires may extend from a generally first side of the memory device to a generally second side of the memory device. Each of the plurality of wires may be electrically coupled to a bonding pad, a first probe pad, and a second probe pad. The bonding pad may be located on or near the first side. The bonding pad may be configured to receive power. The first probe pad may be located on or near the first side. The first probe pad may be configured to be electrically coupled to a probe. The second probe pad may be located on or near the second side.

[0007] Some embodiments of this disclosure include a system comprising: at least one input device; at least one output device; at least one processor device operatively coupled to the input device and the output device; and at least one memory device operatively coupled to the at least one processor device. The at least one memory device may include a plurality of memory cells; a first side; a second side opposite to the first side; and a metal layer disposed above the plurality of memory cells. The metal layer may include a plurality of metal lines extending substantially from the first side to substantially the second side. The plurality of metal lines may be configured to supply power to the plurality of memory cells. Each of the plurality of metal lines may be electrically coupled to: a bonding pad, a first probe pad, and a second probe pad. The bonding pad may be located at or near the first side and within the metal layer. The bonding pad may be adapted to receive power for the plurality of memory cells. The first probe pad may be located at or near the first side and within the metal layer. The first probe pad may be adapted to provide electrical coupling with probes used for testing the plurality of memory cells. The second probe pad may be located in or near the metal layer on the second side. The second probe pad may be adapted to provide electrical coupling with the probe.

[0008] Some embodiments of this disclosure include a memory device comprising a plurality of memory cells and a plurality of wires. The plurality of wires may be disposed in a metal layer above the plurality of memory cells. The plurality of wires may extend from a generally first side of the memory device to a generally second side of the memory device. Each of the plurality of wires may be electrically coupled to: a bonding pad and a probe pad. The bonding pad may be located at or near the first side and is configured to receive power. The probe pad may be located at or near the first side and may be configured to be electrically coupled to a probe. The memory device may further include wires electrically coupled to at least two of the plurality of wires. The wires may be disposed below the metal layer.

[0009] Some embodiments of this disclosure include a system comprising: at least one input device; at least one output device; at least one processor device operatively coupled to the input device and the output device; and at least one memory device operatively coupled to the at least one processor device. The at least one memory device may include: a plurality of memory cells; a first side; a second side opposite to the first side; and a first metal layer disposed above the plurality of memory cells. The first metal layer may include a plurality of metal lines extending substantially from the first side to substantially the second side. The plurality of metal lines may be configured to supply power to the plurality of memory cells. Each of the plurality of metal lines may be electrically coupled to: a bonding pad and a probe pad. The bonding pad may be located at or near the first side and within the first metal layer. The bonding pad may be configured to receive power for the plurality of memory cells. The probe pad may be located at or near the first side and within the first metal layer. The probe pad may be configured to provide electrical coupling with probes used for testing the plurality of memory cells. The at least one memory device may further include a second metal layer disposed beneath the first metal layer. The second metal layer may include metal lines electrically coupled to at least two of the plurality of metal lines.

[0010] Some embodiments of this disclosure include a method for testing a memory device. The method may include electrically coupling probes to first probe pads and second probe pads of a single-channel memory device. The single-channel memory device may include a first number of memory cells and a first number of lines disposed above the first number of memory cells. The first number of lines may extend from substantially a first side of the single-channel memory device to substantially a second side of the single-channel memory device. Each of the first number of lines may be electrically coupled to a first probe pad in the first probe pads and a second probe pad in the second probe pads. The first probe pad may be disposed at or near the first side. The second probe pad may be disposed at or near the second side. The method may further include providing one or more test signals to the single-channel memory device through the first probe pads and the second probe pads. Attached Figure Description

[0011] Although this disclosure concludes with claims that particularly point out and clearly claim protection for certain embodiments, various features and advantages of embodiments within the scope of this disclosure can be more readily identified from the following description, read in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating an example memory device according to at least one embodiment of the present disclosure.

[0013] Figure 2 This is a functional block diagram illustrating an example layout of a dual-channel memory device.

[0014] Figure 3 This is a functional block diagram illustrating an example layout of a single-channel memory device.

[0015] Figure 4 This is a functional block diagram illustrating an example layout of a single-channel memory device according to at least one embodiment of the present disclosure.

[0016] Figure 5 This is a functional block diagram illustrating another example layout of a single-channel memory device according to at least one embodiment of the present disclosure.

[0017] Figure 6 This is a functional block diagram illustrating yet another example layout of a single-channel memory device according to at least one embodiment of the present disclosure.

[0018] Figure 7 This is a functional block diagram illustrating an example layout of contact points of probes that can be used to test a memory device according to at least one embodiment of the present disclosure.

[0019] Figure 8A and 8BCommonly, there are flowcharts illustrating example methods according to at least one embodiment of the present disclosure.

[0020] Figure 9 This is a simplified block diagram illustrating an instance memory system according to at least one embodiment of the present disclosure.

[0021] Figure 10 This is a simplified block diagram illustrating an example electronic system according to at least one embodiment of the present disclosure. Detailed Implementation

[0022] A composite die can be part of a memory device; for example, a composite die can contain one or more memory cells arranged in one or more layers on the die. Depending on the metal layer (e.g., a redistribution layer) arranged above the composite die, the composite die can be included in a single-channel memory device (e.g., one channel containing the full memory size (e.g., 16GB)) or a dual-channel memory device (e.g., two channels each containing half a memory size (e.g., 8GB)) and / or function as a single-channel or dual-channel memory device. For example, a single-channel memory device can be manufactured by forming a metal layer in a first layout above the composite die. A dual-channel memory device can also be manufactured by forming a metal layer in a second layout above the same composite die.

[0023] To simplify testing operations and / or reduce the cost of testing equipment, it is advantageous to configure the metal layers of a single-channel memory device so that a single probe can be used to test a single-channel memory device comprising a combination of dies or a dual-channel memory device comprising the same combination of dies. Some embodiments of this disclosure include a layout of one or more metal layers for a single-channel memory device, which allows the use of probes that can also test dual-channel memory devices to test the single-channel memory device.

[0024] Some embodiments of this disclosure include layouts of lines, bonding pads, and probe pads. Some layouts include probe pads on both a first and a second side of the memory device. Including probe pads on both sides of the memory device allows probe testing of various embodiments disclosed herein (e.g., single-channel memory devices) as well as dual-channel memory devices.

[0025] Additionally, some layouts include one or more wires (e.g., "inter-pad wires") that can be electrically coupled to probe pads on both sides of the memory device. This wire can provide better electrical coupling between the wire and the probe, which can allow for improved testing and / or performance of the memory device (e.g., by reducing the impedance of the inter-pad wire).

[0026] Additionally, some embodiments of this disclosure relate to means comprising one or more conductors (e.g., "inter-line conductors") that provide electrical coupling between various conductors in a metal layer of a memory device. These conductors can reduce the overall resistivity of the metal layer. In some embodiments, the conductors may be located in a channel region of the line. For example, in a single-channel memory device, there may be no bonding pads in channel B region of the single-channel memory device, and the conductors may be arranged in channel B region. In some embodiments, some conductors may be in the same layer as other conductors in the various conductors of the metal layer. In these or other embodiments, some conductors may be in a lower layer of the metal layer.

[0027] Although various embodiments have been described herein with reference to memory devices, this disclosure is not limited thereto, and the embodiments are generally applicable to microelectronic systems and / or semiconductor devices that may or may not include memory devices. Embodiments of this disclosure will now be explained with reference to the accompanying drawings.

[0028] Figure 1 This is a functional block diagram illustrating an example memory device 100 according to at least one embodiment of the present disclosure. The memory device 100 may include, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), DDR SDRAM (Double Data Rate SDRAM, such as DDR4 SDRAM), SGRAM (Synchronous Graphics Random Access Memory), or three-dimensional (3D) DRAM. The memory device 100, which may be integrated on a semiconductor chip, may include a memory cell array 102.

[0029] exist Figure 1 In one embodiment, the memory cell array 102 is shown as comprising eight memory banks BANK0-7. In other embodiments, the memory cell array 102 may comprise more or fewer memory banks. Each memory bank comprises multiple access lines (word lines WL), multiple data lines (bit lines BL and / BL), and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. The selection of word lines WL can be performed by the row decoder 104, while the selection of bit lines BL and / BL can be performed by the column decoder 106. Figure 1 In one embodiment, row decoder 104 may include a corresponding row decoder for each memory bank BANK0-7, and column decoder 106 may include a corresponding column decoder for each memory bank BANK0-7.

[0030] Bit lines BL and / BL are coupled to their respective sense amplifiers (SAMPs). Data read from bit line BL or / BL can be amplified by the sense amplifiers (SAMPs) and transmitted to the read / write amplifier 160 via the complementary local data line (LIOT / B), the transmission gate (TG), and the complementary master data line (MIOT / B). Conversely, write data output from the read / write amplifier 160 can be transmitted to the sense amplifiers (SAMPs) via the complementary master data line (MIOT / B), the transmission gate (TG), and the complementary local data line (LIOT / B), and written to the memory cell MC coupled to bit line BL or / BL.

[0031] Memory device 100 can typically be configured to receive various inputs via various terminals (such as address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118) (e.g., from an external controller or host). Memory device 100 may include additional terminals, such as power terminals, including power supply terminals 120 and 122. Additionally, memory device 100 may include probe pads 124 configured to allow connection between memory device 100 and probes configured to test memory device 100.

[0032] During expected operation, one or more command signals COM received via command terminal 112 can be transmitted to command decoder 150 via command input circuitry 152. Command decoder 150 may include circuitry configured to generate various internal commands by decoding one or more command signals COM. Examples of internal commands include the valid command ACT and the read / write signal R / W.

[0033] Furthermore, one or more address signals ADD received via address terminal 110 can be transmitted to address decoder 130 via address input circuit 132. Address decoder 130 can be configured to provide row address XADD to row decoder 104 and column address YADD to column decoder 106. Although command input circuit 152 and address input circuit 132 are shown as separate circuits, in some embodiments, address signals and command signals can be received via a common circuit.

[0034] The valid command ACT may include a pulse signal that is activated in response to a command signal COM (e.g., a valid command) indicating row access. In response to the valid signal ACT, the row decoder 104 specifying the memory address can be activated. As a result, the word line WL specified by the row address XADD can be selected and activated.

[0035] The read / write signal R / W may include a pulse signal that is activated in response to a command signal COM (e.g., a read command or a write command) indicating column access. In response to the read / write signal R / W, the column decoder 106 may be activated, and the bit line BL specified by the column address YADD may be selected.

[0036] In response to the valid command ACT, the read signal, the row address XADD, and the column address YADD, data can be read from the memory cell MC specified by the row address XADD and the column address YADD. The read data can be output via the sense amplifier SAMP, the transmission gate TG, the read / write amplifier 160, the input / output circuit 162, and the data terminal 116. Furthermore, in response to the valid command ACT, the write signal, the row address XADD, and the column address YADD, write data can be provided to the memory cell array 102 via the data terminal 116, the input / output circuit 162, the read / write amplifier 160, the transmission gate TG, and the sense amplifier SAMP. Write data can be written to the memory cell MC specified by the row address XADD and the column address YADD.

[0037] Clock signals CK and / CK can be received via clock terminal 114. CLK input circuit 170 can generate an internal clock signal ICLK based on clock signals CK and / CK. The internal clock signal ICLK can be transmitted to various components of memory device 100, such as command decoder 150 and internal clock generator 172. Internal clock generator 172 can generate an internal clock signal LCLK, which can be transmitted to input / output circuit 162 (e.g., for controlling the timing of input / output circuit 162's operation). Furthermore, data mask terminal 118 can receive one or more data mask signals DM. When a data mask signal DM is activated, the corresponding data can be prevented from being overwritten.

[0038] Figure 2 This is a functional block diagram illustrating an example layout 200, which includes lines 202 (collectively referred to as lines 202a and 202b), bonding pads 204 (collectively referred to as bonding pads 204a and 204b), and probe pads 206 (collectively referred to as probe pads 206a and 206b). Layout 200 can be used in memory devices (e.g., Figure 1 The line 202 may be part of one or more redistribution layers, which may be configured to be in the memory device 100. Figure 1 All data terminals 116, power terminals 120, power terminals 122, and probe pads 124) are connected to other components of the memory device (e.g., Figure 1The signal and / or power are redistributed among the cells of the memory cell array 102, the sensing amplifier, the transmission gate, the row decoder 104, the column decoder 106 and / or the read / write amplifier 160.

[0039] Line 202 may be a wire disposed in a metal layer. Bonding pads 204 and probe pads 206 may, for example, be disposed in the metal layer and may be electrically coupled to line 202. For example, line 202 may be covered by a passivation film (e.g., polyimide); however, bonding pads 204 and / or probe pads 206 may be exposed (e.g., having openings in the passivation film). The components described herein may include multiple instances having the same or similar components. These components are generally indicated by numerical names (e.g., 202) and specifically by a numerical indicator followed by a letter name (e.g., 202a). For example, line 202 includes line 202a extending from a generally first side of the memory device to a middle portion of the memory device and line 202b extending from a generally second side of the memory device to a middle portion of the memory device. Bonding pads 204 include bonding pad 204a disposed in channel A region 208 and bonding pad 204b disposed in channel B region 210. The probe pad 206 includes a probe pad 206a arranged in channel A region 208 and a probe pad 206b arranged in channel B region 210.

[0040] The bonding pad 204 can be configured to receive power and allow electrical coupling between line 202 and the power supply. The bonding pad 204 can be... Figure 1 Examples of power supply terminals 120 and / or 122. The bonding pad 204 can be configured to be electrically coupled to a voltage line, for example, one or more V lines. DD Line, or one or more V-shaped lines SS Wire.

[0041] Line 202 can be configured to direct to a memory cell (e.g., Figure 1 The memory cells of the memory cell array 102 and / or other elements of the memory device (e.g., memory cells of the memory cell array 102) and / or other elements of the memory device. Figure 1 The row decoder 104, column decoder 106, and / or read / write amplifier 160 are powered. Specifically, line 202 can be configured to supply power from the bonding pad 204 to elements of the memory device by selectively coupling word lines, bit lines, sense amplifiers, and / or transmission gates to the bonding pad 204.

[0042] Various additional lines may exist in the various additional layers (not shown) between line 202 and the memory cell. For example, line 202 may be arranged in the uppermost metal layer, and one or more metal layers may exist between line 202 and the memory cell. The additional lines may be used to further distribute power (e.g.,) from line 202 to the various elements of the memory device. Furthermore, the additional lines may be used to transmit signals (e.g., data signals) to and from the memory cell. Additionally, there may be additional lines for providing data input and / or output (e.g., ...). Figure 1 Additional input / output pads (not shown) for any or all of the address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118.

[0043] The probe pad 206 can be configured to allow electrical coupling between a line and a probe, which can be used to test a memory device. The probe contacts can be arranged to correspond to the arrangement of the probe pad 206. The probe pad can be configured to receive power from the probe, for example, during a test operation.

[0044] exist Figure 2 In the diagram, 20 lines 202 are shown for illustrative purposes. Similarly, for illustrative purposes, in... Figure 2 The diagram shows 20 bonding pads 204. Similarly, for illustrative purposes, in Figure 2 The diagram shows 12 probe pads 206. However, these descriptions are non-limiting, and the systems and apparatus of this disclosure may include any number of lines, bonding pads, and / or probe pads.

[0045] Figure 3 This is a functional block diagram illustrating another example layout 300 including line 302, bonding pad 304, and probe pad 306. Layout 300 can be used in memory devices (e.g., Figure 1 Implemented in the memory device 100. Line 302 may be part of one or more redistribution layers, which may be configured to redistribute signals and / or power between terminals and / or pads and other elements of the memory device.

[0046] Line 302 may be a conductor disposed in a metal layer. Bonding pad 304 and probe pad 306 may, for example, be disposed in a metal layer and may be electrically coupled to line 302. Line 302 extends from a generally first side of the memory device to a generally second side of the memory device. Bonding pad 304 and probe pad 306 are disposed in channel A region 308.

[0047] The bonding pad 304 can be used with Figure 2 The bonding pad 204 is the same as or substantially similar to the probe pad 306. Figure 2The probe pads 206 are the same or roughly similar.

[0048] Line 302 can be roughly similar to Figure 2 Line 202. However, line 202 extends from approximately one side of the memory device to the middle portion, while line 302 extends from approximately the first side of the memory device to approximately the second side.

[0049] exist Figure 3 In the diagram, 10 lines 302 are shown for illustrative purposes. Similarly, for illustrative purposes, in... Figure 3 The image shows 10 bonding pads 304. Similarly, for illustrative purposes, in Figure 3 Six probe pads 306 are shown. However, these descriptions are non-limiting, and the systems and apparatus of this disclosure may include any number of lines, bonding pads, and / or probe pads.

[0050] Figure 2 The layout 200 includes components for electrically coupling on two opposite sides of the memory device (i.e., channel A region 208 and channel B region 210). Specifically, Figure 2 Layout 200 includes bonding pads 204a and probe pads 206a in channel A region 208 and bonding pads 204b and probe pads 206b in channel B region 210. It includes components arranged according to layout 200 (e.g., including...). Figure 2 The memory device (with lines 202, bonding pads 204 and probe pads 206 arranged in the middle) can be a dual-channel memory device.

[0051] In comparison, Figure 3 The layout 300 includes components for electrical coupling only on one side of the memory device (i.e., channel A region 308). Specifically, Figure 3 Layout 300 includes bonding pads 304 and probe pads 306 in channel A region 308, while channel B region 310 does not include components for electrical coupling. It includes components arranged according to layout 300 (e.g., including...). Figure 3 The memory device (with lines 302, bonding pads 304 and probe pads 306 arranged in the middle) can be a single-channel memory device.

[0052] ( Figure 2 The layout 200 (including lines 202, bonding pads 204, and probe pads 206) can be configured to be implemented on memory cells of a memory device having a specific layout. Furthermore, Figure 3The redistribution layer 300 (including lines 302, bonding pads 304, and probe pads 306) can be configured to be implemented on memory cells having a specific layout. In other words, the redistribution layer (including lines, bonding pads, and probe pads) can be arranged above memory cells of a memory device having a specific layout, according to either layout 200 or layout 300. The memory die according to the specific layout can be a composite die. For example, if the elements of the redistribution layer are arranged above the composite die according to layout 200, the composite die is used as and / or may be part of a dual-channel memory device. Alternatively, if the elements of the redistribution layer are arranged above the composite die according to layout 300, the composite die can be used as and / or may be part of a single-channel memory device.

[0053] As will be understood, probes can be configured to be electrically coupled to probe pads of a memory device to allow testing of the memory device. Probes can include multiple electrical contacts, which can be arranged according to the probe pads of the memory device configured for testing.

[0054] Embodiments of this disclosure include the layout of elements for a single-channel memory device that can be tested using probes configured to test a dual-channel memory device. Specifically, some embodiments of this disclosure include a layout of metal layers for a single-channel memory device that includes probe pads on both sides (e.g., opposite sides) of the memory device. This layout allows for testing of the single-channel memory device via probes configured to test either a dual-channel or single-channel memory device arranged according to the layout of this disclosure, for example, without requiring probe reconfiguration. For example, the electrical contacts of the probes can alternatively contact the probe pads in the dual-channel or single-channel memory device arranged according to the layout of this disclosure.

[0055] Therefore, some embodiments of this disclosure provide improvements over existing layouts by providing a layout that allows testing of a single-channel memory device using probes configured for testing a dual-channel memory device. Thus, embodiments of this disclosure can provide improvements in the production and testing of memory devices and / or reduce the cost of testing equipment. The layouts described herein may have additional advantages, for example, over other single-channel layouts. Some of these additional advantages are described below.

[0056] Figure 4 This is a functional block diagram illustrating an example layout 400 of a single-channel memory device according to at least one embodiment of the present disclosure, the layout including lines 402 (uniformly referring to lines 402a and 402b), bonding pads 404 (uniformly referring to bonding pads 404a and 404b), and probe pads 406 (uniformly referring to probe pads 406a and 406b). Layout 400 can be used in memory devices (e.g., Figure 1 Implemented in a memory device 100. Line 402 and line portion 412 may be part of one or more redistribution layers, which may be configured to be connected to the memory device (e.g., memory device 100) at terminals and / or pads. Figure 1 The signal and / or power are redistributed among other components of the memory device 100.

[0057] Line 402 may be a conductor disposed in a metal layer. Bonding pad 404 and probe pad 406 may, for example, be disposed in a metal layer and may be electrically coupled to line 402. Line 402 extends from a generally first side of the memory device to a generally second side of the memory device. Bonding pad 404 is disposed in channel A region 408. Probe pad 406a is disposed in channel A region 408, while probe pad 406b is disposed in channel B region 410.

[0058] 404 bonding pads can be used with Figure 2 The bonding pad 204 is the same as or substantially similar to the probe pad 406. Figure 2 The probe pad 206 is the same as or substantially similar to the probe pad 402. Figure 3 Line 302.

[0059] However, with Figure 3 Unlike layout 300, in layout 400, line 402 is electrically coupled to probe pad 406a in channel A region 408 and probe pad 406b in channel B region 410. One advantage of including probe pad 406b in channel B region 410 for a single-channel memory device is that probe pad 406b allows the same probe to be used to test the single-channel device (e.g., containing…). Figure 4 The layout 400) and dual-channel device. For example, the same probe can be used (e.g., without reconfiguring the probe) to test, for example, components according to... Figure 2 The dual-channel memory device with layout 200 of line 202 and probe pad 206, and including, for example, according to Figure 4 A single-channel memory device with layout 400, line 402, and probe pad 406.

[0060] Another advantage of including probe pad 406b in channel B region 410 is that it improves the electrical coupling from line 402 to the probe. For example, during test operations, the improved electrical coupling between line 402 and the probe may result in lower resistivity in the metal layer and reduced capacitive effects in line 402 (including, for example, a reduced charging time for line 402). For example, without probe pad 406b, such as in… Figure 3 In layout 300, between the proximal side (e.g., near channel A region 308) and the distal side (e.g., near channel B region 310) Figure 3 The impedance of line 302 (as seen at probe pad 306) can be greater than the impedance of line 402 (as seen at probe pads 406a and 406b). The impedance between the near and far sides of line 302 may cause a voltage drop and / or delay when charging line 302. Line 402, including probe pads 406a and 406b, may have a lower impedance than line 302, which may result in a lower voltage drop and / or less delay when charging line 402 compared to line 302.

[0061] Additionally, layout 400 includes a line portion 412 that can be configured to electrically couple two or more lines 402. Specifically, the line portion 412 can electrically couple lines 402a, both of which can be configured to electrically couple to voltage lines having the same voltage. For example, bonding pads 404a (which can be electrically coupled to line 402a) can be configured to electrically couple to a specific voltage line, such as V. DD2 Electrical coupling of line 402a through line portion 412 may result in line 402a (which may contain elements configured to couple to a specific voltage line (e.g., V)) being coupled to a specific voltage line. DD2 The impedance of all lines is reduced. Therefore, by reducing the impedance in the metal layer, line portion 412 can represent an improvement relative to at least some other layouts.

[0062] Line portion 412 may have the same conductive material as line 402. Furthermore, line portion 412 may be disposed in the same metal layer as line 402. Line portion 412 may be disposed in channel B region 410. Layout 400 may exclude bonding pads in channel B region 410, thereby leaving available space in the metal layer of channel B region 410. Specifically, because there are no bonding pads in channel B region 410 (and no lines for electrical coupling to bonding pads), available space may exist in channel B region 410 for line portion 412.

[0063] exist Figure 4 In the diagram, 10 lines 402 are shown for illustrative purposes. Similarly, for illustrative purposes, in... Figure 4 The image shows 10 bonding pads 404. Similarly, for illustrative purposes, in Figure 4 The diagram shows 12 probe pads 406. However, these illustrations are non-limiting, and the systems and apparatus of this disclosure may include any number of lines, bonding pads, and / or probe pads. Furthermore, the line portion 412 may be configured to electrically couple any number of lines 402.

[0064] Figure 5This is a functional block diagram illustrating an example layout 500 of a single-channel memory device according to at least one embodiment of the present disclosure, the layout including lines 502 (uniformly referring to lines 502a, 502b, and 502c), bonding pads 504 (uniformly referring to bonding pads 504a, 504b, and 504c), and probe pads 506. Layout 500 can be used in memory devices (e.g., Figure 1 The memory device 100 is implemented therein. Line 502, line portion 512, and lower line 514 may be part of one or more redistribution layers, which may be configured to be connected to the memory device (e.g., memory device 100) at terminals and / or pads. Figure 1 The signal and / or power are redistributed among other components of the memory device 100.

[0065] Line 502 may be a conductor disposed in a metal layer. Bonding pad 504 and probe pad 506 may, for example, be disposed in a metal layer and may be electrically coupled to line 502. Line 502 extends from a generally first side of the memory device to a generally second side of the memory device. Bonding pad 504 and probe pad 506 are disposed in channel A region 508.

[0066] Bonding pad 504 can be with Figure 2 The bonding pad 204 is the same as or substantially similar to the probe pad 506. Figure 2 The probe pad 206 is the same as or substantially similar to the probe pad 502. Figure 4 Line 402. Line part 512 can be connected to... Figure 4 The line portion 412 is the same or roughly similar.

[0067] Additionally, layout 500 includes a lower layer line 514 that can be configured to electrically couple two or more lines 502. Specifically, the lower layer line 514 can electrically couple lines 502b, both of which can be configured to electrically couple to voltage lines having the same voltage. For example, bonding pad 504b (which can be electrically coupled to line 502b) can be configured to electrically couple to a specific voltage line, such as V. SS Electrical coupling of line 502b through the underlying line 514 may result in line 502b (which may contain elements configured to couple to a specific voltage line (e.g., V)) being coupled to a specific voltage line. SS The impedance of all lines in the lower layer is reduced. Therefore, by reducing the impedance in the metal layer, the lower line 514 can represent an improvement relative to the layout of at least some other metal layers.

[0068] The lower layer line 514 may have the same conductive material as line 502. The lower layer line 514 may be in a metal layer (e.g., below line 502) and may be electrically coupled to line 502 through via 516.

[0069] The lower-level line 514 can be arranged in area 510 of channel B. Figure 5 The layout may not include the bonding pads in channel B region 510, thus leaving available space in the metal layer of channel B region 510. Specifically, because there are no bonding pads in channel B region 510 (and no lines for electrical coupling to the bonding pads), there may be available space in channel B region 510 for the underlying layer 514.

[0070] exist Figure 5 In the diagram, 10 lines 502 are shown for illustrative purposes. Similarly, for illustrative purposes, in... Figure 5 The image shows 10 bonding pads 504. Similarly, for illustrative purposes, in Figure 5 Six probe pads 506 are shown. However, these illustrations are non-limiting, and the systems and apparatus of this disclosure may include any number of lines, bonding pads, and / or probe pads. Furthermore, each of the line portions 512 and the underlying lines 514 may be configured to electrically couple any number of lines 502.

[0071] Figure 6 This is a functional block diagram illustrating an example layout 600 of a single-channel memory device according to at least one embodiment of the present disclosure, the layout including lines 602 (uniformly referring to lines 602a, 602b, and 602c), bonding pads 604 (uniformly referring to bonding pads 604a, 604b, and 604c), and probe pads 606 (uniformly referring to probe pads 606a and 606b). Layout 600 can be used in memory devices (e.g., Figure 1 Implemented in a memory device 100. Line 602, line portion 612, and lower line 614 may be part of one or more redistribution layers, which may be configured to be connected to the memory device (e.g., memory device 100) at terminals and / or pads. Figure 1 The signal and / or power are redistributed among other components of the memory device 100.

[0072] Line 602 may be a conductor disposed in a metal layer. Bonding pads 604 and probe pads 606 may, for example, be disposed in a metal layer and may be electrically coupled to line 602. Line 602 extends from a generally first side of the memory device to a generally second side of the memory device. Bonding pads 604 are disposed in channel A region 608. (Similar to...) Figure 4 As described by probe pads 406a and 406b, probe pad 606a is arranged in channel A region 608, while probe pad 606b is arranged in channel B region 610.

[0073] 604 bonding pads can be used with Figure 2 The bonding pad 204 is the same as or substantially similar to the probe pad 606. Figure 2 The probe pad 206 is the same as or substantially similar to the probe pad 602. Figure 4 Line 402. Line part 612 can be connected to... Figure 4 The line portion 412 is the same as or roughly similar to the line portion 614. The lower layer line 614 can be the same as... Figure 5 The lower layer line 514 is the same as or substantially similar. Through-hole 616 can be with... Figure 5 The through-holes are the same as or roughly similar to those of 516.

[0074] The layout 600, including probe pad 606b, line portion 612, and lower layer line 614, can exhibit the characteristics described above. Figure 4 406b probe pads Figure 4 The layout of line 400 and line 412 and Figure 5 The advantages described in the lower layer line 514 of layout 500. Specifically, a probe can be used to test memory devices arranged according to layout 600, the probe being further configured to test dual-channel memory devices (e.g., according to...) due to probe pads 606b. Figure 2 (The arrangement of the apparatus). Furthermore, due to the probe pad 606b, line 602b can be better electrically coupled to the power supply. Additionally, due to line portion 612, the line according to layout 600 can exhibit lower impedance at line 602a. Furthermore, due to the lower layer line 614, the line according to layout 600 can exhibit lower impedance at line 602b.

[0075] exist Figure 6 In the diagram, 10 lines 602 are shown for illustrative purposes. Similarly, for illustrative purposes, in... Figure 6 The image shows 10 bonding pads 604. Similarly, for illustrative purposes, in Figure 6 The diagram shows 12 probe pads 606. However, these descriptions are non-limiting, and the systems and apparatus of this disclosure may include any number of lines, bonding pads, and / or probe pads. Furthermore, each of the line portions 612 and the underlying lines 614 may be configured to electrically couple any number of lines 602.

[0076] Figure 7 This is a functional block diagram illustrating the layout of contact points of a probe 700 that can be used to test a memory device according to at least one embodiment of the present disclosure. The probe 700 includes test contact points 706a arranged in channel A region 708 and test contact points 706b arranged in channel B region 710.

[0077] Test contact 706 can be configured, for example, to supply power from probe 700 to the memory device during test operation. Test contact 706 can be arranged to be electrically coupled to... Figure 3 The layout of the 300 probe pads is 306. Figure 4 The layout includes 400 probe pads and / or 406. Figure 6 Any of the probe pads 606 in the layout 600. Specifically, the arrangement of the test contacts 706 on the probe 700 can reflect... Figure 4 The probe pads 406 and / or in the layout 400 Figure 6 The arrangement of any or all of the probe pads 606 in the layout 600.

[0078] Additionally, in some embodiments, although not shown, probe 700 may include one or more input / output contacts arranged to be electrically coupled to other pads of the memory device, such as input / output pads (e.g., ...). Figure 1 The probe 700 may be configured to provide and / or receive test signals (e.g., data inputs and outputs) from the memory device via input / output contacts. (This includes address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118.)

[0079] Additionally, in some embodiments, although not shown, probe 700 may include one or more contacts for an internal power supply. The internal power supply may include one or more wires or components configured to regulate and / or distribute power within the memory device. Probe 700 may be configured to supply power to the memory device under test through the contacts for the internal power supply as part of a test operation. Furthermore, probe 700 may be configured to observe the voltage and / or current at the contacts of the internal power supply as part of a test operation.

[0080] Figure 8A and 8B Commonly, there are flowcharts illustrating an example method 800 according to at least one embodiment of the present disclosure. In some embodiments, method 800 may consist of a probe (e.g., Figure 7 The method 800 can be performed on a device or system containing probe 700. The method 800 can be performed on a memory device (e.g., probe 700). Figure 1 Memory device 100 Figure 9 Memory system 900, Figure 10 The method 800 can be performed on an electronic system 1000 or another device or system. The method 800 can be performed on a dual-channel memory device (e.g., according to...). Figure 2 The method 800 can be executed on a memory device with layout 200. Alternatively, the method 800 can be executed on a single-channel memory device (e.g., according to...). Figure 4 Layout 400 or Figure 6 The layout 600 is executed on the memory device. Although shown as discrete boxes, the various boxes can be divided into additional boxes, combined into fewer boxes, or eliminated, depending on the desired implementation.

[0081] At frame 802, probes can be electrically coupled to a first probe pad and a second probe pad of a single-channel memory device. The first probe pad can be located on or near a first side of the memory device, while the second probe pad can be located on or near a second side of the memory device. For example, according to Figure 4 Layout 400 or Figure 6 The layout is 600 to arrange single-channel memory devices.

[0082] A single-channel memory device may include a first number of memory cells and a first number of lines disposed above the first number of memory cells. The first number of lines may extend from a generally first side of the single-channel memory device to a generally second side of the single-channel memory device. Each of the first number of lines may be electrically coupled to a first probe pad in a first probe pad and a second probe pad in a second probe pad.

[0083] At box 804, power can be supplied to the single-channel memory device via the first probe pad and the second probe pad. One or more test signals may be part of or associated with a test operation.

[0084] For example, at block 806, when the probe is electrically coupled to the first probe pad and the second probe pad, a first test operation can be performed on a single-channel memory device.

[0085] After box 806, the probe can be electrically decoupled from the first probe pad and the second probe pad of the single-channel memory device.

[0086] At frame 808, the probe can be electrically coupled to the third probe pad and the fourth probe pad of the dual-channel memory device. The third probe pad can be located on or near the third side of the dual-channel memory device, while the fourth probe pad can be located on or near the fourth side of the dual-channel memory device. For example, it can be based on... Figure 2 The layout 200 is used to arrange dual-channel memory devices.

[0087] A dual-channel memory device may include a second number of memory cells, a second number of lines disposed above the second number of memory cells, a third number of memory cells, and a third number of lines disposed above the third number of memory cells. The second number of lines may extend from approximately a third side of the dual-channel memory device to a middle portion of the dual-channel memory device. The third number of lines may extend from approximately a fourth side of the dual-channel memory device to a middle portion. Each of the second number of lines may be electrically coupled to a third probe pad in a third probe pad, and each of the third number of lines may be electrically coupled to a fourth probe pad in a fourth probe pad.

[0088] At box 810, the dual-channel memory device can be powered through the third and fourth probe pads. One or more test signals can be part of or associated with a test operation.

[0089] For example, at block 812, when the probe is electrically coupled to the third probe pad and the fourth probe pad, a second test operation can be performed on the dual-channel memory device.

[0090] Because the first probe pad can be positioned in the same location in a single-channel memory device as the third probe pad in a dual-channel memory device, and the second probe pad can be positioned in the same location in a single-channel memory device as the fourth probe pad in a dual-channel memory device, the same probe can be used to perform a first test operation on the single-channel memory device and a second test operation on the second memory device. Furthermore, the probe can be configured to perform the first test operation on both the single-channel and dual-channel memory devices without reconfiguring (e.g., rearranging the contacts) the probe.

[0091] Method 800 may be modified, added to, or omitted without departing from the scope of this disclosure. Furthermore, the operations and actions outlined are provided by way of example only, and some operations and actions may be optional, may be combined into fewer operations and actions, or may be extended into additional operations and actions without departing from the spirit of the disclosed embodiments. As an example, any or all of blocks 806, 808, 810, and / or 812 may be optional. Furthermore, the operations of method 800 may be performed in a different order. As an example, blocks 808, 810, and 812 may precede blocks 802, 804, and 806.

[0092] Figure 9 This is a simplified block diagram illustrating an example memory system 900 implemented according to at least one embodiment of the present disclosure. The memory system 900, which may include, for example, semiconductor devices, includes a plurality of memory devices 902 and a controller 904. The controller 904 is operatively coupled to the memory devices 902 to transmit command / address signals (e.g., by...) Figure 1 The command / address signals received by the command terminal 112 and / or address terminal 110 are transmitted to the memory device 902.

[0093] Memory device 902 may include line, bonding pads, and / or probe pads as described herein. For example, memory device 902 may include according to... Figure 4 Layout 400 Figure 5 Layout 500 or Figure 6 The layout of the components is arranged in a 600-fold pattern.

[0094] An electronic system is also disclosed. According to various embodiments, the electronic system may include a memory device comprising a plurality of memory dies, each memory die having an array of memory cells. Each memory cell may include an access transistor and a memory element operatively coupled to the access transistor.

[0095] Figure 10 This is a simplified block diagram illustrating an electronic system 1000 implemented according to at least one embodiment of the present disclosure. The electronic system 1000 includes at least one input device 1002, which may include, for example, a keyboard, mouse, or touchscreen. The electronic system 1000 further includes at least one output device 1004, such as a monitor, touchscreen, or speaker. The input device 1002 and the output device 1004 need not be separate from each other. The electronic system 1000 further includes a storage device 1006. The input device 1002, output device 1004, and storage device 1006 may be coupled to a processor 1008. The electronic system 1000 further includes a memory device 1010 coupled to the processor 1008. The memory device 1010 may include… Figure 9 The electronic system 1000 may include at least a portion of the memory system 900. The electronic system 1000 may comprise, for example, computing, processing, industrial, or consumer products. For example, but not limited to, the electronic system 1000 may include personal computers or computer hardware components, servers or other networking hardware components, database engines, intrusion prevention systems, handheld devices, tablet computers, electronic notebooks, cameras, telephones, music players, wireless devices, displays, chipsets, game consoles, vehicles, or other known systems.

[0096] Some embodiments of this disclosure include a memory device comprising a plurality of memory cells and a plurality of wires disposed above the plurality of memory cells. The plurality of wires may extend from a generally first side of the memory device to a generally second side of the memory device. Each of the plurality of wires may be electrically coupled to a bonding pad, a first probe pad, and a second probe pad. The bonding pad may be located on or near the first side. The bonding pad may be configured to receive power. The first probe pad may be located on or near the first side. The first probe pad may be configured to be electrically coupled to a probe. The second probe pad may be located on or near the second side.

[0097] Some embodiments of this disclosure include a system comprising: at least one input device; at least one output device; at least one processor device operatively coupled to the input device and the output device; and at least one memory device operatively coupled to the at least one processor device. The at least one memory device may include a plurality of memory cells; a first side; a second side opposite to the first side; and a metal layer disposed above the plurality of memory cells. The metal layer may include a plurality of metal lines extending substantially from the first side to substantially the second side. The plurality of metal lines may be configured to supply power to the plurality of memory cells. Each of the plurality of metal lines may be electrically coupled to: a bonding pad, a first probe pad, and a second probe pad. The bonding pad may be located at or near the first side and within the metal layer. The bonding pad may be adapted to receive power for the plurality of memory cells. The first probe pad may be located at or near the first side and within the metal layer. The first probe pad may be adapted to provide electrical coupling with probes used for testing the plurality of memory cells. The second probe pad may be located in or near the metal layer on the second side. The second probe pad may be adapted to provide electrical coupling with the probe.

[0098] Some embodiments of this disclosure include a memory device comprising a plurality of memory cells and a plurality of wires. The plurality of wires may be disposed in a metal layer above the plurality of memory cells. The plurality of wires may extend from a generally first side of the memory device to a generally second side of the memory device. Each of the plurality of wires may be electrically coupled to: a bonding pad and a probe pad. The bonding pad may be located at or near the first side and is configured to receive power. The probe pad may be located at or near the first side and may be configured to be electrically coupled to a probe. The memory device may further include wires electrically coupled to at least two of the plurality of wires. The wires may be disposed below the metal layer.

[0099] Some embodiments of this disclosure include a system comprising: at least one input device; at least one output device; at least one processor device operatively coupled to the input device and the output device; and at least one memory device operatively coupled to the at least one processor device. The at least one memory device may include: a plurality of memory cells; a first side; a second side opposite to the first side; and a first metal layer disposed above the plurality of memory cells. The first metal layer may include a plurality of metal lines extending substantially from the first side to substantially the second side. The plurality of metal lines may be configured to supply power to the plurality of memory cells. Each of the plurality of metal lines may be electrically coupled to: a bonding pad and a probe pad. The bonding pad may be located at or near the first side and within the first metal layer. The bonding pad may be configured to receive power for the plurality of memory cells. The probe pad may be located at or near the first side and within the first metal layer. The probe pad may be configured to provide electrical coupling with probes used for testing the plurality of memory cells. The at least one memory device may further include a second metal layer disposed beneath the first metal layer. The second metal layer may include metal lines electrically coupled to at least two of the plurality of metal lines.

[0100] Some embodiments of this disclosure include a method for testing a memory device. The method may include electrically coupling probes to first probe pads and second probe pads of a single-channel memory device. The single-channel memory device may include a first number of memory cells and a first number of lines disposed above the first number of memory cells. The first number of lines may extend from substantially a first side of the single-channel memory device to substantially a second side of the single-channel memory device. Each of the first number of lines may be electrically coupled to a first probe pad in the first probe pads and a second probe pad in the second probe pads. The first probe pad may be disposed at or near the first side. The second probe pad may be disposed at or near the second side. The method may further include providing one or more test signals to the single-channel memory device through the first probe pads and the second probe pads.

[0101] As is customary, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations used to describe various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Additionally, some drawings may be simplified for clarity. Therefore, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0102] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For example, an apparatus or memory device may include a system-on-a-chip (SoC).

[0103] As used herein, unless otherwise specified, the term “semiconductor” shall be interpreted broadly to include microelectronic and MEMS devices (e.g., magnetic storage, optical devices, etc.) that may or may not operate using semiconductor functions.

[0104] The terms used herein, particularly in the appended claims (e.g., the body of the appended claims), are generally expected to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0105] Furthermore, if a specific number of the introduced claim statements are required, such intent will be explicitly stated in the claims, and if no such statements are present, such intent does not exist. For example, to aid understanding, appended claims may use the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing a claim statement with the indefinite article “a (a / an)” would limit any particular claim containing this introduced claim statement to an embodiment containing only one of such statements, even if the same claim contains the introductory phrases “one or more” or “at least one” and the indefinite article (e.g., “a (a / an)”) (e.g., “a (a / an)” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim statements. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0106] Furthermore, even if a specific number of the described claims are explicitly stated, it should be understood that such a statement should be interpreted as meaning at least the number stated (e.g., simply stating "two statements" without any other modifiers to indicate at least two statements or two or more statements). Moreover, in cases where similar conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, such structures are generally intended to include a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term "and / or" is intended to be interpreted in this way.

[0107] Furthermore, any transitional words or phrases presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to presuppose the possibility of including one, one, or both of these terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0108] Furthermore, the use of terms such as "first," "second," and "third" does not necessarily imply a specific order or quantity of elements herein. Generally, the terms "first," "second," and "third" are used to distinguish different elements as general identifiers. Unless otherwise stated, the terms "first," "second," and "third" should not be construed as implying a specific order. Similarly, if the terms "first," "second," and "third" are stated as implying a specific number of elements, they should not be construed as implying a specific number of elements.

[0109] Additionally, as used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and to a certain extent includes what a person of ordinary skill in the art would understand as meeting a given parameter, characteristic, or condition with minor variations, such as, for example, within acceptable manufacturing tolerances. For example, depending on whether a particular parameter, characteristic, or condition is substantially met, it could be met at least 90%, at least 95%, or even at least 99%. Furthermore, as used herein, the term "close to" can mean physically close, adjacent, or near.

[0110] The embodiments of this disclosure described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, various modifications to this disclosure, such as alternative useful combinations of the described elements, will be apparent to those skilled in the art from the specification, in addition to those modifications shown and described herein. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. A memory device comprising: Several memory units; as well as A plurality of wires are arranged in a first metal layer above the plurality of memory cells, the plurality of wires extending from a substantially first side of the memory device to a substantially second side of the memory device, at least two of the plurality of wires being electrically coupled together at or near the second side by wires arranged in a second metal layer below the first metal layer, each of the plurality of wires being electrically coupled to: A corresponding bonding pad, the corresponding bonding pad being located at or near the first side, the bonding pad being configured to receive power; A corresponding first probe pad, the corresponding first probe pad being located at or near the first side, the first probe pad being configured to be electrically coupled to the probe; as well as The corresponding second probe pad is located on or near the second side.

2. The memory device according to claim 1, wherein, The memory device contains bonding pads only on or near the first side.

3. The memory device according to claim 1, wherein, The memory device includes a single-channel memory device with bonding pads located only on or near the first side of the memory device.

4. The memory device according to claim 1, wherein, Each of the bonding pads, the first probe pad, and the second probe pad is arranged in the same layer as the plurality of conductors.

5. The memory device according to claim 1, wherein, The several wires are arranged in a single metal layer of the memory device.

6. The memory device according to claim 5, wherein, The single metal layer is the uppermost metal layer in one or more redistribution layers of the memory device.

7. The memory device according to claim 1, wherein, The plurality of wires are arranged in a metal layer, and at least two of the plurality of wires are electrically coupled together in the metal layer at or near the second side.

8. The memory device according to claim 1, wherein, At least two of the several wires are electrically coupled together in the first metal layer at or near the second side.

9. A system comprising: At least one input device; At least one output device; At least one processor device, the at least one processor device being operatively coupled to the input device and the output device; as well as At least one memory device, operatively coupled to the at least one processor device, the at least one memory device comprising: Several memory units; First side; The second side opposite to the first side; and A metal layer disposed above the plurality of memory cells, the metal layer comprising a plurality of metal lines extending from substantially a first side to substantially a second side, the plurality of metal lines being configured to supply power to the plurality of memory cells, at least two of the plurality of metal lines being electrically coupled together at or near the second side via metal lines disposed in a second metal layer below the metal layer, each of the plurality of metal lines being electrically coupled to: Corresponding bonding pads, the corresponding bonding pads being located at or near the first side and within the metal layer, the bonding pads being adapted to receive power for the plurality of memory cells; A corresponding first probe pad, located at or near the first side and within the metal layer, the first probe pad being adapted to provide electrical coupling with probes used for testing the plurality of memory cells; and A corresponding second probe pad is located on or near the second side and within the metal layer, the second probe pad being adapted to provide electrical coupling with the probe.

10. The system according to claim 9, wherein, The at least one memory device contains bonding pads only on or near the first side.

11. The system according to claim 9, wherein, The at least one memory device includes at least one single-channel memory device having bonding pads located only on or near the first side of the at least one memory device.

12. The system according to claim 9, wherein, The metal layer is the uppermost metal layer in one or more redistribution layers of the at least one memory device.

13. The system according to claim 9, wherein, At least two of the plurality of metal wires are electrically coupled together in the metal layer at or near the second side.

14. The system according to claim 9, wherein, At least two of the metal wires are electrically coupled together in the metal layer at or near the second side.

15. A memory device comprising: Several memory units; A plurality of wires are arranged in a metal layer above the plurality of memory cells, the plurality of wires extending from a generally first side of the memory device to a generally second side of the memory device, each of the plurality of wires being electrically coupled to: A corresponding bonding pad, the corresponding bonding pad being located at or near the first side, the bonding pad being configured to receive power; as well as A corresponding probe pad, the corresponding probe pad being located at or near the first side, the probe pad being configured to be electrically coupled to the probe; as well as A conductor electrically coupled to at least two of the plurality of conductors, the conductor being disposed beneath the metal layer.

16. The memory device according to claim 15, wherein, The memory device contains bonding pads only on or near the first side.

17. The memory device according to claim 15, wherein, The memory device includes a single-channel memory device with bonding pads located only on or near the first side of the memory device.

18. The memory device according to claim 15, wherein, The metal layer is the uppermost metal layer in one or more redistribution layers of the memory device.

19. The memory device according to claim 15, wherein, Each of the bonding pads and the probe pads is arranged in the same layer as the metal layer.

20. The memory device according to claim 15, wherein, At least two of the plurality of wires are electrically coupled together in the metal layer at the second side.

21. The memory device according to claim 15, wherein, The wire is arranged in a second metal layer below the first metal layer.

22. The memory device according to claim 15, wherein, The probe pad includes a first probe pad, and each of the plurality of wires is further electrically coupled to a second probe pad at or near the second side.

23. A system comprising: At least one input device; At least one output device; At least one processor device, the at least one processor device being operatively coupled to the input device and the output device; as well as At least one memory device, operatively coupled to the at least one processor device, the at least one memory device comprising: Several memory units; First side; The second side opposite to the first side; and A first metal layer, disposed above the plurality of memory cells, includes a plurality of metal lines extending from substantially a first side to substantially a second side, the plurality of metal lines being configured to supply power to the plurality of memory cells, each of the plurality of metal lines being electrically coupled to: Corresponding bonding pads, located on or near the first side and within the first metal layer, are configured to receive power for the plurality of memory cells; and Corresponding probe pads, located on or near the first side and within the first metal layer, are configured to provide electrical coupling with probes used for testing the plurality of memory cells; and A second metal layer is disposed below the first metal layer, and the second metal layer includes metal wires electrically coupled to at least two of the plurality of metal wires.

24. The system according to claim 23, wherein, The at least one memory device contains bonding pads only on or near the first side.

25. The system according to claim 23, wherein, The at least one memory device includes a single-channel memory device with bonding pads located only on or near the first side of the at least one memory device.

26. The system according to claim 23, wherein, The first metal layer is the uppermost metal layer in one or more redistribution layers of the memory device.

27. The system according to claim 23, wherein, Each of the bonding pads and the probe pads is arranged in the first metal layer.

28. The system according to claim 23, wherein, At least two of the plurality of metal wires are electrically coupled together in the first metal layer at the second side.

29. The system according to claim 23, wherein, The probe pad includes a first probe pad, and each of the plurality of metal lines is further electrically coupled to a second probe pad at or near the second side.

30. A method for testing a memory device, the method comprising: The probes are electrically coupled to the first and second probe pads of the single-channel memory device. The single-channel memory device includes: The first number of memory units; and A first number of wires disposed in a first metal layer above the first number of memory cells, the first number of wires extending from substantially a first side of the single-channel memory device to substantially a second side of the single-channel memory device, at least two of the first number of wires being electrically coupled together at or near the second side via wires disposed in a second metal layer below the first metal layer, each of the first number of wires being electrically coupled to: A corresponding bonding pad, the corresponding bonding pad being located at or near the first side, the bonding pad being configured to receive power; The corresponding first probe pad in the first probe pad, the first probe pad being arranged at or near the first side; and The corresponding second probe pad in the second probe pad, the second probe pad being arranged at or near the second side; and The single-channel memory device is powered through the first probe pad and the second probe pad.

31. The method of claim 30, further comprising performing a first test operation on the single-channel memory device.

32. The method of claim 30, further comprising: The probes are electrically coupled to a third probe pad and a fourth probe pad of a dual-channel memory device, the dual-channel memory device comprising: The second number of memory units; A second number of lines are arranged above the second number of memory cells, the second number of lines extending from approximately a third side of the dual-channel memory device to the middle portion of the dual-channel memory device, each of the second number of lines being electrically coupled to a corresponding third probe pad in the third probe pad, the third probe pad being arranged at or near the third side; The third number of memory units; and A third number of lines are arranged above the third number of memory cells, the third number of lines extending from approximately a fourth side of the dual-channel memory device to the intermediate portion, each of the third number of lines being electrically coupled to a corresponding fourth probe pad in the fourth probe pad, and the fourth probe pad being arranged at or near the fourth side; and The dual-channel memory device is powered through the third probe pad and the fourth probe pad.

33. The method of claim 32, further comprising: When the probe is electrically coupled to the first probe pad and the second probe pad, a first test operation is performed on the single-channel memory device. as well as When the probe is electrically coupled to the third probe pad and the fourth probe pad, a second test operation is performed on the dual-channel memory device.

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