Shielded gate trench field effect transistor with low on-resistance and method of manufacturing the same

Abstract

The application relates to a shielded gate trench field effect transistor with low on-resistance, which comprises a substrate region, a drift region, a base region, a source region, a trench region, a drain and a source; the trench region comprises a shield gate, a control gate, an insulating layer and a metal gate; the shield gate is of a variable doping concentration structure, and the doping concentration of the shield gate gradually decreases from top to bottom. When the transistor is forward blocked, the doping concentration of the part of the shield gate close to the substrate region is lower. Thus, the part of the shield gate close to the substrate region is more easily depleted under the same applied voltage, that is, the part close to the substrate region has a thicker depletion layer width. The width of the depletion layer is inversely proportional to the capacitance size of the parasitic capacitance, thus, the parasitic capacitance formed between the shield gate and the substrate region in the embodiment of the application is smaller, the parasitic capacitance formed between the shield gate and the substrate region is weakened, and the switching speed of the device is improved.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, and in particular to a shielded gate trench field-effect transistor with low on-resistance and its fabrication method. Background Technology

[0002] Split-gate trench field-effect transistors (SGTs) have been widely used in important low-voltage applications such as power management. SGTs feature high channel density and good charge compensation. Furthermore, their shielded gate structure effectively isolates the coupling between the control gate and drain, thus significantly reducing transfer capacitance.

[0003] Therefore, SGT has lower specific on-resistance, lower conduction and switching losses, and higher operating frequency.

[0004] In SGT devices, due to the electric field concentration effect and the high polysilicon doping concentration of the shielding gate, when the SGT device is forward blocked, the charge flux emitted by the ionized donors in the breakdown region is concentrated at the corner of the trench shielding gate, resulting in a higher peak voltage at the corner of the trench shielding gate, and it is also easier to be broken down at this point.

[0005] Therefore, in order to improve the withstand voltage at the corner of the trench shielding gate in SGT devices, it is urgent to design a new type of shielding gate trench field-effect transistor. Summary of the Invention

[0006] To overcome the problems existing in related technologies, this application provides a shielded gate trench field-effect transistor with low on-resistance, comprising:

[0007] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source 7;

[0008] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 as the top, and the substrate region 3 and the source region 4 are sequentially disposed above the drift region 2;

[0009] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively;

[0010] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate; the control gate 52 and the shielding gate 51 are arranged sequentially from top to bottom in the trench region 5 and are separated by the insulating layer 53; the control gate 52 is connected to the substrate region 3 and the source region 4 respectively through the insulating layer 53, and the shielding gate 51 is connected to the drift region 2 through the insulating layer 53;

[0011] The shielding gate 51 has a variable doping concentration structure, and the doping concentration of the shielding gate 51 decreases step by step from top to bottom;

[0012] The source region 4 is composed of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are arranged sequentially along the top surface of the substrate region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53.

[0013] The source electrode 7 is disposed above the source region 4.

[0014] In one embodiment, the shielding grid 51 includes a first-level shielding grid 510, a second-level shielding grid 511, and a third-level shielding grid 512;

[0015] The first-stage shielding gate 510 has a heavy doping concentration; the second-stage shielding gate 511 has a medium doping concentration; and the third-stage shielding gate 512 has a low doping concentration.

[0016] In one embodiment, the insulating layer 53 includes: a low dielectric sublayer 531 and an oxide sublayer 532;

[0017] The control gate 52 is connected to the substrate region 3 through the oxide sublayer 532;

[0018] The shielding gate 51 is connected to the drift region 2 through the low dielectric coefficient sublayer 531.

[0019] In one embodiment, the bottom surface of the low dielectric coefficient sublayer 531 is on the same plane as the bottom surface of the drift region 2.

[0020] In one embodiment, the doping concentrations of both the P-type source region 42 and the N-type source region 41 are heavily doped.

[0021] In one embodiment, the substrate region 1 is doped with N-type doping and the doping concentration of the substrate region 1 is a heavily doped concentration.

[0022] The drift region 2 is N-type doped, and the doping concentration of the drift region 2 is light doping concentration;

[0023] The substrate region 3 is p-type doped, and the doping concentration of the substrate region 3 is medium.

[0024] The doping concentration of the source region 4 is a heavily doped concentration; the doping concentration of the control gate 52 is a heavily doped concentration.

[0025] A second aspect of this application provides a method for fabricating a shielded gate trench field-effect transistor with low on-resistance, used to fabricate a shielded gate trench field-effect transistor with low on-resistance as described in any one of the first aspects of this application, comprising:

[0026] The substrate region is prepared using semiconductor materials;

[0027] A drift region is epitaxially formed on the substrate region;

[0028] A matrix region is formed on the drift region by ion implantation or diffusion.

[0029] Grooves are etched on the side of the drift region;

[0030] Oxide, polysilicon, oxide, polysilicon and oxide are deposited sequentially in the trench to form an insulating layer, a shielding gate and a control gate; the shielding gate has a variable doping concentration structure;

[0031] A source region is formed on the matrix region;

[0032] Metal is deposited on the source region to form a source electrode;

[0033] The drain is fabricated below the substrate region.

[0034] In one embodiment, the step of sequentially depositing oxide, polysilicon, oxide, polysilicon, and oxide within the trench to form an insulating layer, a shielding gate, and a control gate includes:

[0035] A low-dielectric-coefficient dielectric, polysilicon, and another low-dielectric-coefficient dielectric are sequentially deposited within the trench to form a low-dielectric-coefficient sublayer and a shielding gate.

[0036] Oxide, polysilicon and oxide are sequentially deposited on the low dielectric sublayer to form an oxide sublayer and a control gate;

[0037] The low dielectric constant sublayer and the oxide sublayer constitute the insulating layer.

[0038] In one embodiment, the step of sequentially depositing a low-dielectric-coefficient dielectric, polysilicon, and another low-dielectric-coefficient dielectric within a trench to form a low-dielectric-coefficient sublayer and a shielding gate includes:

[0039] A low-dielectric-coefficient dielectric, polysilicon, and another low-dielectric-coefficient dielectric are sequentially deposited within a trench to form a low-dielectric-coefficient sublayer, a first-level shielding gate, a second-level shielding gate, and a third-level shielding gate. The first-level shielding gate has a high doping concentration, the second-level shielding gate has a medium doping concentration, and the third-level shielding gate has a low doping concentration.

[0040] The technical solution provided in this application may include the following beneficial effects:

[0041] In traditional SGTs, the shielding gate is made of heavily doped polysilicon. When the transistor is forward-blocked, parasitic capacitance exists between the depletion layer in the shielding gate and the substrate region. This parasitic capacitance slows down the switching speed of the transistor in a traditional transistor.

[0042] Therefore, in this application, the shielding gate has a variable doping concentration structure, with the doping concentration decreasing progressively from top to bottom. When the transistor is forward-biased, the doping concentration of the shielding gate is lower in the portion near the substrate region. Consequently, the portion of the shielding gate near the substrate region is more easily depleted under the same applied voltage, meaning that the portion near the substrate region has a thicker depletion layer width. Since the width of the depletion layer is inversely proportional to the size of the parasitic capacitance, the parasitic capacitance formed between the shielding gate and the substrate region in this embodiment is smaller, weakening the parasitic capacitance between the shielding gate and the substrate region, thereby improving the switching speed of the device.

[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0044] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0045] Figure 1 This is a schematic diagram of the structure of a shielded gate trench field-effect transistor with low on-resistance shown in the embodiments of this application;

[0046] Figure 2 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor with low on-resistance according to an embodiment of this application.

[0047] Figure 3 This is another schematic diagram of the fabrication method of a shielded gate trench field-effect transistor with low on-resistance shown in the embodiments of this application. Detailed Implementation

[0048] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0049] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0050] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0051] Example 1

[0052] In SGT devices, due to the electric field concentration effect and the high polysilicon doping concentration of the shielding gate, the parasitic capacitance formed between the shielding gate and the substrate region is large when the SGT device is forward blocked, which reduces the switching speed of the transistor.

[0053] Therefore, to improve the switching speed of SGT devices, it is necessary to reduce the parasitic capacitance formed between the shielding gate and the substrate region. This application provides a shielded gate trench field-effect transistor with low on-resistance.

[0054] Figure 1 This is a schematic diagram of the structure of a shielded gate trench field-effect transistor with low on-resistance shown in an embodiment of this application.

[0055] See Figure 1 The low on-resistance shielded gate trench field-effect transistor shown in this application embodiment includes:

[0056] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source 7;

[0057] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 as the top, and the substrate region 3 and the source region 4 are sequentially disposed above the drift region 2;

[0058] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively;

[0059] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate; the control gate 52 and the shielding gate 51 are arranged sequentially from top to bottom in the trench region 5 and are separated by the insulating layer 53; the control gate 52 is connected to the substrate region 3 and the source region 4 respectively through the insulating layer 53, and the shielding gate 51 is connected to the drift region 2 through the insulating layer 53;

[0060] The shielding gate 51 has a variable doping concentration structure, and the doping concentration of the shielding gate 51 decreases step by step from top to bottom;

[0061] The source region 4 is composed of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are arranged sequentially along the top surface of the substrate region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53.

[0062] The source electrode 7 is disposed above the source region 4.

[0063] In this embodiment, the substrate region 1 is doped with N-type doping and has a heavy doping concentration; the drift region 2 is doped with N-type doping and has a light doping concentration; the substrate region 3 is doped with P-type doping and has a medium doping concentration; the source region 4 has a heavy doping concentration; and the control gate 52 has a heavy doping concentration, and the control gate 52 is doped with either P-type or N-type doping.

[0064] In this embodiment, the light doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The doping concentration ranges from 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The range of heavily doped concentration is 1×10. 19 cm -3 Up to 5×10 20 cm -3 .

[0065] In the embodiments of this application, the doping type of the shielding gate is P-type doping or N-type doping.

[0066] Furthermore, the doping concentration of the shielding gate can be either heavily doped or moderately doped.

[0067] In traditional SGTs, the shielding gate is made of heavily doped polysilicon. When the transistor is forward-blocked, parasitic capacitance exists between the depletion layer in the shielding gate and the substrate region. This parasitic capacitance slows down the switching speed of the transistor in a traditional transistor.

[0068] Therefore, in this embodiment, the shielding gate is a variable doping concentration structure, with the doping concentration decreasing progressively from top to bottom. When the transistor is forward-biased, the doping concentration of the shielding gate is lower in the portion near the substrate region. Consequently, the portion of the shielding gate near the substrate region is more easily depleted under the same applied voltage, meaning it has a thicker depletion layer width. Since the width of the depletion layer is inversely proportional to the size of the parasitic capacitance, the parasitic capacitance formed between the shielding gate and the substrate region in this embodiment is smaller, weakening the parasitic capacitance between the shielding gate and the substrate region, thereby improving the switching speed of the device.

[0069] Example 2

[0070] Based on the transistor described in Embodiment 1, due to the electric field concentration effect, when the SGT device is forward blocked, the charge flux emitted by the ionized donors in the withstand voltage region is concentrated at the corner of the trench shielding gate, resulting in a higher peak voltage at the corner of the trench shielding gate.

[0071] Therefore, to improve the breakdown voltage of SGT devices, it is necessary to reduce the electric field strength at the corners of the shielding gate in the trench region. This application provides a shielding gate trench field-effect transistor with low on-resistance.

[0072] Figure 1 This is a schematic diagram of the structure of a shielded gate trench field-effect transistor with low on-resistance shown in an embodiment of this application.

[0073] See Figure 1 The low on-resistance shielded gate trench field-effect transistor shown in this application embodiment includes:

[0074] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source 7;

[0075] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 as the top, and the substrate region 3 and the source region 4 are sequentially disposed above the drift region 2;

[0076] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively;

[0077] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate; the control gate 52 and the shielding gate 51 are arranged sequentially from top to bottom in the trench region 5 and are separated by the insulating layer 53; the control gate 52 is connected to the substrate region 3 and the source region 4 respectively through the insulating layer 53, and the shielding gate 51 is connected to the drift region 2 through the insulating layer 53;

[0078] In this embodiment, the shielding gate 51 is a variable doping concentration structure, and the doping concentration of the shielding gate 51 decreases gradually from top to bottom.

[0079] Furthermore, the shielding gate 51 includes a first-level shielding gate 510, a second-level shielding gate 511, and a third-level shielding gate 512; the first-level shielding gate 510 has a heavily doped concentration; the second-level shielding gate 511 has a medium doped concentration; and the third-level shielding gate 512 has a low doped concentration.

[0080] In this embodiment, the third-level shielding gate is disposed at the bottom of the shielding gate, close to the substrate region, and the doping concentration of the third-level shielding gate is low. Therefore, when the transistor is forward-blocked, the third-level shielding gate is more easily depleted under the same applied voltage, resulting in a thicker depletion layer width. Consequently, the parasitic capacitance formed between the third-level shielding gate and the substrate region is smaller, weakening the parasitic capacitance between the shielding gate and the substrate region, thereby improving the switching speed of the device.

[0081] The source region 4 is composed of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are arranged sequentially along the top surface of the substrate region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53.

[0082] The source electrode 7 is disposed above the source region 4.

[0083] It should be noted that the doping concentration and arrangement of the substrate region 1, drift region 2, substrate region 3, source region 4 and trench region 5 in this embodiment are the same as in Embodiment 1, and will not be repeated here.

[0084] In this embodiment, to improve the withstand voltage capability of the SGT device, it is necessary to reduce the electric field strength at the corner of the trench shielding gate. Further, the insulating layer 53 includes a low-dielectric-coefficient sublayer 531 and an oxide sublayer 532. The control gate 52 is connected to the substrate region 3 through the oxide sublayer 532; the shielding gate 51 is connected to the drift region 2 through the low-dielectric-coefficient sublayer 531. The bottom surface of the low-dielectric-coefficient sublayer 531 is on the same plane as the bottom surface of the drift region 2.

[0085] In this embodiment, the shielding gate is connected to the drift region via a low-dielectric-coefficient sublayer. Since the low-dielectric-coefficient sublayer can withstand a certain lateral voltage drop compared to the oxide sublayer under the same lateral voltage, when the transistor is forward-blocked, the low-dielectric-coefficient sublayer can suppress the lateral depletion effect between the drift region and the shielding gate, thereby weakening the electric field strength at the corner of the trench region's shielding gate and improving the trench region's withstand voltage at the corner.

[0086] Example 3

[0087] Corresponding to the low on-resistance shielded gate trench field-effect transistor shown in Embodiment 1, this application also provides a method for fabricating a low on-resistance shielded gate trench field-effect transistor and corresponding embodiments.

[0088] Figure 2 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor according to an embodiment of this application.

[0089] like Figure 2 As shown in the embodiments of this application, the fabrication method of the low on-resistance shielded gate trench field-effect transistor includes the following steps:

[0090] 201. Fabrication of substrate regions using semiconductor materials;

[0091] In the embodiments of this application, the substrate region is prepared using N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is the heavy doping concentration.

[0092] 202. A drift region is epitaxially formed on the substrate region;

[0093] In the embodiments of this application, different epitaxial processes can be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0094] 203. A matrix region is formed on the drift region by ion implantation or diffusion;

[0095] Ion implantation is a process of doping silicon materials. In practical applications, the power device is placed at one end of the ion implanter, and the dopant ion source is placed at the other end. At the dopant ion source, the dopant atoms are ionized, thus acquiring a certain charge. They are then accelerated to ultra-high speed by an electric field, penetrating the product surface and using their momentum to implant the dopant atoms into the power device, forming a doped region.

[0096] Diffusion is a process of incorporating pure impurity atoms into the surface of silicon materials. In practical applications, diborane or phosphine are usually used as ion sources, and pure impurity atoms are incorporated into the surface of silicon materials through intermittent diffusion or substitutional diffusion.

[0097] It should be noted that the embodiments of this application do not have strict limitations on the preparation method of the substrate region. In actual process, different processes described above can be selected to complete the preparation of the substrate region according to actual needs.

[0098] 204. Etch grooves on the side of the drift zone;

[0099] In this embodiment, a trench is etched on one side of the drift region using photolithography, and the residual photoresist is removed by wet etching or dry etching.

[0100] 205. Oxide, polysilicon, oxide, polysilicon and oxide are deposited sequentially in the trench to form an insulating layer, a shielding gate and a control gate;

[0101] Preferably, in this embodiment of the application, oxide, heavily doped polysilicon, oxide and heavily doped polysilicon are sequentially deposited in the trench to form the shielding gate, insulating layer and control gate.

[0102] In this embodiment, the doping concentration of the shielding gate decreases gradually from top to bottom, that is, the doping concentration of the portion of the shielding gate near the control gate is the highest, while the doping concentration of the portion of the shielding gate near the substrate region is the lowest.

[0103] 206. A source region is formed on the matrix region;

[0104] 207. Deposit metal on the source region to form a source electrode;

[0105] 208. Fabricate the drain below the substrate region.

[0106] In traditional SGTs, the shielding gate is made of heavily doped polysilicon. When the transistor is forward-blocked, parasitic capacitance exists between the depletion layer in the shielding gate and the substrate region. This parasitic capacitance slows down the switching speed of the transistor in a traditional transistor.

[0107] Therefore, in this embodiment, the shielding gate is a variable doping concentration structure, with the doping concentration decreasing progressively from top to bottom. When the transistor is forward-biased, the doping concentration of the shielding gate is lower in the portion near the substrate region. Consequently, the portion of the shielding gate near the substrate region is more easily depleted under the same applied voltage, meaning it has a thicker depletion layer width. Since the width of the depletion layer is inversely proportional to the size of the parasitic capacitance, the parasitic capacitance formed between the shielding gate and the substrate region in this embodiment is smaller, weakening the parasitic capacitance between the shielding gate and the substrate region, thereby improving the switching speed of the device.

[0108] Example 4

[0109] Corresponding to the low on-resistance shielded gate trench field-effect transistor shown in Embodiment 2, this application also provides a method for fabricating a low on-resistance shielded gate trench field-effect transistor and corresponding embodiments.

[0110] Figure 3 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor with low on-resistance, as shown in an embodiment of this application.

[0111] like Figure 3 As shown, it includes the following steps:

[0112] 301. Fabrication of a substrate region using semiconductor materials;

[0113] 302. A drift region is epitaxially formed on the substrate region;

[0114] 303. A matrix region is formed on the drift region by ion implantation or diffusion;

[0115] 304. Etch grooves on the side of the drift zone;

[0116] 305. A low dielectric constant dielectric, polysilicon and another low dielectric constant dielectric are sequentially deposited in the trench to form a low dielectric constant sublayer, a first-level shielding gate, a second-level shielding gate and a third-level shielding gate.

[0117] In this embodiment, the first-level shielding gate has a high doping concentration, the second-level shielding gate has a medium doping concentration, and the third-level shielding gate has a low doping concentration.

[0118] 306. Oxide, polysilicon and oxide are sequentially deposited on the low dielectric constant sublayer to form an oxide sublayer and a control gate;

[0119] In this embodiment, the low dielectric sublayer and the oxide sublayer constitute the insulating layer.

[0120] 307. A source region is formed on the matrix region;

[0121] 308. Deposit metal on the source region to form a source electrode;

[0122] 309. Fabricate the drain below the substrate region.

[0123] In this embodiment, to improve the breakdown voltage of the SGT device, it is necessary to reduce the electric field strength at the corner of the trench shielding gate. Further, the control gate is connected to the substrate region through the oxide sublayer; the shielding gate is connected to the drift region through the low-dielectric-coefficient sublayer. The bottom surface of the low-dielectric-coefficient sublayer and the bottom surface of the drift region are on the same plane.

[0124] In this embodiment, the shielding gate is connected to the drift region via a low-dielectric-coefficient sublayer. Since the low-dielectric-coefficient sublayer can withstand a certain lateral voltage drop compared to the oxide sublayer under the same lateral voltage, when the transistor is forward-blocked, the low-dielectric-coefficient sublayer can suppress the lateral depletion effect between the drift region and the shielding gate, thereby weakening the electric field strength at the corner of the trench region's shielding gate and improving the trench region's withstand voltage at the corner.

[0125] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate trench field-effect transistor with low on-resistance, characterized in that, include: Substrate region (1), drift region (2), substrate region (3), source region (4), trench region (5), drain (6), and source (7); The drift region (2) is connected to the substrate region (1), with the direction from the substrate region (1) to the drift region (2) as the top, and the substrate region (3) and the source region (4) are sequentially disposed above the drift region (2); The trench area (5) is located on the side of the substrate area (3) and is connected to the drift area (2), the substrate area (3) and the source area (4) respectively; The trench region (5) includes a shielding gate (51), a control gate (52), an insulating layer (53), and a metal gate; the control gate (52) and the shielding gate (51) are arranged sequentially from top to bottom in the trench region (5) and separated by the insulating layer (53); the control gate (52) is connected to the substrate region (3) and the source region (4) respectively through the insulating layer (53), and the shielding gate (51) is connected to the drift region (2) through the insulating layer (53); The shielding gate (51) is a variable doping concentration structure, and the doping concentration of the shielding gate (51) decreases step by step from top to bottom; The source region (4) is composed of an N-type source region (41) and a P-type source region (42); the P-type source region (42), the N-type source region (41) and the trench region (5) are arranged sequentially along the top surface of the substrate region (3), and the N-type source region (41) is connected to the control gate through the insulating layer (53); The source electrode (7) is disposed above the source region (4).

2. The low on-resistance shielded gate trench field-effect transistor according to claim 1, characterized in that, The shielding grid (51) includes a first-level shielding grid (510), a second-level shielding grid (511), and a third-level shielding grid (512); The first-level shielding gate (510) has a heavy doping concentration; the second-level shielding gate (511) has a medium doping concentration; and the third-level shielding gate (512) has a low doping concentration.

3. The low on-resistance shielded gate trench field-effect transistor according to claim 1, characterized in that, The insulating layer (53) includes: a low dielectric sublayer (531) and an oxide sublayer (532); The control gate (52) is connected to the substrate region (3) through the oxide sublayer (532); The shielding gate (51) is connected to the drift region (2) through the low dielectric coefficient sublayer (531).

4. The low on-resistance shielded gate trench field-effect transistor according to claim 3, characterized in that, The bottom surface of the low dielectric coefficient sublayer (531) is on the same plane as the bottom surface of the drift region (2).

5. The low on-resistance shielded gate trench field-effect transistor according to claim 1, characterized in that, Both the P-type source region (42) and the N-type source region (41) have heavy doping concentrations.

6. The low on-resistance shielded gate trench field-effect transistor according to claim 1, characterized in that, The substrate region (1) is N-type doped, and the doping concentration of the substrate region (1) is a heavily doped concentration. The drift region (2) is N-type doped, and the doping concentration of the drift region (2) is light doping concentration; The substrate region (3) is P-type doped, and the doping concentration of the substrate region (3) is medium. The doping concentration of the source region (4) is a heavily doped concentration; the doping concentration of the control gate (52) is a heavily doped concentration.

7. A method for fabricating a shielded gate trench field-effect transistor with low on-resistance, characterized in that, For fabricating a shielded gate trench field-effect transistor with low on-resistance as described in any one of claims 1 to 6, comprising: The substrate region is prepared using semiconductor materials; A drift region is epitaxially formed on the substrate region; A matrix region is formed on the drift region by ion implantation or diffusion. Grooves are etched on the side of the drift region; Oxide, polysilicon, oxide, polysilicon and oxide are deposited sequentially in the trench to form an insulating layer, a shielding gate and a control gate; the shielding gate has a variable doping concentration structure; A source region is formed on the matrix region; Metal is deposited on the source region to form a source electrode; The drain is fabricated below the substrate region.

8. The method for fabricating a low on-resistance shielded gate trench field-effect transistor according to claim 7, characterized in that, The process of sequentially depositing oxide, polysilicon, oxide, polysilicon, and oxide within the trench to form an insulating layer, a shielding gate, and a control gate includes: A low-dielectric-coefficient dielectric, polysilicon, and another low-dielectric-coefficient dielectric are sequentially deposited within the trench to form a low-dielectric-coefficient sublayer and a shielding gate. Oxide, polysilicon and oxide are sequentially deposited on the low dielectric sublayer to form an oxide sublayer and a control gate; The low dielectric constant sublayer and the oxide sublayer constitute the insulating layer.

9. The method for fabricating a low on-resistance shielded gate trench field-effect transistor according to claim 8, characterized in that, The process of sequentially depositing a low-dielectric-coefficient dielectric, polysilicon, and another low-dielectric-coefficient dielectric within a trench to form a low-dielectric-coefficient sublayer and a shielding gate includes: A low-dielectric-coefficient dielectric, polysilicon, and another low-dielectric-coefficient dielectric are sequentially deposited within a trench to form a low-dielectric-coefficient sublayer, a first-level shielding gate, a second-level shielding gate, and a third-level shielding gate. The first-level shielding gate has a high doping concentration, the second-level shielding gate has a medium doping concentration, and the third-level shielding gate has a low doping concentration.

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