Gallium oxide field effect transistor

Abstract

The application provides a gallium oxide field effect transistor, which comprises a substrate, an n-type gallium oxide channel layer formed on the substrate, a source electrode, a drain electrode and a gate electrode formed on the n-type gallium oxide channel layer respectively; a plurality of etching pits arranged periodically are arranged in a preset channel region of the n-type gallium oxide channel layer, and two side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer; the two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner of moving away from each other; and the gate electrode further covers the upper surface and the two side walls of the fin-shaped mesa, forming a FinFET structure. The gallium oxide field effect transistor provided by the application can further improve the breakdown characteristic of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a gallium oxide field effect transistor. BACKGROUND

[0002] In recent years, super-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices, and are expected to replace traditional Si-based power devices in certain specific fields. As a new semiconductor material, super-wide bandgap gallium oxide has outstanding advantages in breakdown field strength, Baliga figure of merit and cost. The Baliga figure of merit is usually used internationally to represent the degree to which a material is suitable for a power device. The Baliga figure of merit of β-Ga2O3 material is 4 times that of GaN material, 10 times that of SiC material, and 3444 times that of Si material. Under the same withstand voltage, the β-Ga2O3 power device has lower on-resistance and lower power consumption, which can greatly reduce the electrical energy loss of the device during operation.

[0003] In 2016, NICT used Al2O3 as a gate dielectric and combined a gate field plate structure to prepare a Ga2O3 MOSFET device with a breakdown voltage of 750V. In 2019, ETRI used a source field plate structure, and during the test, the device was isolated from air breakdown by a fluorinated liquid, and the device had a breakdown voltage of 2320V. In 2020, Buffalo University used SU-8 photoresist passivation, and the device had a breakdown voltage of 8000V.

[0004] However, the breakdown voltage and on-state characteristics of the Ga2O3 field effect transistor (FET) devices reported so far are still far lower than the expected values of the material. How to further improve the breakdown characteristics of the device has become a problem that needs to be solved. SUMMARY

[0005] The gallium oxide field effect transistor provided by the embodiments of the present application solves the problem of poor breakdown characteristics of the Ga2O3 field effect transistor.

[0006] The gallium oxide field effect transistor provided by the embodiments of the present application includes a substrate, an n-type gallium oxide channel layer formed on the substrate, a source electrode and a drain electrode formed on the n-type gallium oxide channel layer, respectively;

[0007] A plurality of periodically arranged etching pits are arranged in a preset channel region of the n-type gallium oxide channel layer, and two side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer; the two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a mutually away manner;

[0008] The gate electrode also covers the upper surface and the two side walls of the fin-shaped mesa, forming a FinFET structure.

[0009] In a possible implementation, an included angle between the two sidewalls of the fin-shaped platform is α, and 10°≤α≤170°.

[0010] Optionally, a top view of the etching pit on the n-type gallium oxide channel layer is quadrilateral, a first side of which is close to the source electrode, a second side opposite to the first side is close to the drain electrode, and a length of the first side is greater than that of the second side; a third side and a fourth side connected between the first side and the second side extend from the drain electrode side to the source electrode side in a manner of moving away from each other.

[0011] Optionally, the length of the first side is 20nm-4000nm, and the length of the second side is 10nm-2000nm.

[0012] Optionally, a top view of the etching pit on the n-type gallium oxide channel layer is isosceles trapezoidal.

[0013] In a possible implementation, the gate electrode arranged on the fin-shaped platform accounts for 1 / 4-2 / 3 of the length of the fin-shaped platform.

[0014] Optionally, a gate dielectric layer is further arranged between the n-type gallium oxide channel layer and the gate electrode.

[0015] In a possible implementation, a doping concentration of the n-type gallium oxide channel layer gradually changes or varies in a gradient along a growth direction thereof.

[0016] In a possible implementation, a depth of the etching pit is greater than a thickness of the n-type gallium oxide channel layer or less than the thickness of the n-type gallium oxide channel layer.

[0017] In a possible implementation, the substrate is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate or a sapphire substrate.

[0018] The gallium oxide field effect transistor provided by the embodiment of the present application forms a plurality of fin-shaped platforms arranged at intervals by arranging a plurality of periodically arranged etching pits in a preset channel region on the n-type gallium oxide channel layer, and the two sidewalls of the fin-shaped platform extend from the source electrode side to the drain electrode side in a manner of moving away from each other, thereby forming an inclined Fin channel. The gate electrode prepared on the fin-shaped platform has different heights in the vertical direction, thereby forming a three-dimensional gate electrode.

[0019] Therefore, since the gate electrode has a higher surface area to volume ratio, the gate control capability is better, thereby adjusting the threshold voltage of the device and making the threshold voltage positively shift. The three-dimensional gate electrode also plays a role of a field plate, can make the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device, and can further improve the breakdown characteristics of the device. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0021] Figure 1 is a structure schematic diagram of a gallium oxide field effect transistor provided by an embodiment of the present application;

[0022] Figure 2 is a structure schematic diagram of an etching pit provided by an embodiment of the present application;

[0023] Figure 3 is a structure schematic diagram of another gallium oxide field effect transistor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures, techniques, etc. are presented in order to thoroughly understand the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits and methods are omitted in order not to obscure the description of the present application with unnecessary details.

[0025] In order to make the objects, technical solutions and advantages of the present application clearer, the following will be described by specific embodiments in conjunction with the drawings.

[0026] Fin Field-Effect Transistor (FinFET) is a new complementary metal-oxide-semiconductor transistor. Fin is the meaning of fish fin, and the name of FinFET is named according to the similarity between the shape of the transistor and the fish fin.

[0027] With the continuous expansion of field effect transistors, FinFET has become a research hotspot. The main advantage of the FinFET device structure is that it has excellent electrostatic integrity, but to a large extent, it depends on the morphology of the channel, and how to change the morphology of the channel and thus improve the breakdown characteristics of the device has become a technical problem that needs to be solved at present.

[0028] In order to solve the above problems, the present application provides a gallium oxide field effect transistor, which comprises a substrate, an n-type gallium oxide channel layer formed on the substrate, a source electrode, a drain electrode and a gate electrode formed on the n-type gallium oxide channel layer respectively.

[0029] Specifically, a plurality of etching pits arranged periodically are arranged in a preset channel region of the n-type gallium oxide channel layer, and two side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer. The two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner away from each other. A gate electrode is formed on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode. The gate electrode also covers the upper surface and the two side walls of the fin-shaped mesa, forming a FinFET structure. It should be noted that the gate electrode on the side close to the drain electrode can cover the entire fin-shaped mesa at most, but cannot exceed the fin-shaped mesa. Thus, an inclined Fin channel is formed, but there can be a gate electrode on the n-type gallium oxide channel layer close to the source electrode. In addition, there can also be a gate electrode on the side wall of the etching pit connected to the n-type gallium oxide channel layer in the etching pit and the etching pit close to the source electrode side.

[0030] The preset channel region can be a middle channel of the n-type gallium oxide channel layer, or other regions, which can be selected by a user according to requirements.

[0031] In some embodiments, the included angle between the two side walls of the fin-shaped mesa is α, and 10°≤α≤170°. By adjusting the included angle between the two side walls of the fin-shaped mesa, fin-shaped mesas of different shapes can be formed.

[0032] Specifically, the top view of the etching pit on the n-type gallium oxide channel layer can be a quadrilateral, in which a first side is close to the source electrode, a second side opposite to the first side is close to the drain electrode, the length of the first side is greater than that of the second side, and a third side and a fourth side connected between the first side and the second side extend from the drain electrode side to the source electrode side in a manner away from each other, so that the side walls of the fin-shaped mesa form an inclined Fin channel. It should be noted that, for the convenience of description, Fin is used instead of fin-shaped in the following.

[0033] For example, for the convenience of processing, the top view of the etching pit on the n-type gallium oxide channel layer can be a trapezoid, and the included angle between the first side and the inclined side of the trapezoid is greater than or equal to 5 degrees and less than or equal to 85 degrees. The trapezoid can be an isosceles trapezoid, and the shape can be set according to user requirements.

[0034] The length of the first side is 20 nm-4000 nm, and the length of the second side is 10 nm-2000 nm. A user can select appropriate lengths of the first side and the second side according to the size of the substrate, the size and function of the product, so as to meet the requirements.

[0035] In some embodiments, the gate electrode can only cover part of the fin-shaped mesa, i.e., the gate electrode is not provided on the fin-shaped mesa close to the drain electrode, so that a gate electrode with different heights can be formed. That is, the height of the gate electrode formed on the unetched n-type gallium oxide channel layer close to the source electrode is higher than the gate electrode on the two sidewalls of the fin-shaped mesa and in the etched pit, so that part of the gate electrode covers the Fin structure and part of the gate electrode covers the unetched channel at one end of the source electrode. The gate electrode on the Fin mesa structure has a higher surface-to-volume ratio, thus having better gate control capability, thereby adjusting the threshold voltage of the device and making the threshold voltage positively shift. It should be noted that the gate electrode close to the drain electrode can at most cover the entire fin-shaped mesa, but cannot exceed the fin-shaped mesa. However, the n-type gallium oxide channel layer close to the source electrode can have a gate electrode.

[0036] Specifically, the length of the gate electrode provided on the fin-shaped mesa can account for 1 / 4 to 2 / 3 of the length of the fin-shaped mesa.

[0037] In some embodiments, in order to improve the performance of the gallium oxide field effect transistor, a gate dielectric layer can be provided between the n-type gallium oxide channel layer and the gate electrode. Specifically, the gate dielectric layer can be provided only on the lower part of the n-type gallium oxide channel layer under the gate electrode, or can be provided on the n-type gallium oxide channel layer except for the source electrode and the drain electrode, which can be prepared according to the needs of customers.

[0038] Specifically, the gate dielectric layer can be Al2O3 / HfO2 / SiO2, or a composite dielectric layer of Al2O3 and HfO2.

[0039] In addition, a p-type dielectric layer can also be used as the gate dielectric layer, which can be grown by sputtering, PLD, ALD, etc. The p-type dielectric layer can be, but is not limited to, NiO x / SnO2 / CuO x / MnO x / FeO x / CuMO2 / ZnM2O4, etc., and the growth thickness is 10 nm to 1000 nm.

[0040] In some embodiments, the thickness of the etched pit can be less than the thickness of the n-type gallium oxide channel layer, or can be greater than the thickness of the n-type gallium oxide channel layer, which is not limited here.

[0041] Specifically, the n-type gallium oxide channel layer can be realized by doping Si or Sn, etc. The doping concentration is 1.0×10 15 cm -3 to 1.0×10 20 cm -3The n-type gallium oxide channel layer can have a thickness of 10 nm to 1000 nm. In addition, the n-type gallium oxide channel layer can have a doping concentration that is gradually changed or graded along a growth direction thereof, or can have a same concentration, which can be selected as needed. The doping concentration can gradually increase or be graded to increase along the growth direction thereof, or can gradually decrease or be graded to decrease along the growth direction thereof.

[0042] In some embodiments, the substrate is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.

[0043] In addition, the source electrode and the drain electrode can be made of Ti / Au or Ti / Al / Ni / Au, and other metals can also be selected according to the use scenario.

[0044] The length of the gate electrode can be greater than or equal to 50 nm and less than or equal to 10 μm, and the deposited metal can be Ni / Au or Pt / Au.

[0045] The gallium oxide field effect transistor provided by the application forms a plurality of fin-shaped mesas arranged at intervals by arranging a plurality of periodically arranged etching pits in a preset channel region on the n-type gallium oxide channel layer, and two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner away from each other, so as to form an inclined Fin channel. In addition, the gate electrode prepared on the fin-shaped mesa has different heights in the vertical direction, so as to form a three-dimensional gate electrode.

[0046] Since the conventional right-angle gate electrode has a sharp peak electric field below an end point close to the drain electrode, the breakdown of the device often occurs in this region. The gallium oxide field effect transistor provided by the application has a higher surface area to volume ratio, and thus has better gate control capability, so as to adjust the threshold voltage of the device and make the threshold voltage positively shift. The three-dimensional gate electrode also functions as a field plate, can make the electric field distribution of the device more uniform, so as to reduce the peak field strength of the device, and can further improve the breakdown characteristics of the device.

[0047] The structure of the gallium oxide field effect transistor will be described in detail below:

[0048] A gallium oxide field effect transistor, please refer to Figure 1 and Figure 2 , comprising a substrate, an n-type gallium oxide channel layer 20 formed on the substrate 10, a source electrode 30 and a drain electrode 40 formed on the n-type gallium oxide channel layer 20, respectively.

[0049] The plurality of periodically arranged trapezoidal etching pits 50 are arranged in the middle channel region of the n-type gallium oxide channel layer 20, and the adjacent etching pits 50 and the adjacent sidewalls form a plurality of Fin surfaces on the n-type gallium oxide channel layer. The two sidewalls of the Fin surface extend from the source electrode 30 to the drain electrode 40 in a manner away from each other. That is, the length of the first side 51 of the etching pit 50 close to the source electrode 30 is greater than the length of the second side 52 of the etching pit close to the drain electrode 40. The angle between the sidewall of the Fin surface and the source electrode 30 is α, and 5°≤α≤85°. The length of the first side 51 can be 20nm-4000nm, and the length of the second side 52 can be 10nm-2000nm.

[0050] In addition, on the n-type gallium oxide channel layer 20, a gate medium 60 prepared by atomic layer deposition is arranged on the region other than the source electrode 30 and the drain electrode 40. The gate medium 60 can be Al2O3 / HfO2 / SiO2, or a composite medium of Al2O3 and HfO2.

[0051] The gate electrode 70 is formed on the upper surface and the two sidewalls of the Fin surface and the n-type gallium oxide channel layer 20 close to the source electrode 30. The gate electrode 70 partially covers the Fin structure and partially covers the channel on one end of the source electrode 30 which is not etched, thereby forming a three-dimensional gate structure. The gate electrode 70 arranged on the Fin surface only occupies a part of the length of the Fin surface, and the other part is not covered by the gate electrode. The gate electrode on the Fin surface can occupy 1 / 4-2 / 3 of the length of the Fin surface.

[0052] In the embodiment, by preparing the inclined Fin channel structure, the gate electrode on the Fin structure has a higher surface area to volume ratio, thereby having a better gate control capability, so as to adjust the threshold voltage of the device and make the threshold voltage positively shift. The three-dimensional gate structure can also play a role of a field plate, so as to make the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device and improving the breakdown characteristics of the device.

[0053] In addition, the application also provides another structure of a gallium oxide field effect transistor, please refer to Figure 3 , which comprises a substrate, an n-type gallium oxide channel layer 20 formed on the substrate 10, a source electrode 30 and a drain electrode 40 formed on the n-type gallium oxide channel layer 20, respectively.

[0054] The plurality of periodically arranged trapezoidal etching pits 50 are arranged in the middle channel region of the n-type gallium oxide channel layer 20, and the adjacent etching pits 50 and the adjacent sidewalls form a plurality of Fin mesa on the n-type gallium oxide channel layer 20, and the two sidewalls of the Fin mesa extend from the source electrode 30 to the drain electrode 40 in a manner away from each other. That is, the length of the first side 51 of the etching pit 50 close to the source electrode 30 is greater than the length of the second side 52 of the etching pit close to the drain electrode 40. The angle between the sidewall of the Fin mesa and the source electrode 30 is α, and 5°≤α≤85°. The length of the first side 51 can be 20nm-4000nm, and the length of the second side 52 can be 10nm-2000nm.

[0055] In addition, only the upper surface of the n-type gallium oxide channel layer 20 where the gate electrode 70 is needed to be prepared, the lower surface of the gate electrode 70 is prepared with a p-type medium as a gate medium, which can be grown by sputtering, PLD, ALD and the like, and the p-type medium can be but not limited to NiO x / SnO2 / CuO x / MnO x / FeO x / CuMO2 / ZnM2O4, and the growth thickness is 10nm-1000nm.

[0056] The gate electrode 70 is formed on the upper surface and the two sidewalls of the Fin mesa and the n-type gallium oxide channel layer 20 close to the source electrode 30. The gate electrode 70 partially covers the Fin structure and partially covers the channel on one end of the source electrode 30, thereby forming a three-dimensional gate structure. The gate electrode 70 arranged on the Fin mesa only occupies a part of the length of the Fin mesa, and the other part is not covered by the gate electrode. The gate electrode on the Fin mesa can occupy 1 / 4-2 / 3 of the length of the Fin mesa.

[0057] In this embodiment, by preparing an inclined Fin channel structure, the gate electrode on the Fin structure has a higher surface area to volume ratio, thereby having a better gate control capability, so as to adjust the threshold voltage of the device and make the threshold voltage positive. The three-dimensional gate structure also has the function of a field plate, which can make the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device and improving the breakdown characteristics of the device.

[0058] On the other hand, the application also provides a preparation method of a gallium oxide field effect transistor, comprising:

[0059] First, an n-type gallium oxide channel layer is epitaxially grown on a substrate, and a source electrode and a drain electrode are deposited at both ends of the n-type gallium oxide channel layer;

[0060] Then, a photoetching mask pattern comprising a plurality of periodically arranged trapezoidal structures is prepared in a preset channel region of the n-type gallium oxide channel layer.

[0061] Next, the n-type gallium oxide channel layer is etched to obtain a plurality of etching pits, and the side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer. The two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner of moving away from each other.

[0062] Finally, the gate electrode is deposited on the upper surface of the fin-shaped mesa, the two side walls, and the unetched n-type gallium oxide channel layer close to the source electrode.

[0063] It should be understood that the size of the serial number of each step in the above embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0064] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A gallium oxide field effect transistor, comprising a substrate, an n-type gallium oxide channel layer formed on the substrate, a source electrode, a drain electrode and a gate electrode formed on the n-type gallium oxide channel layer respectively; characterized in that: a plurality of periodic etching pits are arranged in a preset channel region of the n-type gallium oxide channel layer, two side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer, the two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner away from each other, a top view of the etching pits on the n-type gallium oxide channel layer is a quadrilateral, a first side of which is close to the source electrode, a second side opposite to the first side is close to the drain electrode, and the length of the first side is greater than that of the second side, a third side and a fourth side connected between the first side and the second side extend from the drain electrode side to the source electrode side in a manner away from each other, wherein an included angle between the two side walls of the fin-shaped mesa is α, and 10°≤α≤170°, and the doping concentration of the n-type gallium oxide channel layer gradually changes along the growth direction thereof; wherein the gate electrode also covers the upper surface and the two side walls of the fin-shaped mesa, forming a FinFET structure, the gate electrode arranged on the fin-shaped mesa accounts for 1 / 4 to 2 / 3 of the length of the fin-shaped mesa, forming an inclined Fin channel, so that the gate electrode on the Fin structure has a higher surface area to volume ratio, to adjust the threshold voltage of the device, to make the threshold voltage positive shift, to reduce the peak field strength of the device. The length of the first side is 20 nm-4000 nm, and the length of the second side is 10 nm-2000 nm.

2. The gallium oxide field effect transistor of claim 1, wherein, The top view of the etching pits on the n-type gallium oxide channel layer is an isosceles trapezoid.

3. The gallium oxide field effect transistor of claim 2, wherein, A gate dielectric layer is further arranged between the n-type gallium oxide channel layer and the gate electrode.

4. The gallium oxide field effect transistor of claim 1, wherein, The depth of the etching pits is greater than or less than the thickness of the n-type gallium oxide channel layer.

5. The gallium oxide field effect transistor of claim 1, wherein, The substrate is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate or a sapphire substrate.

6. The gallium oxide field effect transistor of claim 1, wherein, ​

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