A dual-inductor bridgeless Boost PFC circuit and control method thereof

Abstract

The present invention discloses a dual-inductor bridgeless Boost PFC circuit and a control method thereof, wherein the dual-inductor bridgeless Boost PFC circuit comprises a main topology structure circuit, a dual closed-loop control loop, a first logic circuit, and a second logic circuit. The control method based on the dual-inductor bridgeless Boost PFC circuit obtains four different PWM control signals through the operation of input voltage and the logic control of the output signal of the dual closed-loop control loop, which are respectively used to control the corresponding four switch tubes. Finally, the dual-inductor bridgeless Boost PFC circuit can realize accurate control of the output voltage and correction of the power factor after being controlled by the dual closed-loop control loop and the first logic circuit and the second logic circuit designed by the present invention.

Description

Technical Field

[0001] The invention belongs to the field of power factor correction of power supplies, and in particular relates to a dual-inductor bridgeless Boost PFC circuit, and also relates to a control method based on the dual-inductor bridgeless Boost PFC circuit. Background Art

[0002] With the development of the global economy and the advancement of science and technology, power electronic equipment is widely used in various fields of social production. The continuous popularization of various electronic equipment has provided many conveniences for our lives, but also caused a series of problems such as energy shortage, harmonic pollution and power quality degradation. It is estimated that in 2020, the power consumption of data centers alone will reach 10% of the world's total power. Saving 1% of power in data centers is equivalent to the annual power generation of three nuclear power plants. Energy conservation, emission reduction and improvement of power quality have become hot issues of concern. Traditional PFC converters have low efficiency and complex structures and high costs at low voltage input. The proposal of the bridgeless PFC solution in the 1980s solved this problem and attracted widespread attention from experts and scholars at home and abroad. The development of the third-generation wide bandgap device has made it possible for bridgeless PFC to work in CCM mode, and bridgeless PFC has a wider range of application scenarios. At present, the control method in this field basically adopts digital control. However, digital chips such as DSP, FPGA, STM32 are expensive and require complicated programs. In addition, digital control systems also have problems such as reduced phase margin, high modeling accuracy requirements for converters, and difficulties in targeted design of compensators.

[0003] In response to the above problems, there is a solution that uses a single-cycle control strategy of a power IC chip to realize analog control of a bridgeless PFC circuit (such as a bridgeless PFC circuit named, application number: CN201720470420.5). The bridgeless PFC circuit adopts a single-cycle control method, and power factor correction can be achieved only by sampling the input current and output voltage. This type of solution solves the control problem of bridgeless PFC well and saves the input voltage sampling circuit, but there are still some problems. For example, the scope of application of this solution is small. In order to improve the transmission efficiency, the bridgeless PFC circuit generally adopts a synchronous rectification solution, and uses a dedicated power MOSFET with extremely low on-resistance to replace the rectifier diode to reduce the rectification loss. At this time, it is necessary to control different states of multiple switch tubes at the same time, and the above solution can only output one control signal, which means that it can only be used to control switch tubes in the same switch state, which cannot meet the requirements at this time. In addition, for bridgeless PFC, the setting of the dead time of the upper and lower tubes is also particularly important; if the dead time is set too short, there will be a risk of tube explosion, and if the dead time is set too long, it will cause input current distortion and reduce the power factor. The setting of dead time is often related to multiple parameters. It is necessary to clarify the relationship between them and design a control method with adaptive dead time adjustment. Summary of the invention

[0004] The purpose of the present invention is to provide a dual-inductor bridgeless Boost PFC circuit and a control method thereof. By calculating the input voltage and logically controlling the output signal of the dual closed-loop control loop, four different PWM control signals are obtained, which are respectively used to control the corresponding four switch tubes. Finally, the dual-inductor bridgeless Boost PFC circuit can achieve accurate control of the output voltage and correction of the power factor after being controlled by the dual closed-loop control loop and the first logic circuit and the second logic circuit designed by the present invention.

[0005] In order to realize the above functions, the present invention designs a dual-inductor bridgeless Boost PFC circuit, including a main topology circuit, a dual closed-loop control circuit, a first logic circuit, and a second logic circuit;

[0006] The main topology circuit includes a first inductor L1, a second inductor L2, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first resistor R1, a second resistor R2, a first electrolytic capacitor C1, a load R Load ;

[0007] One end of the first inductor L1 is connected to the AC power supply, and the other end is connected to the source of the first switch tube Q1. The source of the first switch tube Q1 is also connected to the drain of the second switch tube Q2. The drain of the first switch tube Q1 is respectively connected to the drain of the third switch tube Q3, the positive electrode of the first electrolytic capacitor C1, one end of the first resistor R1, and the load R Load The source of the second switch tube Q2 is respectively connected to the source of the fourth switch tube Q4, the negative electrode of the first electrolytic capacitor C1, one end of the second resistor R2, and the load R Load The other end of the first resistor R1 is connected to the other end of the second resistor R2, the source of the third switch tube Q3 is connected to the drain of the fourth switch tube Q4, one end of the second inductor L2 is connected to the AC power supply, and the other end is connected to the source of the third switch tube Q3 and the drain of the fourth switch tube Q4 respectively;

[0008] The double closed-loop control loop includes a comparator, a triangular carrier module, a current loop PI controller, a voltage loop PI controller, a reference voltage source, a first absolute value circuit, and a second absolute value circuit;

[0009] The input voltage sampling of the AC power supply is input to the input end of the first absolute value circuit, the output end of the first absolute value circuit is connected to the input end of the current loop PI controller, the input current sampling of the AC power supply is input to the input end of the second absolute value circuit, the output end of the second absolute value circuit is connected to the input end of the current loop PI controller, the reference voltage source is connected to the input end of the voltage loop PI controller, the input end of the voltage loop PI controller is simultaneously connected to the other end of the first resistor R1 and the other end of the second resistor R2, and the voltage sampling is output to the voltage loop PI controller, the output end of the voltage loop PI controller is connected to the input end of the current loop PI controller, the output end of the current loop PI controller is connected to the inverting input end of the comparator, the triangular carrier module is connected to the in-phase input end of the comparator, and the output signal of the comparator output end is PMW0;

[0010] The first logic circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal; the second logic circuit includes an input terminal, a first output terminal, and a second output terminal. The input voltage of the AC power supply is sampled and input into the input terminal of the second logic circuit. The first output terminal of the second logic circuit outputs a signal PMW3, and the first output terminal of the second logic circuit is connected to the gate of the third switch tube Q3 through a driving module. The second output terminal of the second logic circuit outputs a signal PMW4, and the second output terminal of the second logic circuit is connected to the gate of the fourth switch tube Q4 through a driving module; the first output terminal of the second logic circuit is simultaneously connected to the first input terminal of the first logic circuit, and outputs a PMW3 signal to the first input terminal of the first logic circuit. The second output terminal of the second logic circuit is simultaneously connected to the second input terminal of the first logic circuit, and outputs a PMW4 signal to the second input terminal of the first logic circuit; the output terminal of the comparator is connected to the third input terminal of the first logic circuit, and the comparator outputs PMW0 to the third input terminal of the first logic circuit. The first output end of the first logic circuit is connected to the gate of the first switch tube Q1 through the driving module, and the output signal of the first output end of the first logic circuit is PMW1. The second output end of the first logic circuit is connected to the gate of the second switch tube Q2 through the driving module, and the output signal of the first output end of the first logic circuit is PMW2.

[0011] As a preferred technical solution of the present invention: the first logic circuit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a first OR gate OR1, a second OR gate OR2, a first NOT gate NOT1, and a second NOT gate NOT2;

[0012] The first input terminal of the first AND gate AND1 serves as the first input terminal of the first logic circuit, the second input terminal of the first AND gate AND1 and the first input terminal of the fourth AND gate AND4 serve as the third input terminal of the first logic circuit, the output terminal of the first OR gate OR1 serves as the first output terminal of the first logic circuit, and the output terminal of the second OR gate OR2 serves as the second output terminal of the first logic circuit;

[0013] A first input terminal of the first AND gate AND1 inputs the PWM3 signal, and the first input terminal is simultaneously connected to the first input terminal of the third AND gate AND3, a second input terminal of the first AND gate AND1 inputs the PWM0 signal, and the second input terminal is simultaneously connected to the first input terminal of the fourth AND gate AND4, an output terminal of the first AND gate AND1 is connected to the first input terminal of the first OR gate OR1, a first input terminal of the fourth AND gate AND4 inputs the PWM0 signal, a second input terminal of the fourth AND gate AND4 inputs the PWM4 signal, and the second input terminal is simultaneously connected to the first input terminal of the second AND gate AND2, an output terminal of the fourth AND gate AND4 is connected to the first input terminal of the second OR gate OR2, an output terminal of the first OR gate OR1 outputs the PWM1 signal, an output terminal of the first OR gate OR1 is simultaneously connected to an input terminal of the first NOT gate NOT1, and the first NOT gate NOT1 The output end of is connected to the second input end of the third AND gate AND3, the second input end of the first OR gate OR1 is connected to the output end of the second AND gate AND2, the second input end of the second AND gate AND2 is connected to the output end of the second NOT gate NOT2, the input end of the second NOT gate NOT2 is connected to the output end of the second OR gate OR2, the output end of the second OR gate OR2 outputs the PWM2 signal, and the second input end of the second OR gate OR2 is connected to the output end of the third AND gate AND3.

[0014] As a preferred technical solution of the present invention: the second logic circuit includes a first comparator U1A, a second comparator U1B, a first operational amplifier U1C, a second operational amplifier U1D, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; wherein the first operational amplifier U1C and the third resistor R3, the fourth resistor R4, and the fifth resistor R5 form a common-phase proportional amplifier, and the second operational amplifier U1D and the sixth resistor R6 form a voltage follower;

[0015] One end of the fifth resistor R5 serves as an input end of the second logic circuit, the output end of the first comparator U1A serves as a first output end of the second logic circuit, and the output end of the second comparator U1B serves as a second output end of the second logic circuit;

[0016] Among them, one end of the third resistor R3 is grounded, and the other end is connected to the inverting input terminal of the second operational amplifier U1D and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the output terminal of the second operational amplifier U1D, the input voltage of the AC power supply is sampled and input to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the non-inverting input terminal of the second operational amplifier U1D, one end of the sixth resistor R6 is connected to the output terminal of the second operational amplifier U1D, the other end of the sixth resistor R6 is connected to the non-inverting input terminal of the first operational amplifier U1C, the inverting input terminal of the first operational amplifier U1C is connected to the output terminal of the first operational amplifier U1C, the inverting input terminal of the first comparator U1A is connected to the output terminal of the first operational amplifier U1C, and the dead zone reference voltage -V is input to the non-inverting input terminal of the first comparator U1A th The output terminal of the first comparator U1A outputs the PWM3 signal, the non-inverting input terminal of the second comparator U1B is connected to the output terminal of the first operational amplifier U1C, and the inverting input terminal of the second comparator U1B inputs the dead zone reference voltage V th , the output end of the second comparator U1B outputs the PWM4 signal.

[0017] The present invention also designs a control method based on a dual-inductor bridgeless Boost PFC circuit, characterized in that the following steps S1 to S5 are executed to complete the rectification, boosting, and power factor correction of the input voltage:

[0018] S1: sampling the input voltage, input current and output voltage of the dual-inductor bridgeless Boost PFC circuit;

[0019] S2: Based on the average current control strategy, a double closed-loop control loop is built so that the input current waveform follows the input voltage waveform;

[0020] S3: Based on the control strategy of S2, the double closed-loop control loop obtains the signal PWM0 by adjusting the current loop PI controller and the voltage loop PI controller for the sampled values ​​of the input voltage, input current and output voltage;

[0021] S4: setting the dead time of the third switch tube Q3 and the fourth switch tube Q4 according to the amplitude, frequency, sampling ratio and dead zone reference voltage of the input voltage;

[0022] S5: the input voltage is processed by the second logic circuit to obtain the signal PWM3 and the signal PWM4, the signal PWM3 and the signal PWM4 respectively control the on and off of the third switch tube Q3 and the fourth switch tube Q4, the control signal PWM3, the control signal PWM4 and the control signal PWM0 are processed by the first logic circuit to obtain the control signal PWM1 and the control signal PWM2, the control signal PWM1 and the control signal PWM2 respectively control the on and off of the first switch tube Q1 and the second switch tube Q2;

[0023] Based on the main topology circuit, the double closed-loop control circuit, the first logic circuit and the second logic circuit, the rectification, boosting and power factor correction of the input voltage are completed.

[0024] As a preferred technical solution of the present invention: in step S4, the dead time T of the third switch tube Q3 and the fourth switch tube Q4 is set according to the amplitude, frequency, sampling ratio and dead zone reference voltage of the input voltage. th As follows:

[0025]

[0026] Where V is the sampling ratio of the input voltage, f is the frequency of the AC input voltage, and U m is the amplitude of the input voltage, R3 is the resistance of the third resistor R3, and R4 is the resistance of the fourth resistor R4.

[0027] As a preferred technical solution of the present invention: the operation processing process of the second logic circuit in step S5 is as follows:

[0028] A: The input voltage is processed by the in-phase proportional amplifier and the voltage follower in sequence. The processed voltage is simultaneously input to the inverting input terminal of the first comparator U1A and the in-phase input terminal of the second comparator U2A. The dead zone reference voltage -V th Input to the non-inverting input terminal of the first comparator U1A, the dead zone reference voltage V th The first comparator U1A and the second comparator U1B output signals PWM3 and PWM4 respectively. The expressions of signals PWM3 and PWM4 are as follows:

[0029]

[0030]

[0031] Where V is the sampling ratio of the input voltage, U m is the amplitude of the input voltage, w is the angular frequency, t is the time, R3 is the resistance value of the third resistor R3, and R4 is the resistance value of the fourth resistor R4;

[0032] B: When the input voltage is in the positive half cycle, the signal PWM3 is low level, the signal PWM4 is high level, the fourth switch tube Q4 is turned on, the third switch tube Q3 is turned off, the second switch tube Q2 is turned on, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·V in Forward voltage drop, where V in The first inductor L1 and the second inductor L2 store energy, the inductor current increases linearly, and the first electrolytic capacitor C1 supplies power to the load R Load Transfer energy until the second switch tube Q2 is turned off and the inductor current rises to a peak value;

[0033] C: When the input voltage is in the negative half cycle, the signal PWM3 is high level, the signal PWM4 is low level, the fourth switch tube Q4 is turned off, the third switch tube Q3 is turned on, the first switch tube Q1 is turned on, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·V in Forward voltage drop, the first inductor L1 and the second inductor L2 store energy, the inductor current increases linearly, and the first electrolytic capacitor C1 supplies power to the load R Load Transfer energy until the first switch tube Q1 is turned off and the inductor current rises to a peak value;

[0034] As a preferred technical solution of the present invention: the operation processing process of the first logic circuit in step S5 is as follows:

[0035] A: The signals PWM3, PWM4 and PWM0 are input to the first logic circuit. After being processed by the first logic circuit, the expressions of the signals PWM1 and PWM2 are obtained as follows:

[0036]

[0037]

[0038] B: When the input voltage is in the positive half cycle, the signal PWM3 is at a low level, the signal PWM4 is at a high level, the outputs of the first and third AND gates AND1 and AND3 are at a low level, the signal PMW2 controls the level change of the signal PMW1, and the level state of the signal PMW2 is opposite to that of the signal PMW1; after the second switch tube Q2 is turned off, the first switch tube Q1 is turned on, the inductor current continues to flow through the first switch tube Q1, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·(V in -V o ) reverse voltage drop, where V o is the output voltage, the first inductor L1 and the second inductor L2 supply voltage to the load R Load Energy is transferred and the inductor current decreases linearly;

[0039] C: When the input voltage is in the negative half cycle, the signal PWM3 is high level, the signal PWM4 is low level, the outputs of the second AND gate AND2 and the fourth AND gate AND4 are low level, the signal PMW1 controls the level change of the signal PMW2, and the level states of the signal PMW1 and the signal PMW2 are opposite; after the first switch tube Q1 is turned off, the second switch tube Q2 is turned on, the inductor current continues to flow through the second switch tube Q2, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·(V in -V o ) reverse voltage drop, the first inductor L1 and the second inductor L2 to the load R Load Energy is transferred and the inductor current decreases linearly;

[0040] Beneficial effects: Compared with the prior art, the advantages of the present invention include:

[0041] 1. The control method based on the dual-inductor bridgeless Boost PFC circuit designed by the present invention adopts analog control, requires fewer components, saves digital chips such as DSP, STM32, and FPGA, and greatly reduces the cost of the system circuit compared to digital control;

[0042] 2. The control method based on the dual-inductor bridgeless Boost PFC circuit designed by the present invention can autonomously adjust the dead time according to the amplitude and frequency of the input voltage. Compared with the traditional dead time setting method, it can improve the output performance of the converter and realize the precise control of the output voltage and the correction of the power factor;

[0043] 3. The dual-inductor bridgeless Boost PFC circuit designed in the present invention has the advantages of simple structure, easy debugging, easy implementation, high integration and long service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a circuit diagram of a main topology structure circuit provided according to an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of the overall architecture of a dual-inductor bridgeless Boost PFC circuit provided according to an embodiment of the present invention;

[0046] Figure 3 is a schematic diagram of a first logic circuit provided according to an embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of a second logic circuit provided according to an embodiment of the present invention;

[0048] Figure 5 is a simulation waveform diagram of input current and input voltage provided according to an embodiment of the present invention;

[0049] Figure 6is a schematic diagram of the working state of the main topology structure circuit during the dead time according to an embodiment of the present invention;

[0050] Figure 7 is a simulation waveform diagram of the third switch tube Q3 and the fourth switch tube Q4 provided according to an embodiment of the present invention;

[0051] Figure 8 is a simulation waveform diagram of the first switch tube Q1 and the second switch tube Q2 provided according to an embodiment of the present invention;

[0052] Fig. 9 is a schematic diagram of working state 1 provided according to an embodiment of the present invention;

[0053] Fig.10 is a schematic diagram of working state 2 provided according to an embodiment of the present invention;

[0054] Fig.11 is a schematic diagram of working state 3 provided according to an embodiment of the present invention;

[0055] Fig.12 It is a schematic diagram of working state 4 provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0057] A dual-inductor bridgeless Boost PFC circuit provided by an embodiment of the present invention includes a main topology circuit, a dual closed-loop control circuit, a first logic circuit, and a second logic circuit;

[0058] Among them, reference Figure 1 , Figure 2 The main topology circuit includes a first inductor L1, a second inductor L2, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first resistor R1, a second resistor R2, a first electrolytic capacitor C1, and a load R Load ;

[0059] One end of the first inductor L1 is connected to the AC power supply, and the other end is connected to the source of the first switch tube Q1. The source of the first switch tube Q1 is also connected to the drain of the second switch tube Q2. The drain of the first switch tube Q1 is respectively connected to the drain of the third switch tube Q3, the positive electrode of the first electrolytic capacitor C1, one end of the first resistor R1, and the load R Load The source of the second switch tube Q2 is respectively connected to the source of the fourth switch tube Q4, the negative electrode of the first electrolytic capacitor C1, one end of the second resistor R2, and the load R LoadThe other end of the first resistor R1 is connected to the other end of the second resistor R2, the source of the third switch tube Q3 is connected to the drain of the fourth switch tube Q4, one end of the second inductor L2 is connected to the AC power supply, and the other end is connected to the source of the third switch tube Q3 and the drain of the fourth switch tube Q4 respectively;

[0060] In one embodiment, each switch tube in the main topology circuit adopts a third-generation wide bandgap device, silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET), the first switch tube Q1 and the second switch tube Q2 form a high-frequency bridge arm, the third switch tube Q3 and the fourth switch tube Q4 form an industrial frequency bridge arm, and the inductor current operates in a continuous current mode.

[0061] refer to Figure 2 , the dual closed-loop control loop includes a comparator, a triangular carrier module, a current loop PI controller, a voltage loop PI controller, a reference voltage source, a first absolute value circuit, and a second absolute value circuit;

[0062] The input voltage sampling of the AC power supply is input to the input end of the first absolute value circuit, the output end of the first absolute value circuit is connected to the input end of the current loop PI controller, the input current sampling of the AC power supply is input to the input end of the second absolute value circuit, the output end of the second absolute value circuit is connected to the input end of the current loop PI controller, the reference voltage source is connected to the input end of the voltage loop PI controller, the input end of the voltage loop PI controller is simultaneously connected to the other end of the first resistor R1 and the other end of the second resistor R2, and the voltage sampling is output to the voltage loop PI controller, the output end of the voltage loop PI controller is connected to the input end of the current loop PI controller, the output end of the current loop PI controller is connected to the inverting input end of the comparator, the triangular carrier module is connected to the in-phase input end of the comparator, and the output signal of the comparator output end is PMW0;

[0063] The first logic circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal; the second logic circuit includes an input terminal, a first output terminal, and a second output terminal. The input voltage of the AC power supply is sampled and input into the input terminal of the second logic circuit. The first output terminal of the second logic circuit outputs a signal PMW3, and the first output terminal of the second logic circuit is connected to the gate of the third switch tube Q3 through a driving module. The second output terminal of the second logic circuit outputs a signal PMW4, and the second output terminal of the second logic circuit is connected to the gate of the fourth switch tube Q4 through a driving module; the first output terminal of the second logic circuit is simultaneously connected to the first input terminal of the first logic circuit, and outputs a PMW3 signal to the first input terminal of the first logic circuit. The second output terminal of the second logic circuit is simultaneously connected to the second input terminal of the first logic circuit, and outputs a PMW4 signal to the second input terminal of the first logic circuit; the output terminal of the comparator is connected to the third input terminal of the first logic circuit, and the comparator outputs PMW0 to the third input terminal of the first logic circuit. The first output end of the first logic circuit is connected to the gate of the first switch tube Q1 through the driving module, and the output signal of the first output end of the first logic circuit is PMW1. The second output end of the first logic circuit is connected to the gate of the second switch tube Q2 through the driving module, and the output signal of the first output end of the first logic circuit is PMW2.

[0064] refer to Figure 3 The first logic circuit designed by the present invention includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a first OR gate OR1, a second OR gate OR2, a first NOT gate NOT1, and a second NOT gate NOT2;

[0065] The first input terminal of the first AND gate AND1 serves as the first input terminal of the first logic circuit, the second input terminal of the first AND gate AND1 and the first input terminal of the fourth AND gate AND4 serve as the third input terminal of the first logic circuit, the output terminal of the first OR gate OR1 serves as the first output terminal of the first logic circuit, and the output terminal of the second OR gate OR2 serves as the second output terminal of the first logic circuit;

[0066] A first input terminal of the first AND gate AND1 inputs the PWM3 signal, and the first input terminal is simultaneously connected to the first input terminal of the third AND gate AND3, a second input terminal of the first AND gate AND1 inputs the PWM0 signal, and the second input terminal is simultaneously connected to the first input terminal of the fourth AND gate AND4, an output terminal of the first AND gate AND1 is connected to the first input terminal of the first OR gate OR1, a first input terminal of the fourth AND gate AND4 inputs the PWM0 signal, a second input terminal of the fourth AND gate AND4 inputs the PWM4 signal, and the second input terminal is simultaneously connected to the first input terminal of the second AND gate AND2, an output terminal of the fourth AND gate AND4 is connected to the first input terminal of the second OR gate OR2, an output terminal of the first OR gate OR1 outputs the PWM1 signal, an output terminal of the first OR gate OR1 is simultaneously connected to an input terminal of the first NOT gate NOT1, and the first NOT gate NOT1 The output end of is connected to the second input end of the third AND gate AND3, the second input end of the first OR gate OR1 is connected to the output end of the second AND gate AND2, the second input end of the second AND gate AND2 is connected to the output end of the second NOT gate NOT2, the input end of the second NOT gate NOT2 is connected to the output end of the second OR gate OR2, the output end of the second OR gate OR2 outputs the PWM2 signal, and the second input end of the second OR gate OR2 is connected to the output end of the third AND gate AND3.

[0067] refer to Figure 4 The second logic circuit designed by the present invention includes a first comparator U1A, a second comparator U1B, a first operational amplifier U1C, a second operational amplifier U1D, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; wherein the first operational amplifier U1C and the third resistor R3, the fourth resistor R4, and the fifth resistor R5 form a common-phase proportional amplifier, and the second operational amplifier U1D and the sixth resistor R6 form a voltage follower;

[0068] One end of the fifth resistor R5 serves as an input end of the second logic circuit, the output end of the first comparator U1A serves as a first output end of the second logic circuit, and the output end of the second comparator U1B serves as a second output end of the second logic circuit;

[0069] Among them, one end of the third resistor R3 is grounded, and the other end is connected to the inverting input terminal of the second operational amplifier U1D and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the output terminal of the second operational amplifier U1D, the input voltage of the AC power supply is sampled and input to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the non-inverting input terminal of the second operational amplifier U1D, one end of the sixth resistor R6 is connected to the output terminal of the second operational amplifier U1D, the other end of the sixth resistor R6 is connected to the non-inverting input terminal of the first operational amplifier U1C, the inverting input terminal of the first operational amplifier U1C is connected to the output terminal of the first operational amplifier U1C, the inverting input terminal of the first comparator U1A is connected to the output terminal of the first operational amplifier U1C, and the dead zone reference voltage -V is input to the non-inverting input terminal of the first comparator U1A th The output terminal of the first comparator U1A outputs the PWM3 signal, the non-inverting input terminal of the second comparator U1B is connected to the output terminal of the first operational amplifier U1C, and the inverting input terminal of the second comparator U1B inputs the dead zone reference voltage V th , the output end of the second comparator U1B outputs the PWM4 signal.

[0070] A control method based on a dual-inductor bridgeless Boost PFC circuit provided in an embodiment of the present invention executes the following steps S1 to S5 to complete rectification, boosting, and power factor correction of an input voltage:

[0071] S1: sampling the input voltage, input current and output voltage of the dual-inductor bridgeless Boost PFC circuit;

[0072] S2: Based on the average current control strategy, a double closed-loop control loop is built so that the input current waveform follows the input voltage waveform. The simulation waveform diagram is referenced Figure 5 ;

[0073] S3: Based on the control strategy of S2, the double closed-loop control loop obtains the signal PWM0 by adjusting the current loop PI controller and the voltage loop PI controller for the sampled values ​​of the input voltage, input current and output voltage;

[0074] When the input voltage is near the zero crossing point, the working state of the main topology circuit is referenced Figure 6In order to prevent tube explosion, a dead time needs to be set for the third switch tube Q3 and the fourth switch tube Q4 in the power frequency bridge arm. At this time, under the control of the first logic circuit, the first switch tube Q1 and the second switch tube Q2 remain disconnected during the dead time; when the third switch tube Q3 or the fourth switch tube Q4 is disconnected, the other switch tube is turned on after a preset time delay. This can not only prevent the occurrence of tube explosion, but also improve the current spike problem at the zero-crossing point of the input current. According to the following step S4, the dead time of the third switch tube Q3 and the fourth switch tube Q4 is set:

[0075] S4: setting the dead time of the third switch tube Q3 and the fourth switch tube Q4 according to the amplitude, frequency, sampling ratio and dead zone reference voltage of the input voltage;

[0076] The input voltage Va of the inverting input terminal of the first comparator U1A and the non-inverting input terminal of the second comparator U1B is as follows:

[0077]

[0078] Where V is the sampling ratio of the input voltage, U m is the amplitude of the input voltage, w is the angular frequency of the input voltage, t is the time, R3 is the resistance value of the third resistor R3, and R4 is the resistance value of the fourth resistor R4.

[0079] Taking the input voltage entering the positive half cycle from 0 potential as an example, the dead zone end condition can be obtained as follows:

[0080] Va=V th

[0081] The above two equations can further be used to calculate the 1 / 2 dead time t h The expression is:

[0082]

[0083] In the formula, w = 2πf, and the dead time when the input voltage enters the positive half cycle from 0 potential is the same as the dead time when the input voltage enters the zero potential from the negative half cycle, then the total dead time of the switch tube T can be further obtained. th As follows:

[0084]

[0085] Where V is the sampling ratio of the input voltage, f is the frequency of the AC input voltage, and U m is the amplitude of the input voltage, R3 is the resistance of the third resistor R3, and R4 is the resistance of the fourth resistor R4.

[0086] That is, when the hardware circuit determines that the dead time of the third switch tube Q3 and the fourth switch tube Q4 is only related to the amplitude Um of the input voltage and the frequency f of the AC input voltage, the logic circuit can dynamically adjust the dead time of the third switch tube Q3 and the fourth switch tube Q4 according to the difference in the input voltage amplitude and the frequency of the AC input voltage. Compared with the traditional fixed dead time, the output performance of the converter can be improved.

[0087] S5: the input voltage is processed by the second logic circuit to obtain the signal PWM3 and the signal PWM4, the signal PWM3 and the signal PWM4 respectively control the on and off of the third switch tube Q3 and the fourth switch tube Q4, the control signal PWM3, the control signal PWM4 and the control signal PWM0 are processed by the first logic circuit to obtain the control signal PWM1 and the control signal PWM2, the control signal PWM1 and the control signal PWM2 respectively control the on and off of the first switch tube Q1 and the second switch tube Q2;

[0088] When the input voltage is in the positive half cycle, the fourth switch tube Q4 in the power frequency bridge arm is turned on, the third switch tube Q3 is turned off, the second switch tube Q2 in the high frequency bridge arm is the main switch tube, and the first switch tube Q1 is a synchronous rectifier tube; when the input voltage is in the negative half cycle, the third switch tube Q3 in the power frequency bridge arm is turned on, the fourth switch tube Q4 is turned off, the first switch tube Q1 in the high frequency bridge arm is the main switch tube, the second switch tube Q2 is a synchronous rectifier tube, and the simulation waveforms of the third switch tube Q3 and the fourth switch tube Q4 are referenced Figure 7 , the simulation waveform reference of the first switch tube Q1 and the second switch tube Q2 Figure 8 .

[0089] The operation process of the second logic circuit is as follows:

[0090] A: The input voltage is processed by the in-phase proportional amplifier and the voltage follower in sequence. The processed voltage is simultaneously input to the inverting input terminal of the first comparator U1A and the in-phase input terminal of the second comparator U2A. The dead zone reference voltage -V th Input to the non-inverting input terminal of the first comparator U1A, the dead zone reference voltage V th The first comparator U1A and the second comparator U1B output signals PWM3 and PWM4 respectively. The expressions of signals PWM3 and PWM4 are as follows:

[0091]

[0092]

[0093] Where V is the input voltage sampling ratio, U mis the amplitude of the input voltage, w is the angular frequency of the input voltage, t is the time, R3 is the resistance value of the third resistor R3, and R4 is the resistance value of the fourth resistor R4;

[0094] The control process of the signal PWM3 and the signal PWM4 on the third switch tube Q3 and the fourth switch tube Q4 is as follows:

[0095] B: When the input voltage is in the positive half cycle, the signal PWM3 is low level, the signal PWM4 is high level, the fourth switch tube Q4 is turned on, the third switch tube Q3 is turned off, and the second switch tube Q2 is turned on. At this time, it is working state 1, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·V in Forward voltage drop, where V in The first inductor L1 and the second inductor L2 store energy, the inductor current increases linearly, and the first electrolytic capacitor C1 supplies power to the load R Load Energy is transferred until the second switch tube Q2 is turned off and the inductor current rises to its peak value; its schematic diagram refers to Fig. 9 .

[0096] C: When the input voltage is in the negative half cycle, the signal PWM3 is high level, the signal PWM4 is low level, the fourth switch tube Q4 is turned off, and the third switch tube Q3 is turned on. At this time, it is working state 3, the first switch tube Q1 is turned on, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·V in Forward voltage drop, the first inductor L1 and the second inductor L2 store energy, the inductor current increases linearly, and the first electrolytic capacitor C1 supplies power to the load R Load Energy is transferred until the first switch tube Q1 is turned off and the inductor current rises to its peak value; its schematic diagram refers to Fig.11 .

[0097] The operation process of the first logic circuit is as follows:

[0098] A: Signal PWM3, signal PWM4, signal PWM0 are input to the first logic circuit;

[0099] When the input AC voltage is in the first half cycle, the signal PWM3 outputs a low level, the signal PWM4 outputs a high level, and the outputs of the first and third AND gates AND1 and AND3 are both low levels; at this time, the signal PWM2 is not affected by the signal PWM1, and the level change of the signal PWM1 is completely controlled by the signal PWM2, and the level states of the signal PWM1 and the signal PWM2 are completely opposite. When the input AC voltage is in the second half cycle: the signal PWM3 outputs a high level, the signal PWM4 outputs a low level, and the outputs of the second and fourth AND gates AND2 and AND4 are both low levels; at this time, the signal PWM1 is not affected by the signal PWM2, and the level change of the signal PWM2 is completely controlled by the signal PWM1, and the level states of the signal PWM1 and the signal PWM2 are still completely opposite. Under the control of this logic circuit: the signal PWM1 is completely opposite to the signal PWM2, and corresponding to the AC input voltage, the level change of the signal PWM2 in the first half cycle controls the level change of the signal PWM1, and the level change of the signal PWM1 in the second half cycle controls the level change of the signal PWM2. According to the first logic circuit, the relationship between a, b, c, d, signal PWM1 and signal PWM2 can be obtained respectively:

[0100] a=PWM0·PWM3

[0101] b=PWM0·PWM4

[0102]

[0103]

[0104] PWM1=a+c

[0105] PWM2=b+d

[0106] Wherein, a represents the level of the output terminal of the first AND gate AND1, b represents the level of the output terminal of the fourth AND gate AND4, c represents the level of the output terminal of the second AND gate AND2, and d represents the level of the output terminal of the third AND gate AND3;

[0107] The expressions of the control signals PWM1 and PWM2 of the first switch tube Q1 and the second switch tube Q2 are further derived from the above relationship as follows:

[0108]

[0109]

[0110] Based on the control logic of the first logic circuit, and the expressions of signal PWM1, signal PWM2, signal PWM3, and signal PWM4, the truth table of the first logic circuit is obtained as shown in Table 1:

[0111] Table 1 Control logic circuit truth table

[0112]

[0113] In summary, according to the expressions of the signal PWM1 and the signal PWM2 and the truth table of the first logic circuit, the first logic circuit can realize the complementary output of the signal PWM1 and the signal PWM2. In the positive half cycle of the input voltage, the second switch tube Q2 is the main switch tube, and the first switch tube Q1 is the synchronous rectifier tube; in the negative half cycle, the first switch tube Q1 is the main switch tube, and the second switch tube Q2 is the synchronous rectifier tube. In addition, during the duration of the dead zone, all the switches remain in the closed state, and the circuit resumes normal operation after the dead zone time ends.

[0114] The control process of the signal PWM1 and the signal PWM2 on the first switch tube Q1 and the second switch tube Q2 is as follows:

[0115] B: When the input voltage is in the positive half cycle, the signal PWM3 is at a low level, the signal PWM4 is at a high level, the outputs of the first and third AND gates AND1 and AND3 are at a low level, the signal PMW2 controls the level change of the signal PMW1, and the level state of the signal PMW2 is opposite to that of the signal PMW1; after the second switch tube Q2 is turned off, the first switch tube Q1 is turned on, and it is working state 2 at this time. The inductor current continues to flow through the first switch tube Q1, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·(V in -V o ) reverse voltage drop, where V o is the output voltage, the first inductor L1 and the second inductor L2 supply voltage to the load R Load Energy is transferred, and the inductor current decreases linearly; its schematic diagram refers to Fig.10 .

[0116] C: When the input voltage is in the negative half cycle, the signal PWM3 is high level, the signal PWM4 is low level, the outputs of the second AND gate AND2 and the fourth AND gate AND4 are low level, the signal PMW1 controls the level change of the signal PMW2, and the level states of the signal PMW1 and the signal PMW2 are opposite; after the first switch tube Q1 is turned off, the second switch tube Q2 is turned on, and it is working state 4 at this time. The inductor current continues to flow through the second switch tube Q2, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·(V in -V o ) reverse voltage drop, the first inductor L1 and the second inductor L2 to the load R Load Energy is transferred, and the inductor current decreases linearly; its schematic diagram refers to Fig.12 .

[0117] Based on the main topology circuit, the double closed-loop control circuit, the first logic circuit and the second logic circuit, the rectification, boosting and power factor correction of the input voltage are completed.

[0118] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A dual-inductor bridgeless Boost PFC circuit, characterized in that: It includes a main topology circuit, a double closed-loop control circuit, a first logic circuit, and a second logic circuit; The main topology circuit includes a first inductor L1, a second inductor L2, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first resistor R1, a second resistor R2, a first electrolytic capacitor C1, a load R Load ; One end of the first inductor L1 is connected to the AC power supply, and the other end is connected to the source of the first switch tube Q1. The source of the first switch tube Q1 is also connected to the drain of the second switch tube Q2. The drain of the first switch tube Q1 is respectively connected to the drain of the third switch tube Q3, the positive electrode of the first electrolytic capacitor C1, one end of the first resistor R1, and the load R Load The source of the second switch tube Q2 is respectively connected to the source of the fourth switch tube Q4, the negative electrode of the first electrolytic capacitor C1, one end of the second resistor R2, and the load R Load The other end of the first resistor R1 is connected to the other end of the second resistor R2, the source of the third switch tube Q3 is connected to the drain of the fourth switch tube Q4, one end of the second inductor L2 is connected to the AC power supply, and the other end is connected to the source of the third switch tube Q3 and the drain of the fourth switch tube Q4 respectively; The double closed-loop control loop includes a comparator, a triangular carrier module, a current loop PI controller, a voltage loop PI controller, a reference voltage source, a first absolute value circuit, and a second absolute value circuit; The input voltage sampling of the AC power supply is input to the input end of the first absolute value circuit, the output end of the first absolute value circuit is connected to the input end of the current loop PI controller, the input current sampling of the AC power supply is input to the input end of the second absolute value circuit, the output end of the second absolute value circuit is connected to the input end of the current loop PI controller, the reference voltage source is connected to the input end of the voltage loop PI controller, the input end of the voltage loop PI controller is simultaneously connected to the other end of the first resistor R1 and the other end of the second resistor R2, and the voltage sampling is output to the voltage loop PI controller, the output end of the voltage loop PI controller is connected to the input end of the current loop PI controller, the output end of the current loop PI controller is connected to the inverting input end of the comparator, the triangular carrier module is connected to the in-phase input end of the comparator, and the output signal of the comparator output end is PMW0; The first logic circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal; the second logic circuit includes an input terminal, a first output terminal, and a second output terminal. The input voltage of the AC power supply is sampled and input into the input terminal of the second logic circuit. The first output terminal of the second logic circuit outputs a signal PMW3, and the first output terminal of the second logic circuit is connected to the gate of the third switch tube Q3 through a driving module. The second output terminal of the second logic circuit outputs a signal PMW4, and the second output terminal of the second logic circuit is connected to the gate of the fourth switch tube Q4 through a driving module. The first output terminal of the second logic circuit is simultaneously connected to the first input terminal of the first logic circuit, and outputs a signal PMW4 to the gate of the fourth switch tube Q4 through a driving module. The first input end of a logic circuit outputs a PMW3 signal, and the second output end of the second logic circuit is simultaneously connected to the second input end of the first logic circuit, and outputs a PMW4 signal to the second input end of the first logic circuit; the output end of the comparator is connected to the third input end of the first logic circuit, and the comparator outputs a PMW0 signal to the third input end of the first logic circuit, the first output end of the first logic circuit is connected to the gate of the first switch tube Q1 through the driving module, and the first output end of the first logic circuit outputs a signal of PMW1, the second output end of the first logic circuit is connected to the gate of the second switch tube Q2 through the driving module, and the first output end of the first logic circuit outputs a signal of PMW2.

2. A dual-inductor bridgeless Boost PFC circuit according to claim 1, characterized in that: The first logic circuit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a first OR gate OR1, a second OR gate OR2, a first NOT gate NOT1, and a second NOT gate NOT2; The first input terminal of the first AND gate AND1 serves as the first input terminal of the first logic circuit, the second input terminal of the first AND gate AND1 and the first input terminal of the fourth AND gate AND4 serve as the third input terminal of the first logic circuit, the output terminal of the first OR gate OR1 serves as the first output terminal of the first logic circuit, and the output terminal of the second OR gate OR2 serves as the second output terminal of the first logic circuit; The first input terminal of the first AND gate AND1 inputs the PWM3 signal, and the first input terminal is simultaneously connected to the first input terminal of the third AND gate AND3. The second input terminal of the first AND gate AND1 inputs the PWM0 signal, and the second input terminal is simultaneously connected to the first input terminal of the fourth AND gate AND4. The output terminal of the first AND gate AND1 is connected to the first input terminal of the first OR gate OR1. The first input terminal of the fourth AND gate AND4 inputs the PWM0 signal, and the second input terminal of the fourth AND gate AND4 inputs the PWM4 signal. The second input terminal is simultaneously connected to the first input terminal of the second AND gate AND2. The output terminal of the fourth AND gate AND4 is connected to the first input terminal of the second OR gate OR2. The input ends of the first OR gate OR1 are connected, the output end of the first OR gate OR1 outputs the PWM1 signal, the output end of the first OR gate OR1 is simultaneously connected to the input end of the first NOT gate NOT1, the output end of the first NOT gate NOT1 is connected to the second input end of the third AND gate AND3, the second input end of the first OR gate OR1 is connected to the output end of the second AND gate AND2, the second input end of the second AND gate AND2 is connected to the output end of the second NOT gate NOT2, the input end of the second NOT gate NOT2 is connected to the output end of the second OR gate OR2, the output end of the second OR gate OR2 outputs the PWM2 signal, and the second input end of the second OR gate OR2 is connected to the output end of the third AND gate AND3.

3. The dual-inductor bridgeless Boost PFC circuit according to claim 2, characterized in that: The second logic circuit includes a first comparator U1A, a second comparator U1B, a first operational amplifier U1C, a second operational amplifier U1D, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; wherein the first operational amplifier U1C and the third resistor R3, the fourth resistor R4, and the fifth resistor R5 form a common-phase proportional amplifier, and the second operational amplifier U1D and the sixth resistor R6 form a voltage follower; One end of the fifth resistor R5 serves as an input end of the second logic circuit, the output end of the first comparator U1A serves as a first output end of the second logic circuit, and the output end of the second comparator U1B serves as a second output end of the second logic circuit; Among them, one end of the third resistor R3 is grounded, and the other end is connected to the inverting input terminal of the second operational amplifier U1D and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the output terminal of the second operational amplifier U1D, the input voltage of the AC power supply is sampled and input to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the non-inverting input terminal of the second operational amplifier U1D, one end of the sixth resistor R6 is connected to the output terminal of the second operational amplifier U1D, the other end of the sixth resistor R6 is connected to the non-inverting input terminal of the first operational amplifier U1C, the inverting input terminal of the first operational amplifier U1C is connected to the output terminal of the first operational amplifier U1C, the inverting input terminal of the first comparator U1A is connected to the output terminal of the first operational amplifier U1C, and the dead zone reference voltage -V is input to the non-inverting input terminal of the first comparator U1A th The output terminal of the first comparator U1A outputs the PWM3 signal, the non-inverting input terminal of the second comparator U1B is connected to the output terminal of the first operational amplifier U1C, and the inverting input terminal of the second comparator U1B inputs the dead zone reference voltage V th , the output end of the second comparator U1B outputs the PWM4 signal.

4. A control method based on a dual-inductor bridgeless Boost PFC circuit, characterized in that: Based on a dual-inductor bridgeless Boost PFC circuit as described in any one of claims 1 to 3, the following steps S1 to S5 are performed to complete the rectification, boosting, and power factor correction of the input voltage: S1: sampling the input voltage, input current and output voltage of the dual-inductor bridgeless Boost PFC circuit; S2: Based on the average current control strategy, a double closed-loop control loop is built so that the input current waveform follows the input voltage waveform; S3: Based on the control strategy of S2, the double closed-loop control loop obtains the signal PWM0 by adjusting the current loop PI controller and the voltage loop PI controller for the sampled values ​​of the input voltage, input current and output voltage; S4: setting the dead time of the third switch tube Q3 and the fourth switch tube Q4 according to the amplitude, frequency, sampling ratio and dead zone reference voltage of the input voltage; S5: the input voltage is processed by the second logic circuit to obtain signals PWM3 and PWM4, which respectively control the on and off of the third switch tube Q3 and the fourth switch tube Q4; the control signals PWM3, PWM4 and PWM0 are processed by the first logic circuit to obtain control signals PWM1 and PWM2, which respectively control the on and off of the first switch tube Q1 and the second switch tube Q2; Based on the main topology circuit, the double closed-loop control circuit, the first logic circuit and the second logic circuit, the rectification, boosting and power factor correction of the input voltage are completed.

5. The control method based on dual-inductor bridgeless Boost PFC circuit according to claim 4, characterized in that: In step S4, the dead time T of the third switch tube Q3 and the fourth switch tube Q4 is set according to the amplitude, frequency, sampling ratio and dead zone reference voltage of the input voltage. th As follows: Where V is the sampling ratio of the input voltage, f is the frequency of the AC input voltage, and U m is the amplitude of the input voltage, R3 is the resistance of the third resistor R3, and R4 is the resistance of the fourth resistor R4.

6. The control method based on dual-inductor bridgeless Boost PFC circuit according to claim 5, characterized in that: The operation process of the second logic circuit in step S5 is as follows: A: The input voltage is processed by the in-phase proportional amplifier and the voltage follower in sequence. The processed voltage is simultaneously input to the inverting input terminal of the first comparator U1A and the in-phase input terminal of the second comparator U2A. The dead zone reference voltage -V th Input to the non-inverting input terminal of the first comparator U1A, the dead zone reference voltage V th The first comparator U1A and the second comparator U1B output signals PWM3 and PWM4 respectively. The expressions of signals PWM3 and PWM4 are as follows: Where V is the sampling ratio of the input voltage, U m is the amplitude of the input voltage, w is the angular frequency, t is the time, R3 is the resistance value of the third resistor R3, and R4 is the resistance value of the fourth resistor R4; B: When the input voltage is in the positive half cycle, the signal PWM3 is low level, the signal PWM4 is high level, the fourth switch tube Q4 is turned on, the third switch tube Q3 is turned off, the second switch tube Q2 is turned on, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·V in Forward voltage drop, where V in The first inductor L1 and the second inductor L2 store energy, the inductor current increases linearly, and the first electrolytic capacitor C1 supplies power to the load R Load Transfer energy until the second switch tube Q2 is turned off and the inductor current rises to a peak value; C: When the input voltage is in the negative half cycle, the signal PWM3 is high level, the signal PWM4 is low level, the fourth switch tube Q4 is turned off, the third switch tube Q3 is turned on, the first switch tube Q1 is turned on, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·V in Forward voltage drop, the first inductor L1 and the second inductor L2 store energy, the inductor current increases linearly, and the first electrolytic capacitor C1 supplies power to the load R Load Energy is transferred until the first switch tube Q1 is turned off and the inductor current rises to a peak value.

7. The control method based on dual-inductor bridgeless Boost PFC circuit according to claim 6, characterized in that: The operation process of the first logic circuit in step S5 is as follows: A: The signals PWM3, PWM4 and PWM0 are input to the first logic circuit. After being processed by the first logic circuit, the expressions of the signals PWM1 and PWM2 are obtained as follows: B: When the input voltage is in the positive half cycle, the signal PWM3 is at a low level, the signal PWM4 is at a high level, the outputs of the first and third AND gates AND1 and AND3 are at a low level, the signal PMW2 controls the level change of the signal PMW1, and the level state of the signal PMW2 is opposite to that of the signal PMW1; after the second switch tube Q2 is turned off, the first switch tube Q1 is turned on, the inductor current continues to flow through the first switch tube Q1, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·(V in -V o ) reverse voltage drop, where V o is the output voltage, the first inductor L1 and the second inductor L2 supply voltage to the load R Load Energy is transferred and the inductor current decreases linearly; C: When the input voltage is in the negative half cycle, the signal PWM3 is high level, the signal PWM4 is low level, the outputs of the second AND gate AND2 and the fourth AND gate AND4 are low level, the signal PMW1 controls the level change of the signal PMW2, and the level states of the signal PMW1 and the signal PMW2 are opposite; after the first switch tube Q1 is turned off, the second switch tube Q2 is turned on, the inductor current continues to flow through the second switch tube Q2, and the first inductor L1 and the second inductor L2 are subjected to 1 / 2·(V in -V o ) reverse voltage drop, the first inductor L1 and the second inductor L2 to the load R Load Energy is transferred and the inductor current decreases linearly.

Images