An integrated receiving system for broadband and large dynamic range optical network signals

Abstract

The present application relates to an integrated receiving system for broadband and large dynamic optical network signals. The system includes: a coherent optical receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module; the coherent optical receiving module is used to demodulate the received optical signal; the high-speed ADC module is used to perform analog-to-digital conversion on the demodulated analog electrical signal; the FPGA module includes a Virtex Ultrascale+ module, which is used to control the high-speed ADC module to achieve analog-to-digital conversion, collect the digital signal output by it and cache it; the clock module is used to provide the sampling clock and start signal of the high-speed ADC module, the reference clock of the FPGA module, and the optical port module is used to output the cached sampling data. In this system, the high-speed ADC module and the FPGA module can select general ADC modules and FPGA modules according to actual needs, the system has strong compatibility, and can reduce the development cost of the system.

Description

Technical Field

[0001] The present application relates to the technical field of broadband signal sampling, and in particular to an integrated receiving system for broadband large dynamic range optical network signals. Background Art

[0002] Lightwave communication, with its huge bandwidth resources, good networking capabilities, strong anti-interference ability, and low cost, will serve as one of the foundations of the next generation of broadband communication networks. Optical network technology is to use optical cross-connect (OXC) and optical add-drop multiplexing (OADM) technologies in point-to-point wavelength division multiplexing systems to form an optical transport network (OTN) based on wavelength channels. However, with the development of communication systems, the signal specifications on the carrier of the optical network wavelength division multiplexing system are increasing, including different symbol rates, different modulation formats, etc. These factors bring great difficulties to the construction of the next generation of reconfigurable optical networks. Faced with the challenges posed by the modern complex communication environment to optical network design, the design of an integrated receiving architecture for broadband and large dynamic optical network signals is imperative.

[0003] The existing coherent optical receiving module is a customized DSP module, which must be a product of a specified manufacturer to match it. The system compatibility is relatively poor and it cannot adapt to different rates and multiple modulation formats. Summary of the invention

[0004] Based on this, it is necessary to provide an integrated receiving system for broadband and large dynamic optical network signals to address the above technical issues. The system can adapt to optical network signals with multiple rates and multiple modulation formats.

[0005] An integrated receiving system for broadband and large dynamic optical network signals comprises: a coherent optical receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module.

[0006] The coherent optical receiving module is used to receive an input optical signal and demodulate the optical signal.

[0007] The high-speed ADC module is used to perform analog-to-digital conversion on the analog electrical signal obtained after demodulation.

[0008] The FPGA module includes a Virtex Ultrascale+ module, which is used to control the high-speed ADC module to realize analog-to-digital conversion, collect the digital signal output by the high-speed ADC module, and cache the obtained sampled data.

[0009] The clock module is used to provide a sampling clock and a start signal for the high-speed ADC module and a reference clock for the high-speed transceiver of the Virtex Ultrascale+ module.

[0010] The optical port module is used to output the sampled data cached in the FPGA module.

[0011] The power circuit module is used to provide power to the coherent optical receiving module, the high-speed ADC module, the clock module, the FPGA module and the optical port module, and to perform power management and monitoring.

[0012] Furthermore, the coherent optical receiving module includes an integrated coherent receiver and an integrated tunable laser component.

[0013] The integrated adjustable laser component is connected to the integrated coherent receiver; the integrated coherent receiver is connected to the high-speed ADC.

[0014] Furthermore, the high-speed ADC module includes multiple high-speed analog-to-digital conversion modules with a sampling rate of up to 56 GSPS; the high-speed analog-to-digital conversion module is connected to the coherent optical receiving module and the FPGA module.

[0015] The multiple high-speed analog-to-digital conversion modules are sampled synchronously under the action of the start signal provided by the sampling clock module.

[0016] Furthermore, the high-speed analog-to-digital conversion module is an AAD08S056G module; the number of the high-speed analog-to-digital conversion modules is 4.

[0017] The output of the AAD08S056G module is connected to the high-speed transceiver of the Virtex Ultrascale+ module through a CML interface.

[0018] The SPI signal and SYNC signal of the AAD08S056G module are connected to the Virtex Ultrascale+ module. The SPI signal is used to configure the AAD08S056G module, and the SYNC signal is used for synchronous sampling between four AAD08S056G modules.

[0019] The sampling clocks of the four AAD08S056Gs and the reference clock and data processing clock of the high-speed transceiver of the Virtex Ultrascale+ module are the same source clocks, all provided by the clock module.

[0020] Furthermore, the clock module includes: a phase-locked medium oscillator, a multi-way power divider and a clock chip.

[0021] The phase-locked dielectric oscillator is used to output a 13dB sinusoidal clock signal; the multi-channel power divider is used to divide the sinusoidal clock signal into multiple clock signals, and use the multiple clock signals as the reference clock source of the high-speed ADC module.

[0022] The phase-locked medium oscillator is also used to output a homologous 100 MHz low-frequency clock, which serves as a reference clock source for the receiving end of the Virtex Ultrascale+ module and a source of a synchronous start signal for a high-speed ADC module.

[0023] The clock chip is used to provide a reference clock for high-speed signal transmission to the Virtex Ultrascale+ module.

[0024] Furthermore, the optical port module includes a QSFP28 module; the QSFP28 module is connected to the VirtexUltrascale+ module.

[0025] Furthermore, the FPGA module also includes: a high-speed cache FPGA module for caching the sampled data.

[0026] The input port of the cache FPGA module is connected to the Virtex Ultrascale+ module, and the output port of the cache FPGA module is connected to the optical port module.

[0027] Furthermore, the optical port module includes a QSFP28 module and an SFP+ optical network port; the QSFP28 module and the SFP+ optical network port are both connected to the cache FPGA module.

[0028] Furthermore, the integrated receiving system also includes a network management module.

[0029] The network management module includes: RK3399 chip, Xilinx XC6SLX45T-2FGG484C chip, integrated dense analog-to-digital conversion module and digital-to-analog conversion module.

[0030] The RK3399 chip is connected to the FPGA module via an SGMII interface, the integrated dense analog-to-digital conversion module and the digital-to-analog conversion module are both connected to the coherent optical receiving module and the RK3399 chip; the RK3399 chip is connected to the coherent optical receiving module.

[0031] Furthermore, the power circuit module includes an ATCA power management module and a power module.

[0032] The power supply module includes: DC / DC switching power supply circuit, DC / DC LDO power supply circuit and DC / DC bus power supply circuit; the DC / DC switching power supply circuit is used to provide various digital power supplies with a voltage range of -5V to +5V for the digital circuit; the DC / DCLDO power supply circuit is used to provide various analog power supplies with a voltage range of -5.2V to +10V for the analog circuit; the DC / DC bus power supply circuit is used to provide a +12V bus power supply with an output current of 30A and a maximum output power of 360W.

[0033] The ATCA power management module includes a power-on sequence control circuit for controlling the power-on sequence of various digital or analog power supplies.

[0034] The above-mentioned integrated receiving system for broadband and large dynamic optical network signals includes: a coherent optical receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module; the coherent optical receiving module is used to receive the input optical signal and demodulate the optical signal; the high-speed ADC module is used to perform analog-to-digital conversion on the analog electrical signal obtained after demodulation; the FPGA module includes a Virtex Ultrascale+ module, which is used to control the high-speed ADC module to achieve analog-to-digital conversion, collect the digital signal output by the high-speed ADC module, and cache the obtained sampled data; the clock module is used to provide the sampling clock and start signal of the high-speed ADC module and the reference clock of the high-speed transceiver of the Virtex Ultrascale+ module; the optical port module is used to output the sampled data cached in the FPGA module; the power circuit module is used to provide power to the system, and perform power management and monitoring. The high-speed ADC module and FPGA module in this system can select general ADC modules and FPGA modules according to actual design requirements, the system has strong compatibility, and can reduce the development cost of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A structural block diagram of an integrated receiving system for broadband and large dynamic optical network signals in one embodiment;

[0036] Figure 2 It is a structural block diagram of an integrated receiving system for broadband and large dynamic optical network signals in another embodiment;

[0037] Figure 3 is a block diagram of a coherent optical demodulation module in one embodiment;

[0038] Figure 4 FIG. 4 is a block diagram of a network management module in another embodiment. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] In one embodiment, Figure 1 As shown, an integrated receiving system for broadband and large dynamic optical network signals is provided, and the integrated receiving system includes: a coherent optical receiving module 10, a high-speed ADC module 20, a clock module 30, an FPGA module 40, an optical port module 50 and a power circuit module 60.

[0041] The coherent optical receiving module 10 is used to receive an input optical signal and demodulate the optical signal.

[0042] The high-speed ADC module 20 is used to perform analog-to-digital conversion on the analog electrical signal obtained after demodulation.

[0043] The FPGA module 30 includes a Virtex Ultrascale+ module 301, which is used to control the high-speed ADC module 20 to realize analog-to-digital conversion, collect the digital signal output by the high-speed ADC module 20, and cache the obtained sampled data. Preferably, the Virtex Ultrascale+ module 30 uses a Xilinx Virtex Ultrascale+ series FPGA chip with model XCVU13P-FLGA2577. The Virtex Ultrascale+ module controls the ADC module to sample through the JESD204B protocol. The high-speed GTY transceiver of the Xilinx Virtex Ultrascale+ series XCVU13P-FLGA2577 model FPGA chip can reach a maximum rate of 32.75Gbps, with a total of 128 pairs. Among the 128 pairs of GTY interfaces, the high-speed ADC module needs to occupy 64 pairs, which are used for the XCVU13P-FLGA2577 model FPGA chip to receive the digital signals converted by the high-speed ADC module; 64 pairs of GTY interfaces are reserved for the XCVU13P-FLGA2577 model FPGA chip to exchange data with the extended high-speed cache FPGA module; in addition, the number of other interfaces is not less than 100 (2 banks).

[0044] The clock module 40 is used to provide a sampling clock and a start signal for the high-speed ADC module and a reference clock for the high-speed transceiver of the Virtex Ultrascale+ module.

[0045] The optical port module 50 is used to output the sampled data cached in the FPGA module 40 .

[0046] The power circuit module 60 is used to provide power to the coherent optical receiving module 10, the high-speed ADC module 20, the clock module 30, the FPGA module 40 and the optical port module 50, and to perform power management and monitoring.

[0047] The integrated receiving system for broadband and large dynamic optical network signals is based on the coherent optical reception solution to demodulate optical signals of different specifications at the 128G rate level; it uses the domestic 56G8bitADC module to perform digital-to-analog conversion to obtain front-end data; and it uses FPGA products with high-speed SERDES interface and high-throughput HBM to achieve correct acquisition and caching of high-speed electrical signals.

[0048] In the above-mentioned integrated receiving system of broadband large dynamic optical network signals, the system includes: a coherent optical receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module; the coherent optical receiving module is used to receive the input optical signal and demodulate the optical signal; the high-speed ADC module is used to perform analog-to-digital conversion on the analog electrical signal obtained after demodulation; the FPGA module includes a Virtex Ultrascale+ module, which is used to control the high-speed ADC module to realize analog-to-digital conversion, collect the digital signal output by the high-speed ADC module, and cache the obtained sampled data; the clock module is used to provide the sampling clock and start signal of the high-speed ADC module and the reference clock of the high-speed transceiver of the Virtex Ultrascale+ module; the optical port module is used to output the sampled data cached in the FPGA module; the power circuit module is used to provide power to the system, and perform power management and monitoring. The high-speed ADC module and FPGA module in this system can select general ADC modules and FPGA modules according to actual design requirements, the system has strong compatibility, and can reduce the development cost of the system.

[0049] Furthermore, the coherent optical receiving module includes an integrated coherent receiver and an integrated adjustable laser component; the integrated adjustable laser component is connected to the integrated coherent receiver; and the integrated coherent receiver is connected to the high-speed ADC.

[0050] Specifically, the coherent optical receiving module uses an integrated coherent receiver (ICR) and an integrated tunable laser assembly (ITLA) to realize demodulation and detection of optical signals of multiple modulation formats (QPSK / PM-QPSK / 4QAM, 16QAM, 64QAM) in the C band. Preferably, the integrated coherent receiver uses FUJITSU MICRO ICR, and the integrated tunable laser assembly uses MICRO-ITLA.

[0051] Furthermore, the high-speed ADC module includes multiple high-speed analog-to-digital conversion modules with a sampling rate of up to 56GSPS; the high-speed analog-to-digital conversion module is connected to the coherent optical receiving module and the FPGA module; the multiple high-speed analog-to-digital conversion modules are synchronously sampled under the action of the start signal provided by the sampling clock module.

[0052] Furthermore, the high-speed analog-to-digital conversion module is an AAD08S056G module; the number of high-speed analog-to-digital conversion modules is 4; the output end of the AAD08S056G module is connected to the high-speed transceiver of the Virtex Ultrascale+ module through a CML interface; the SPI signal and SYNC signal of the AAD08S056G module are connected to the Virtex Ultrascale+ module, the SPI signal is used to configure the AAD08S056G module, and the SYNC signal is used for synchronous sampling between four AAD08S056G modules; the sampling clocks of the four AAD08S056Gs and the reference clock of the high-speed transceiver of the Virtex Ultrascale+ module and the data processing clock are the same source clocks, all provided by the clock module.

[0053] Specifically, the high-speed analog-to-digital conversion module uses the AAD08S056G chip. The AAD08S056G chip has 128 channels and 8-bit sampling, with a sampling rate of up to 56GSPS and data transmission using the 16-way JESD204B protocol. The AAD08S056G chip supports 128 channels @ 56000Msps analog-to-digital sampling function; supports input bandwidth up to 18.5GHz; supports external SYNC input for multi-board synchronization; and each chip consumes as little as 3W of power.

[0054] Compared with the prior art, the advantages of the present invention are: direct sampling of the integrated receiving architecture of optical network signals is realized through four AAD08S056G chips, and the single-channel sampling speed is up to 56 GHz, with the characteristics of wide instantaneous bandwidth, large dynamic range, strong data storage capacity, and high sampling clock accuracy.

[0055] Furthermore, the clock module includes: a phase-locked dielectric oscillator, a multi-channel power divider and a clock chip; the phase-locked dielectric oscillator is used to output a 13dB sinusoidal clock signal; the multi-channel power divider is used to divide the sinusoidal clock signal into multiple clock signals, and use the multiple clock signals as the reference clock source of the high-speed ADC module; the phase-locked dielectric oscillator is also used to output a homologous 100MHz low-frequency clock, and the 100MHz low-frequency clock is used as the reference clock source of the Virtex Ultrascale+ module receiving end and the source of the high-speed ADC module synchronization start signal; the clock chip is used to provide the Virtex Ultrascale+ module with a reference clock for high-speed signal transmission.

[0056] Specifically, the clock module uses a phase-locked medium oscillator as a clock source, and the clock chip Si5347 is used as a reference clock for high-speed signal transmission.

[0057] Furthermore, the optical port module includes a QSFP28 module; the QSFP28 module is connected to the Virtex Ultrascale+ module.

[0058] Furthermore, the FPGA module also includes: a high-speed cache FPGA module for caching the sampled data; an input port of the high-speed cache FPGA module is connected to the Virtex Ultrascale+ module, and an output port of the high-speed cache FPGA module is connected to the optical port module.

[0059] Specifically, when the cache space of the Virtex Ultrascale+ module in the FPGA module cannot meet the system requirements, a high-speed cache FPGA module can be expanded. Preferably, the high-speed cache FPGA module uses the 1SM21BEU2F55E2VG chip of the Intel Stratix10MX series, which supports a total of 96 serial data channels (transceivers), of which 72 channels have a rate of 28.3Gbps and 24 channels have a rate of 26.0Gbps. Internally integrated on-chip storage HBM (512GByte / s, 8G). Among the 96 high-speed channels, 64 channels are occupied for data interaction with the previous level FPGA, 1 channel is reserved for the optical module, and 10 channels are reserved for the optical network port; in addition, the number of other interfaces is not less than 100 (2 banks). The optical signal transceiver interface is an LC interface.

[0060] Furthermore, the optical port module includes a QSFP28 module and an SFP+ optical network port; the QSFP28 module and the SFP+ optical network port are both connected to the high-speed cache FPGA module.

[0061] Specifically, the optical port modules include QSFP28 and SFP+ optical network ports. Intel Stratix 10MX FPGA reserves 1 channel for QSFP28 optical modules and 12 channels for SFP+ optical network ports. The optical signal transceiver interface is an LC interface. After the SFP+ module completes the photoelectric conversion, it is directly connected to the high-speed port of the cache FPGA module. Optional high-performance SFP+ optical modules have a sensitivity of -16dBm.

[0062] In addition, the 1SM21BEU2F55E2VG chip of the Intel Stratix 10MX series supports the HBM 3D memory protocol stack, which includes multiple memory chips and optional basic logic chips, which are connected together through silicon vias (TSV). The memory bandwidth of an HBM2 protocol stack exceeds 1Tbps, and multiple protocol stacks can be integrated into one device.

[0063] Furthermore, the integrated receiving system also includes a network management module; the network management module includes: RK3399 chip, Xilinx XC6SLX45T-2FGG484C chip, integrated dense analog-to-digital conversion module and digital-to-analog conversion module; the RK3399 chip is connected to the FPGA module through the SGMII interface, and the integrated dense analog-to-digital conversion module and the digital-to-analog conversion module are both connected to the coherent optical receiving module and the RK3399 chip; the RK3399 chip is connected to the coherent optical receiving module.

[0064] Specifically, the network management module uses RK3399 chip and Xilinx XC6SLX45T-2FGG484C chip to realize intelligent monitoring of the acquisition system status, mainly completing the basic configuration of Virtex Ultrascale+ module, signal loss alarm, frame loss alarm, input and output signal type and rate, channel parameters, signal bit error rate statistics, branch time slot allocation, port time slot allocation, line service carrying status, equipment power status, board temperature information and other peripheral equipment status monitoring and control. The network management protocol is planned to be based on the TCP / IP protocol, manage the equipment downward, and open access ports upward to facilitate data access by third-party network management systems.

[0065] As a preferred option, the integrated dense analog-to-digital conversion module uses the AD5628 chip, and the digital-to-analog conversion module uses the DA7091 chip. The ICR is externally connected to the AD5628 chip and the DA7091 chip to provide the output amplitude control signal and output peak envelope detection parameters of the ICR. The AD5628 and DA7091 chips communicate with the network management module through the SPI protocol and the high-speed serial interface respectively to complete the instruction transmission. ITLA connects to the network management module through the RS232 protocol to configure the wavelength and amplitude, and completes the wavelength alignment with the input optical signal.

[0066] Furthermore, the power circuit module includes an ATCA power management module and a power module; the power module includes: a DC / DC switching power circuit, a DC / DC LDO power circuit and a DC / DC bus power circuit; the DC / DC switching power circuit is used to provide various digital power supplies with a voltage range of -5V to +5V for the digital circuit; the DC / DC LDO power circuit is used to provide various analog power supplies with a voltage range of -5.2V to +10V for the analog circuit; the DC / DC bus power circuit is used to provide a +12V bus power supply with an output current of 30A and a maximum output power of 360W; the ATCA power management module includes a power-on timing control circuit, which is used to control the power-on timing of various digital or analog power supplies.

[0067] In one embodiment, Figure 2As shown, this embodiment provides a multi-channel broadband large dynamic optical network signal integrated receiving system based on Virtex Ultrascale+FPGA, including a coherent optical receiving module, a domestic ADC module, a sampling clock module, a Xilinx Virtex Ultrascale+FPGA, a cache FPGA module (Intel Stratix 10MX module), an optical port module, a network management module and a power supply module.

[0068] like Figure 3 As shown, the coherent optical receiving module uses an integrated coherent receiver (ICR) and an integrated tunable laser assembly (ITLA) to realize the demodulation and detection of optical signals of various modulation formats (QPSK / PM-QPSK / 4QAM, 16QAM, 64QAM) in the C band. The ICR is externally connected to the AD5628 and DA7091 chips to provide the output amplitude control signal and output peak envelope detection parameters of the ICR. The AD5628 and DA7091 chips communicate with the network management module through the SPI protocol and the high-speed serial interface respectively to complete the instruction transmission. The ITLA is connected to the network management module through the RS232 protocol to configure the wavelength and amplitude, and complete the wavelength alignment with the input optical signal.

[0069] The domestic ADC module of the present invention adopts 4 AAD08S056G modules to realize 4-way synchronous sampling. AAD08S056G converts the input analog signal into an 8-bit digital signal, and after scrambling the data, it is connected to FPGA 64 pairs of high-speed transceivers through the CML interface output, occupying 8 high-speed transceiver banks for high-speed transmission of sampled data; the SPI signal and SYNC signal of AAD08S056G are connected to Xilinx FPGA, the SPI signal is used to configure ADC, and the SYNC signal is used for synchronous sampling between four ADCs; the sampling clocks of the four AAD08S056Gs and the reference clocks of the FPGA high-speed transceivers and the data processing clocks need the same source clock, which is connected to the phase-locked medium oscillator (PLDRO); the key to the synchronous sampling of the four AAD08S056Gs is that the SYNC signal of each ADC must have a certain phase relationship, a fast jump edge and a low jitter time. The phase-locked medium oscillator (PLDRO) can generate a 13dB sinusoidal clock signal, which can be used as the reference clock source of multiple ADCs through a multi-channel power divider (PD). At the same time, PLDRO can output a 100MHz low-frequency clock of the same source, which can be used as the reference clock source of the FPGA receiving end and the source of the ADC synchronization start signal SYNC.

[0070] like Figure 4As shown in the figure, in order to systematically manage the two FPGAs, four ADC modules, and multiple output optical modules as data receiving front-end and data storage units, the board is designed with a network management module based on the RK3399 chip. RK3399 is a domestically produced high-performance and cost-effective control chip. It is combined with the 45T FPGA as an interface expansion and the LPC1788 ARM chip as the baseboard management controller (BMC) in the ATCA protocol to jointly realize the register reading and writing and data transmission functions of the main functional modules of the board.

[0071] The power circuit module consists of two parts: ATCA power management module and power module. They provide stable and reliable digital power and analog power for this system, control the power-on sequence of different power supplies, monitor overvoltage and undervoltage monitoring and implement protection. The two input -48V power supplies that back up each other are sent to the power switching circuit after the protection circuit. The power switching circuit issues a switching command to switch the power supply and shut down the power output according to the overvoltage, undervoltage, overcurrent and other conditions in the power management circuit. The energy storage circuit realizes the function that the output power will not jitter during the power switching process. The EMI filter circuit filters out EMI interference. The DC / DC bus power circuit uses the BQ60120HEB25NKS device produced by Synqor, which converts the -48V input power into a +12V bus power supply with an output current of 30A and a maximum output power of 360W. The +12V bus power supply is designed to be 360W to meet the actual 300W power consumption requirement, and can be safely and stably supplied. The power supply power-on control circuit shuts down the bus power supply according to the power-on and power-off commands given by the monitoring circuit. The power module has three parts: DC / DC switching power supply circuit, DC / DC LDO power supply circuit and power-on timing control circuit. The DC / DC switching power supply circuit provides various digital power supplies with a voltage range of -5V to +5V for digital circuits. The DC / DC LDO power supply circuit provides various analog power supplies with a voltage range of -5.2V to +10V for analog circuits. The entire power module provides 73 types of power supplies for the system. The power-on timing control circuit controls the power-on timing of various digital or analog power supplies to meet the power-on requirements of each device and avoid excessive impact current during the power-on process. When each unit of this system is working normally at full speed, the input current is less than 20A / 12V, and the maximum impact current during the power-on process is less than 6A / 12V.

[0072] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An integrated receiving system for broadband and large dynamic optical network signals, characterized in that: The integrated receiving system includes: a coherent optical receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module; The coherent optical receiving module is used to receive an input optical signal and demodulate the optical signal; The high-speed ADC module is used to perform analog-to-digital conversion on the analog electrical signal obtained after demodulation; The FPGA module includes a Virtex Ultrascale+ module, which is used to control the high-speed ADC module to realize analog-to-digital conversion, collect the digital signal output by the high-speed ADC module, and cache the obtained sampled data; The clock module is used to provide a sampling clock and a start signal for the high-speed ADC module and a reference clock for the high-speed transceiver of the VirtexUltrascale+ module; The optical port module is used to output the sampled data cached in the FPGA module; The power circuit module is used to provide power to the coherent optical receiving module, the high-speed ADC module, the clock module, the FPGA module and the optical port module, and perform power management and monitoring; The coherent optical receiving module includes an integrated coherent receiver and an integrated adjustable laser assembly; The integrated adjustable laser assembly is connected to the integrated coherent receiver; the integrated coherent receiver is connected to the high-speed ADC module; The integrated receiving system also includes a network management module, which includes an RK3399 chip, a Xilinx XC6SLX45T-2FGG484C chip, an integrated dense analog-to-digital conversion module, and a digital-to-analog conversion module; The RK3399 chip is connected to the FPGA module via an SGMII interface, and the integrated dense analog-to-digital conversion module and the digital-to-analog conversion module are both connected to the coherent optical receiving module and the RK3399 chip; the RK3399 chip is connected to the coherent optical receiving module; The integrated dense analog-to-digital conversion module and the digital-to-analog conversion module communicate with the network management module respectively to complete the instruction transmission; the instruction transmission includes the transmission of the amplitude control signal and the peak envelope detection parameter of the integrated coherent receiver; The integrated tunable laser assembly is connected to the network management module to configure the wavelength and amplitude, and complete the wavelength alignment with the input optical signal; The high-speed ADC module includes multiple high-speed analog-to-digital conversion modules with a sampling rate of up to 56 GSPS; the high-speed analog-to-digital conversion module is connected to the coherent light receiving module and the FPGA module; The multiple high-speed analog-to-digital conversion modules are sampled synchronously under the action of the start signal provided by the clock module; The high-speed analog-to-digital conversion module is an AAD08S056G module; the number of the high-speed analog-to-digital conversion modules is 4; The output of the AAD08S056G module is connected to the high-speed transceiver of the Virtex Ultrascale+ module through a CML interface. The SPI signal and SYNC signal of the AAD08S056G module are connected to the Virtex Ultrascale+ module. The SPI signal is used to configure the AAD08S056G module, and the SYNC signal is used for synchronous sampling between four AAD08S056G modules. The sampling clocks of the four AAD08S056Gs and the reference clock and data processing clock of the high-speed transceiver of the Virtex Ultrascale+ module are the same source clocks, all provided by the clock module; The clock module includes: a phase-locked medium oscillator, a multi-way power divider and a clock chip; The phase-locked dielectric oscillator is used to output a 13dB sinusoidal clock signal; the multi-channel power divider is used to divide the sinusoidal clock signal into multiple clock signals, and use the multiple clock signals as the reference clock source of the high-speed ADC module; The phase-locked medium oscillator is also used to output a homologous 100 MHz low-frequency clock, which serves as a reference clock source for the receiving end of the Virtex Ultrascale+ module and a source of a synchronous start signal for a high-speed ADC module; The clock chip is used to provide a reference clock for high-speed signal transmission to the Virtex Ultrascale+ module; The FPGA module also includes: a high-speed cache FPGA module, used for caching the sampled data; The input port of the cache FPGA module is connected to the Virtex Ultrascale+ module, and the output port of the cache FPGA module is connected to the optical port module.

2. The integrated receiving system according to claim 1, characterized in that: The optical port module includes a QSFP28 module; the QSFP28 module is connected to the Virtex Ultrascale+ module.

3. The integrated receiving system according to claim 1, characterized in that: The optical port module includes a QSFP28 module and an SFP+ optical network port; The QSFP28 module and the SFP+ optical network port are both connected to the high-speed cache FPGA module.

4. The integrated receiving system according to claim 1, characterized in that: The power circuit module includes an ATCA power management module and a power module; The power module includes: a DC / DC switching power supply circuit, a DC / DC LDO power supply circuit and a DC / DC bus power supply circuit; The DC / DC switching power supply circuit is used to provide various digital power supplies with a voltage range of -5V to +5V for digital circuits; the DC / DC LDO power supply circuit is used to provide various analog power supplies with a voltage range of -5.2V to +10V for analog circuits; the DC / DC bus power supply circuit is used to provide a +12V bus power supply with an output current of 30A and a maximum output power of 360W; The ATCA power management module includes a power-on sequence control circuit for controlling the power-on sequence of various digital or analog power supplies.

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