Processor unit for multiplication and accumulation operations

Abstract

A processor unit for multiplication and accumulation (“MAC”) operations is provided, the processor unit comprising: a plurality of MAC units for performing a set of MAC operations, wherein each MAC unit of the plurality of MAC units comprises an execution unit and a one-write-one-read (“1W / 1R”) register file, wherein the 1W / 1R register file has at least one accumulator; and another register file, wherein the execution unit of each MAC unit is configured to perform the set of MAC operations by calculating the product of a set of values received from the another register file and adding the calculated product to the content of at least one accumulator, wherein each MAC unit is configured to perform the corresponding subset of MAC operations in a single clock cycle.

Description

Technical Field

[0001] The present invention relates to the field of digital computer systems and, more particularly, to a processor unit for performing a set of one or more multiply and accumulate ("MAC") operations. Background Art

[0002] The computation of MAC operations is commonly used in many algorithms, such as the training of deep neural networks, image processing, and other machine learning techniques. For example, in the case of a deep neural network, MAC operations can involve activations and gradients. However, conventional electronic systems for computing MAC operations can be resource-intensive. In particular, there is a need for an energy-efficient and resource-saving architecture for performing such operations. Summary of the Invention

[0003] Various embodiments provide a processor unit, a method, a computer program product, and a MAC unit for performing a set of one or more MAC operations as described in the subject matter of the independent claims. Advantageous embodiments are described in the dependent claims. If the embodiments of the present invention are not mutually exclusive, they can be freely combined with each other.

[0004] In one aspect, embodiments of the present invention disclose a processor unit for multiply and accumulate ("MAC") operations. In one embodiment, the processor unit may include a plurality of MAC units for performing respective subsets of MAC operations of a set of MAC operations. In one embodiment, each MAC unit of the plurality of MAC units may include a respective execution unit and a respective one write-one read ("1W / 1R") register file. In one embodiment, the respective 1W / 1R register file may have at least one accumulator. In one embodiment, the processor unit may include another register file. In one embodiment, the respective execution unit of each MAC unit may be configured to perform a respective subset of the set of MAC operations by computing the product of a set of values received from the other register file and adding the computed product to the content of at least one accumulator of the MAC unit. In one embodiment, each MAC unit may be configured to perform the respective subset of MAC operations in a single clock cycle.

[0005] In advantageous embodiments, each MAC unit of the plurality of MAC units may include an associated index. Thus, each MAC unit may be configured to perform the respective subset of MAC operations by executing a processor instruction that references the associated index.

[0006] In advantageous embodiments, the associated index may include an architected accumulator register index of at least one accumulator of each MAC unit.

[0007] In advantageous embodiments, at least one accumulator may include corresponding accumulator elements, where the computed product may be added to the content of the corresponding accumulator element. In advantageous embodiments, each MAC unit may be configured to perform a corresponding subset of the set of MAC operations using the corresponding accumulator element of at least one accumulator.

[0008] In advantageous embodiments, the processor unit may include a dispatch / issue unit. In advantageous embodiments, the dispatch / issue unit may be configured to process multiple processor instructions, use an associated index to select MAC units, and send a corresponding set of processor instructions to the selected MAC units for performing the set of MAC operations. In advantageous embodiments, the dispatch / issue unit may include MAC units therein.

[0009] In advantageous embodiments, the corresponding set of processor instructions may include at least one operand. The at least one operand may indicate the at least one accumulator as a source register and a target register of the corresponding set of processor instructions. The at least one operand may also indicate at least one additional register of another register file as including a set of numbers.

[0010] In advantageous embodiments, the dispatch / issue unit may be configured to dispatch multiple processor instructions according to a single-threaded (“ST”) mode such that the selected MAC units may receive the corresponding set of processor instructions from a single thread.

[0011] In advantageous embodiments, the dispatch / issue unit may be configured to dispatch multiple processor instructions according to a simultaneous multithreading two-way (“SMT2”) mode such that the selected MAC units may receive the corresponding set of processor instructions from any one of two threads.

[0012] In advantageous embodiments, the dispatch / issue unit may be configured to dispatch multiple processor instructions according to a simultaneous multithreading four-way (“SMT4”) mode such that each of the multiple MAC units may receive the corresponding set of processor instructions from a corresponding two threads.

[0013] In advantageous embodiments, each MAC unit may include at least one multiplier for computing a product and at least one adder for performing the addition of the computed product.

[0014] In advantageous embodiments, the processor unit may be configured to perform an additional set of MAC operations, where all sets of MAC operations provide all elements of an output matrix. In advantageous embodiments, the output matrix may include the result of a matrix convolution of an input matrix.

[0015] In one aspect, embodiments of the present invention disclose a method and a computer program product for performing MAC operations. The present invention may include receiving a set of values from a register file at a multiplier of a MAC unit. The present invention may include using the multiplier to calculate the product of the received set of values. The present invention may include: reading the current content of an accumulator of the MAC unit. The present invention may include using an adder of the MAC unit to calculate the sum of the read current content of the accumulator and the calculated product of the received set of values. The present invention may include writing the calculated sum to the accumulator of the MAC unit.

[0016] In one aspect, embodiments of the present invention disclose a MAC unit. In one embodiment, the MAC unit may include an execution unit and a one-write / one-read (“1W / 1R”) ported register file. In one embodiment, the 1W / 1R ported register file may include at least one accumulator. In one embodiment, the execution unit of the MAC unit may be configured to perform MAC operations by calculating a product and adding the product to the content of at least one accumulator of the MAC unit.

[0017] In advantageous embodiments, the execution unit of the MAC unit may be configured to continuously perform multiple MAC operations using the same accumulator for accumulating the products of each of the multiple MAC operations.

[0018] In advantageous embodiments, the MAC unit may include multiple accumulators. In advantageous embodiments, the MAC unit may be configured to perform multiple MAC operations in parallel using corresponding accumulators among the multiple accumulators.

[0019] In advantageous embodiments, at least one accumulator of the MAC unit may include multiple accumulator elements. In advantageous embodiments, the MAC unit may include multiple multipliers and adders. In advantageous embodiments, the MAC unit may be configured to perform multiple MAC operations in parallel using corresponding accumulator elements among the multiple accumulator elements and corresponding multipliers among the multiple multipliers.

[0020] The present disclosure may provide an energy - efficient and application - specific processor for performing MAC operations. The processor unit has a small number of register - file ports, which may be superior to architectures with a larger number of ports. Specifically, using a register file with a single read port and a single write port can achieve simplified hardware control and reduced energy consumption. Compared with, for example, a 2W / 2R register file that provides two read ports and two write ports to connect two MAC execution units, the implementation of a 1 - write - port / 1 - read - port register file (“1W / 1R”) may require less wiring, a smaller footprint, and less power demand. Reduced connectivity can maintain the same application speed, reduce energy consumption, and allow an increase in the processor frequency. Additionally, the subject matter can prevent sharing a register file among MAC units. It is contemplated that providing each MAC unit with its own register file can accelerate MAC operations because each execution unit can be independently and optimally connected to its respective register file.

[0021] The subject matter can enable performing MAC operations using single - instruction multiple - data (“SIMD”) operands as basic arithmetic operations. This can improve the efficiency of the processor because SIMD operands can be efficiently stored in separate register files, such that they can be loaded from the register file into the MAC unit in a single clock cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the invention, which is to be read in conjunction with the accompanying drawings. The various features of the drawings are not to scale as the illustration is for clarity in enabling a person skilled in the art to understand the invention in conjunction with the detailed description. In the drawings:

[0023] Figure 1 is a block diagram showing an exemplary structure of a processor system according to at least one embodiment;

[0024] Figure 2A is a block diagram showing an exemplary matrix operation of a MAC operation according to at least one embodiment;

[0025] Figure 2B is a block diagram showing an accumulator for calculating elements of a matrix operation according to at least one embodiment;

[0026] Figure 2C is a block diagram showing an exemplary MAC unit according to at least one embodiment;

[0027] Figure 3 is a block diagram showing, according to at least one embodiment, the Figure 1 exemplary MAC unit shown in;

[0028] Figure 4 is a block diagram showing an exemplary processor unit according to at least one embodiment;

[0029] Figure 5A is a block diagram showing an exemplary processor unit according to at least one embodiment;

[0030] Figure 5B is a block diagram showing an exemplary processor unit according to at least one embodiment;

[0031] Figure 6A is an operation flowchart showing an exemplary process for performing one or more sets of MAC operations according to at least one embodiment;

[0032] Figure 6B is showing according to at least one embodiment in relation to Figure 6A the MAC operations associated with an exemplary MAC unit; and

[0033] Figure 6C is showing according to at least one embodiment in relation to Figure 6A the MAC operations associated with an exemplary MAC unit. DETAILED DESCRIPTION

[0034] The description of the different embodiments of the present invention will be presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to a person of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology found in the market, or to enable a person of ordinary skill in the art to understand.

[0035] According to one embodiment, each MAC unit in a MAC unit is associated with an index, where the MAC unit is configured to perform a MAC operation by executing a processor instruction that references the index. This enables identifying a particular MAC unit to process an instruction in an optimal manner by reading the index of the instruction. This can be optimal because such a read is anyway performed in a processor system to identify the operands of the instruction (e.g., no additional operation may be required to read the index).

[0036] Each MAC unit in a MAC unit can be configured to perform a corresponding subset of one or more MAC operations in a set of MAC operations. The subset of MAC operations to be performed by the MAC unit can, for example, compute one or more elements of a matrix C. For example, matrix C can be defined by the following formula [1]:

[0037] C ij = ∑ k Aki B jk [I] [1]

[0039] In the above formula [1], for a given value k, a subset of the MAC operations can include the product ∑ k A ki B jk and sums. For example, if A, B, and C are 4x4 matrices, a subset of the MAC operations can include 4 MAC operations A11*B11, A21*B12, A31*B13, and A41*B14 for obtaining the element C11. Each group of one or more MAC operations that can be executed by a MAC unit in one clock cycle can be executed by executing a processor instruction. The processor instruction can be executed in parallel by the MAC unit, for example. For example, a set of MAC operations includes N MAC operations to be executed by one MAC unit and another N MAC operations to be executed by another MAC unit. Two MAC units can be configured to execute each pair of MAC operations in parallel continuously (e.g., if N = 3, 3 pairs of MAC operations can be executed in parallel continuously). This can be particularly advantageous if each MAC unit includes a single accumulator for storing one element. The accumulator can be a register. In another example, the accumulator can include multiple fields or accumulator elements (e.g., m elements), where each accumulator element can be used to accumulate the result of a corresponding MAC operation. In this case, the MAC unit can be configured to execute m MAC operations in parallel in one clock cycle.

[0040] If there is more than one accumulator in each MAC unit, pipelined execution of instructions can be advantageously used. According to one embodiment, each MAC unit in the MAC unit is configured to execute the corresponding MAC operation in at least one clock cycle (e.g., in multiple clock cycles). The execution of the MAC operation can include four clock cycles, for example, to generate the result of the processor instruction. The processor instruction can include four steps, where each step contributes to obtaining the overall result of the processed processor instruction. In each clock cycle, a different accumulator register can be used to start a new processor instruction. Once the result of the instruction is available, after 4 cycles, the accumulator used by the first instruction can be used again by subsequent instructions. According to one embodiment, the processor instruction is decoded in one clock cycle.

[0041] According to one embodiment, the index is the architected accumulator register index of the accumulator of the MAC unit. This can save processing resources because the same index is used to index both the accumulator and the MAC unit including the accumulator. This is contrary to another implementation that requires separate indexing of the MAC unit and the accumulator.

[0042] According to one embodiment, the processor unit further includes a dispatch and / or issue unit. The dispatch and / or issue unit is configured to process multiple processor instructions, select MAC units using an index, and send the processor instructions to the selected MAC units for performing a set of MAC operations. This can achieve seamless integration of the subject matter in existing systems with minimal changes to existing dispatch and / or issue units.

[0043] According to one embodiment, each processor instruction includes an operand that indicates the accumulator as both the source and target register of the instruction and indicates additional registers of another register file, which include source data to be multiplied and accumulated. The source data includes numbers. Using the accumulator as both the source and target register enables saving resources for data access. This is contrary to a MAC unit that uses two separate accumulators (one for writing and one for reading data), which can introduce additional latency and additional source-target dependency tracking logic. Due to the reduced connectivity in a processor unit with a single accumulator (e.g., by appropriately placing the single accumulator near the execution unit), the single accumulator can be accessed many times faster than accessing separate accumulators.

[0044] According to one embodiment, the MAC unit is part of the dispatch and / or issue unit. This can save chip area and power compared to a separate implementation of the MAC unit. For example, in cases where the MAC units are implemented as separate components of the dispatch and / or issue unit, they can occupy more space and consume additional power.

[0045] According to one embodiment, the dispatch and / or issue unit is configured to dispatch multiple processor instructions according to a single-threaded ("ST") mode such that the MAC units receive single-threaded processor instructions.

[0046] For example, the processor unit can operate in the ST mode such that only one thread of MAC operations can be executed or processed at a time.

[0047] According to one embodiment, the dispatch and / or issue unit is configured to dispatch the multiple processor instructions according to a simultaneous multithreading two-way ("SMT2") mode such that the MAC units receive processor instructions of either of the two threads.

[0048] According to one embodiment, the dispatch and / or issue unit is configured to dispatch the multiple processor instructions according to a simultaneous multithreading four-way ("SMT4") mode such that each of the MAC units receives processor instructions from two corresponding threads.

[0049] These embodiments can achieve seamless integration of the subject matter with existing thread-enabled systems.

[0050] According to one embodiment, the processor unit is configured to perform an additional set of MAC operations, where all the sets of MAC operations provide all the elements of an output matrix. The output matrix is the result of a matrix convolution of an input matrix. For example, the input matrix may represent the pixels of an image. A kernel can be used to perform a convolution with the pixel data stored in the input matrix. The kernel performs, for example, edge detection and operates on a sub-matrix of the input matrix that is the same size as the kernel. The output matrix is the result of the convolution of the sub-matrix that matches the kernel size at the input matrix positions.

[0051] Reference Figure 1 shows a block diagram depicting the structure of a processor system 101 according to one embodiment.

[0052] The processor system 101 can enable the storage of data for performing operations on the stored data. According to one embodiment, one or more levels of the cache 103 of the processor system 101 can be used to cache memory data in order to improve processor performance. The cache 103 can include a cache memory that holds cache lines of memory data that may be used. For example, a typical cache line can include 64, 128, or 256 bytes of memory data. According to one embodiment, the cache 103 can be configured to cache data from a higher-level storage device such as the main memory storage device 105.

[0053] According to one embodiment, the processor system 101 can further include a register file 119 that includes registers 120a-n. The registers 120a-n can include, for example, general-purpose registers, each register including a specific number of bits for storing data items processed by instructions executed in the processor system 101.

[0054] According to one embodiment, instructions can be provided by a compiler. For example, the source code of a program can be compiled into a series of machine-executable instructions defined in an instruction set architecture (“ISA”) associated with the processor system 101. The ISA can include at least one processor instruction defined according to at least one embodiment of the present disclosure. The instructions of the ISA can be provided to process data stored in the memory 105 and / or the registers 120a-n of the register file 119 of the processor system 101. According to one embodiment, when the processor system 101 begins to execute the executable instructions, these machine-executable instructions can be placed to be executed sequentially.

[0055] According to one embodiment, the instruction fetch / decode unit 109 may be used to fetch placed instructions. For example, the instruction fetch / decode unit 109 may fetch the next sequential instruction, the target instruction of a branch fetch instruction, or the first instruction of a program after a context switch. The fetched instructions may be decoded by the instruction fetch / decode unit 109.

[0056] According to one embodiment, the decoded instructions may be passed to the dispatch / issue unit 111. The dispatch / issue unit 111 may deposit the instructions in one or more issue queues 112, where the instructions may wait for their source operands and the appropriate MAC units 113 of the processor system 101 to become available. For example, each of the MAC units 113 in the MAC units 113 may be associated with an issue queue 112 such that the instructions to be executed by the MAC unit 113 may be queued in the issue queue 112 associated with the MAC unit 113. The dispatch / issue unit 111 may deposit the instructions in the issue queue 112 based on the index of the MAC unit 113 assigned to the issue queue. This index may be part of the instruction. That is, by reading the index from the instruction, the dispatch / issue unit 111 may know (e.g., determine) which MAC unit 113 may execute the instruction. Each of the MAC units 113 in the MAC units 113 may be configured to execute a corresponding type of instruction that may not be executed by other MAC units 113. In one embodiment, the type of instruction may be defined by a register associated with the instruction.

[0057] In a conventional method, each execution unit may be implemented to execute each instruction (e.g., any instruction may go to any execution unit). However, compared with the operation of the present disclosure, the conventional method may be more expensive in terms of processing resources.

[0058] According to one embodiment, each issue queue 112 may include window logic, which may be responsible for monitoring dependencies between instructions in the queue and issuing instructions to the corresponding MAC units 113. The window logic may include wake-up logic and selection logic. The wake-up logic may be responsible for invoking instructions waiting in the issue queue 112 for the source operands to become available. Once all the source operands of an instruction are available, the instruction may be marked ready for execution. The selection logic may be responsible for selecting instructions for execution from the pool of ready instructions. An instruction may be ready if all its source operands are available. Then, the load / store unit 117 may be used to load the operand values of the instruction from the memory 105 and / or registers.

[0059] The MAC unit 113 can generally receive information about an instruction from the dispatch / issue unit 111 and can perform an operation on an operand according to the operation code of the instruction. According to the present disclosure, the operand is provided to the MAC unit 113 from a register. The execution result can be stored in the memory 105 and / or the register 119 when stored. According to one embodiment, each MAC unit 113 in the MAC unit 113 can include at least one multiplier and at least one adder. If the MAC unit 113 includes more than one multiplier, each multiplier can be associated with a corresponding accumulator element of the accumulator of the MAC unit 113. Each multiplier of the MAC unit 113 can be configured to perform the multiplication of two numbers, and the adder can be configured to add the product to the content of the accumulator associated with the multiplier or the content of the accumulator element associated with the multiplier. The MAC unit 113 can be configured to perform a MAC operation in at least one clock cycle. In one example, the MAC unit 113 can include X multipliers, and the X multipliers can enable the MAC unit 113 to perform X MAC operations in at least one clock cycle.

[0060] According to one embodiment, the program counter (instruction counter) 107 can keep track of the address of the current instruction to be executed. For example, the program counter 107 in a processor such as (z / Architecture and all IBM-based trademarks and logos are trademarks or registered trademarks of International Business Machines Corporation and / or its subsidiaries) can include 64 bits and can be truncated to 31 or 24 bits to support previous addressing limitations. The program counter 107 can generally be included in the program status word ("PSW") of a computer so that it persists during a context switch. In one embodiment, the program counter can be incremented by an amount equal to the number of bytes of the current instruction.

[0061] The processor system 101 can be configured to perform pipelined execution of instructions. For example, each MAC unit 113 of the processor system 101 can use a four-cycle latency pipelined execution, so that each instruction can take four clock cycles in the MAC unit 113 to produce the result of a MAC operation. To this end, the execution of an instruction at the MAC unit 113 can be decomposed into four processes, one of the four processes can include a multiplication process, and another one of the four processes can include an accumulation process of the MAC unit.

[0062] According to one embodiment, the processor system 101 may be configured to operate in ST mode, SMT2 mode, or SMT4 mode. In ST mode, MAC operations from one thread may be executed or processed by the MAC unit 113 at a time. For example, in ST mode, each of the MAC units 113 may be configured such that the MAC unit 113 receives instructions from a specific thread (e.g., T0). In SMT2 mode, the MAC unit 113 may receive instructions from either of the two threads. For example, in SMT2 mode, each of the MAC units 113 may be configured such that the MAC unit 113 receives instructions from thread T0 and / or thread T1. In SMT4 mode, each MAC unit 113 among the MAC units 113 may receive processor instructions from all four threads (e.g., T0, T1, T2, and T3), or the MAC unit 113 may operate in a split mode to receive two threads. For example, in the split mode, if the processor system 101 includes two MAC units 113, one MAC unit 113 may be configured to process instructions from thread T0 and / or thread T2, and the other MAC unit 113 may be configured to process instructions from thread T1 and / or thread T3.

[0063] Thus, the processor system 101 may use the MAC unit 113 to process instructions from one or more programs. For example, the source code of a program may implement one or more MAC operations. A MAC operation may include multiplying two numbers and adding the result of the multiplication to an accumulated value. At least one MAC operation may be performed by the MAC unit 113 by executing the corresponding processor instructions of the ISA.

[0064] Now referring to Figure 2A , a block diagram is described that shows an exemplary matrix operation illustrating a MAC operation according to at least one embodiment.

[0065] According to one embodiment, Figure 2A the matrix operation may be referred to as a matrix multiply and accumulate ("MMA") operation. The matrix operation may multiply the input matrix 201 by the input matrix 203, and the accumulated result may include the resulting matrix 205. If matrix 201 includes an M-by-K matrix and matrix 203 includes a K-by-N matrix, then the resulting matrix 205 may include an M-by-N matrix. Thus, each element of the resulting matrix 205 may be obtained through K MAC operations. As Figure 2A shown, the input matrix 201 may include a 4x4 matrix, and the input matrix 203 may include a 4x4 matrix. According to one embodiment, the matrix operation may not be limited to Figure 2A the dimensions provided as examples in

[0066] One or more accumulators may be used to compute MAC operations and store the elements of the resulting matrix 205. The accumulator may have an accumulator size indicative of the size of the accumulator, e.g., 512 bits. The accumulator may include a plurality of accumulator elements or fields. The accumulator elements may have an accumulator element size that may be less than the accumulator size, e.g., the accumulator element size may be 32 bits. Each accumulator element of the accumulator may have or occupy a corresponding number of bits of the accumulator, e.g., the first accumulator element may occupy bits 0 to 31 of the accumulator, the second accumulator element may occupy bits 32 to 63 and the sixteenth accumulator element may occupy bits 480 to 511. In one embodiment, the accumulator element size may be defined as the size of the elements of the resulting matrix 205. This may be advantageous because the accumulator may be configured to include as many accumulator elements as there are elements in the resulting matrix 205. This may enable all the elements of the resulting matrix 205 to be stored in one accumulator.

[0067] Now referring to Figure 2B , a block diagram of an accumulator for computing elements of matrix operations is depicted in accordance with at least one embodiment. Further reference is made to Figure 2C , which describes a block diagram showing an exemplary MAC unit in accordance with at least one embodiment.

[0068] According to one embodiment, Figures 2B - 2C indicates that one MAC unit having one accumulator 223, one adder 222 and 16 multipliers 221 may be used to compute the elements of the resulting matrix 205. As Figure 2B shown, each element of the resulting matrix 205 may be stored in a corresponding accumulator element of a single accumulator ACC(0). The accumulator elements of the accumulator ACC(0) may be referred to as ACC Figure 2B (0) in j , where j = 1,..., 16. The element C11 of the resulting matrix 205 may be stored in the accumulator element ACC 1 (0) having bits 0 to 31 of the accumulator ACC(0), C21 may be stored in the accumulator element ACC 2 (0) having bits 32 to 63 of the accumulator ACC(0), C31 may be stored in the accumulator element ACC 3 (0) having bits 64 to 95 of the accumulator ACC(0), C41 may be stored in the accumulator element ACC 4 (0) having bits 96 to 127 of the accumulator ACC(0), and so on. Thus, the storage of 16 by 32-bit elements may result in the full width of 512 bits of the accumulator 223 being used.

[0069] Prior to computing the elements of the resulting matrix 205, each accumulator element ACC of the accumulator ACC(0) j(0) can be initialized (or stored) with an initial value. This initial value can be, for example, zero. In another example, the element ACC j (0) can be initialized by other values (such as pre-computed parts of matrix elements) (e.g., in order to obtain C11, the accumulator element ACC 1 (0) can be initialized with the value A11*B11). In another example, the initialization can be performed by a first instruction different from the MAC operation instruction, so that the multiplication result can be stored in the accumulator element of the accumulator ACC(0) without using the accumulator ACC(0) as an input. Figure 2B The example in uses the K dimension of matrix 201 as the outermost loop of the programming loop for calculating the outer product. The MMA operation can load the columns of matrix 201 and the rows of matrix 203 from another register file once as operands to calculate their outer product, and accumulate the result of the outer product as an element in the resulting matrix 205. After that, the columns of matrix 201 and the rows of matrix 203 can no longer be used.

[0070] For example, in order to obtain each of the 16 elements C11 to C44 of the resulting matrix 205, four MAC operations can be performed using the corresponding accumulator elements. As Figure 2B shown, in order to obtain the element C11, the MAC operations 210.1, 211.1, 212.1, and 213.1 can use the content of the accumulator element ACC 1 (0) to perform.

[0071] Given the structure of the resulting matrix and the nature of the MMA operation, the MAC unit can be configured to perform the MMA operation in an optimal manner. For example, the MMA operation can be split into a set of MAC operations such that each set of MAC operations can be executed by the MAC unit in one clock cycle. According to Figure 2A the example and as Figure 2B shown, the matrix operation can involve four sets of MAC operations 210.1-16, 211.1-16, 212.1-16, and 213.1-16, and each set of MAC operations can be performed by Figure 2CThe MAC unit processes in one clock cycle. Each MAC operation involves a multiplication operation and adding the result of the multiplication operation to the content of the corresponding accumulator element. Execution of each set of four MAC operations can be performed by issuing a corresponding instruction (such as, for example, an integer-based GER instruction). The accumulator element used by each MAC operation in the set of MAC operations can be indicated in the GER instruction. For example, the accumulator element used by each MAC operation in the set of MAC operations can be determined by the GER instruction type (e.g., the GER instruction can have different types, where each type can be used for a different number of MAC operations). The GER instruction name determines the operands and the number of accumulator elements and data types in the 512-bit accumulator.

[0072] In the first MAC operation of the set of 16 MAC operations, the product A11*B11 can be executed, and the result of the product can be added to the first accumulator element ACC of bits 0 to 31 of the accumulator ACC(0). 1 (0), which can be zero. Thus, after the first MAC operation, the first accumulator element ACC 1 (0) can contain the product A11*B11. In the second MAC operation of the set of 16 MAC operations, the product A11*B21 is executed, and the result of the product is added to the content of the second accumulator element ACC 2 (0) of the accumulator ACC(0), which can be zero. Thus, after executing the set of 16 MAC operations 210.1 - 210.16, each element ACC j (0) of the accumulator ACC(0) can include the intermediate value of the corresponding element of the resulting matrix as Figure 2B shown. After completing the set of 16 MAC operations 210.1 - 210.16, the MAC unit can execute another set of 16 MAC operations 211.1 - 211.16. This repetition can be performed until all sets of MAC operations have been executed. Figure 2B Shows the evolution of the content of each accumulator element ACC j (0) of the accumulator ACC(0) obtained from the non-pipelined execution of the set of MAC operations.

[0073] However, for performing multiple matrix operations (e.g., similar to Figure 2A matrix operations), pipelined execution of MAC operations can be advantageous. For example, in the case of four matrix operations, where each matrix operation includes four sets of MAC operations as described in the Figure 2A matrix operation, the execution of the set of 16 MAC operations can be carried out as follows.

[0074] In the case of four-cycle pipelined execution, each MAC operation can be executed in four steps. Thus, each set of 16 MAC operations can be executed in four clock cycles. For example, the first step of each MAC operation in a set of MAC operations can be executed by the MAC unit in one same clock cycle (e.g., all the first steps in a set of MAC operations can be executed in one same clock cycle). The second step of each MAC operation in a set of MAC operations can be executed by the MAC unit in another same clock cycle. The third step of each MAC operation in a set of MAC operations can be executed by the MAC unit in another same clock cycle. The fourth step of each MAC operation in a set of MAC operations can be executed by the MAC unit in another same clock cycle. Pipelined execution enables different steps of different sets of MAC operations to be executed in the same clock cycle.

[0075] Elements of each of the four resulting matrices of the four matrix operations are stored in accumulators ACC(0), ACC(1), ACC(2), and ACC(3), respectively.

[0076] Figures 2A to 2C The examples provided show MAC calculations of 4×32-bit elements as input sources: SRC1 and SRC2. However, it is contemplated that other element widths (such as, for example, 8x16 bits or 16x8 bits) can be handled in a similar manner by multiplying and adding pairs of 16 bits in a 32-bit wide accumulator element or performing MAC operations on four pairs of 8 bits to calculate a 32-bit wide accumulator field during four-cycle execution. In a similar manner, the accumulator element size can be less than or greater than 32 bits, as well as the number of elements stored in the ACC register. Figure 2C Details of a 4x4 implementation are shown, where 4x32-bit operand A (e.g., representing a column) and 4x32-bit operand B (e.g., representing a row) are inputs, and a 512-bit accumulator is shown at the output storing 16 32-bit results. Figure 2B The operation of an external multiplication calculation algorithm is shown. However, matrix operations are not limited to these outer product calculation algorithms. Other algorithms can be used, including inner product or dot product algorithms.

[0077] Now referring to Figure 3 , a block diagram showing a MAC unit according to at least one embodiment is described. According to one embodiment, Figure 3 the MAC unit of

[0078] According to one embodiment, the MAC unit 113 may include an execution unit 301 and a register file 303. The execution unit 301 reads accumulator data (ACC(i) data) from the register file 303 and writes the accumulator data to the register file 303. The register file 303 may include one or more accumulators. In one embodiment, each accumulator of the register file 303 may include an architected accumulator register index i such that each accumulator may be referred to as ACC(i). The index may be an integer, which may include even or odd numbers. The architected accumulator ACC(i) may be renamed such that the register file entry storing the accumulator ACC(i) is different from the register file entry number. The logic of the dispatch / issue unit 111 may track the register file entry number that contains the state of the accumulator ACC(i).

[0079] The register file 303 may include a 1W / 1R ported register file. The register file 303 may be advantageous because it may require less wiring, less area, and less power requirements compared to, for example, a 2W / 2R register file.

[0080] The MAC unit 113 may be configured to receive processor instructions from respective issue queues of the dispatch / issue unit 111 for performing MAC operations. The processor instructions may be named, for example, "GER" and may be defined as follows: GER ACC(i) ← ACC(i), vector scalar register ("VSR")(j), VSR(k). The processor instruction GER may include operands that indicate the accumulator ACC(i) as the source and destination register of the processor instruction and indicate another source register VSR(j), VSR(k) of the register file 119. The source registers VSR(j), VSR(k) may include numbers to be multiplied. As Figure 3 shown, the execution unit 301 may read the values / numbers 304 and 305 to be multiplied from the register file 119 and read the content (referred to as SRC0) of the accumulator ACC(i) from the register file 303 to perform a MAC operation. The result of the MAC operation (referred to as TGT) may be stored in the accumulator ACC(i). Thus, each accumulator ACC(i) of the register file 303 may enable the MAC unit 113 to perform a corresponding set of one or more MAC operations such that the result values of the set of MAC operations are accumulated in the accumulator ACC(i).

[0081] According to Figure 2A an example, the MAC unit 113 may be configured to use the accumulator ACC(0) to perform four sets of 16 MAC operations to obtain the elements C11...C44 of the resulting matrix 205. To this end, the execution unit 301 may include multiple multipliers, and the accumulator ACC(0) may include multiple elements, as referred to in Figure 2C described.

[0082] To compute the overall resulting matrix 205, four processor instruction streams can be received at the MAC unit, with each processor instruction performing a set of 16 MAC operations to obtain C11…C44. Each processor instruction of the stream references the accumulator ACC(0) of the MAC unit, and which accumulator element of the accumulator ACC(0) receives which result of the multiplication. For each processor instruction of the stream, the MAC unit can perform 16 MAC operations and accumulate the results into the corresponding content of the accumulator element referenced in the processor instruction. For example, among other products, a processor instruction can compute the product A11*B11 and add the product to the corresponding accumulator element ACC1(0), followed by another instruction that computes at least A21*B12 and adds the product to the corresponding accumulator, etc.

[0083] The execution steps of each MAC operation can be performed by the MAC unit 113 in one clock cycle or in multiple clock cycles by means of a pipelined implementation.

[0084] Now referring to Figure 4 , a block diagram is described showing a processor unit 400 according to at least one embodiment.

[0085] The processor unit 400 may include two MAC units 413A and 413B. The MAC unit 413A may include an execution unit 401A and a register file 403A. The execution unit 401A may read data from the register file 403A and may write data into the register file 403A. The register file 403A may include one or more accumulators. Each accumulator of the register file 403A may include an architected accumulator register index that is odd, such that each accumulator may be referred to as ACC(odd). The index odd may be an odd number. The MAC unit 413B may include an execution unit 401B and a register file 403B. The execution unit 401B may read data from the register file 403B and may write data into the register file 403B. The register file 403B may include one or more accumulators. Each accumulator of the register file 403B may include an architected accumulator register index that is even, such that each accumulator may be referred to as ACC(even). The index even may be an even number. Each of the register files 403A and 403B may be a 1W / 1R ported register file. Each of the MAC units 413A-B may be configured to operate as described for the MAC unit 113 with reference to Figure 3 as described.

[0086] In one embodiment, the processor unit 400 may further include a register file 419, and the register file 419 may provide numbers to be multiplied with each of the MAC units 413A and 413B.

[0087] According to one embodiment, each of the MAC units may be associated with a corresponding index. For example, the MAC unit 413A may be associated with an odd index, and the MAC unit 413B may be associated with an even index. Each MAC unit may receive its own instructions from a corresponding issue queue (e.g., the dispatch and / or issue unit that issues instructions to the processor unit 400 may include two issue queues, one issue queue for odd-index instructions and another issue queue for even-index instructions). In another embodiment, the dispatch and / or issue unit may include a single issue queue having at least two issue ports. In this embodiment, one issue port may be configured to issue even-index instructions to the even MAC unit 413B, and the other issue port may be configured to issue odd-index instructions to the odd MAC unit 413A. However, the present disclosure is not limited to these implementations.

[0088] For example, the MAC unit 413A includes four accumulators ACC(1), ACC(3), ACC(5), and ACC(7), and the MAC unit 413B includes four accumulators ACC(0), ACC(2), ACC(4), and ACC(6). Each of the MAC units 413A-B may receive corresponding processor instructions as described Figure 3 above. The processor instructions may reference the index corresponding to the MAC unit that receives the instructions. Thus, the processor unit 400 may execute two processor instructions in parallel through the MAC units 413A-B.

[0089] The processor unit 400 may be configured to perform pipelined execution of instructions. For example, assume that eight processor instructions (e.g., as an instruction stream, GER(0), GER(2), GER(3), GER(1), GER(5), GER(6), GER(7), and GER(4), where see Figure 4The GER(i) uses the accumulator ACC(i) as the source SRC0 and the target TGT, and the latency for executing the GER(i) instruction is four cycles). Each instruction GER has an even or odd index. In this case, the instructions GER(0), GER(2), GER(4), and GER(6) can be in the issue queue associated with the MAC unit 413B, and the instructions GER(1), GER(3), GER(5), and GER(7) can be in the issue queue associated with the MAC unit 413A. If there is a single accumulator that can include only one element, then GER(i) can enable one of the four steps of performing one MAC operation. If there are m accumulator elements in one accumulator that can include m elements, then GER(i) can enable one same step of each of the m MAC operations of performing m MAC operations. After the latency of the four pipeline execution examples, the instruction stream can be executed cycle by cycle as follows:

[0090] Cycle c: GER(0), GER(3)

[0091] c + 1: GER(2), GER(1)

[0092] c + 2: GER(4), GER(5)

[0093] c + 3: GER(6), GER(7)

[0094] c + 4: GER(0), GER(3)…

[0095] During clock cycle c, the instructions GER(0) and GER(3) are issued to the MAC units 413B and 413A and are then executed by the MAC units 413B and 413A respectively. In the next cycle c + 1, the instructions GER(2) and GER(1) are issued to the MAC units 413B and 413A and are then executed by the MAC units 413B and 413A respectively. In the next cycle c + 2, the instructions GER(4) and GER(5) are issued to the MAC units 413B and 413A and are then executed by the MAC units 413B and 413A respectively. In the next cycle c + 3, the instructions GER(6) and GER(7) are issued to be executed by the MAC units 413B and 413A respectively. The processor unit 400 can achieve a throughput comparable to or better than existing systems. In cycle c + 4, the execution of the GER(0) and GER(3) instructions is completed, so new GER(0) and GER(3) instructions can be issued in cycle c + 4 for the external multiplication calculation of the accumulators ACC(0) and ACC(3). GER(0) in cycle c can execute the first step of the MAC operation, and GER(0) in cycle c + 4 can execute the second step of the same MAC operation.

[0096] In another example, the instruction stream may only include instructions GER(0), GER(2), GER(4), and GER(6) with even indices. That is, only one issue queue includes instructions to be executed. In this case, only one MAC unit can be used to execute the following instruction stream:

[0097] Cycle cc: GER(0), none

[0098] cc + 1: GER(2), none

[0099] cc + 2: GER(4), none

[0100] cc + 3: GER(6), none

[0101] During clock cycle cc, the instruction GER(0) is issued to MAC unit 413B and then executed by MAC unit 413B, while MAC unit 413A does not execute any instructions. In the next cycle cc + 1, the instruction GER(2) is issued to MAC unit 413B and then executed by MAC unit 413B, while MAC unit 413A does not execute any instructions. In the next cycle cc + 2, the instruction GER(6) is issued to MAC unit 413B and then executed by MAC unit 413B, while MAC unit 413A does not execute any instructions. In the next cycle cc + 3, the instruction GER(6) is issued to MAC unit 413B and then executed by MAC unit 413B, while MAC unit 413A does not execute any instructions. Not using execution unit 410A may not affect the overall throughput because there are 4 ACCs in use. If it takes 4 cycles of latency for an instruction to complete the ACC result calculation, the overall throughput may not be higher than 4 instructions.

[0102] Now referring to Figure 5A , a block diagram showing the dispatch logic of the processor unit 500 according to at least one embodiment is described. Also referring to Figure 5B , a block diagram showing the issue logic of the processor unit 500 according to at least one embodiment is described. The processor unit 500 may include a dispatch / issue unit 511 and MAC units 413A and 413B, as described in Figure 4 .

[0103] As Figure 5AAs shown, the dispatch / issue unit 511 may be configured to receive fetched and decoded instructions. The received instructions may reference an accumulator ACC(i) having a given index i. The dispatch and / or issue unit 511 includes logic circuitry 514. The logic circuitry 514 may be configured to determine, based on the index i, which of the issue queues ("ISQs") 412A and 412B of the dispatch / issue unit 511 will receive the instruction. Alternatively, as Figure 5B shown, the processor unit 500 may include a common issue queue port for the logic circuitry 514, and the combined issue queue 412A-B issue logic may be configured to issue individual instructions to the even or odd ports of the MAC units 413A-B based on the index i of the accumulator ACC(i) in use.

[0104] Now referring to Figure 6A , an operation flow diagram is described that illustrates an exemplary process for performing a set of one or more MAC operations according to at least one embodiment. Also referring to Figures 6B - 6C , a block diagram of a MAC unit associated with the Figure 6A MAC operations according to at least one embodiment is depicted.

[0105] To simplify the following description, Figures 6A - 6C the set of MAC operations in

[0106] may include (but is not limited to) MAC operations for determining a matrix element equal to A11*B11+A21*B12.

[0107] At 601, the accumulator is initialized. According to one embodiment, the accumulator of the MAC unit 613 may be initialized to zero. The accumulator may be part of a 1W / 1R register file.

[0108] Then at 602, an instruction is received. According to one embodiment, the first instruction of the stream may be received at 602. The first instruction may reference two VSR registers as source registers. The first instruction may further reference the accumulator as both a source register and a destination register of the first instruction. The first instruction may be defined, for example, using the GER instruction as: GERACC(i)←ACC(i),VSR(j),VSR(k). As Figure 6B shown, the VSR registers VSR(j) and VSR(k) include the values A11 and B11 to be multiplied, and the accumulator stores the initial value. The values A11 and B11 may be stored, for example, in the VSR registers of the register file 119 by the load / store unit 117 for enabling the execution of the first instruction.

[0109] Then, at 603, these values are multiplied. According to one embodiment, values A11 and B11 can be received at the multiplier of MAC unit 613. The multiplier can multiply values A11 and B11 at 603 and provide the multiplied result A11*B11 to the adder of MAC unit 613.

[0110] Then, at 604, the result of the multiplication is added to the accumulator. According to one implementation, the adder can read the current content of accumulator ACC, as Figure 6B shown, and this current content can be zero. In step 604, the adder adds the content of accumulator ACC to the result of multiplying A11 and B11.

[0111] Then, at 605, the result is written. According to one embodiment, the added result (e.g., A11*B11) can be written to the accumulator at 605. This can cause the first instruction to be executed and completed.

[0112] The next instruction of the stream can be processed by repeating 602 to 605 for the second instruction of the stream (as described above). Figure 6C The state of MAC unit 613 for executing the second instruction is shown. VSR registers VSR(j) and VSR(k) can include values A21 and B12 to be multiplied, and the accumulator can store the value A11*B11. The second instruction can, for example, have the same syntax as the first instruction. 602 to 605 can be repeated until all instructions of the stream are processed.

[0113] Aspects of the present invention will now be described with reference to the flowchart and / or block diagram of a method, apparatus (system), and computer program product according to embodiments of the present invention. It should be understood that each block of the flowchart and / or block diagram, and the combinations of blocks in the flowchart and / or block diagram, can be implemented by computer-readable program instructions.

[0114] The present invention can be a system, method, and / or computer program product with any possible degree of integration of technical details. The computer program product can include a computer-readable storage medium (one or more media) having computer-readable program instructions thereon for causing a processor to execute aspects of the present invention.

[0115] A computer-readable storage medium can be a tangible device that retains and stores instructions for use by an instruction execution device. The computer-readable storage medium can be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punched card or a raised structure in a groove having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable) or an electrical signal transmitted through a wire.

[0116] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or an external storage device. The network can include a copper transmission cable, an optical transmission fiber, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0117] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages (such as Smalltalk, C++, etc.) and procedural programming languages (such as the "C" programming language, the Python programming language, or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., using an Internet service provider through the Internet). In some embodiments, an electronic circuit, including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), may execute the computer-readable program instructions by using the state information of the computer-readable program instructions to personalize the electronic circuit, so as to perform various aspects of the present invention.

[0118] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing device create a means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium, which instructions cause a computer, a programmable data processing device, and / or other devices to work in a particular manner, so that the computer-readable storage medium storing the instructions includes a manufacture containing instructions for implementing the aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0119] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device, such that a series of operation steps are executed on the computer, other programmable device, or other device to produce a computer-implemented process, such that the instructions executed on the computer, other programmable device, or other device implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0120] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of the possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be completed as one step, executed simultaneously, substantially simultaneously, in partial or complete temporal overlap, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A processor unit for multiplication and accumulation (MAC) operations, the processor unit comprising: A plurality of MAC units including a first MAC unit and a second MAC unit, for performing respective subsets of MAC operations of a set of MAC operations, each MAC unit of the first and second MAC units including a respective execution unit and a respective one-write-one-read (1W / 1R) ported register file independently connected to the respective execution unit, the respective 1W / 1R ported register file having at least one respective accumulator, wherein at least one respective accumulator of the first MAC unit includes an even-architectured accumulator register index that only contains even index numbers, and at least one respective accumulator of the second MAC unit includes an odd-architectured accumulator register index that only contains odd index numbers, wherein each MAC unit is configured to perform the respective subset of MAC operations in the set of MAC operations by executing processor instructions that reference corresponding index numbers associated with the MAC unit and the at least one respective accumulator; And Another register file, wherein the respective execution unit of each MAC unit is configured to perform the respective subset of MAC operations in the set of MAC operations by calculating the product of a set of values received from the another register file and adding the calculated product to the content of at least one respective accumulator of the MAC unit, wherein each MAC unit is configured to perform the respective subset of MAC operations in a single clock cycle.

2. The processor unit according to claim 1, wherein the at least one respective accumulator includes a respective accumulator element, and the calculated product is added to the content of the respective accumulator element, wherein each MAC unit is configured to perform the respective subset of MAC operations in the set of MAC operations using the respective accumulator element of the at least one respective accumulator.

3. The processor unit according to claim 1, further comprising a dispatch / issue unit configured to process a plurality of processor instructions, select a MAC unit from the first and second MAC units using a corresponding index number, and send a respective set of processor instructions to the selected MAC unit for performing the set of MAC operations.

4. The processor unit according to claim 3, wherein the respective set of processor instructions further includes at least one operand that indicates the at least one respective accumulator as a source and target register of the respective set of processor instructions, and indicates at least one additional register of the another register file as including a set of numbers.

5. The processor unit according to claim 3, wherein the dispatch / issue unit is also associated with the selected MAC unit.

6. The processor unit according to claim 3, wherein the dispatch / issue unit is configured to dispatch the plurality of processor instructions according to a single-thread (ST) mode such that the selected MAC unit receives a respective set of processor instructions from a single thread.

7. The processor unit according to claim 3, wherein the dispatch / issue unit is configured to dispatch the plurality of processor instructions according to a simultaneous multithreading SMT2 mode such that the selected MAC unit receives the corresponding set of processor instructions from any one of two threads.

8. The processor unit according to claim 3, wherein the dispatch / issue unit is configured to dispatch the plurality of processor instructions according to a simultaneous multithreading SMT4 mode such that each of the first MAC unit and the second MAC unit receives the corresponding set of processor instructions from two corresponding threads.

9. The processor unit according to claim 1, wherein each MAC unit further comprises at least one multiplier for calculating the product and at least one adder for performing addition of the calculated product.

10. The processor unit according to claim 1, configured to perform an additional set of MAC operations, wherein all sets of MAC operations provide all elements of an output matrix that is a result of matrix convolution of an input matrix.

11. A method for performing multiply-accumulate MAC operations, comprising: selecting a MAC unit from a first MAC unit and a second MAC unit for executing the processor instruction based on a corresponding index number associated with the MAC unit referenced in the processor instruction, wherein each of the first and second MAC units includes a corresponding execution unit and a corresponding one-write-one-read 1W / 1R ported register file independently connected to the corresponding execution unit, the corresponding 1W / 1R ported register file having at least one corresponding accumulator, wherein at least one corresponding accumulator of the first MAC unit includes an even-architectured accumulator register index containing only even index numbers, and at least one corresponding accumulator of the second MAC unit includes an odd-architectured accumulator register index containing only odd index numbers; receiving the processor instruction at the corresponding execution unit of the selected MAC unit, wherein the processor instruction includes a set of values from a vector-scalar register file, and wherein the corresponding execution unit includes a multiplier and an adder; calculating a product of the set of values from the vector-scalar register file using the multiplier of the corresponding execution unit; reading current contents of at least one corresponding accumulator of the selected MAC unit; calculating a sum of the read current contents of the at least one corresponding accumulator and the calculated product of the set of values from the vector-scalar register file using the adder of the corresponding execution unit; and writing the calculated sum to the at least one corresponding accumulator of the selected MAC unit.

12. A computer program product for performing multiply-accumulate MAC operations, the computer program product comprising: one or more computer-readable storage media and program instructions jointly stored on the one or more computer-readable storage media, the program instructions comprising: Program instructions for selecting one of a first MAC unit and a second MAC unit for executing the processor instruction based on a corresponding index number associated with a MAC unit referenced in the processor instruction, wherein each MAC unit of the first and second MAC units includes a respective execution unit and a respective one-write-one-read 1W / 1R ported register file independently connected to the respective execution unit, the respective 1W / 1R ported register file having at least one respective accumulator, wherein at least one respective accumulator of the first MAC unit includes an even-architectured accumulator register index containing only even index numbers, and at least one respective accumulator of the second MAC unit includes an odd-architectured accumulator register index containing only odd index numbers; Program instructions for receiving the processor instruction at the respective execution unit of the selected MAC unit, wherein the processor instruction contains a set of values from a vector-scalar register file, and wherein the respective execution unit includes a multiplier and an adder; Program instructions for calculating a product of the set of values from the vector-scalar register file using the multiplier of the respective execution unit; Program instructions for reading the current content of at least one respective accumulator of the selected MAC unit; Program instructions for calculating a sum of the read current content of the at least one respective accumulator and the calculated product of the set of values from the vector-scalar register file using the adder of the respective execution unit; and Program instructions for writing the calculated sum to the at least one respective accumulator of the selected MAC unit.

13. A processor unit for multiply-accumulate MAC operations, the processor unit comprising: A first MAC unit and a second MAC unit; Respective execution units for each of the first MAC unit and the second MAC unit; And Respective one-write-one-read 1W / 1R ported register files independently connected to the respective execution units, the respective 1W / 1R ported register files including at least one respective accumulator, wherein at least one respective accumulator of the first MAC unit includes an even-architectured accumulator register index containing only even index numbers, and at least one respective accumulator of the second MAC unit includes an odd-architectured accumulator register index containing only odd index numbers, wherein each MAC unit is configured to perform a MAC operation by executing a processor instruction referencing a corresponding index number associated with the MAC unit and the at least one respective accumulator, and wherein the respective execution unit of each MAC unit is configured to perform the MAC operation by calculating a product and adding the product to the content of at least one respective accumulator of the MAC unit.

14. The multiply-accumulate unit of claim 13, wherein the respective execution unit of each MAC unit is configured to continuously perform the plurality of MAC operations using the same accumulator for accumulating the products of each of the plurality of MAC operations.

15. The multiply-accumulate unit according to claim 13, wherein the at least one corresponding accumulator further comprises a plurality of accumulators, and each MAC unit is configured to perform a plurality of MAC operations in parallel using a corresponding accumulator among the plurality of accumulators.

16. The multiply-accumulate unit according to claim 13, further comprising: at least one multiplier for performing the calculation of the product; and at least one adder for performing the addition of the product.

17. The multiply-accumulate unit according to claim 13, wherein the at least one corresponding accumulator further comprises a plurality of accumulator elements, each MAC unit comprises a plurality of multipliers and adders, and each MAC unit is configured to perform a plurality of MAC operations in parallel using a corresponding accumulator element among the plurality of accumulator elements and a corresponding multiplier among the plurality of multipliers.

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