Display data processing method, device, display driving chip, and display device

Abstract

The present application relates to a display data processing method, apparatus, display driving chip, display device, and computer-readable storage medium, including: obtaining a display data stream of an image to be displayed and parsing it to obtain a first display timing signal and display data; performing data processing on the first display timing signal to obtain a second display timing signal; the vertical blanking time of the second display timing signal is less than the vertical blanking time of the first display timing signal; analyzing according to the first display timing signal and the second display timing signal to obtain data reading parameters; reading the display data according to the data reading parameters, and performing scaling processing on the read display data to obtain target display data, and by increasing the frame effective data time of each frame of display data, without changing the hardware architecture of the driving chip, the problem of display disorder or loss of display data caused by an increase in data volume when magnifying a low-resolution image to the fixed resolution of the display screen for display is solved.

Description

Technical Field

[0001] This application relates to the field of image display technology, and in particular, to a display data processing method, apparatus, display driver chip, display device, and computer-readable storage medium. Background Art

[0002] With the advent of the intelligent era, the popularity of smartphones or terminals is getting higher and higher. At the same time, in order to meet the needs of different user groups, the function of setting different display resolutions for video image display is required on a display screen with the same resolution. Young people with good eyesight may tend to increase the display resolution to display higher-definition images, while older people may need to enlarge the fonts and icons and set a low display resolution.

[0003] In order to display images with different resolutions on a display screen with the same resolution, the display driver chip of LCD (Liquid Crystal Display) / OLED (Organic Light-Emitting Diode) needs to support the picture scaling function to process the display data with different resolutions sent by the mobile phone into data adapted to the fixed resolution of the display screen. However, when enlarging a low-resolution image to the fixed resolution of the display screen for display, the amount of enlarged display data will increase significantly. When the amount of display data exceeds the performance limit of the display driver chip to process data in real-time synchronization, problems such as display disorder or loss of display data will occur. Summary of the Invention

[0004] Based on this, in view of the problem of display disorder or loss of display data caused by the increase in data volume when enlarging a low-resolution image to the fixed resolution of the display screen, it is necessary to provide a display data processing method, apparatus, display driver chip, display device, and computer-readable storage medium.

[0005] In a first aspect, this application provides a display data processing method, the method includes:

[0006] Obtain the display data stream of the image to be displayed, and parse the display data stream to obtain a first display timing signal and display data; wherein, the first display timing signal includes a vertical blanking time and a frame valid data time;

[0007] Perform data processing on the first display timing signal to obtain a second display timing signal; the vertical blanking time of the second display timing signal is less than the vertical blanking time of the first display timing signal;

[0008] Analyze based on the first display timing signal and the second display timing signal to obtain data reading parameters;

[0009] Read the display data according to the data reading parameters, and perform scaling processing on the read display data to obtain target display data.

[0010] In one embodiment, the first display timing signal includes a first vertical synchronization signal, a first horizontal synchronization signal, and a first display enable signal. The data processing of the first display timing signal to obtain a second display timing signal includes:

[0011] Analyze the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal;

[0012] Perform timing adjustment on the first display timing signal according to the vertical blanking time of the first display timing signal and a preset time parameter to obtain a second display timing signal.

[0013] In one embodiment, the performing timing adjustment on the first display timing signal according to the vertical blanking time of the first display timing signal and a preset time parameter to obtain a second display timing signal includes:

[0014] Perform timing adjustment on the first vertical synchronization signal according to the vertical blanking time of the first display timing signal to obtain a second vertical synchronization signal;

[0015] Perform timing adjustment on the first display enable signal according to the preset time parameter to obtain a second display enable signal;

[0016] Obtain the second display timing signal based on the second vertical synchronization signal and the second display enable signal.

[0017] In one embodiment, the frame valid data time includes a horizontal blanking time, and the data reading parameters include a first-line reading delay time and a reading time interval; the analyzing the first display timing signal and the second display timing signal to obtain data reading parameters includes:

[0018] Obtain the first-line reading delay time according to the difference between the first vertical synchronization signal of the first display timing signal and the second vertical synchronization signal of the second display timing signal;

[0019] Obtain the reading time interval according to the horizontal blanking time of the first display timing signal.

[0020] In one embodiment, the reading the display data according to the data reading parameters, and performing scaling processing on the read display data to obtain target display data includes:

[0021] Read the display data line by line according to the first-line reading delay time and the reading time interval;

[0022] Perform scaling processing on the read display data for each line to obtain the target display data.

[0023] In one embodiment, the above display data processing method further includes:

[0024] Display the image to be displayed according to the second display timing signal and the target display data.

[0025] In a second aspect, the present application also provides a display data processing device. The device includes:

[0026] A data acquisition module, configured to acquire a display data stream of an image to be displayed, and parse the display data stream to obtain a first display timing signal and display data; wherein, the first display timing signal includes a vertical blanking time and a frame valid data time;

[0027] A data processing module, configured to perform data processing on the first display timing signal to obtain a second display timing signal; the vertical blanking time of the second display timing signal is less than the vertical blanking time of the first display timing signal; and is further configured to analyze according to the first display timing signal and the second display timing signal to obtain data reading parameters;

[0028] A data scaling module, configured to read the display data according to the data reading parameters, and perform scaling processing on the read display data to obtain target display data.

[0029] In a third aspect, the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed, the steps of the above method are implemented.

[0030] In a fourth aspect, the present application also provides a display driving chip. The display driving chip includes a first-in first-out module, a data processing module, and a scaling module. The first-in first-out module is connected to the data processing module and the scaling module, and the data processing module is connected to the scaling module;

[0031] The first-in first-out module is configured to acquire a display data stream of an image to be displayed, and parse the display data stream to obtain a first display timing signal and display data, and send the first display timing signal to the data processing module; wherein, the first display timing signal includes a vertical blanking time and a frame valid data time;

[0032] The data processing module processes the first display timing signal to obtain a second display timing signal; the vertical blanking time of the second display timing signal is less than that of the first display timing signal; the data processing module then analyzes based on the first display timing signal and the second display timing signal to obtain data reading parameters and sends them to the scaling module;

[0033] The scaling module is configured to read the display data from the first-in first-out module according to the reading parameters, and perform scaling processing on the read display data to obtain target display data.

[0034] In a fifth aspect, the present application further provides a display device. The display device includes a display screen and the above-mentioned display driving chip, and the display driving chip is connected to the display screen.

[0035] After parsing the display data stream of the image to be displayed to obtain the first display timing signal and the display data, the above-mentioned display data processing method, device, display driving chip, display device and computer-readable storage medium reduce the vertical blanking time of the first display timing signal to obtain the second display timing signal, and then correspondingly generate reading parameters for reading the display data for scaling processing and outputting the target display data, which can increase the frame effective data time in each frame of display data. Without changing the hardware architecture of the display driving chip, it solves the problem of display disorder or loss of display data caused by the increase in data volume when magnifying a low-resolution image to the fixed resolution of the display screen for display. Description of the Drawings

[0036] Figure 1 It is an application environment diagram of the display data processing method in an embodiment;

[0037] Figure 2 It is a flowchart of the display data processing method in an embodiment;

[0038] Figure 3 It is a timing diagram of a frame of display timing signal in an embodiment;

[0039] Figure 4 It is a timing diagram of a row of display timing signal in an embodiment;

[0040] Figure 5 It is a flowchart of the second display timing signal acquisition step in an embodiment;

[0041] Figure 6 It is a flowchart of the second display timing signal acquisition step in another embodiment;

[0042] Figure 7Schematic flowchart of the read parameter acquisition step in an embodiment;

[0043] Figure 8 Schematic flowchart of the scaling process step for acquiring display data according to read parameters in an embodiment;

[0044] Figure 9 Block diagram of the structure of a display data processing device in an embodiment;

[0045] Figure 10 Block diagram of the structure of a display driving chip in an embodiment. Detailed implementation manners

[0046] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] The display data processing method provided by the embodiments of the present application can be applied to an application environment such as that of the terminal 10 with a settable display resolution as Figure 1 shown. Among them, the display device 102 of the terminal 10 is connected to the main controller 104 for communication, and obtains the display data stream of the image to be displayed from the main controller 104 for display. However, when the terminal 10 switches its display device 102 from a high display resolution to a low display resolution, in each frame of display data output by its main controller 104, due to the reduction in the amount of data, the vertical blanking time will increase and the frame effective data time will decrease. However, the display device 102 still needs to enlarge the low-resolution image to the fixed resolution of the display screen for display. Due to the enlargement process, the amount of display data will increase significantly. When the magnification exceeds a certain level and the amount of display data exceeds the performance limit of the display device 102 to synchronously process the display data output by the main controller 104 in real time, problems such as display disorder or loss of display data will occur.

[0048] Based on this, the present application provides a display data processing method. The display device 102 obtains the display data stream of the image to be displayed sent by the main controller 104, and parses the display data stream to obtain a first display timing signal and display data. The first display timing signal is composed of a vertical blanking time and a frame valid data time. The first display timing signal is processed to obtain a second display timing signal. The vertical blanking time of the second display timing signal is less than that of the first display timing signal. The data reading parameter is obtained by analyzing the first display timing signal and the second display timing signal. The display data is read according to the data reading parameter, and the read display data is scaled to obtain the target display data. Among them, the terminal 10 may be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things devices may be smart TVs and in-vehicle devices, etc. The portable wearable devices may be smart watches, smart bracelets, head-mounted devices, etc.

[0049] In one embodiment, as Figure 2 shown, a display data processing method is provided. Taking the method applied to the Figure 1 display device 102 in it as an example for illustration, it includes the following steps 202 to 208, where:

[0050] Step 202: Obtain the display data stream of the image to be displayed, and parse the display data stream to obtain a first display timing signal and display data. The first display timing signal includes a vertical blanking time and a frame valid data time.

[0051] The image to be displayed is the image that needs to be displayed in the display device of the terminal, and it can be picture or video data. The image to be displayed can be that the main controller of the terminal generates a display data stream, sends it to the display device for parsing to obtain a display timing signal and display data, and then displays it. Among them, as Figure 3 and Figure 4 shown, the image to be displayed is composed of frames of display data, and is controlled by frames of timing display signals to be displayed on the display screen. Each frame of display timing signal is composed of a vertical blanking time and a frame valid data time, and the frame valid data time in each frame of display timing signal is composed of a line valid data time and a horizontal blanking time.

[0052] The display data is the pixel point data corresponding to the image to be displayed on the display screen. Each pixel point data is composed of red, green, and blue (RGB) color components, and each color component is 8 bits, a total of 24-bit binary signals.

[0053] The display timing signal is a control signal for controlling the display of display data on the pixel points of the display screen, and may include a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a display enable signal DE, and may also include a pixel clock signal PCLK. The vertical synchronization signal VSYNC is used to indicate the end of the transmission of a frame of pixel point data. After each frame of pixel point data is transmitted, the level of the vertical synchronization signal VSYNC jumps. The horizontal synchronization signal HSYNC is used to indicate the end of the transmission of a row of pixel point data. After each row of pixel point data is transmitted, the level of the horizontal synchronization signal HSYNC jumps. The display enable signal DE is used to indicate the validity of the data. When the DE signal is at a high level, the pixel point data input by RGB is valid. The pixel clock signal PCLK is a synchronous clock. Driven by this synchronous clock, one RGB pixel point data is transmitted per clock.

[0054] Specifically, after receiving the display data stream of the image to be displayed when the terminal switches from a high display resolution to a low display resolution, the main controller inputs the display data stream of the image to be displayed into the first-in first-out (FIFO) module of the display device. After the FIFO module obtains the display data stream of the image to be displayed, it first decodes the display data stream to obtain a first display timing signal and display data. And the display data is stored in the cache space of the FIFO module row by row, waiting for the scaling module to read. It also outputs the first display timing signal to the data processing module so that the data processing module adjusts the timing of the first display timing signal. Among them, the way for the FIFO module to decode the display data stream is not unique. For example, it can decode the display data stream of the image to be displayed according to the DSI timing specification to obtain a first display timing signal and display data, or it can be other ways recognized by those skilled in the art, which is not limited.

[0055] Step 204: Perform data processing on the first display timing signal to obtain a second display timing signal; the vertical blanking time of the second display timing signal is less than the vertical blanking time of the first display timing signal.

[0056] The vertical blanking time is the time other than the frame valid data time in each frame of display time. When the timing is in the vertical blanking time, there is no image display on the display screen. Specifically, as Figure 3 shown, the vertical blanking time includes the pulse width VSW (Vertical Sync Width) time of the vertical synchronization signal VSYNC, and also includes the number of invalid display rows VBP (Vertical Back Porch) after the vertical synchronization signal VSYNC jumps at the beginning of a frame of image, and also includes the number of invalid display rows VFP (Vertical Front Porch) before the vertical synchronization signal VSYNC jumps at the end of a frame of image.

[0057] Among them, the second display timing signal can be understood as being obtained by performing timing adjustment data processing on the first display timing signal. The vertical blanking time of the second display timing signal after timing adjustment is less than that of the first display timing signal, so as to increase the frame valid data time in each frame. Specifically, first, analyze according to the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal in the first display timing signal to obtain the vertical blanking time of the first display timing signal of the first display timing signal. Then, adjust the first vertical synchronization signal in the first display timing signal according to the vertical blanking time of the first display timing signal to obtain the second vertical synchronization signal, and adjust the first display enable signal in the first display timing signal according to the preset time parameter to obtain the second display enable signal. The first horizontal synchronization signal in the first display timing signal and the first pixel clock signal are not adjusted. Further, based on the second vertical synchronization signal, the second display enable signal, the first horizontal synchronization signal, and the first pixel clock signal, the second display timing signal is obtained. The preset time parameter is a parameter for adjusting the first display enable signal, and its value is not unique and can be determined according to the vertical blanking time of the first display timing signal and the difference between the resolution of the image to be displayed and the fixed resolution of the display screen.

[0058] Step 206: Analyze according to the first display timing signal and the second display timing signal to obtain the data reading parameters.

[0059] The scaling module needs to read the display data from the FIFO module row by row and perform scaling processing to obtain the target display data for display. Among them, the scaling module can perform reduction or magnification processing on the read display data. In the application scenario where the resolution of the image to be displayed in this embodiment is less than the fixed resolution of the display device, it can be understood that the scaling processing here is magnification processing. After the timing of the display timing signal is adjusted, the scaling module needs to read the display data based on the adjusted second timing signal to ensure consistency during transmission and display. Among them, the reading parameters include the first row reading delay time and the reading time interval. The first row reading delay time is the time for the scaling module to read the first row display data of each frame of display data, and the reading time interval is the time interval between each row of display data in each frame of display data.

[0060] The data processing module needs to output the reading parameters to the scaling module according to the vertical blanking time difference between the adjusted and unadjusted display timing signals, so that the scaling module reads the display data from the FIFO module row by row according to the reading parameters and performs scaling processing to obtain the target display data for display.

[0061] Step 208: Read the display data according to the data reading parameters, and perform scaling processing on the read display data to obtain the target display data.

[0062] After the scaling module obtains the reading parameters output by the data processing module, it sequentially reads the display data row by row according to the reading parameters, and performs scaling processing according to the preset scaling ratio to obtain the target display data. It can be understood that the target display data is also obtained row by row. The preset scaling ratio is not unique and can be determined according to the difference between the resolution of the image to be displayed and the fixed resolution of the display screen.

[0063] The above display data processing method, device, display driving chip, display device and computer-readable storage medium, after parsing the display data stream of the image to be displayed to obtain the first display timing signal and the display data, reduce the vertical blanking time of the first display timing signal to obtain the second display timing signal, and then correspondingly generate reading parameters for reading and scaling the display data, and output the target display data, which can increase the frame valid data time in each frame of display data, and solve the problem of display disorder or loss of display data caused by the increase in data volume when magnifying a low-resolution image to the fixed resolution of the display screen without changing the hardware architecture of the driving chip.

[0064] In one embodiment, the above display data processing method further includes: Step 210: Display the image to be displayed according to the second display timing signal and the target display data.

[0065] The data processing module adjusts the output timing between each row of display data according to the horizontal blanking time in the second display timing signal for each row of target display data output by the scaling module, and correspondingly performs processes such as digital-to-analog conversion, GAMMA adjustment, and GIP timing adjustment, and then outputs a driving signal to drive the display screen to display the image to be displayed.

[0066] Among them, the horizontal blanking time is the time when the display screen has no image display during each row of display time. Specifically, as Figure 4 shown, the horizontal blanking time includes the pulse width HSW (Horizontal Sync Width) time of the horizontal sync signal HSYNC, and also includes the HBP (Horizontal Back Porch) time from the falling edge of the horizontal sync signal HSYNC to the rising edge of the display enable signal DE, and further includes the HFP (Horizontal Front Porch) time from the falling edge of the display enable signal DE to the rising edge of the next horizontal sync signal HSYNC. The units of the above times are all the number of pixel clock signals PLCK.

[0067] In one embodiment, as Figure 5As shown, the data processing of the first display timing signal in step 204 to obtain the second display timing signal includes steps 320 to 340, where:

[0068] Step 320: Analyze the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal.

[0069] The method for the data processing module to analyze and obtain the vertical blanking time of the first display timing signal is not unique. It can be obtained by means of timer timing or by counting the number of pixel clock signals PCLK. Since the pixel clock signal PCLK does not require timing adjustment and is generated according to the internal clock of the display device itself, the method of obtaining the vertical blanking time of the first display timing signal by counting the number of pixel clock signals PCLK is more suitable for adjusting the first display timing signal.

[0070] Specifically, it can be by counting the time difference between the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal. The vertical blanking time of the first display timing signal includes the VSW time, the VBP time, and the VFP time. Among them, it can be by counting the number of PCLK between the rising edge and the falling edge of the first vertical synchronization signal to obtain the VSW time of the vertical blanking time of the first display timing signal. Then count the number of PCLK between the first falling edge of the first horizontal synchronization signal after the rising edge of the first vertical synchronization signal and the falling edge of the first horizontal synchronization signal before the first rising edge of the first display enable signal in each row to obtain the VBP time of the vertical blanking time of the first display timing signal. Then count the number of PCLK between the falling edge of the first horizontal synchronization signal after the last falling edge of the first display enable signal in each row and the first falling edge of the first horizontal synchronization signal after the falling edge of the first vertical synchronization signal to obtain the VFP time of the vertical blanking time of the first display timing signal.

[0071] Step 340: Perform timing adjustment on the first display timing signal according to the vertical blanking time of the first display timing signal and the preset time parameter to obtain the second display timing signal.

[0072] The data processing module can perform timing adjustment on each timing signal in the first display timing signal according to the vertical blanking time of the first display timing signal obtained by analysis, so as to obtain a second display timing signal with a shorter vertical blanking time and a longer frame valid data time. It can be understood that the first vertical synchronization signal and the first display enable signal that affect the vertical blanking time distribution need to be adjusted in timing respectively to obtain a second vertical synchronization signal and a second display enable signal, and further obtain a second display timing signal based on the second vertical synchronization signal and the second display enable signal.

[0073] In this embodiment, when the subsequent module displays the display data according to the second display timing signal, it has a longer frame valid data time to process the display data. When the display device enlarges a low-resolution image to the fixed resolution of the display screen and the amount of display data increases, there is also enough time to process the display data, without changing the hardware architecture to increase the operating speed of the display driver chip itself to solve the problem of display disorder or loss of display data caused by the increase in data volume.

[0074] In one embodiment, as Figure 6 shown, the step of performing timing adjustment on the first display timing signal according to the vertical blanking time of the first display timing signal and the preset time parameter to obtain the second display timing signal includes:

[0075] Step 342: Perform timing adjustment on the first vertical synchronization signal according to the vertical blanking time of the first display timing signal to obtain a second vertical synchronization signal. The data processing module adds the VBP time in the vertical blanking time of the first display timing signal to the generation time of the first vertical synchronization signal as the generation time of the second vertical synchronization signal. And the VSW time of the second vertical synchronization signal is the same as the VSW time of the first vertical synchronization signal. Among them, the generation times of the first vertical synchronization signal and the second vertical synchronization signal can be understood as the arrival times of their rising edges.

[0076] Step 344: Perform timing adjustment on the first display enable signal according to the preset time parameter to obtain a second display enable signal. The data processing module adds the preset time parameter to the generation time of the first display enable signal as the generation time of the second display enable signal. Among them, the preset time parameter is determined according to the vertical blanking time of the first display timing signal and the difference between the resolution of the image to be displayed and the fixed resolution of the display screen. In this embodiment, the preset time parameter is less than the VBP time in the vertical blanking time of the first display timing signal, and when the difference between the resolution of the image to be displayed and the fixed resolution of the display screen is larger, the preset time parameter can be set to a time smaller than the VBP time. Among them, the generation times of the first display enable signal and the second display enable signal can be understood as the arrival times of their rising edges.

[0077] Step 346: Obtain a second display timing signal based on the second vertical synchronization signal and the second display enable signal.

[0078] The data processing module obtains a second display timing signal based on the second vertical synchronization signal and the second display enable signal obtained after timing adjustment, as well as the first horizontal synchronization signal and the first pixel clock signal without timing adjustment. Then, by counting, analyze the vertical blanking time of the second display timing signal according to the second vertical synchronization signal, the second display enable signal, and the first horizontal synchronization signal. It can be obtained that since the preset time parameter for adjusting the second display enable signal is less than the VBP time of the vertical blanking time of the first display timing signal, the vertical blanking time of the second display timing signal will be less than the vertical blanking time of the first display timing signal in the first display timing signal. Further, since the overall duration remains unchanged, it has a longer frame valid data time.

[0079] In one embodiment, as Figure 7 shown, analyzing according to the first display timing signal and the second display timing signal in step 206 to obtain data reading parameters, including:

[0080] Step 402: Obtain the first-line reading delay time according to the difference between the first vertical synchronization signal of the first display timing signal and the second vertical synchronization signal of the second display timing signal. Since the start time of each frame of image in the display timing signal is adjusted, it is necessary to correspondingly adjust the time for the scaling module to read each line of display data. Then, the data processing module can obtain the first-line reading delay time according to the difference between the generation time of the first vertical synchronization signal and the generation time of the second vertical synchronization signal, and send it to the scaling module.

[0081] Step 404: Obtain the reading time interval according to the horizontal blanking time of the first display timing signal.

[0082] Similarly, since the horizontal synchronization signal in the second display timing signal is not adjusted in timing, the horizontal blanking time of the first display timing signal is used as the reading time interval and output to the scaling module to control the scaling module to read a line of display data at a fixed time interval.

[0083] In one embodiment, as Figure 8 shown, reading the display data according to the data reading parameters in step 208 and performing scaling processing on the read display data to output the target display data, including:

[0084] Step 502: Read the display data line by line according to the first-line reading delay time and the reading time interval. After obtaining the first-line reading delay time and the reading time interval, the scaling module reads the display data line by line from the FIFO module according to the above two reading parameters.

[0085] Step 504: Scale the read display data for each line and output the target display data.

[0086] After the scaling module reads a line of display data, it performs scaling processing according to a preset scaling ratio and outputs the target display data. Among them, the scaling algorithm adopted in this application is the bilinear interpolation algorithm. The scaling module reads two lines of display data from the FIFO module row by row according to the read parameters, and obtains a line of target display data after bilinear interpolation and outputs it.

[0087] It should be understood that although each step in the flowcharts involved in the above-described embodiments is shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0088] Based on the same inventive concept, the embodiments of the present application also provide a display data processing device for implementing the above-mentioned display data processing method. The implementation solutions provided by this device to solve problems are similar to the implementation solutions described in the above method. Therefore, the specific limitations in one or more embodiments of the following display data processing devices can refer to the limitations on the display data processing method in the above text, and will not be repeated here.

[0089] In one embodiment, as Figure 9 shown, a display data processing device is provided, including a data acquisition module 910, a data processing module 920, and a data scaling module 930, where:

[0090] The data acquisition module 910 is configured to acquire a display data stream of an image to be displayed, and parse the display data stream to obtain a first display timing signal and display data; among them, the first display timing signal includes a vertical blanking time and a frame valid data time;

[0091] The data processing module 920 is configured to perform data processing on the first display timing signal to obtain a second display timing signal; the vertical blanking time of the second display timing signal is less than the vertical blanking time of the first display timing signal; it is also configured to analyze according to the first display timing signal and the second display timing signal to obtain data read parameters;

[0092] A data scaling module 930 is configured to read display data according to data reading parameters and perform scaling processing on the read display data to obtain target display data.

[0093] In one embodiment, the first display timing signal includes a first vertical synchronization signal, a first horizontal synchronization signal, and a first display enable signal. The data processing module 920 is further configured to analyze the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal; perform timing adjustment on the first display timing signal according to the vertical blanking time of the first display timing signal and a preset time parameter to obtain a second display timing signal.

[0094] In one embodiment, the data processing module 920 is further configured to perform timing adjustment on the first vertical synchronization signal according to the vertical blanking time of the first display timing signal to obtain a second vertical synchronization signal; perform timing adjustment on the first display enable signal according to the preset time parameter to obtain a second display enable signal; obtain a second display timing signal based on the second vertical synchronization signal and the second display enable signal.

[0095] In one embodiment, the frame valid data time includes a horizontal blanking time, and the data reading parameters include a first-line reading delay time and a reading time interval. The data processing module 920 is further configured to obtain the first-line reading delay time according to the difference between the first vertical synchronization signal of the first display timing signal and the second vertical synchronization signal of the second display timing signal; obtain the reading time interval according to the horizontal blanking time of the first display timing signal.

[0096] In one embodiment, the data scaling module 930 is further configured to read display data row by row according to the first-line reading delay time and the reading time interval; perform scaling processing on each row of the read display data to obtain target display data.

[0097] In one embodiment, it further includes a data display module 940 configured to display the image to be displayed according to the second display timing signal and the target display data.

[0098] Each module in the above display data processing device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above respective modules.

[0099] In one embodiment, as Figure 10As shown, a display driving chip is also provided. The display driving chip includes a first-in-first-out module 110, a data processing module 120, and a scaling module 130. The first-in-first-out module 110 is connected to the data processing module 120 and the scaling module 130, and the data processing module 120 is connected to the scaling module 130. The first-in-first-out module 110 is configured to obtain a display data stream of an image to be displayed, parse the display data stream to obtain a first display timing signal and display data, and send the first display timing signal to the data processing module 120. The data processing module 120 performs data processing on the first display timing signal to obtain a second display timing signal. The vertical blanking time of the second display timing signal is less than that of the first display timing signal. The data processing module 120 further analyzes the first display timing signal and the second display timing signal to obtain a data reading parameter and sends it to the scaling module 130. The scaling module 130 is configured to read the display data from the first-in-first-out module 110 according to the reading parameter and perform scaling processing on the read display data to obtain target display data.

[0100] The main controller of the display device inputs the display data stream of the image to be displayed into the first-in-first-out (FIFO) module 110. After the FIFO module obtains the display data stream of the image to be displayed, it first decodes the display data stream to obtain a first display timing signal and display data. The display data is stored row by row in the buffer space of the FIFO module, waiting to be read by the scaling module 130. The first display timing signal is also output to the data processing module 120 so that the data processing module 120 can perform timing adjustment on the first display timing signal.

[0101] The data processing module 120 first analyzes the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal in the first display timing signal to obtain the vertical blanking time of the first display timing signal. Then, it adjusts the first vertical synchronization signal in the first display timing signal according to the vertical blanking time of the first display timing signal to obtain a second vertical synchronization signal, and adjusts the first display enable signal in the first display timing signal according to a preset time parameter to obtain a second display enable signal. The first horizontal synchronization signal and the first pixel clock signal in the first display timing signal are not adjusted. Further, a second display timing signal is obtained based on the second vertical synchronization signal, the second display enable signal, the first horizontal synchronization signal, and the first pixel clock signal.

[0102] After the timing signal is adjusted in the display timing, the scaling module 130 needs to read the display data based on the adjusted second timing signal to ensure consistency during the transmission and display processes. Among them, the reading parameters include the first-line reading delay time and the reading time interval. The first-line reading delay time is the time for the scaling module to read the first-line display data of each frame of display data, and the reading time interval is the time interval between each line of display data when reading each frame of display data. The data processing module 120 needs to output the reading parameters to the scaling module 130 according to the vertical blanking time difference between the display timing signals before and after adjustment. After obtaining the reading parameters output by the data processing module, the scaling module 130 reads the display data row by row according to the reading parameters, and after performing scaling processing according to the preset scaling ratio, the target display data is obtained. It can be understood that the target display data also corresponds to being obtained row by row.

[0103] The data processing module 120 adjusts the output timing between each line of display data according to the horizontal blanking time in the first display timing signal for each line of target display data output by the scaling module 130, and after corresponding processes such as digital-to-analog conversion, GAMMA adjustment, and GIP timing adjustment, it outputs a driving signal to drive the display screen to display the image to be displayed.

[0104] Among them, due to the increase in data volume caused by the picture magnification process of the scaling module 130, the FIFO module also requires a certain amount of buffer space to store the data that the subsequent module has not had time to process. The capacity of the required FIFO storage space can be calculated according to the following formula:

[0105]

[0106] In the formula, X represents the width resolution of the display before magnification, Y represents the height resolution of the display before magnification, X1 represents the width resolution of the display after magnification, and Y1 represents the height resolution of the display after magnification. HBP, HFP, and HSW are the horizontal blanking times described above, and the specific values can be obtained according to the actual display timing signal.

[0107] Based on the same inventive concept, the specific limitations in one or more of the above-described display driver chip embodiments can refer to the limitations on the display data processing method in the above text, and will not be elaborated here.

[0108] In one embodiment, a display device is provided. The display device includes a display screen and the above-described display driver chip. The display driver chip is connected to the display screen. After parsing and processing the display data stream of the image to be displayed, the display driver chip displays the image to be displayed through the display screen.

[0109] Specifically, the steps for the display driver chip to parse and process the display data stream of the image to be displayed are as follows: Obtain the display data stream of the image to be displayed, and parse the display data stream to obtain a first display timing signal and display data; perform data processing on the first display timing signal to obtain a second display timing signal; the vertical blanking time of the second display timing signal is less than that of the first display timing signal; analyze based on the first display timing signal and the second display timing signal to obtain a data reading parameter; read the display data according to the data reading parameter, and perform scaling processing on the read display data to obtain target display data.

[0110] Based on the same inventive concept, the specific limitations in one or more of the above-provided display device embodiments can be referred to the limitations on the display data processing method in the foregoing text, and will not be elaborated here.

[0111] In one embodiment, a computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed, the following steps are implemented: Obtain the display data stream of the image to be displayed, and parse the display data stream to obtain a first display timing signal and display data; perform data processing on the first display timing signal to obtain a second display timing signal; the vertical blanking time of the second display timing signal is less than that of the first display timing signal; analyze based on the first display timing signal and the second display timing signal to obtain a data reading parameter; read the display data according to the data reading parameter, and perform scaling processing on the read display data to output target display data.

[0112] In one embodiment, the first display timing signal includes a first vertical synchronization signal, a first horizontal synchronization signal, and a first display enable signal. When the computer program is executed by a processor, the following steps are further implemented: Analyze the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal; perform timing adjustment on the first display timing signal according to the vertical blanking time of the first display timing signal and a preset time parameter to obtain a second display timing signal.

[0113] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: Perform timing adjustment on the first vertical synchronization signal according to the vertical blanking time of the first display timing signal to obtain a second vertical synchronization signal; perform timing adjustment on the first display enable signal according to the preset time parameter to obtain a second display enable signal; obtain a second display timing signal based on the second vertical synchronization signal and the second display enable signal.

[0114] In one embodiment, the frame valid data time includes a horizontal blanking time, and the data reading parameters include a first row reading delay time and a reading time interval; when the computer program is executed by a processor, the following steps are further implemented: obtaining the first row reading delay time according to the difference between the first vertical synchronization signal of the first display timing signal and the second vertical synchronization signal of the second display timing signal; obtaining the reading time interval according to the horizontal blanking time of the first display timing signal.

[0115] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: reading the display data row by row according to the first row reading delay time and the reading time interval; performing a scaling process on each row of the read display data to obtain target display data.

[0116] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: displaying the image to be displayed according to the second display timing signal and the target display data.

[0117] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0118] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0119] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0120] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A display data processing method, characterized in that, The method includes: Obtain the display data stream of the image to be displayed, and parse the display data stream to obtain a first display timing signal and display data; wherein, the first display timing signal includes a vertical blanking time and a frame valid data time, and the first display timing signal includes a first vertical synchronization signal, a first horizontal synchronization signal, and a first display enable signal; Analyze the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal; Perform timing adjustment on the first vertical synchronization signal according to the vertical blanking time of the first display timing signal to obtain a second vertical synchronization signal; Perform timing adjustment on the first display enable signal according to a preset time parameter to obtain a second display enable signal; Obtain a second display timing signal based on the second vertical synchronization signal and the second display enable signal; the vertical blanking time of the second display timing signal is less than the vertical blanking time of the first display timing signal; Analyze the first display timing signal and the second display timing signal to obtain a data reading parameter; Read the display data according to the data reading parameter, and perform scaling processing on the read display data to obtain target display data.

2. The method according to claim 1, wherein The analyzing the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal includes: Obtain the vertical blanking time of the first display timing signal by counting the time difference between the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal.

3. The method according to claim 2, wherein The preset time parameter is determined according to the vertical blanking time of the first display timing signal and the difference between the resolution of the image to be displayed and the fixed resolution of the display screen.

4. The method according to claim 1, characterized in that, The frame valid data time includes a horizontal blanking time, and the data reading parameter includes a first-line reading delay time and a reading time interval; the analyzing the first display timing signal and the second display timing signal to obtain a data reading parameter includes: Obtain the first-line reading delay time according to the difference between the first vertical synchronization signal of the first display timing signal and the second vertical synchronization signal of the second display timing signal; Obtain the reading time interval according to the horizontal blanking time of the first display timing signal.

5. The method according to claim 4, wherein The reading the display data according to the data reading parameter and performing scaling processing on the read display data to obtain target display data includes: Read the display data line by line according to the first-line reading delay time and the reading time interval; Perform scaling processing on each line of the read display data to obtain the target display data.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: Display the image to be displayed according to the second display timing signal and the target display data.

7. A display data processing device, characterized in that, The device includes: A data acquisition module, configured to acquire a display data stream of an image to be displayed, and parse the display data stream to obtain a first display timing signal and display data; wherein, the first display timing signal includes a vertical blanking time and a frame valid data time, and the first display timing signal includes a first vertical synchronization signal, a first horizontal synchronization signal, and a first display enable signal; A data processing module, configured to analyze the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal; perform timing adjustment on the first vertical synchronization signal according to the vertical blanking time of the first display timing signal to obtain a second vertical synchronization signal; perform timing adjustment on the first display enable signal according to a preset time parameter to obtain a second display enable signal; obtain a second display timing signal based on the second vertical synchronization signal and the second display enable signal; the vertical blanking time of the second display timing signal is less than the vertical blanking time of the first display timing signal; and is further configured to analyze the first display timing signal and the second display timing signal to obtain a data reading parameter; A data scaling module, configured to read the display data according to the data reading parameter, and perform scaling processing on the read display data to obtain target display data.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the steps of the method according to any one of claims 1 to 6.

9. A display driving chip, characterized in that, It includes a first-in first-out module, a data processing module, and a scaling module. The first-in first-out module is connected to the data processing module and the scaling module, and the data processing module is connected to the scaling module; The first-in first-out module is configured to acquire a display data stream of an image to be displayed, and parse the display data stream to obtain a first display timing signal and display data, and send the first display timing signal to the data processing module; wherein, the first display timing signal includes a vertical blanking time and a frame valid data time, and the first display timing signal includes a first vertical synchronization signal, a first horizontal synchronization signal, and a first display enable signal; The data processing module analyzes the first vertical synchronization signal, the first horizontal synchronization signal, and the first display enable signal to obtain the vertical blanking time of the first display timing signal; performs timing adjustment on the first vertical synchronization signal according to the vertical blanking time of the first display timing signal to obtain a second vertical synchronization signal; performs timing adjustment on the first display enable signal according to a preset time parameter to obtain a second display enable signal; obtains a second display timing signal based on the second vertical synchronization signal and the second display enable signal; the vertical blanking time of the second display timing signal is less than the vertical blanking time of the first display timing signal; the data processing module further analyzes the first display timing signal and the second display timing signal to obtain a data reading parameter and sends it to the scaling module; The scaling module is configured to read the display data from the FIFO module according to the reading parameter, and perform scaling processing on the read display data to obtain target display data.

10. A display device, comprising a display screen and the display driving chip according to claim 9, wherein the display driving chip is connected to the display screen.

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