Internal voltage generating circuit and semiconductor device including the same

Abstract

The internal voltage generating circuit includes: a first voltage generator, which generates a first initial voltage by buffering a first reference voltage input from a first time point to a second time point, and generates the first initial voltage by integrating a difference between a predetermined reference voltage and the first reference voltage input after the second time point; a voltage divider, which outputs a second initial voltage by dividing the potential level of the first initial voltage at a first preset ratio from the first time point to the second time point, and outputs the first initial voltage as the second initial voltage after the second time point; a selector, which selects and outputs the second initial voltage or the second reference voltage based on a comparison of the levels of the feedback voltage and the second reference voltage; and a second voltage generator, which generates an internal voltage based on a result of a comparison of the output voltage of the selector and the levels of the feedback voltage, and generates a feedback voltage by dividing the internal voltage at a second preset ratio.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0003288, filed on January 11, 2021, which is hereby incorporated by reference in its entirety. Technical Field

[0003] One or more embodiments described herein relate to an internal voltage generating circuit and a semiconductor device including the internal voltage generating circuit. Background Art

[0004] Memory devices can be classified into one of two types: volatile memory devices and non-volatile memory devices. In volatile memory devices, data is lost when the power is interrupted. Examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). In non-volatile memory devices, data can be stored even when the power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Examples of flash memory include NOR-type and NAND-type memories.

[0005] Semiconductor memory devices can operate based on an internal voltage derived from a power supply voltage provided by an external source. When the power supply voltage is provided, the memory device can be said to be "powered on." In many cases, the power supply voltage is not in a completely stable state. Therefore, during the power-on operation, the memory device may have difficulty determining whether signals and / or data are in a logic high state or a logic low state.

[0006] In many memory devices, an initialization operation may be performed when a power supply voltage is first applied from an external source during power-up. Initialization may be performed using a power-on reset circuit that prevents operation of the memory device when the external power supply voltage is unstable. The power-on reset circuit may also initialize the memory device. One type of power-on reset circuit detects when the external power supply voltage rises above a preset voltage level (e.g., when power to the memory device is turned on) and then generates a power-on reset signal. In these memory devices, all circuits of the memory device are initialized by the power-on reset signal. Summary of the Invention

[0007] One or more embodiments described herein provide an internal voltage generating circuit capable of suppressing peak current generation during an internal voltage generating operation.

[0008] One or more embodiments also provide a semiconductor device including such an internal voltage generating circuit.

[0009] In one embodiment, the internal voltage generator may include: a first voltage generator configured to generate a first initial voltage by buffering a first reference voltage input from a first time point to a second time point, and to generate the first initial voltage by integrating a difference between a predetermined reference voltage and the first reference voltage input after the second time point, wherein the first time point is after a power-on time point and the second time point is after the first time point; a voltage divider configured to output a second initial voltage by dividing a potential level of the first initial voltage at a first preset ratio from the first time point to the second time point, and to output the first initial voltage as the second initial voltage after the second time point; a selector configured to select and output the second initial voltage or the second reference voltage based on a comparison of a potential level of a feedback voltage with a potential level of a second reference voltage; and a second voltage generator configured to generate an internal voltage by receiving or blocking an external power supply voltage according to a result of comparing a potential level of an output voltage of the selector with a potential level of the feedback voltage, and to generate a feedback voltage by dividing the internal voltage at a second preset ratio.

[0010] In one embodiment, the internal voltage generator may include: a first voltage generator configured to generate a first initial voltage by buffering a first reference voltage input from a first time point to a second time point, and to generate the first initial voltage by integrating a difference between a predetermined reference voltage and the first reference voltage input after the second time point, wherein the first time point is after a power-on time point and the second time point is after the first time point; an enable signal generator configured to generate first to third enable signals in response to a power-on reset signal, activate the first enable signal at a first time point when a potential level of an external power supply voltage rises above a preset level, activate the second enable signal at a second time point that is later than the first enable signal by a preset delay amount, and generate a third enable signal that maintains an activated state between the first time point and the second time point; A control signal generator is configured to generate a plurality of control signals in response to a first enable signal and a second enable signal, the plurality of control signals being activated in a predetermined order in each of a plurality of time periods; a voltage divider is configured to output a second initial voltage by dividing a potential level of a first initial voltage at a first preset ratio that changes based on the plurality of control signals during an activation period of a third enable signal, and to output the first initial voltage as the second initial voltage during a deactivation period of the third enable signal; and a second voltage generator is configured to generate an internal voltage by receiving or blocking an external power supply voltage according to a result of comparing a potential level of a feedback voltage with a potential level of one of the second initial voltage and a second reference voltage, and to generate a feedback voltage by dividing the internal voltage at a second preset ratio.

[0011] In one embodiment, a semiconductor device may include: a power-on reset circuit configured to detect a potential level of an external power supply voltage and generate a power-on reset signal converted at a first time point at which the potential level of the external power supply voltage rises above a preset level; a reference voltage generator configured to receive the external power supply voltage and generate a first reference voltage and a second reference voltage; and an internal voltage generator configured to: start operating in response to the power-on reset signal; output the second initial voltage by dividing the potential level of a first initial voltage generated by buffering the first reference voltage by a first preset ratio from the first time point to a second time point later than the first time point; after the second time point, output the first initial voltage having a potential level rising at a constant slope as the second initial voltage by integrating a difference between the first reference voltage and a ground voltage; generate the internal voltage by receiving or blocking the external power supply voltage according to a result of comparing the potential level of a feedback voltage with the potential level of one of the second initial voltage and the second reference voltage; and generate the feedback voltage by dividing the internal voltage by a second preset ratio.

[0012] In the present technology, by operating the voltage generating circuit using a voltage that rises at a constant slope during the initial operation of generating the internal voltage, it is possible to suppress the voltage generating circuit from generating a peak current.

[0013] Additionally, in the present technology, in order to prevent a phenomenon in which the current consumption of the external power supply voltage increases due to a sudden increase in the potential level of the internal voltage during the initial operation of generating the internal voltage, a voltage divider circuit that operates only in a predetermined part of the time period during the initial operation of generating the internal voltage is included, thereby stabilizing the operation of the voltage generating circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 One embodiment of a memory system is illustrated.

[0015] Figure 2 One embodiment of a memory device is illustrated.

[0016] Figure 3 One embodiment of an internal voltage generating circuit is illustrated.

[0017] Figure 4 One embodiment of an initial voltage generating circuit is shown.

[0018] Figure 5 One embodiment of a voltage divider circuit is shown.

[0019] Figure 6 One embodiment of a selection circuit is shown.

[0020] Figure 7 One embodiment of a voltage generating circuit is illustrated.

[0021] Figure 8 One embodiment of a waveform diagram including signals used to generate internal voltages in a memory device is illustrated. DETAILED DESCRIPTION

[0022] Various examples of the present disclosure are described in more detail below with reference to the accompanying drawings. However, various aspects and features of the present invention may be embodied in different ways to form other embodiments, including variations of any of the disclosed embodiments. Therefore, the present invention is not limited to the embodiments set forth herein. On the contrary, the described embodiments are provided to make this disclosure thorough and complete, and to fully convey this disclosure to those skilled in the art to which the invention pertains. Throughout this disclosure, throughout the various figures and examples of this disclosure, like reference numerals refer to like parts. It should be noted that references to "one embodiment," "another embodiment," etc. do not necessarily mean only one embodiment, and different references to any such phrases do not necessarily refer to the same (multiple) embodiments.

[0023] It will be understood that although the terms "first," "second," "third," etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Thus, a first element in one instance may be referred to as a second element or a third element in another instance without indicating any change in the element itself.

[0024] The accompanying drawings are not necessarily drawn to scale, and in some cases, proportions may be exaggerated to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it is understood that the former can be directly connected or coupled to the latter, or electrically connected or coupled to the latter via one or more intermediate elements therebetween. Additionally, it is also understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements can also be present.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular is intended to include the plural, and vice versa. Similarly, the indefinite articles "a" and "an" mean one or more unless the language or context clearly indicates only one.

[0026] It will be further understood that when used in this specification, the terms "comprises," "comprising," "includes," and "containing" specify the presence of stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art in view of the disclosure. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of this disclosure and the related art, and should not be idealized or overly formally interpreted unless explicitly defined herein.

[0028] In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. The present invention can be practiced without some or all of these specific details. In other cases, well-known process structures and / or processes have not been described in detail to avoid unnecessarily obscuring the present invention.

[0029] It should also be noted that in some cases, as is apparent to those skilled in the relevant art, features or elements described in conjunction with one embodiment may be used alone or in combination with other features or elements of another embodiment, unless specifically stated otherwise.

[0030] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, wherein like reference numerals represent like elements.

[0031] Figure 1 is a block diagram illustrating one embodiment of a memory system 110 , which may include a memory device 150 that stores data and a controller 130 that controls the memory device 150 , for example, under the control of a host 102 .

[0032] The host 102 may include at least one operating system (OS) that manages and controls functions and operations performed in the host 102. The OS may also provide interoperability between the host 102 and a user of the memory system 110 that interfaces with the memory system 110. The OS may support functions and operations corresponding to user requests.

[0033] As an example and not limitation, for example, based on the mobility of the host 102, the OS can be classified as a general-purpose operating system and a mobile operating system. Depending on the system requirements and / or user environment, the general-purpose operating system can include a personal operating system or an enterprise operating system. Personal operating systems (e.g., Windows, Chrome, etc.) may be subject to support services for various purposes. Enterprise operating systems can be dedicated to protection and support high performance. Examples of these types of operating systems include Windows Server, Linux, Unix, etc.

[0034] Mobile operating systems include, for example, Android, iOS, Windows Mobile, etc. Mobile operating systems may be subject to support services or functions (eg, power saving functions) for mobility.

[0035] In some cases, the host 102 may include multiple operating systems. In response to user requests, the host 102 may execute multiple operating systems interlocked with the memory system 110. The host 102 may transmit multiple commands corresponding to the user requests to the memory system 110, so that operations corresponding to the commands are executed within the memory system 110.

[0036] Storage devices for the memory system 110 may be implemented using volatile memory devices (e.g., dynamic random access memory (DRAM) and static RAM (SRAM)) and / or non-volatile memory devices (such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory).

[0037] The controller 130 and the memory device 150 in the memory system 110 may be integrated into a single semiconductor device, which may be included in any of the various types of memory systems as discussed above in the examples.

[0038] As an example and not a limitation, the controller 130 and the memory device 150 may be implemented using a solid-state drive (SSD). When the memory system 110 is implemented as an SSD, the operating speed of the host 102 connected to the memory system 110 may be significantly improved compared to when the host 102 is implemented as a hard disk. In one embodiment, the controller 130 and the memory device 150 may be integrated into a semiconductor device to form a memory card, such as a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a general-purpose flash memory.

[0039] The memory system 110 may be configured as, for example, part of a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional (3D) television, a smart TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a storage device configuring a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, a radio frequency identification (RFID) device, or one of various components configuring a computing system.

[0040] The memory device 150 can receive a command CMD and an address ADD from the memory controller 130 via a channel and can access a region of the memory cell array corresponding to the address ADD. For example, the memory device 150 can perform an internal operation corresponding to the command CMD on the region selected by the address ADD. In one embodiment, the memory device 150 can perform a program operation on a selected block in response to the command CMD, the address ADD, and the data corresponding to a program operation. In addition, the memory device 150 can perform a read operation on a selected memory block in response to the command CMD and the address ADD corresponding to a read operation and can output the read data to the memory controller 130.

[0041] The controller 130 may control the overall operation of the memory device 150, such as read, write, program, and erase operations. For example, the controller 130 may control the memory device 150 in response to a request from the host 102. The controller 130 may provide the host 102 with data read from the memory device 150. The controller 130 may also store data provided by the host 102 in the memory device 150.

[0042] Each of the memory device 150 and the memory controller 130 may be provided with an external power supply voltage VCCE and then may be operated. For example, the memory device 150 may be provided with an external power supply voltage VCCE to generate one or more internal voltages and may use the one or more internal voltages to perform an overall or predetermined operation.

[0043] In one embodiment, the memory system 110 may include a single memory device 150, but in another embodiment, it may include multiple memory devices 150. During a power-up interval of the memory system 110, the multiple memory devices 150 may simultaneously generate one or more internal voltages using the external power supply voltage VCCE. Consequently, the generation of the internal voltages may increase instantaneous current consumption. This, in turn, may result in an increase in peak current.

[0044] Figure 2 One embodiment of a memory device 150 is illustrated, which may include a power-on reset circuit 202 , an internal voltage generation circuit 204 , a reference voltage generation circuit 206 , and an internal circuit 208 .

[0045] The power-on reset circuit 202 can detect the potential level of the external power supply voltage VCCE and then generate and output a power-on reset signal POR. For example, during a power-on operation of the memory system, when the potential level of the external power supply voltage VCCE rises above a preset level, the power-on reset circuit 202 can change and output the logic level of the power-on reset signal POR. Here, the time point at which the logic level of the power-on reset signal POR changes when the external power supply voltage VCCE exceeds the preset level can be defined as a first time point. Therefore, the first time point can be later than the power-on time point at which power is supplied to the memory system 110.

[0046] The reference voltage generation circuit 206 can receive an external power supply voltage VCCE and generate and output a first reference voltage VREF1 and a second reference voltage VREF2. Each of the first reference voltage VREF1 and the second reference voltage VREF2 can be, for example, a constant level. In one embodiment, the reference voltage generation circuit 206 can be implemented as a bandgap reference circuit, which provides a reference voltage or reference current with a constant level and is, for example, unaffected by variations in power supply voltage or temperature or process variations. For example, the constant level can be achieved based on output characteristics having a negative (-) temperature coefficient and a positive (+) temperature coefficient that are offset from each other. In one embodiment, each of the first reference voltage VREF1 and the second reference voltage VREF2 can have a constant level regardless of variations in PVT (process, voltage, and temperature) during the power-up period.

[0047] The internal voltage generating circuit 204 may start operating in response to a power-on reset signal POR. For example, the internal voltage generating circuit 204 may start operating at a first time point. The internal voltage generating circuit 204 may receive an external power supply voltage VCCE and generate an internal voltage VCCI. During the power-on period, the internal voltage generating circuit 204 may prevent the voltage level of the internal voltage VCCI from rising too suddenly (e.g., above a predetermined rate). For example, this may be achieved by appropriately adjusting the rate at which the voltage level of the internal voltage VCCI increases, which in turn may suppress a sudden increase in current consumption.

[0048] The internal circuit 208 can be initialized in response to the power-on reset signal POR output from the power-on reset circuit 202 or the selection signal VTEM output from the internal voltage generating circuit 204. When the generation of the internal voltage VCCI is completed, for example, when it is detected that the potential level of the internal voltage VCCI generated therein reaches the target potential level, the internal voltage generating circuit 204 can generate the selection signal VTEM and transmit the selection signal VTEM to the internal circuit 208. The internal circuit 208 can operate using the internal voltage VCCI (generated in the internal voltage generating circuit 204) as a power supply and can respond to the internal voltage VCCI output from the internal voltage generating circuit 204. Figure 1 The controller 130 receives commands, addresses, and data to perform operations (eg, a write / program operation to store data, a read operation to read stored data, an erase operation to erase stored data).

[0049] Figure 3 The figure illustrates an embodiment of an internal voltage generating circuit (or voltage generator) 204, which may include an initial voltage generating circuit (or first voltage generator) 302, a voltage divider circuit (or voltage divider) 304, a selection circuit (or selector) 306, a voltage generating circuit (or second voltage generator) 308, an enable signal generating circuit (or enable signal generator) 303, and a control signal generating circuit (or control signal generator) 305.

[0050] The voltage divider circuit 304 can output a second initial voltage VINI2 by dividing the potential level of the first initial voltage VINI1 by a first preset ratio. The first initial voltage VINI1 can be generated by the initial voltage generation circuit 302 buffering the first reference voltage VREF1 from a first time point (at the first time point, as the potential level of the external power supply voltage VCCE rises above a preset level and the power-on reset signal POR transitions) to a second time point later than the first time point. After the second time point, the first initial voltage VINI1, which has a potential level that rises at a constant slope, can be output as the second initial voltage VINI2. This can be achieved by integrating the difference between the first reference voltage VREF1 and a predetermined reference (e.g., ground) voltage VSS. The internal voltage VCCI can be generated by receiving or blocking the external power supply voltage VCCE based on the result of comparing the potential level of either the second initial voltage VINI2 or the second reference voltage VREF2 with the potential level of the feedback voltage VFEED.

[0051] The power-on reset signal POR can be found in the above reference Figure 2 The first reference voltage VREF1 and the second reference voltage VREF2 can be generated in the power-on reset circuit 202 described above. Figure 2 The feedback voltage VFEED may be generated in the voltage generating circuit 308 in the internal voltage generating circuit 204 and may have a potential level obtained by dividing the potential level of the internal voltage VCCI by a second preset ratio.

[0052] In operation, the initial voltage generating circuit 302 can generate the first initial voltage VINI1 by buffering the first reference voltage VREF1 input from a first time point to a later second time point. The first time point may be later than the power-on time point, and the second time point may be later than the first time point. The initial voltage generating circuit 302 can then generate the first initial voltage VINI1 by integrating the difference between the first reference voltage VREF1 (input after the second time point) and a predetermined reference voltage VSS. In one embodiment, the potential of the first initial voltage VINI1 can rise at a constant slope, and the reference voltage VSS can be a ground voltage.

[0053] The potential level of the first initial voltage VINI1 (generated by the integration operation in the initial voltage generating circuit 302 ) may be a potential level obtained by dividing the potential level difference between the first reference voltage VREF1 and the ground voltage VSS by a preset resistance value.

[0054] In one embodiment, the power-on time point may correspond to the time point at which the external power supply voltage VCCE starts to be supplied, and the first time point may correspond to the time point at which the potential level of the external power supply voltage VCCE rises above a preset level. Therefore, the first time point at which the potential level of the external power supply voltage VCCE rises above the preset level may be later than the power-on time point.

[0055] From the first time point to the second time point, the voltage divider circuit 304 may divide the potential level of the first initial voltage VINI1 by a first preset ratio. Then, the voltage divider circuit 304 may output the second initial voltage VINI2 based on the voltage division result. In one embodiment, the voltage divider circuit 304 may output the first initial voltage VINI1 as the second initial voltage VINI2 after the second time point.

[0056] For example, the voltage divider circuit 304 can be coupled to the output terminal of the initial voltage generating circuit 302 and can output the second initial voltage VINI2 by dividing the potential level of the first initial voltage VINI1 by a first preset ratio. In one embodiment, the first preset ratio can be changed according to a predetermined sequence in multiple time periods between the first time point and the second time point. The change in the preset ratio will cause a proportional change in the level of the first initial voltage VINI1. This can be due to, for example, changing the resistor combination coupled within the voltage divider circuit.

[0057] The multiple time periods between the first time point and the second time point can be preset by a designer, for example. For example, the number of time periods to be set as the multiple time periods between the first time point and the second time point can be preset by the designer. Additionally or alternatively, the length of each of the multiple time periods can be preset by the designer.

[0058] In one implementation, the period between the first time point and the second time point may be divided into N time points with a constant interval, such that the plurality of time periods includes a total of N+1 time points. (N is a natural number equal to or greater than 1). When N is 1, two time periods may be set based on one time point between the first time point and the second time point.

[0059] The selection circuit 306 can compare the potential level of the feedback voltage VFEED with the potential level of the second reference voltage VREF2, and can select the second initial voltage VINI2 or the second reference voltage VREF2 based on the comparison to generate the output voltage VSEL. For example, the selection circuit 306 can output the second initial voltage VINI2 from the first time point to the third time point (at the third time point, the potential level of the feedback voltage VFEED and the potential level of the second reference voltage VREF2 become equal to each other), and can output the second reference voltage VREF2 after the third time point.

[0060] The third time point may be later than the second time point in time. This is because the second initial voltage VINI2 has a potential level lower than the second reference voltage VREF2 (the second reference voltage VREF2 has a potential level equal to or higher than the first reference voltage VREF1) between the first time point and the second time point. This may be because the potential level of the second initial voltage VINI2 is determined by dividing the potential level of the buffered first reference voltage VREF1 (which rises at a constant slope from the second time point) by a first preset ratio. Therefore, from the first time point to the third time point, the second initial voltage VINI2 may have a potential level lower than the second reference voltage VREF2.

[0061] The voltage generation circuit 308 can generate an internal voltage VCCI. In operation, the voltage generation circuit 308 can receive or block the external power supply voltage VCCE based on the result of comparing the potential level of the output voltage VSEL with the potential level of the feedback voltage VFEED. For example, the voltage generation circuit 308 can adjust the potential level of the internal voltage VCCI by adjusting the amount of current supplied from the node of the external power supply voltage VCCE to the node of the internal voltage VCCI. The potential can be adjusted, for example, based on the result of comparing the potential level of the output voltage VSEL with the potential level of the feedback voltage VFEED. The voltage generation circuit 308 can generate the feedback voltage VFEED by dividing the potential level of the internal voltage VCCI generated therein by a second predetermined ratio.

[0062] For example, the voltage generation circuit 308 may receive the second initial voltage VINI2 from the selection circuit 306 from the first time point to the third time point, and may increase the potential level of the internal voltage VCCI by comparing the potential level of the second initial voltage VINI2 with the potential level of the feedback voltage VFEED. In this regard, as described above, the potential level of the second initial voltage VINI2 may have a value obtained by dividing the potential level of the buffered first reference voltage VREF1 by a first preset ratio (between the first time point and the second time point), and may have a value that increases at a constant slope between the second time point and the third time point. Therefore, when generating the internal voltage VCCI between the first time point and the third time point, the voltage generation circuit 308 may prevent a sudden increase in current consumption (between the first time point and the second time point), and may reduce the current consumption (between the second time point and the third time point) by reducing the rate at which the potential level of the internal voltage VCCI increases.

[0063] In one embodiment, the first preset ratio and the second preset ratio may correspond to voltage division ratios having different values. In one embodiment, the first preset ratio and the second preset ratio may be predetermined by a designer, for example, by selecting resistor values ​​in the voltage divider circuit and may be determined independently of each other.

[0064] The enable signal generation circuit 303 can generate a first enable signal EN1, a second enable signal EN2, and a third enable signal EN3 in response to a power-on reset signal POR. The enable signal generation circuit 303 can activate the first enable signal EN1 at a first time point (at the first time point, as the potential level of the external power supply voltage VCCE rises above a preset level, the power-on reset signal POR transitions). The enable signal generation circuit 303 can activate the second enable signal EN2 at a second time point that is later than the first enable signal EN1 by a preset delay amount. The enable signal generation circuit 303 can generate the third enable signal EN3 to maintain an active state between the first time point and the second time point. The first enable signal EN1 and the second enable signal EN2 can be deactivated, for example, at the same time point.

[0065] In one embodiment, the first enable signal EN1 and the second enable signal EN2 can be activated at a first time point and a second time point, respectively. Therefore, the initial voltage generating circuit 302 (which operates in response to the first enable signal EN1 and the second enable signal EN2) can generate the first initial voltage VINI1 by buffering the first reference voltage VREF1 in response to the activation of the first enable signal EN1. The initial voltage generating circuit 302 can generate the first initial voltage VINI1 to have a potential level that rises at a constant slope. This can be achieved by integrating the difference between the first reference voltage VREF1 and the ground voltage VSS in response to the activation of the second enable signal EN2. The selection circuit 306 and the voltage generating circuit 308 can begin operating in response to the activation of the first enable signal EN1 and can continue operating during the period in which the first enable signal EN1 remains in an activated state.

[0066] The control signal generation circuit 305 can generate a plurality of control signals S<1:2> in response to the first enable signal EN1 and the second enable signal EN2. The plurality of control signals S<1:2> can be activated in a predetermined sequence in each period between the first time point and the second time point. The sequence of activation can control different voltage division ratios of the voltage divider circuit.

[0067] The third enable signal EN3 can maintain an activated state between a first time point and a second time point, and the control signals S<1:2> generated by the control signal generating circuit 305 can be activated in a predetermined order in each period of the period between the first time point and the second time point. Therefore, the voltage divider circuit 304 (which operates in response to the third enable signal EN3 and the plurality of control signals S<1:2>) can output the second initial voltage VINI2 by dividing the potential level of the first initial voltage VINI1 by a first preset ratio. In one embodiment, during the activation period of the third enable signal EN3, the first preset ratio can be changed in response to the plurality of control signals S<1:2>. During the deactivation period of the third enable signal EN3, the voltage divider circuit 304 can output the first initial voltage VINI1 as the second initial voltage VINI2.

[0068] Figure 4 An embodiment of an initial voltage generating circuit 302 is shown. The initial voltage generating circuit 302 can be configured to include a resistor R1, a capacitor C1, an amplifier AMP1, a first switch SW1, and a second switch SW2. The resistor R1 has a first node coupled to a terminal of a reference (e.g., ground) voltage VSS and a second node coupled to a first node of the first switch SW1. The second node of the first switch SW1 is coupled to a first node of the second switch SW2, a first node of the capacitor C1, and a first input terminal (-) of the amplifier AMP1. The first switch SW1 can be controlled by a second enable signal EN2.

[0069] Amplifier AMP1 has a first input terminal (-), a second input terminal (+), and an output terminal. The first input terminal (-) is coupled to the second node of the first switch SW1, the first node of the second switch SW2, and the first node of the capacitor C1; the second input terminal (+) is coupled to a terminal of a first reference voltage VREF1; and the output terminal is coupled to a second node of the second switch SW2, a second node of the capacitor C1, and a terminal of a first initial voltage VINI1. Amplifier AMP1 can be controlled by a first enable signal EN1.

[0070] A first node of the capacitor C1 is coupled to a second node of the first switch SW1, a first node of the second switch SW2 and a first input terminal (-) of the amplifier AMP1; and a second node of the capacitor C1 is coupled to a second node of the second switch SW2, an output terminal of the amplifier AMP1 and a terminal of the first initial voltage VINI1.

[0071] A first node of the second switch SW2 is coupled to the second node of the first switch SW1, the first node of the capacitor C1, and the first input terminal (-) of the amplifier AMP1; and a second node of the second switch SW2 is coupled to the second node of the capacitor C1, the output terminal of the amplifier AMP1, and the terminal of the first initial voltage VINI1. The second switch SW2 can be controlled by a power-on reset signal POR.

[0072] The operation of the initial voltage generating circuit 302 can be described as follows: When the second switch SW2 switches from a closed state to an open state as the power-on reset signal POR transitions from an active state to a deactivated state, the initial voltage generating circuit 302 may start operating.

[0073] During the period in which the first enable signal EN1 is activated as the power-on reset signal POR transitions and the second enable signal EN2 remains in a deactivated state (e.g., during the period between the first time point and the second time point), the amplifier AMP1 begins operating. However, at this time, the first switch SW1 is in an off state. Therefore, only the output terminal of the amplifier AMP1 and the terminal of the first initial voltage VINI1 can be coupled to the first input terminal (-) of the amplifier AMP1, with the capacitor C1 inserted therebetween. In other words, the resistor R1 may not be coupled to the first input terminal (-) of the amplifier AMP1.

[0074] A terminal of the first reference voltage VREF1 may be coupled to the second input terminal (+) of the amplifier AMP1. Thus, the amplifier AMP1 may operate as a unity gain buffer during a period between the first time point and the second time point. For example, during a period between the first time point and the second time point, the amplifier AMP1 may buffer the first reference voltage VREF1 received through the second input terminal (+), and may output the buffered first reference voltage VREF1 as the first initial voltage VINI1.

[0075] During a period in which both the first enable signal EN1 and the second enable signal EN2 are activated (for example, during a period after the second time point), the first switch SW1 is switched to a closed state. Therefore, not only the output terminal of the amplifier AMP1 and the terminal of the first initial voltage VINI1 can be coupled to the first input terminal (-) of the amplifier AMP1 (with the capacitor C1 inserted therebetween), but also the resistor R1 can be coupled to the first input terminal (-) of the amplifier AMP1. Therefore, during the period after the second time point, the amplifier AMP1 can operate as an integration circuit. For example, during the period after the second time point, the amplifier AMP1 can output the first initial voltage VINI1 (whose potential level rises at a constant slope) by integrating the difference in potential level between the ground voltage VSS received through the first input terminal (-) and the first reference voltage VREF1 received through the second input terminal (+).

[0076] Figure 5 One embodiment of a voltage divider circuit 304 is illustrated, and the voltage divider circuit 304 may be configured to include a third switch SW3 , a fourth switch SW4 , a fifth switch SW5 , a sixth switch SW6 , a second resistor R2 , a third resistor R3 , and a fourth resistor R4 .

[0077] A first node of the third switch SW3 is coupled to a terminal of the first initial voltage VINI1 and a first node of the fourth switch SW4; and a second node of the third switch SW3 is coupled to a terminal of the second initial voltage VINI2, a second node of the fifth switch SW5, and a second node of the sixth switch SW6. The third switch SW3 can be controlled by a second enable signal EN2.

[0078] A first node of the fourth switch SW4 is coupled to a terminal of the first initial voltage VINI1 and a first node of the third switch SW3; and a second node of the fourth switch SW4 is coupled to a first node of the second resistor R2. The fourth switch SW4 may be controlled by a third enable signal EN3.

[0079] A first node of the fifth switch SW5 is coupled to the second node of the second resistor R2 and the first node of the third resistor R3; and a second node of the fifth switch SW5 is coupled to a terminal of the second initial voltage VINI2, a second node of the third switch SW3, and a second node of the sixth switch SW6. The fifth switch SW5 can be controlled by the second control signal S2 among the plurality of control signals S<1:2>.

[0080] A first node of the sixth switch SW6 is coupled to the second node of the third resistor R3 and the first node of the fourth resistor R4; and a second node of the sixth switch SW6 is coupled to a terminal of the second initial voltage VINI2, a second node of the third switch SW3, and a second node of the fifth switch SW5. The sixth switch SW6 can be controlled by a first control signal S1 among a plurality of control signals S<1:2>.

[0081] A first node of the second resistor R2 is coupled to a second node of the fourth switch SW4 ; and a second node of the second resistor R2 is coupled to a first node of the fifth switch SW5 and a first node of the third resistor R3 .

[0082] A first node of the third resistor R3 is coupled to a first node of the fifth switch SW5 and a second node of the second resistor R2 ; and a second node of the third resistor R3 is coupled to a first node of the sixth switch SW6 and a first node of the fourth resistor R4 .

[0083] A first node of the fourth resistor R4 is coupled to a first node of the sixth switch SW6 and a second node of the third resistor R3 ; and a second node of the fourth resistor R4 is coupled to a terminal of the ground voltage VSS.

[0084] The operation of the voltage divider circuit 304 can be described as follows. During the period in which the third enable signal EN3 maintains an active state and the second enable signal EN2 maintains a deactivated state (e.g., during the period between the first time point and the second time point), the third switch SW3 is in an open state and the fourth switch SW4 is in a closed state. Therefore, the terminal for the first initial voltage VINI1 and the terminal for the second initial voltage VINI2 are not coupled to each other, and the terminal for the first initial voltage VINI1 is coupled to the first node of the second resistor R2.

[0085] Between a first time point (at which the third enable signal EN3 is activated) and a second time point (at which the third enable signal EN3 is deactivated), the plurality of control signals S<1:2> may be activated in a predetermined order in a period between the first time point and the second time point. According to one embodiment, it may be assumed that the first control signal S1 among the plurality of control signals S<1:2> is first activated at the first time point, and then the first control signal S1 is deactivated and the second control signal S2 is activated at an intermediate time point between the first time point and the second time point.

[0086] Therefore, the second initial voltage VINI2 can be output by dividing the potential level of the first initial voltage VINI1 by a first preset ratio. During the period between the first time point and the second time point, the potential level of the first initial voltage VINI1 can change based on the changing state of the control signals S<1:2>. In other words, changing the activation order of the control signals S<1:2> changes the voltage division ratio of the voltage divider circuit, which in turn changes the potential level of the first initial voltage VINI1. After the second time point, the first initial voltage VINI1 can be output as the second initial voltage VINI2.

[0087] More specifically, according to one embodiment, during a period in which the first control signal S1 among the plurality of control signals S<1:2> is activated and the second control signal S2 is deactivated, the second initial voltage VINI2 may be output by dividing the potential level of the first initial voltage VINI1. The potential level of the first initial voltage VINI1 may be divided by applying a voltage division ratio determined according to a difference between the total resistance value of the second resistor R2 and the third resistor R3 and the resistance value of the fourth resistor R4 as a first preset ratio.

[0088] During a period in which the second control signal S2 among the plurality of control signals S<1:2> is activated and the first control signal S1 is deactivated, the second initial voltage VINI2 can be output by dividing the potential level of the first initial voltage VINI1. The second initial voltage VINI2 can be divided by applying a voltage division ratio determined according to a difference between the total resistance value of the third resistor R3 and the fourth resistor R4 and the resistance value of the second resistor R2 as a first preset ratio.

[0089] In a case where the second resistor R2, the third resistor R3 and the fourth resistor R4 all have the same value, the level of the second initial voltage VINI2 (output during a period in which the first control signal S1 among the multiple control signals S<1:2> is activated and the second control signal S2 among the multiple control signals S<1:2> is deactivated) will be relatively lower than the level of the second initial voltage VINI2 output during a period in which the second control signal S2 among the multiple control signals S<1:2> is activated and the first control signal S1 among the multiple control signals S<1:2> is deactivated.

[0090] Figure 6 The selection circuit 306 includes a comparator AMP2 and a multiplexer MUX1. The comparator AMP2 generates a selection signal VTEM based on a result of comparing the potential level of the feedback voltage VFEED with the potential level of the second reference voltage VREF2.

[0091] The multiplexer MUX1 can receive a second initial voltage VINI2 and a second reference voltage VREF2, and can select and output either the second initial voltage VINI2 or the second reference voltage VREF2 in response to a selection signal VTEM. For example, the comparator AMP2 has a first input terminal (-) coupled to a terminal of the feedback voltage VFEED, a second input terminal (+) coupled to a terminal of the second reference voltage VREF2, and an output terminal coupled to a terminal of the selection signal VTEM. The comparator AMP2 can be controlled by a first enable signal EN1.

[0092] The multiplexer MUX1 has a first input terminal coupled to a second initial voltage VINI2, a second input terminal coupled to a second reference voltage VREF2, and an output terminal coupled to an output voltage VSEL. The multiplexer MUX1 may be controlled by a selection signal VTEM.

[0093] The operation of the selection circuit 306 can be described as follows. The comparator AMP2 can be activated in response to the first enable signal EN1, can receive and compare the feedback voltage VFEED and the second reference voltage VREF2, and can generate and output the selection signal VTEM based on the comparison result. For example, when the potential level of the feedback voltage VFEED is higher than the potential level of the second reference voltage VREF2, the comparator AMP2 can generate and output the selection signal VTEM having a first logic level (e.g., a low level); and when the potential level of the feedback voltage VFEED is lower than the potential level of the second reference voltage VREF2, the comparator AMP2 can generate and output the selection signal VTEM having a second logic level (e.g., a high level).

[0094] The multiplexer MUX1 can receive the second initial voltage VINI2 and the second reference voltage VREF2, and can select and output the second initial voltage VINI2 or the second reference voltage VREF2 as the output voltage VSEL in response to a selection signal VTEM. For example, when the selection signal VTEM is at a first logic level, the multiplexer MUX1 can select and output the second reference voltage VREF2 as the output voltage VSEL. Conversely, when the selection signal VTEM is at a second logic level, the multiplexer MUX1 can select and output the second initial voltage VINI2 as the output voltage VSEL.

[0095] In other words, when the potential level of the second reference voltage VREF2 is higher than the potential level of the feedback voltage VFEED, the selection circuit 306 can output the second initial voltage VINI2 as the output voltage VSEL; and when the potential level of the second reference voltage VREF2 is lower than the potential level of the feedback voltage VFEED, the selection circuit 306 can output the second reference voltage VREF2 as the output voltage VSEL.

[0096] Figure 7 The figure shows one embodiment of the voltage generation circuit 308, which may include an amplifier AMP3, a current supply circuit 702, and a voltage divider circuit 704. The amplifier AMP3 may begin operating in response to a first enable signal EN1 and may generate and output a drive control signal DCS by comparing an output voltage VSEL with a feedback voltage VFEED (output from the voltage divider circuit 704). For example, when the potential level of the output voltage VSEL is higher than the potential level of the feedback voltage VFEED, the amplifier AMP3 may generate and output the drive control signal DCS having a first logic level (e.g., a low level); and when the potential level of the output voltage VSEL is lower than the potential level of the feedback voltage VFEED, the amplifier AMP3 may generate and output the drive control signal DCS having a second logic level (e.g., a high level).

[0097] The current supply circuit 702 can apply the external power supply voltage VCCE to the output node NA or block the external power supply voltage VCCE in response to a drive control signal DCS. For example, the current supply circuit 702 can be configured by a PMOS transistor PM1 coupled between the output node NA and a terminal to which the external power supply voltage VCCE is applied. The PMOS transistor PM1 can be turned on or off in response to the drive control signal DCS and can apply the external power supply voltage VCCE to the output node NA or block the external power supply voltage VCCE.

[0098] The voltage divider circuit 704 may be coupled between the output node NA and a terminal for the ground voltage VSS. The voltage divider circuit 704 may generate a feedback voltage VFEED by dividing the potential level of the output node NA (i.e., the internal voltage VCCI). For example, the voltage divider circuit 704 may be configured to include a fifth resistor R5 and a sixth resistor R6, which are coupled in series between the output node NA and the terminal for the ground voltage VSS. The voltage divider circuit 704 may divide the internal voltage VCCI according to a ratio corresponding to the difference between the resistance value of the fifth resistor R5 and the resistance value of the sixth resistor R6 (e.g., a second preset ratio), and thereby output the feedback voltage VFEED through a node NB between the fifth resistor R5 and the sixth resistor R6.

[0099] When the internal voltage VCCI generated by the voltage generation circuit 308 is lower than the target potential level, the feedback voltage VFEED (generated by dividing the internal voltage VCCI) can have a potential level lower than the output voltage VSEL. Therefore, the amplifier AMP3 can output the drive control signal DCS having a first logic level, and the current supply circuit 702 can increase the potential level of the internal voltage VCCI by applying the external power supply voltage VCCE to the output node NA in response to the drive control signal DCS. When the internal voltage VCCI is higher than the target potential level, the feedback voltage VFEED (generated by dividing the internal voltage VCCI) can have a potential level higher than the output voltage VSEL. As a result, the amplifier AMP3 can output the drive control signal DCS having a second logic level, and the current supply circuit 702 can block the external power supply voltage VCCE from being applied to the output node NA in response to the drive control signal DCS. Therefore, the potential level of the internal voltage VCCI can no longer rise and can be maintained at a constant level.

[0100] In the voltage generating circuit 308, the capacitor C2 may be coupled to the output node NA, and the internal voltage VCCI is output from the output node NA. This can stabilize the level change of the internal voltage VCCI. As the size of the capacitor C2 coupled to the output node NA increases, the level change of the internal voltage VCCI can be stably maintained. However, this may Figure 1 This can cause problems in the internal voltage generation circuit. For example, during the initial operation of the internal voltage generation circuit, the instantaneous current consumption may increase due to the generation of the internal voltage. This in turn may cause an increase in peak current.

[0101] Figure 8 One embodiment of a waveform diagram including signals used to generate internal voltages in a memory device as described herein is illustrated.

[0102] refer to Figure 8 , the level of the external power supply voltage VCCE may start to rise from the power-on time point (A) when power is supplied to the memory device 150. When it is detected that the level of the external power supply voltage VCCE has risen above a preset level, the logic level of the power-on reset signal POR may transition to a low level.

[0103] The time point (B) at which the logic level of the power-on reset signal POR changes can be defined as a first time point. From the power-on time point (A) to the time point (B) at which the logic level of the power-on reset signal POR changes, the various signals EN1, EN2, EN3, S1, S2, VINI2, and VFEED used within the memory device 150 can maintain a state in which they are locked to an initial logic level or a predetermined logic level. In the case of the second reference voltage VREF2 (generated by the reference voltage generation circuit 206 configured using a bandgap reference circuit) and the selection signal VTEM (directly affected by the level change of the second reference voltage VREF2), when the potential level of the external power supply voltage VCCE rises between the power-on time point (A) and the time point (B) at which the logic level of the power-on reset signal POR changes, the potential levels of the second reference voltage VREF2 and the selection signal VTEM can rise together.

[0104] For reference, the change in the level of the second reference voltage VREF2 is described as an example in which the level of the reference voltage increases as the level of the external power supply voltage VCCE increases. However, this is for ease of explanation, and in one embodiment, the level of the first reference voltage VREF1 may also increase similarly to the second reference voltage VREF2. In one embodiment, the level of the first reference voltage VREF1 may be set to be lower than or equal to the level of the second reference voltage VREF2.

[0105] At a time point (B) (eg, a first time point) at which a logic level of the power-on reset signal POR transitions, the first and third enable signals EN1 and EN3 may be activated.

[0106] At a time point (D) that is later in time by a preset delay amount than a time point (B) at which the logic level of the power-on reset signal POR transitions, the logic level of the delayed signal POR_DEL of the power-on reset signal POR may transition. The time point (D) at which the logic level of the delayed signal POR_DEL of the power-on reset signal POR transitions may correspond to a second time point.

[0107] At a time point (D) at which a logic level of the delay signal POR_DEL of the power-on reset signal POR transitions (eg, at a second time point), the second enable signal EN2 may be activated and the third enable signal EN3 may be deactivated.

[0108] At least one intermediate time point (C) can be selected between the time point (B) at which the logic level of the power-on reset signal POR is converted and the time point (D) at which the logic level of the delay signal POR_DEL of the power-on reset signal POR is converted, for example, between the first time point and the second time point.

[0109] Based on the intermediate time point (C) selected in this manner, the plurality of control signals S<1:2> can be sequentially activated in a predetermined order. For example, assuming there is an intermediate time point (C), from the time point (B) at which the logic level of the power-on reset signal POR transitions (e.g., the first time point) to the intermediate time point (C), the first control signal S1 among the plurality of control signals S<1:2> can be activated. Subsequently, from the intermediate time point (C) to the second time point, the second control signal S2 among the plurality of control signals S<1:2> can be activated.

[0110] Although the figure illustrates that only one intermediate time point (C) is selected between the first time point and the second time point, this is because it is assumed that the plurality of control signals S<1:2> include two signals, namely, the first control signal S1 and the second control signal S2. When more control signals are included, more intermediate time points can be selected.

[0111] As mentioned above Figures 1 to 3 and Figure 7 As described, multiple internal voltage generating circuits may be included in one memory device 150. Each internal voltage generating circuit may include a voltage generating circuit 308 and a capacitor C2, wherein the voltage generating circuit 308 is configured to directly drive and generate the internal voltage VCCI, and the capacitor C2 is configured to stabilize the potential level of the internal voltage VCCI at the output node NA of the voltage generating circuit 308.

[0112] However, when the voltage generating circuit 308 is initialized during the initial operation period of the internal voltage generating circuit (e.g., between the first time point and the second time point), the level of the output voltage VSEL input to the voltage generating circuit 308 may suddenly increase, which in turn may suddenly increase the level of the internal voltage VCCI generated by the voltage generating circuit 308. When the level of the internal voltage VCCI suddenly increases in this manner, at the output terminal of the internal voltage VCCI, the peak current may increase more significantly due to the presence of the capacitor C2.

[0113] For example, from Figure 8 As can be seen from the example, at the first time point, a sudden increase (e.g., see the dotted line) may occur in the potential level of the output voltage VSEL input to the voltage generating circuit 308 (which only reflects the rise in the level of the first initial voltage VINI1). This may significantly increase the instantaneous current consumption of the external power supply voltage VCCE.

[0114] According to one or more embodiments, the internal voltage generating circuit 204 can control the level of the second initial voltage VINI2 and the level of the feedback voltage VFEED to rise between the first time point and the second time point in a step-wise manner (or a more gradual manner different from the step-wise manner) over a plurality of time periods (solid line). In other words, as described above with reference to Figure 3 As described, in one embodiment, the voltage divider circuit 304 can perform an operation of determining the potential level of the second initial voltage VINI2 by dividing the potential level of the first initial voltage VINI1 by a first preset ratio (for example, the first preset ratio can be changed between the first time point and the second time point), and output the first initial voltage VINI1 as the second initial voltage VINI2 after the second time point.

[0115] Therefore, according to one or more embodiments, the internal voltage generating circuit 204 can control the potential level of the second initial voltage VINI2 and the potential level of the feedback voltage VFEED to rise in a step-like manner (or a more gradual manner different from the step-like manner) over multiple time periods between the first time point and the second time point. As a result, any increase in the instantaneous current consumption of the external power supply voltage VCCE can be controlled to increase little by little (e.g., more gradually or at a lower rate than a predetermined rate) in a distributed manner over multiple time periods (e.g., solid line). According to one embodiment, the internal voltage generating circuit 204 can control the potential level of the second initial voltage VINI2 and the potential level of the feedback voltage VFEED to rise at a constant slope after the second time point.

[0116] The selection circuit 306 and the voltage generation circuit 308 in the internal voltage generation circuit 204 can compare the potential level of the second reference voltage VREF2 with the potential level of the feedback voltage VFEED during the period between the first time point and the second time point, and even after the second time point. The voltage generation circuit 308 can then determine the potential level of the internal voltage VCCI based on the comparison result. In one embodiment, the operation of determining the potential level of the internal voltage VCCI in this manner can be performed until the time point (E) (e.g., the third time point), at which the potential level of the second reference voltage VREF2 and the potential level of the feedback voltage VFEED become equal to each other.

[0117] For example, from the first time point to the third time point, the level of the internal voltage VCCI may be determined to correspond to the level change of the feedback voltage VFEED, thereby having a relatively low potential level between the second reference voltage VREF2 and the feedback voltage VFEED. For example, from the first time point to the second time point, the potential level of the internal voltage VCCI may also increase in a stepwise manner over multiple time periods, corresponding to the potential level of the feedback voltage VFEED increasing in a stepwise manner over multiple time periods.

[0118] In addition, from the second time point to the third time point, the potential level of the internal voltage VCCI may also increase at a constant slope, corresponding to the potential level of the feedback voltage VFEED increasing at a constant slope.

[0119] After a third time point (e.g., after a time point (E) at which the potential levels of the second reference voltage VREF2 and the feedback voltage VFEED become equal to each other), the potential level of the internal voltage VCCI may be determined based on the potential level of the second reference voltage VREF2. For example, after the third time point, the potential level of the internal voltage VCCI may be stably maintained to correspond to the second reference voltage VREF2, and even if the PVT changes, the second reference voltage VREF2 maintains a stable potential level.

[0120] Method described herein, process and / or operation can be performed by code or the instruction to be performed by computer, processor, controller or other signal processing equipment.Computer, processor, controller or other signal processing equipment can be those described herein or the element except the element described herein.Because the algorithm of the basis of formation method (or the operation of computer, processor, controller or other signal processing equipment) is described in detail, so the code or the instruction for realizing the operation of method embodiment can be transformed into the special-purpose processor for performing the method herein by computer, processor, controller or other signal processing equipment.

[0121] When implemented at least in part with software, controller, processor, device, module, unit, multiplexer, generator, logic, interface, decoder, driver, generator and other signal generation and signal processing features may include: for example, for storing the code or instruction to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing equipment or a memory or other storage device. The computer, processor, microprocessor, controller or other signal processing equipment may be those described herein or elements except the elements described herein. Because the algorithm forming the basis of the method (or the operation of a computer, processor, microprocessor, controller or other signal processing equipment) is described in detail, the code or instruction for realizing the operation of the method embodiment can be used to transform a computer, processor, controller or other signal processing equipment into a special-purpose processor for performing the method described herein.

[0122] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. For example, the positions and types of logic gates and transistors described as examples in the above embodiments should be implemented differently depending on the polarity of the signals input thereto. The embodiments may be combined to form additional embodiments.

Claims

1. An internal voltage generator, comprising: a first voltage generator configured to generate a first initial voltage by buffering a first reference voltage input from a first time point to a second time point, and to generate the first initial voltage by integrating a difference between a predetermined reference voltage and the first reference voltage input after the second time point, wherein the first time point is after a power-on time point and the second time point is after the first time point; a voltage divider configured to output a second initial voltage by dividing the potential level of the first initial voltage by a first preset ratio from the first time point to the second time point, and output the first initial voltage as the second initial voltage after the second time point; a selector configured to select and output the second initial voltage or the second reference voltage based on a comparison between a potential level of the feedback voltage and a potential level of the second reference voltage; as well as A second voltage generator is configured to generate an internal voltage by receiving or blocking an external power supply voltage according to a result of comparing a potential level of the output voltage of the selector and a potential level of the feedback voltage, and to generate the feedback voltage by dividing the internal voltage at a second preset ratio.

2. The internal voltage generator according to claim 1 , wherein the voltage divider is coupled to the output terminal of the first voltage generator and outputs the second initial voltage by dividing the potential level of the first initial voltage by the first preset ratio, and the first preset ratio is changed to different voltage division ratios in a predetermined order within a plurality of time periods between the first time point and the second time point.

3. The internal voltage generator according to claim 2 , further comprising an enable signal generator, wherein the enable signal generator is configured to: generating a first enable signal, a second enable signal, and a third enable signal in response to a power-on reset signal, At the first time point when the potential level of the external power supply voltage rises above a preset level, activating the first enable signal, activating the second enable signal at the second time point later than the first enable signal by a preset delay amount, and The third enable signal is generated, and the third enable signal maintains an active state between the first time point and the second time point.

4. The internal voltage generator according to claim 3 , wherein the first voltage generator is configured as: buffering the first reference voltage in response to activation of the first enable signal, and In response to activation of the second enable signal, the first initial voltage having a potential level rising at a constant slope is generated by integrating a difference between the first reference voltage and the predetermined reference voltage.

5. The internal voltage generator according to claim 3 , further comprising: A control signal generator is configured to generate a plurality of control signals in response to the first enable signal and the second enable signal, the plurality of control signals being activated in the predetermined order in each of the plurality of time periods.

6. The internal voltage generator according to claim 5 , wherein the voltage divider is configured as: outputting the second initial voltage by dividing the potential level of the first initial voltage at the first preset ratio during an activation period of the third enable signal, the first preset ratio being changed to different voltage division ratios based on the plurality of control signals, and During a deactivation period of the third enable signal, the first initial voltage is output as the second initial voltage.

7. The internal voltage generator according to claim 1 , wherein the selector is configured to: outputting the second initial voltage from the first time point to a third time point at which the potential level of the feedback voltage and the potential level of the second reference voltage become equal to each other, and After the third time point, the second reference voltage is output, and the third time point is later than the second time point. 8 . The internal voltage generator according to claim 7 , wherein the second initial voltage from the first time point to the third time point has a lower potential level than the second reference voltage.

9. The internal voltage generator according to claim 7, wherein the second voltage generator is configured to: receiving the second initial voltage from the selector from the first time point to the third time point, and Based on the comparison between the potential level of the second initial voltage and the potential level of the feedback voltage, the potential level of the internal voltage is increased.

10. An internal voltage generator comprising: a first voltage generator configured to generate a first initial voltage by buffering a first reference voltage input from a first time point to a second time point, and to generate the first initial voltage by integrating a difference between a predetermined reference voltage and the first reference voltage input after the second time point, wherein the first time point is after a power-on time point and the second time point is after the first time point; an enable signal generator configured to generate a first enable signal, a second enable signal, and a third enable signal in response to a power-on reset signal, activate the first enable signal at the first time point when the potential level of the external power supply voltage rises above a preset level, activate the second enable signal at the second time point that is later than the first enable signal by a preset delay amount, and generate the third enable signal that maintains an active state between the first time point and the second time point; a control signal generator configured to generate a plurality of control signals in response to the first enable signal and the second enable signal, the plurality of control signals being activated in a predetermined order in each of a plurality of time periods; a voltage divider configured to output a second initial voltage by dividing a potential level of the first initial voltage at a first preset ratio that changes based on the plurality of control signals during an activation period of the third enable signal, and output the first initial voltage as the second initial voltage during a deactivation period of the third enable signal; as well as A second voltage generator is configured to generate an internal voltage by receiving or blocking the external power supply voltage according to a result of comparing the potential level of the feedback voltage with the potential level of one of the second initial voltage and the second reference voltage, and to generate the feedback voltage by dividing the internal voltage at a second preset ratio.

11. A semiconductor device comprising: a power-on reset circuit configured to detect a potential level of an external power supply voltage and generate a power-on reset signal converted at a first time point at which the potential level of the external power supply voltage rises above a preset level; a reference voltage generator configured to receive the external power supply voltage and generate a first reference voltage and a second reference voltage; as well as Internal voltage generator, configured as: starting operation in response to the power-on reset signal; outputting a second initial voltage by dividing a potential level of a first initial voltage generated by buffering the first reference voltage at a first preset ratio from the first time point to a second time point later than the first time point; After the second time point, outputting the first initial voltage having a potential level that rises at a constant slope as the second initial voltage by integrating the difference between the first reference voltage and the ground voltage; generating an internal voltage by receiving or blocking the external power supply voltage according to a result of comparing a potential level of a feedback voltage with a potential level of one of the second initial voltage and the second reference voltage, and The feedback voltage is generated by dividing the internal voltage at a second preset ratio.

12. The semiconductor device according to claim 11, wherein the internal voltage generator comprises: a first voltage generator configured to generate the first initial voltage by buffering the first reference voltage input from the first time point to the second time point, and to generate the first initial voltage having a potential level rising at a constant slope by integrating a difference between a predetermined reference voltage and the first reference voltage input after the second time point; a voltage divider configured to output the second initial voltage by dividing the potential level of the first initial voltage by the first preset ratio from the first time point to the second time point, and output the first initial voltage as the second initial voltage after the second time point; a selector configured to select and output the second initial voltage or the second reference voltage by comparing the potential level of the feedback voltage with the potential level of the second reference voltage; as well as a second voltage generator configured to generate the internal voltage by receiving or blocking the external power supply voltage according to a result of comparing the potential level of the output voltage of the selector and the potential level of the feedback voltage, and to generate the feedback voltage by dividing the internal voltage at the second preset ratio.

13. The semiconductor device according to claim 12 , wherein the voltage divider is coupled to the output terminal of the first voltage generator and outputs the second initial voltage by dividing the potential level of the first initial voltage by the first preset ratio, and the first preset ratio changes in a predetermined order within a plurality of time periods between the first time point and the second time point.

14. The semiconductor device according to claim 13, further comprising an enable signal generator, wherein the enable signal generator is configured to: generating a first enable signal, a second enable signal, and a third enable signal in response to the power-on reset signal, activating the first enable signal at the first time point, activating the second enable signal at the second time point later than the first enable signal by a preset delay amount, and The third enable signal is generated, and the third enable signal maintains an active state between the first time point and the second time point.

15. The semiconductor device according to claim 14, wherein the first voltage generator is configured to: generating the first initial voltage by buffering the first reference voltage in response to activation of the first enable signal, and In response to activation of the second enable signal, the first initial voltage having a potential level rising at a constant slope is generated by integrating a difference between the first reference voltage and the predetermined reference voltage.

16. The semiconductor device according to claim 14, further comprising: A control signal generator is configured to generate a plurality of control signals in response to the first enable signal and the second enable signal, the plurality of control signals being activated in the predetermined order in each of the plurality of time periods.

17. The semiconductor device according to claim 16, wherein the voltage divider is configured to: outputting the second initial voltage by dividing the potential level of the first initial voltage by the first preset ratio during an activation period of the third enable signal, the first preset ratio being changed based on the plurality of control signals, and During a deactivation period of the third enable signal, the first initial voltage is output as the second initial voltage.

18. The semiconductor device according to claim 12, wherein the selector is configured to: outputting the second initial voltage from the first time point to a third time point at which the potential level of the feedback voltage and the potential level of the second reference voltage become equal to each other, the third time point being later than the second time point, and After the third time point, the second reference voltage is output. 19 . The semiconductor device according to claim 18 , wherein the second initial voltage from the first time point to the third time point has a potential level lower than the second reference voltage.

20. The semiconductor device according to claim 18, wherein the second voltage generator is configured to: receiving the second initial voltage from the selector from the first time point to the third time point, and Based on the comparison between the potential level of the second initial voltage and the potential level of the feedback voltage, the potential level of the internal voltage is increased.

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