Content addressable memory and method of operation thereof

Abstract

A content addressable memory (CAM) device and method of operation thereof are provided. The CAM device includes a plurality of CAM sub-banks. Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned along the column dimension into a first stage and a second stage. Each CAM sub-bank includes a plurality of first stage match lines (MLs), a plurality of first stage search line (SL) pairs, a plurality of second stage MLs, a plurality of second stage SL pairs. The first stage MLs indicate whether a first portion of a search key matches a first stage row segment. Each second stage SL pair is coupled to a column of CAM cells of the second stage and is gated by a SL enable signal. The SL enable signal is deasserted when none of the plurality of first stage MLs indicate a match, thereby preventing a second portion of the search key from being provided to the plurality of second stage SL pairs.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to low power design of content addressable memory (CAM) devices. BACKGROUND

[0002] Content addressable memory (CAM) is commonly used in high speed search applications. CAM devices compare a search key with data stored in each row of a CAM cell array and return the address of the matching data. When used in network switches, CAMs can speed up the operation of routing table lookup and data forwarding.

[0003] In a CAM device, each CAM cell is coupled to a match line (ML) that spans the respective row and a search line pair (SL and SLB) that spans the respective column. The match lines and search lines consume the majority of the overall dynamic power; for example, up to 80% of the dynamic power. A common scenario for CAM applications is that most of the CAM rows do not hit when compared with the search key. Before the search, all match lines and all search line pairs are pre-charged. During the search, each search line pair (SL and SLB) is driven to opposite logic states (i.e., one logic high and the other logic low) according to the respective bits of the search key. Thus, one of SL and SLB is toggled every cycle. When a CAM row does not match the search key, the corresponding match line will be discharged (e.g., to ground voltage). If none of the CAM rows match, all match lines will charge and discharge every cycle, consuming maximum power.

[0004] Thus, reducing CAM power consumption is key to reducing the overall dynamic power of a network switch chip. SUMMARY

[0005] In view of the above, the present disclosure provides a novel content addressable memory (CAM) device and method of operation.

[0006] In one embodiment, a content addressable memory (CAM) device is provided. The CAM device includes a plurality of CAM sub-banks. Each CAM sub-bank includes an array of CAM cells arranged in rows and columns, the array of CAM cells being divided along a column dimension into a first stage and a second stage. Each CAM sub-bank further includes a plurality of first stage match lines (MLs), each first stage ML coupled to a first stage row segment of CAM cells and indicating whether a match of a first portion of a search key is found in the first stage row segment. Each CAM sub-bank further includes a plurality of first stage search line (SL) pairs in the first stage, and a plurality of second stage MLs, each second stage ML coupled to a second stage row segment of CAM cells. Each CAM sub-bank further includes a plurality of second stage SL pairs, each second stage SL pair coupled to a column of CAM cells in the second stage and gated by a SL enable signal. Each CAM sub-bank further includes circuitry for receiving the plurality of first stage MLs as input, and the circuitry deasserts the SL enable signal when none of the plurality of first stage MLs indicates a match, wherein deassertion of the SL enable signal prevents a second portion of the search key from being provided to the plurality of second stage SL pairs.

[0007] In another embodiment, a method of operating a CAM device is provided, performed by each CAM sub-bank of the CAM device. Each CAM sub-bank includes an array of CAM cells arranged in rows and columns, and each CAM sub-bank is divided along a column dimension into a first stage and a second stage. The method includes comparing a first portion of a search key to data stored in a first stage row segment of CAM cells; indicating by each first stage ML whether a match to the first portion of the search key is found in a corresponding first stage row segment; generating a SL enable signal based on a logical state of all first stage MLs, wherein the SL enable signal is a gating signal for a plurality of second stage SL pairs coupled to respective columns of CAM cells in the second stage; and deasserting the SL enable signal when none of the first stage MLs indicates a match, wherein deassertion of the SL enable signal prevents a second portion of the search key from being provided to the plurality of second stage SL pairs.

[0008] In the present invention, power is reduced by sub-bank level dynamically gated search lines technology, which can save a large amount of power of the CAM device, thereby improving the overall performance of the device.

[0009] The advantages of the present invention will be explained in detail in the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] The application is illustrated in the accompanying drawings, throughout which like reference characters signify like 5 elements, by way of examples and not limitation. It is to be expressly understood that the description of the applications is intended as an overview and as a summary of significant 10 features. It should be appreciated that many changes can be made to the details of the application without departing from its scope, which is defined by the appended claims. Moreover, the language used in this disclosure has been principally selected for readability and instructional purposes and can not have been selected to 15 delineate or circumscribe the patent rights in the art, resort to means which are already known, novel combinations of elements, equivalents, and / or integrations with other technologies as set forth in the following claims, unless otherwise indicated.

[0011] Figure 1 A CAM device according to one embodiment is illustrated.

[0012] Figure 2 A CAM device according to another embodiment is illustrated.

[0013] Figure 3 A sub-bank of a CAM device according to one embodiment is illustrated.

[0014] Figure 4 A line or circuit according to one embodiment is shown.

[0015] Figure 5 is a flowchart showing a process performed by a sub-bank of a CAM device according to one embodiment.

[0016] Figure 6 is a flowchart showing a method for dynamic strobe search lines in a sub-bank according to one embodiment. DETAILED DESCRIPTION

[0017] In the following description, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without the specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this application. It will be appreciated, however, by one of ordinary skill in the art that the application can be practiced without such specific details. Those of ordinary skill in the art, with the

[0018] Embodiments of the invention provide an ultra-low power content addressable memory (CAM) device. As used herein, the term "CAM" can encompass different types of CAMs, such as binary CAM, ternary CAM (TCAM), quaternary CAM (QCAM), or other types of CAMs. In one embodiment, the CAM device disclosed herein can be part of a system-on-a-chip (SOC), such as an SOC in a processing and / or communication device (e.g., a network device).

[0019] In one usage scenario, a CAM device can be used to store a lookup table in which to search for a matching entry using a search key. In the lookup table, a set of rules (e.g., access control (ACL) rules or other rules) can be stored in priority order. When multiple entries match the search key, the highest address of the matching entries is output as the match address. Correlated rules can be programmed to be adjacent to each other and occupy adjacent entries in the lookup table. Thus, if a given entry matches a search key representing a given rule, additional matches, if any, are likely to be found in the correlated rules stored adjacent to the given entry. For example, the additional matches can be found in entries of slightly higher or lower priority than the given entry, and thus the additional matches are stored near the given entry. Thus, there is often a pattern of spatial locality in search results. The sub-bank level dynamically gated search lines technique disclosed herein seeks to exploit the spatial locality of possible matches in a CAM device to reduce power.

[0020] The CAM device disclosed herein can include any number of memory banks and each memory bank is an array of CAM cells arranged in rows and columns. Each memory bank can be divided into a plurality of sub-banks along the row dimension. Each sub-bank can be further divided into at least two stages along the column dimension, where the second stage of a sub-bank is activated (i.e., enabled) for search only when a match is found in the first stage of the same sub-bank. The second stage search is conditionally enabled at the sub-bank level. That is, each sub-bank can enable or disable its second stage search independently of other sub-banks. The sub-bank level enablement takes advantage of the spatial locality described above because a matching entry is often found in the same sub-bank. A sub-bank whose first stage has no match can disable the search in the second stage. More specifically, a search enable signal is dynamically generated according to the search result of the first stage to gate the search lines in the second stage. When the search enable signal is de-asserted (e.g., is logic low) due to no match in the first stage, the second stage search lines are disabled from searching and the toggling described above. As a result, a significant amount of power can be saved, thus improving the overall performance of the device.

[0021] In the following description, the terms "connection," "coupling," and their derivatives, are used to refer to a relationship between two or more elements, where the elements can be directly in physical contact with each other or not in direct physical contact with each other, and where there can be an electrical connection between the elements. As such, the terms "connection" and "coupling" in the following description are equivalent to the terms "electrical connection" and "electrical coupling," respectively.

[0022] Figure 1 A CAM device 100 according to one embodiment is illustrated. The CAM device 100 includes a CAM bank 101 divided into four sub-banks (e.g., sub-bank 0, sub-bank 1, sub-bank 2, and sub-bank 3) along the row dimension. It can be appreciated that the CAM device 100 can include any number of CAM banks and each CAM bank can include a plurality of sub-banks, not limited to four. The CAM bank 101 has C columns of CAM cells, where C is equal to the number of bits of a search key to be compared with data stored in the CAM cells. In the example of four sub-banks, each sub-bank has R rows and C columns of CAM cells and the CAM bank 101 has (4 x R) rows and C columns.

[0023] In one embodiment, each sub - bank is further divided into multiple stages along the column dimension; for example, a first stage 110 and a second stage 120. The first stage 110 has C1 columns and the second stage 120 has C2 columns, where C1 + C2 = C. In one embodiment of the symmetric cell structure, C1 = C2; in an alternative embodiment of the asymmetric cell structure, C1 and C2 can be different numbers. The CAM library 101 with an asymmetric cell structure can have C1 < C2. As will be described in further detail below, when no match is found in the first stage 110 of the same sub - bank, the search lines in the second stage 120 can be disabled to save power. When most of the search results in the first stage 110 are mismatches, having a wider second stage (i.e., C1 < C2) can save more power than a symmetric cell structure (i.e., C1 = C2), because the wider second stage contains more search lines that can potentially be disabled. However, it should be understood that the dynamic gating of search lines technique described here applies to any positive integer values of C1 and C2.

[0024] The CAM device 100 also includes a search input register 170 that stores a search key to be compared with the data stored in the rows of the CAM cells. In Figure 1 the example, each row of the CAM cells in the sub - bank is divided into a first - stage row segment and a second - stage row segment. The first part of the search key (e.g., the first C1 bits) is compared with the data stored in the first - stage row segment, and the second part of the search key (e.g., the subsequent C2 bits) is compared with the data stored in the second - stage row segment. The search key is provided from the search input register 170 to the CAM cells of each sub - bank via a driver coupled to the sub - bank.

[0025] As will be described in detail with reference to Figure 3 and Figure 4 In the two stages 110 and 120 of the sub - bank, each CAM cell is coupled to a match line (ML) and two complementary search lines (SL) (referred to as a search line pair). Each ML is coupled to all the CAM cells in the same row segment, and each SL pair is coupled to the CAM cells in the same column. The ML in the first stage 110 is referred to as the first - stage ML (i.e., ML1), while the ML in the second stage 120 is referred to as the second - stage ML (i.e., ML2). The SL pair in the first stage 110 is referred to as the first - stage SL pair (i.e., SL1 and SLB1), while the SL pair in the second stage 120 is referred to as the second - stage SL pair (i.e., SL2 and SLB2).

[0026] In Figure 1In the example shown, the first stage driver (e.g., driver 01, driver 11, driver 21, or driver 31) receives the first portion of the search key and drives the first stage SL pair according to the bit value of the first portion of the search key. The second stage driver (e.g., driver 02, driver 12, driver 22, or driver 32) receives the second portion of the search key and drives the second stage SL pair according to the bit value of the second portion of the search key. For example, if the search key bit value is 1, the corresponding SL can be driven to a logic high and the SLB can be driven to a logic low. According to embodiments of the present application, when the first stage 110 of the same sub-bank asserts (e.g., logic high) the SL enable (SL_EN) signal, each second stage SL pair is enabled and driven to the opposite logic level according to the second portion of the search key. When the first stage 110 of the sub-bank de-asserts the SL_EN signal (e.g., SL_EN is at a logic low), the second stage SL pair of the same sub-bank is disabled and no comparison operation is performed in the second stage 120.

[0027] Figure 1 Further illustrated is the control circuit 150 between each pair of corresponding first stage 110 and second stage 120. In alternative embodiments, the control circuit 150 can be placed in other locations in the sub-bank than the locations shown in FIG. 1. In addition, different parts of the control circuit 150 can be placed in different or separate locations of the sub-bank. The control circuit 150 of each sub-bank includes circuit components and the like to generate the SL_EN signal for the sub-bank. Figure 1

[0028] In addition, the CAM device 100 includes an address decoder 160 and a match output circuit 180. The address decoder 160 includes circuitry to select a corresponding row of CAM cells for read, write, and / or other operations in response to an address received from an address bus or other circuitry. When a match occurs in the CAM bank 101, the match output circuit 180 generates a match signal to indicate the index of the row containing the matching entry.

[0029] In some embodiments, each of the first stage 110 and the second stage 120 in a sub-bank can be further divided into multiple CAM blocks (e.g., in this example, two CAM blocks for each stage). In Figure 1 ​This partitioning is indicated by dashed lines in each stage. For example, the first stage 110 of Sub-Bank 0 can include a left CAM block and a right CAM block, each block having (C1 / 2) columns and R rows of CAM cells. In the left CAM block, the left half row segment of CAM cells is coupled to a left ML, while in the right CAM block the corresponding right half row segment is coupled to a right ML. The signals on the left ML and the right ML are combined (e.g., by an AND gate) to generate the first stage ML signal for that row segment. The second stage 120 of Sub-Bank 0 can be similarly partitioned into left and right blocks. It should be understood that each stage of a sub-bank can be partitioned into any number of blocks having any block width (i.e., number of columns), as determined by the circuit design. In the following description, when such block partitioning is used, the terms "first stage ML" and "second stage ML" refer to the combined left and right MLs in the first and second stages, respectively.

[0030] Figure 2 A CAM device 200 is illustrated in accordance with another embodiment, in which the CAM bank 202 is partitioned into four sub-banks. The operations performed by the CAM device 200 and the signals generated by the CAM bank 202 are the same as for the CAM device 100 and the CAM bank 101. However, the arrangement of drivers in the CAM device 200 is different from the arrangement of drivers in the CAM device 100. More specifically, in the CAM device 100, the drivers for Sub-Bank 0 and Sub-Bank 1 are next to each other, and the drivers for Sub-Bank 2 and Sub-Bank 3 are next to each other. In the CAM device 200, the drivers for Sub-Bank 1 and Sub-Bank 2 are next to each other, while the drivers for Sub-Bank 0 and Sub-Bank 3 are separate from the other drivers. In alternative embodiments, the arrangement of drivers in each sub-bank can be different from that shown in Figure 1 and Figure 2 It can be appreciated that the disclosed techniques of dynamically strobing search lines can be applied to different arrangements of drivers in a CAM device.

[0031] Figure 3 Further details of a sub-bank 300 in accordance with an embodiment are illustrated. The sub-bank 300 can be any one of the sub-banks shown in Figure 1 and Figure 2 The sub-bank 300 includes a first stage 110, a second stage 120, and a first stage pre-charge (PRCHG) circuit 361, a second stage PRCHG circuit 362, and an enable generation circuit 380. The first stage 110 includes a CAM cell array 310, and the second stage 120 includes a CAM cell array 320. For simplicity, not all of the CAM cell rows and CAM cell columns are shown in the first stage 110 and the second stage 120.

[0032] Each CAM cell (310 and 320) is located in a row segment and a column. Each CAM cell is coupled to a match line (ML) and a search line pair (SL and SLB). Within the sub-bank 300, each first stage ML (i.e., ML1) is coupled to all CAM cells 310 in the same first stage row segment, and each second stage ML (i.e., ML2) is coupled to all CAM cells 320 in the same second stage row segment. Each first stage SL pair (SL1 and SLB1) is coupled to all CAM cells 310 in the same column of the first stage 110, and each second stage SL pair (e.g., SL2 and SLB2) is coupled to all CAM cells 320 in the same column of the second stage 120. A search key is a combination of data D1_in and D2_in input to the first stage 110 and the second stage 120, respectively. For illustration purposes, D2_in(k) represents one search key bit input to the second stage 120. First stage drivers 331 and second stage drivers 332 drive the respective SL pairs according to the respective data input values.

[0033] The first stage PRCHG circuit 361, the second stage PRCHG circuit 362, and the enable generation circuit 380 can be part of the control circuit 150 in Figure 1 and Figure 2 In alternative embodiments, the arrangement of these circuits 361, 362, 380 can be different from that shown in Figure 3 For simplicity, Figure 3 not all clock signals are shown in the example of

[0034] For each row segment in the first stage 110, the first stage PRCHG circuit 361 includes an AND gate 365 to receive a pre-charge (PRCHG) signal and a valid bit (VBIT) indicator for a particular row. The VBIT indicator indicates whether the data stored in the respective row is valid. The VBIT indicator gates / controls the pre-charge of the first stage ML. Using the top row segment as an example, when VBIT(0) is logic high, the corresponding first stage ML (i.e., ML1(0)) is pre-charged to logic high. If the first part of the search key matches the data stored in the top row segment of the CAM cells 310, ML1(0) remains high and is passed through the corresponding flip-flop (e.g., D flip-flop 352) in the next clock to be used as the ML enable signal (ML_EN(0)) for the top row segment in the second stage 120. The VBIT indicator can not be included in the first stage PRCHG circuit 361 in alternative embodiments.

[0035] For each row segment in the second stage 120, the second stage PRCHG circuit 362 includes an AND gate 366 to receive the PRCHG signal and the ML_EN signal for the corresponding row segment. A logic high state of the ML_EN signal indicates a match in the corresponding row segment in the first stage 110. For example, ML_EN(0) enables ML2(0) to be pre-charged to a logic high level before the second portion search key is searched in the second stage 120.

[0036] A wired-OR circuit 370 receives inputs from ML1 of all R row segments in the first stage 110 and performs a logical OR operation on all ML1. The output of the wired-OR circuit 370 is passed through a D flip-flop 372 in the next clock to be the SL enable (SL_EN) signal for the second stage 120. Note that each sub-bank generates its own SL_EN according to the match result in the first stage of that sub-bank. That is, the SL_EN is a sub-bank level enable signal. An asserted (e.g., logic high) SL_EN signal enables the search (i.e., comparison) operation in the second stage 120. The SL_EN signal is a strobe signal at the input of the second stage driver 332. An asserted SL_EN indicates that there is a match in one or more row segments in the first stage 110 and enables the second portion search key to be passed forward to the second stage SL pair. The second stage driver 332 includes a pair of 3-input AND gates (e.g., AND gates 381 and 382) for each second stage SL pair. The AND gate 381 receives SL_EN, a clock signal CCLK, and a search key bit D2_in(k) as inputs, and the AND gate 382 receives SL_EN, the clock signal CCLK, and an inverted search key bit as inputs.

[0037] Figure 4 Further details of the wired-OR circuit 370 are shown in accordance with one embodiment. For simplicity of illustration, not all rows and columns of CAM cells are shown in the first stage 110 and the second stage 120. The wired-OR circuit 370 includes R row switches 375, which are followed by an inverter 376. The switches 375 are connected in parallel, all of their output terminals are connected to each other, and all of their input terminals are connected to ground. The gate terminal of each switch 375 is connected to the corresponding ML1 in the same row segment. Take the top row segment as an example. When a match is found in the top row segment of the first stage 110, ML1(0) is in a logic high state. The corresponding switch 375 turns on, causing its output terminal to be pulled down to ground. When any switch 375 turns on, all output terminals of all switches 375 are pulled to a logic low state (e.g., ground), and the inverter 376 outputs the SL_EN signal with a logic high state (i.e., an asserted SL_EN).

[0038] Thus, the line or circuit 370 performs a Boolean OR operation on all the first stage MLs. Having one or more first stage row segments with a logical high ML1 enables the line or circuit 370 to enable the SL_EN. When there is no logical high ML1 in the first stage row segment (i.e., no match in the first stage 110), the SL_EN is disabled. The search key input to the second stage 120 is gated by the SL_EN and a clock signal (CCLK). Thus, when there is no match in the first stage 110, no search can be performed in the second stage 120.

[0039] Figure 4 Some of the clock signal connections in the sub-bank 300 are shown in dashed lines. For example, the line or circuit 370 can be gated at the input (i.e., ML1) and the output (i.e., at the inverter 376) by a clock signal (DCLK). All the D flip-flops 352 can be gated by another clock signal (CK). In addition, the first stage driver 331 and the second stage driver 332 can be gated by another clock signal (CCLK). It can be appreciated that the dynamic gating search line technique can be applied to sub-banks that use different clock signals.

[0040] Figure 5 FIG. 5 is a flowchart illustrating a process 500 performed by a sub-bank of a CAM device, according to one embodiment. Figures 1 to 4Some examples of sub-banks are provided. At step 510, first stage MLs (e.g., ML1) and first stage SL pairs (e.g., SL1 and SLB1) are pre-charged (e.g., to logic high). In some embodiments, the pre-charged ML1 corresponds to a valid CAM row entry as indicated by the corresponding VBIT indicator. At step 520, the first stage drivers drive each first stage SL pair to opposite logic levels according to the first portion search key. For example, if the first bit of the search key is 1, then SL1 and SLB1 of the first column can be driven to high logic state and low logic state, respectively. If the first bit of the search key is 0, then SL1 and SLB1 of the first column can be driven to low logic state and high logic state, respectively. At step 530, the first portion search key is compared with the data stored in the first stage row segments; for example, each first stage CAM cell compares its stored value with the logic levels of the corresponding SL pair. At step 540, the ML_EN of the row segment is asserted (e.g., logic high) when the corresponding first stage row segment is a match, or de-asserted (e.g., logic low) when the corresponding first stage row segment is not a match. Process 500 proceeds to step 550 or step 560. At step 550, when none of the first stage row segments match, SL_EN is de-asserted (e.g., logic low), and at step 555, the second stage SL pairs are disabled; thus, there is no match in the sub-bank.

[0041] When process 500 proceeds to step 560, when one or more first stage row segments have a match, SL_EN is asserted (e.g., logic high). Continuing to step 570, for each second stage row segment enabled by ML_EN, the corresponding second stage ML (e.g., ML2) is pre-charged to logic high. In addition, all second stage SL pairs (e.g., SL2 and SLB2) are pre-charged to logic high. At step 580, the asserted SL_EN causes each second stage SL pair to be driven to opposite logic states according to the corresponding bit values of the second portion search key. At step 590, the second portion search key is compared with the data stored in those second stage row segments enabled by the corresponding ML_EN. At step 595, the comparison result is output to indicate a match or no match. The row index of the matching entry can also be output.

[0042] Figure 6 is a flow diagram illustrating a method of dynamically gating search lines in a sub-bank according to one embodiment. Method 600 can be performed by a sub-bank as shown in FIG. 6A. Each sub-bank includes an array of CAM cells arranged in rows and columns. The sub-bank is divided into a first stage and a second stage along the column dimension. Figures 1 to 4

[0043] ​In step 610, the first part of the search keyword is compared with the data stored in the CAM unit of the first stage row segment in the sub-library. In step 620, the first stage ML indicates whether a match of the first part of the search keyword is found in the corresponding first stage row segment. In step 630, an SL_EN signal is generated based on the logical state of all first stage MLs. The SL_EN signal is the strobe signal for the second stage SL pair, which is coupled to the CAM unit of the corresponding column in the second stage. In step 640, when no match is indicated by the first stage MLs, the SL_EN signal is deactivated. Deactivation of the SL_EN signal prevents the second part of the search keyword from being provided to the second stage SL pair.

[0044] Already referenced Figures 1 to 4 An exemplary embodiment is described Figure 5 and Figure 6 The flowchart operation. However, it should be understood that Figure 5 and Figure 6 The flowchart operations can be performed by, in addition to the reference Figures 1 to 4 The invention may be implemented in accordance with embodiments other than those discussed, and references are made to... Figures 1 to 4 The embodiments discussed may perform operations different from those discussed with reference to these flowcharts. Although Figure 5 and Figure 6 The flowchart illustrates a specific sequence of operations performed by certain embodiments of the present invention, but it should be understood that such sequence is exemplary (e.g., alternative embodiments may perform operations in a different order, combine certain operations, repeat certain operations, etc.).

[0045] Although the invention has been described with reference to several embodiments, those skilled in the art will recognize that the invention is not limited to the described embodiments and that modifications and variations can be made within the spirit and scope of the appended claims. Therefore, the invention is to be considered illustrative rather than restrictive.

Claims

1. A content addressable memory (CAM) device comprising: a plurality of CAM banks, each CAM bank comprising: an array of CAM cells arranged in rows and columns, the array of CAM cells divided along a column dimension into a first stage and a second stage; a plurality of first stage match lines (MLs), each first stage ML coupled to a first stage row segment of CAM cells and indicating whether a match for a first portion of a search key is found in the first stage row segment; a plurality of first stage search line (SL) pairs in the first stage; a plurality of second stage MLs, each second stage ML coupled to a second stage row segment of CAM cells; a plurality of second stage SL pairs, wherein each second stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable signal; and circuitry to receive the plurality of first stage MLs as input and to deassert the SL enable signal when none of the plurality of first stage MLs indicates a match, wherein deassertion of the SL enable signal prevents a second portion of a search key from being provided to the plurality of second stage SL pairs; output circuitry to indicate a match between a search key and data stored in one or more rows of the plurality of CAM banks, wherein the search key comprises the first portion of the search key provided to the first stage and the second portion of the search key provided to the second stage.

2. The CAM device of claim 1, wherein the SL enable signal is asserted when one or more first stage MLs indicate a match with the first portion of the search key.

3. The CAM device of claim 1, wherein the circuitry comprises a wire or circuit to perform a logical OR operation on the plurality of first stage MLs to produce the SL enable signal.

4. The CAM device of claim 1, wherein, the circuitry comprises a clock gated flip-flop that receives a first stage ML indicating a match in the first stage row segment and outputs an ML enable signal to enable precharge of a corresponding second stage ML.

5. The CAM device of claim 1, wherein, each CAM bank is a portion of the plurality of CAM banks into which a CAM bank is divided along a row dimension.

6. The CAM device of claim 1, wherein each CAM bank produces a corresponding SL enable signal to indicate a match in the corresponding first stage of the CAM bank.

7. The CAM device of claim 1, wherein the first stage and the second stage comprise the same number of columns of CAM cells, or the first stage comprises fewer columns of CAM cells than the second stage.

8. The CAM device of claim 1, wherein each CAM cell is a ternary CAM cell, a binary CAM cell, or a quaternary CAM cell.

9. The CAM device of claim 1, wherein each second stage SL is coupled to a pair of AND gates, the pair of AND gates comprising a first AND gate receiving the SL enable signal, a clock signal, and a second portion of the search keyword bit as input, and a second AND gate receiving the SL enable signal, the clock signal, and an inverted second portion of the search keyword bit as input.

10. A method of operating a CAM device, executed by each of a plurality of CAM sub-libraries of the CAM device, each CAM sub-library comprising an array of CAM cells arranged in rows and columns, the method comprising: The first part of the search keywords is compared with the data stored in the CAM unit of the first stage row segmentation, where each CAM sub-library is divided into the first stage and the second stage along the column dimension; Each first-stage ML indicator determines whether a match for the first part of the search keyword is found in the corresponding first-stage row segment; An SL enable signal is generated based on the logic states of all first-stage MLs, wherein the SL enable signal is a gating signal for multiple second-stage SL pairs, which are coupled to the CAM units of the corresponding columns in the second stage. as well as When none of the first-stage MLs indicate a match, the SL enable signal is deactivated, wherein the deactivation of the SL enable signal prevents the second part of the search keywords from being provided to the plurality of second-stage SL pairs.

11. The method of claim 10, further comprising: The SL enable signal is activated when one or more first-stage ML indications match.

12. The method of claim 10, further comprising: When the SL enable signal is active, the second part of the search keyword is compared with the data stored in the CAM unit of the second stage row segment.

13. The method of claim 10, further comprising: Perform a logical OR operation on all first-stage ML operations to generate the SL enable signal.

14. The method of claim 10, further comprising: When there is a match in the corresponding first-stage row segment, an ML enable signal is generated to enable the pre-charging of the corresponding second-stage row segment.

15. The method of claim 10, further comprising: When the corresponding valid bit indicator indicates the validity of the CAM cell in the corresponding row, the corresponding first stage ML is precharged.

16. The method of claim 10, further comprising: When a search keyword is found to match data stored in one or more rows of the plurality of CAM sub-libraries, a matching indication is output, wherein the search keyword includes the first part of the search keyword provided to the first stage and the second part of the search keyword provided to the second stage.

17. The method of claim 10, wherein each CAM unit is a ternary CAM unit, a binary CAM unit, or a quaternary CAM unit.

18. The method of claim 10, wherein each CAM sublibrary is part of the plurality of CAM sublibraries divided along the row dimension of the CAM library.

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