Wafer-to-wafer interconnect structure and method of manufacturing the same

Abstract

A wafer-to-wafer interconnect structure and a method of fabricating the same are provided. The wafer-to-wafer interconnect structure includes forming a first etch stop layer having at least two portions on a first surface of a first substrate, and forming a void in a portion of the first etch stop layer. A second etch stop layer is formed on a first surface of a second substrate, and the first surface of the first substrate is bonded to the second substrate with the second etch stop layer aligned to the void. A first opening is formed into the first substrate from a second surface of the first substrate by using the first etch stop layer and the second etch stop layer as etch stop layers, and a second opening is formed through the void to the second substrate. A first through-silicon via is formed in the first opening, and a second through-silicon via is formed in the second opening.

Description

Technical Field

[0001] The present invention relates to a wafer-to-wafer structure and a manufacturing method thereof, and in particular to a wafer-to-wafer interconnection structure and a manufacturing method thereof. Background Art

[0002] With technological advancements, 3D integrated circuit technology has been developed to meet the needs of increasing semiconductor miniaturization and reducing process costs. In 3D integrated circuits, semiconductor chips can be stacked vertically through techniques such as bonding or packaging, and different chips can be connected using through-silicon vias (TSVs). TSVs provide vertical conductive paths and can have advantages such as increasing chip stacking density, improving product efficiency, and reducing energy consumption.

[0003] However, prolonged etching of deeper TSVs will result in charges on the metal etch stop layer of shallower TSVs, and this phenomenon may cause arc discharge and wafer damage. Summary of the Invention

[0004] The present invention provides a method for manufacturing a wafer-to-wafer interconnection structure with an additional metal layer to prevent the wafer from being damaged due to prolonged etching.

[0005] The present invention provides a wafer-to-wafer interconnection structure with excellent yield and stability.

[0006] The method of manufacturing a wafer-to-wafer interconnect structure of the present invention includes the following steps: forming a first etch stop layer on a first surface of a first substrate, wherein the first etch stop layer includes a first portion and a second portion; forming a void in the second portion of the first etch stop layer; forming a second etch stop layer on the first surface of the second substrate; bonding the first surface of the first substrate to the first surface of the second substrate so that the second etch stop layer is aligned with the void; forming a first opening from the second surface of the first substrate into the first substrate and a second opening through the void to the second substrate using the first etch stop layer and the second etch stop layer as etch stop layers; forming a first through-silicon via (TSV) in the first opening and a second through-silicon via (TSV) in the second opening.

[0007] In one embodiment of the present invention, the steps of forming the first etch stop layer and forming the void include depositing a metal layer, patterning the metal layer to form a first portion and a second portion, wherein the void is formed in the second portion, and covering the first etch stop layer and the void with an insulating layer without filling the void.

[0008] In one embodiment of the present invention, the steps of forming the first etch stop layer and forming the void include depositing a metal layer. Patterning the metal layer to form a first portion and a second portion, wherein a hole is formed in the second portion. Conformally depositing a first insulating layer on a surface of the hole. Covering the first etch stop layer with a second insulating layer, and forming a void between the first and second insulating layers in the hole.

[0009] In one embodiment of the present invention, the thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

[0010] In one embodiment of the present invention, the steps of forming the first and second TSVs include forming an oxide liner on the sidewalls of the first and second openings. Conformally depositing a barrier layer on the inner surfaces of the first and second openings to cover the oxide liner. Electroplating a metal material onto the second surface of the first substrate, wherein the first and second openings are filled with the metal material. Planarizing the metal material until the second surface of the first substrate is exposed.

[0011] In one embodiment of the present invention, before or after the step of forming the first opening and the second opening, the method further includes forming a trench on the second surface of the first substrate above the first portion and the second portion of the first etch stop layer.

[0012] In one embodiment of the present invention, after forming the trench, the steps of forming the first and second TSVs include forming an oxide liner on the sidewalls of the first and second openings. Conformally depositing a barrier layer on the inner surfaces of the trench, the first and second openings to cover the oxide liner. Electroplating a metal material onto the second surface of the first substrate, wherein the trench, the first and second openings are filled with the metal material. Planarizing the metal material until the second surface of the first substrate is exposed.

[0013] In one embodiment of the present invention, after the step of bonding the first surface of the first substrate to the first surface of the second substrate, the method further includes: thinning the first substrate from the second surface of the first substrate.

[0014] The present invention provides a wafer-to-wafer interconnect structure comprising a first substrate, a second substrate, a first through-silicon via (TSV), a second TSV, and a first etch stop layer. The second substrate is bonded face-to-face to the first substrate. The first TSV is formed in the first substrate, and the second TSV is formed through the first and second substrates. The first etch stop layer comprises a first portion and a second portion, wherein the first portion is formed at a first end of the first TSV, and the second portion surrounds a sidewall of the second TSV.

[0015] In another embodiment of the present invention, the first portion of the first etch stop layer is separated from the second portion of the first etch stop layer.

[0016] In another embodiment of the present invention, the first portion of the first etch stop layer directly contacts the second portion of the first etch stop layer.

[0017] In another embodiment of the present invention, the wafer-to-wafer interconnect structure further includes a conductive line connecting the second end of the first TSV and the second end of the second TSV.

[0018] In another embodiment of the present invention, the wafer-to-wafer interconnect structure further includes a second etch stop layer formed at the first end of the second TSV.

[0019] In another embodiment of the present invention, the thickness of the first substrate is smaller than the thickness of the second substrate.

[0020] In another embodiment of the present invention, the wafer-to-wafer interconnect structure further includes an oxide liner between the second through-silicon via and the second portion of the first etch stop layer.

[0021] In one embodiment of the present invention, the first etch stop layer is a metal layer.

[0022] In one embodiment of the present invention, the second etch stop layer is a metal layer.

[0023] Based on the above, the present invention provides pre-formed voids in the first substrate, thus reducing the time required to etch deeper openings. This prevents the etch stop layer from becoming charged due to prolonged etching, thereby preventing arcing and wafer damage. Consequently, the yield and stability of wafer-to-wafer interconnect structures can be improved.

[0024] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0026] Figures 1A to 1K A schematic cross-sectional view showing a manufacturing process of a wafer-to-wafer interconnect structure according to a first embodiment of the present invention;

[0027] Figures 2A to 2D A schematic cross-sectional view showing a manufacturing process of a wafer-to-wafer interconnect structure according to a second embodiment of the present invention;

[0028] Figure 3 FIG. 1 is a schematic cross-sectional view of a wafer-to-wafer interconnect structure according to a third embodiment of the present invention.

[0029] Explanation of Figure Numbers

[0030] 100: first substrate;

[0031] 100a, 116a: first surface;

[0032] 100b: second surface;

[0033] 102: first etching stop layer;

[0034] 102', 300': Part I;

[0035] 102”, 300”: Part II;

[0036] 104, 120: wafer;

[0037] 106, 110, 112, 122, 124: insulating layer;

[0038] 108: hole;

[0039] 114: gap;

[0040] 116: second substrate;

[0041] 118: second etch stop layer;

[0042] 126, 130: patterned photoresist;

[0043] 128: groove;

[0044] 132': First opening;

[0045] 132'a, 132"a: side wall;

[0046] 132”: second opening;

[0047] 134: oxide lining;

[0048] 136: barrier layer;

[0049] 138: Metal material;

[0050] 138a: wire;

[0051] 140': first through silicon via;

[0052] 140'a, 140"a: first end;

[0053] 140'b, 140"b: second end;

[0054] 140": second through silicon via;

[0055] 300: continuous film;

[0056] t1, t2, t3, t4: thickness. DETAILED DESCRIPTION

[0057] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0058] Figures 1A to 1K FIG2 is a schematic cross-sectional view showing a manufacturing process of a wafer-to-wafer interconnect structure according to a first embodiment of the present invention.

[0059] Please refer to Figure 1A , a first substrate 100 is provided, and a first etch stop layer 102 is formed on a first surface 100a of the first substrate 100. The first substrate 100, for example, includes at least a wafer 104 and an insulating layer 106 formed thereon, and the first etch stop layer 102 is formed on the insulating layer 106. The first etch stop layer 102 includes a first portion 102' and a second portion 102", and the first portion 102' is separated from the second portion 102". In one embodiment, the first etch stop layer 102 is a metal layer, and thus the step of forming the first etch stop layer 102 may include depositing a metal layer and then patterning the metal layer to form the first portion 102' and the second portion 102". However, the present invention is not limited thereto. In another embodiment, the first etch stop layer 102 is, for example, silicon nitride, polysilicon, silicon carbide, etc. In addition, in order to subsequently form a gap, a hole 108 may be formed in the second portion 102" while patterning the metal layer. Although in Figure 1A The second portion 102 ″ is divided into two parts by the hole 108. The second portion 102 ″ in the top view is still a continuous membrane, and the hole 108 is actually arranged in the center of the second portion 102 ″.

[0060] Then, please refer to Figure 1B , the insulating layer 110 is conformally deposited on the first substrate 100 and covers the surface of the hole 108. However, the present invention is not limited thereto, and the insulating layer 110 can be adjusted to cover more portions of the hole.

[0061] Next, please refer to Figure 1C Another insulating layer 112 is formed on the insulating layer 110 to cover the first etch stop layer 102, wherein the thickness t1 of the insulating layer 110 is less than the thickness t2 of the second insulating layer 112, and the insulating layer 112 may have poor gap-filling ability, so that a void 114 is formed in the second portion 102" without filling the hole 108. In other words, the void 114 is formed between the insulating layer 110 and the insulating layer 112 in the hole 108.

[0062] Afterwards, please refer to Figure 1D , a second substrate 116 is provided, and a second etch stop layer 118 is formed on the first surface 116a of the second substrate 116. The second substrate 116, for example, includes at least a wafer 120 and an insulating layer 122 formed thereon, and the second etch stop layer 118 is formed on the insulating layer 122. In one embodiment, the second etch stop layer 118 is a metal layer, and thus the step of forming the second etch stop layer 118 may include depositing a metal layer and then patterning the metal layer to form the second etch stop layer 118. However, the present invention is not limited thereto. In another embodiment, the second etch stop layer 118 is, for example, silicon nitride, polysilicon, silicon carbide, etc. For subsequent wafer-to-wafer bonding, another insulating layer 124 may be formed on the first surface 116a of the second substrate 116 to cover the second etch stop layer 118. It should be known that in Figure 1A Before or after the step Figure 1C After the steps, a second substrate 116, a second etch stop layer 118 and an insulating layer 124 may be prepared.

[0063] Then, please refer to Figure 1E The first surface 100a of the first substrate 100 is bonded to the first surface 116a of the second substrate 116 such that the second etch stop layer 118 is aligned with the gap 114. The bonding method may be fusion bonding, polymer adhesive bonding, etc. After bonding the first surface 100a to the first surface 116a, the first substrate 100 is thinned, for example, from the second surface 100b of the first substrate 100.

[0064] Next, please refer to Figure 1F For wafer-to-wafer interconnection, a trench 128 may be formed on the second surface 100 b of the first substrate 100 by using the patterned photoresist 126 as an etching mask. The trench 128 is disposed on the first portion 102 ′ and the second portion 102 ″ of the first etch stop layer 102 . However, the present invention is not limited thereto, and the trench 128 may be formed in a subsequent step or omitted.

[0065] Afterwards, please refer to Figure 1G, first remove the patterned photoresist 126, and then form another patterned photoresist 130 on the second surface 100b of the first substrate 100 by using the first etch stop layer 102 and the second etch stop layer 118 as etch stop layers to form a first opening 132' and a second opening 132". The first opening 132' is located from the second surface 100b into the first substrate 100, and the second opening 132" is located through the gap 114 to the second substrate 116. Because the gap 114 is formed in advance, the time for etching a deeper opening (the second opening 132") can be shortened. Therefore, it is possible to prevent the first portion 102' of the first etch stop layer 102 from being charged due to long-term etching, thereby avoiding arc discharge and wafer damage. In addition, a groove 128 can be formed after the steps of forming the first opening 132' and the second opening 132", and how to form the groove 128 is also described. Figure 1F The contents are provided in the description and are not repeated here.

[0066] Then, please refer to Figure 1H For electrical isolation, an oxide liner 134 may be formed on the first opening 132 ′, the second opening 132 ″, and the entire surface of the first substrate 100 . The oxide liner 134 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0067] Next, please refer to Figure 1I The punched oxide liner 134 is formed on the sidewalls 132 ′ a of the first opening 132 ′ and the sidewalls 132 ″ a of the second opening 132 ″, exposing the second etch stop layer 118 and the first portion 102 ′ of the first etch stop layer 102 .

[0068] Afterwards, please refer to Figure 1J The barrier layer 136 is conformally deposited on the inner surface of the trench 128, the inner surface of the first opening 132′, and the inner surface of the second opening 132″ to cover the oxide liner 134. A metal material 138 is then electroplated on the second surface 100 b of the first substrate 100, so that the trench 128, the first opening 132′, and the second opening 132″ are filled with the metal material 138, wherein the metal material 138 can be copper or other suitable metals.

[0069] Then, please refer to Figure 1KThe metal material 138 is formed until the second surface 100b of the first substrate 100 is exposed to form a first through silicon via (TSV) 140' in the first opening 132' and a second through silicon via 140" in the second opening 132". In addition, the wire 138a connects the second end 140'b of the first through silicon via 140' and the second end 140"b of the second through silicon via 140".

[0070] exist Figure 1K In the embodiment, the wafer-to-wafer interconnection structure includes at least a first substrate 100, a second substrate 116 bonded face-to-face to the first substrate 100, a first through-silicon via 140' formed in the first substrate 100, a second through-silicon via 140", and a first etch stop layer 102. The second through-silicon via 140" is formed through the first substrate 100 and the second substrate 116. The first portion 102' is formed at the first end 140'a of the first through-silicon via 140', the second portion 102" surrounds the sidewall of the second through-silicon via 140", and the second etch stop layer 118 is formed at the first end 140"a of the second through-silicon via 140". The thickness t3 of the first substrate 100 is less than the thickness t4 of the second substrate 116. The oxide liner 134 is disposed between the second through-silicon via 140" and the second portion 102" of the first etch stop layer 102 to prevent short circuit.

[0071] Figures 2A to 2D A cross-sectional schematic diagram of the manufacturing process of the wafer-to-wafer interconnection structure of the second embodiment of the present invention is shown, wherein the same reference numerals as in the first embodiment are used to represent the same or similar components, and the contents of the same or similar components are also the same as those in the first embodiment and are not repeated here.

[0072] Please refer to Figure 2A , except for the insulating layer 110 ( Figure 1C In addition to the formation of Figures 1A to 1C In other words, the insulating layer 112 is formed directly on the first etch stop layer 102 , and the void 114 is formed in the hole 108 .

[0073] Then, please refer to Figure 2B , the first surface 100a of the first substrate 100 is bonded to the first surface 116a of the second substrate 116 so that the second etch stop layer 118 is aligned with the gap 114. For details, please refer to Figure 1D and Figure 1E Steps in .

[0074] Next, please refer to Figure 2CThe groove 128, the first opening 132' and the second opening 132" are formed in the first substrate 100, wherein the second opening 132" penetrates the gap 114 to the second substrate 116, so the depth of the second opening 132" is greater than the depth of the first opening 132'. For details, please refer to Figure 1F and Figure 1G Steps in .

[0075] Afterwards, please refer to Figure 2D , an oxide liner 134 is formed on the sidewall 132'a of the first opening 132' and the sidewall 132"a of the second opening 132", and then a first through silicon via 140' is formed in the first opening 132', and a second through silicon via 140" is formed in the second opening 132". For details, please refer to Figures 1H to 1K Steps in .

[0076] Figure 3 The schematic cross-sectional view of the wafer-to-wafer interconnect structure of the third embodiment of the present invention is shown, wherein the first embodiment is used in Figure 1K The same reference numerals are used to represent the same or similar components, and the contents of the same or similar components are the same as those in the first embodiment and are not repeated here.

[0077] Please refer to Figure 3 The difference between the first embodiment and the third embodiment is that the first etch stop layer 300 is a continuous film, wherein the first portion 300' directly contacts the second portion 300". Since the first etch stop layer 300 can be made of metal, the continuous film can be used as a part of the interconnection.

[0078] In summary, the method of the present invention provides a gap in the etch path of deeper TSVs, thereby shortening the etching time for deeper openings. This method also prevents charging of the etch stop layer of shallower TSVs, thereby preventing arcing and wafer damage. Consequently, the yield and stability of wafer-to-wafer interconnect structures can be improved.

[0079] Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A method for manufacturing a wafer-to-wafer interconnect structure, comprising: depositing a metal layer on the first surface of the first substrate; patterning the metal layer to form a first etch stop layer, wherein the first etch stop layer includes a first portion and a second portion, wherein a hole is formed in the second portion; conformally depositing a first insulating layer on the surface of the hole; covering the first etch stop layer with a second insulating layer, and forming a gap between the first insulating layer and the second insulating layer in the hole of the second portion; forming a second etch stop layer on the first surface of the second substrate; bonding the first surface of the first substrate to the first surface of the second substrate so that the second etch stop layer is aligned with the gap; forming a first opening from the second surface of the first substrate into the first substrate and a second opening through the gap to the second substrate by using the first etch stop layer and the second etch stop layer as etch stop layers; forming an oxide lining on the sidewalls of the first opening and the sidewalls of the second opening; as well as A first through silicon via (TSV) is formed in the first opening and a second through silicon via (TSV) is formed in the second opening. 2 . The method for fabricating a wafer-to-wafer interconnect structure according to claim 1 , wherein a thickness of the first insulating layer is smaller than a thickness of the second insulating layer.

3. The method for manufacturing a wafer-to-wafer interconnect structure according to claim 1 , wherein the step of forming the first through-silicon via and the second through-silicon via comprises: Conformally depositing a barrier layer on an inner surface of the first opening and an inner surface of the second opening to cover the oxide liner; electroplating a metal material on the second surface of the first substrate, wherein the first opening and the second opening are filled with the metal material; as well as The metal material is planarized until the second surface of the first substrate is exposed.

4. The method for manufacturing a wafer-to-wafer interconnect structure according to claim 1 , further comprising: before or after the step of forming the first opening and the second opening; A trench is formed in the second surface of the first substrate above the first portion and the second portion of the first etch stop layer.

5. The method for manufacturing a wafer-to-wafer interconnect structure according to claim 4 , wherein after the step of forming the trench, the step of forming the first through-silicon via and the second through-silicon via comprises: Conformally depositing a barrier layer on an inner surface of the trench, an inner surface of the first opening, and an inner surface of the second opening to cover the oxide liner; electroplating a metal material on the second surface of the first substrate, wherein the groove, the first opening, and the second opening are filled with the metal material; as well as The metal material is planarized until the second surface of the first substrate is exposed.

6. The method for manufacturing a wafer-to-wafer interconnect structure according to claim 1 , further comprising: after the step of bonding the first surface of the first substrate to the first surface of the second substrate; The first substrate is thinned from the second surface of the first substrate. 7 . The method for fabricating a wafer-to-wafer interconnect structure according to claim 1 , wherein the second etch stop layer is a metal layer.

8. A wafer-to-wafer interconnect structure comprising: a first substrate; a second substrate bonded face-to-face to the first substrate; A first through silicon via is formed in the first substrate; A second through silicon via is formed through the first substrate and the second substrate; The first etch stop layer includes a first portion and a second portion, wherein the first etch stop layer is a metal layer, the first portion is formed at a first end of the first through-silicon via, and the second portion surrounds a sidewall of the second through-silicon via; as well as an oxide liner between the second through-silicon via and the second portion of the first etch stop layer; a first insulating layer conformally deposited on the first substrate and covering the first etch stop layer; as well as A second insulating layer is formed on the first insulating layer, wherein the thickness of the first insulating layer is smaller than that of the second insulating layer, and the second insulating layer has a poor gap filling capability. 9 . The wafer-to-wafer interconnect structure of claim 8 , wherein the first portion of the first etch stop layer is separated from the second portion of the first etch stop layer. 10 . The wafer-to-wafer interconnect structure of claim 8 , wherein the first portion of the first etch stop layer directly contacts the second portion of the first etch stop layer. 11 . The wafer-to-wafer interconnect structure according to claim 8 , further comprising a conductive line connecting the second end of the first TSV and the second end of the second TSV. 12 . The wafer-to-wafer interconnect structure according to claim 8 , further comprising a second etch stop layer formed at a first end of the second TSV. 13 . The wafer-to-wafer interconnect structure according to claim 12 , wherein the second etch stop layer is a metal layer. 14 . The wafer-to-wafer interconnect structure according to claim 8 , wherein a thickness of the first substrate is smaller than a thickness of the second substrate.

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