Element forming wafer and manufacturing method thereof

Abstract

The following steps are performed: preparing a semiconductor wafer (100) having a plurality of chip forming regions (101); forming a thin layer (110) on the semiconductor wafer (100); defining the portion of the thin layer (110) that constitutes each element in the chip forming region (101) as an element constituting portion (110a), and adjusting stress so that the stress of the element constituting portion (110a) becomes a predetermined value. Furthermore, in the step of adjusting stress, the following steps are performed: disposing a resist (120) on the thin layer (110a); exposing the resist (120) using a photomask (200) having an opening (201) formed therein; developing the resist (120) to form an opening in the resist (120); performing ion implantation using the resist (120) as a mask; and in the step of exposing the resist (120), using a photomask having an opening ratio adjusted based on the stress generated in the element constituting portion (110a).

Description

[0001] Cross-references between related applications

[0002] This application is based on Japanese Patent Application No. 2019-209854 filed on November 20, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a device forming wafer having a thin layer formed on a semiconductor wafer and a method for manufacturing the same. Background Art

[0004] In the past, a device-forming wafer has been proposed in which a thin layer is formed on a semiconductor wafer. Furthermore, since such a device-forming wafer generates stress when the thin layer is formed, the stress is non-uniform in the surface direction of the thin layer. Therefore, for example, Patent Document 1 proposes a method for making the stress of the thin layer uniform by performing ion implantation corresponding to the stress of the thin layer. Specifically, Patent Document 1 proposes a method for making the stress of the device-forming parts of the device-forming elements in the thin layer uniform by performing ion implantation. Furthermore, in this method, when performing ion implantation, the amount of implanted ions is changed by changing the time of ion beam irradiation and the ion current density of the ion beam, thereby making the stress of the thin layer uniform.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 7-78754 Summary of the Invention

[0008] However, in the above-mentioned method for manufacturing a device-forming wafer, detailed control is required during ion beam irradiation, and the manufacturing process tends to become complicated.

[0009] An object of the present invention is to provide a device-forming wafer and a method for manufacturing the same, which can simplify the manufacturing process and make the stress of a thin layer a desired value.

[0010] A technical solution of the present invention is a method for manufacturing an element-forming wafer, which comprises the following steps: preparing a semiconductor wafer having a plurality of chip-forming regions; forming a thin layer on the semiconductor wafer; setting the portion constituting each element in the chip-forming region in the thin layer as an element-constituting portion, and adjusting the stress so that the stress of the element-constituting portion becomes a specified value; in the step of adjusting the stress, performing the following steps: disposing a resist on the thin layer; exposing the resist using a photomask having an opening portion; developing the resist to form an opening portion in the resist; performing ion implantation using the resist as a mask; and in the step of exposing the resist, using a photomask having an opening ratio adjusted based on the stress generated in the element-constituting portion.

[0011] By changing the aperture ratio of the photomask, the stress of the device components in each chip formation region can be adjusted to a desired value. Therefore, detailed control of the ion implantation irradiation time, etc., is unnecessary, and the manufacturing process can be simplified.

[0012] Another technical solution of the present invention is an element forming wafer, comprising: a semiconductor wafer having a plurality of chip forming regions; and a thin layer formed on the semiconductor wafer; the portion constituting each element in the chip forming region in the thin layer is defined as an element constituting portion, and the thin layer has a plurality of regions passing through a portion located on the center of the semiconductor wafer and along a direction in the surface direction of the semiconductor wafer, and, when a plurality of element constituting portions are respectively arranged in the plurality of regions, the stress distribution of the element constituting portions arranged in the plurality of regions along one direction has a maximum value and a minimum value of stress in each region, and the rate of change of stress between the maximum value and the minimum value within the region is smaller than the rate of change of stress at the boundary portion of the adjacent regions.

[0013] Such a device-forming wafer is formed by ion implantation with a modified aperture ratio of a photomask, and does not require detailed control of the irradiation time during ion implantation, etc. Therefore, the manufacturing process can be simplified.

[0014] In addition, the reference numerals in parentheses assigned to each component etc. represent an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a cross-sectional view of the ultrasonic sensor according to the first embodiment.

[0016] Figure 2A Yes Figure 1 A cross-sectional view showing the manufacturing process of an ultrasonic sensor.

[0017] Figure 2B It means next Figure 2A A cross-sectional view of the manufacturing process of an ultrasonic sensor.

[0018] Figure 2C It means next Figure 2B A cross-sectional view of the manufacturing process of an ultrasonic sensor.

[0019] Figure 2D It means next Figure 2C A cross-sectional view of the manufacturing process of an ultrasonic sensor.

[0020] Figure 2E It means next Figure 2D A cross-sectional view of the manufacturing process of an ultrasonic sensor.

[0021] Figure 2F It means next Figure 2E A cross-sectional view of the manufacturing process of an ultrasonic sensor.

[0022] Figure 2G It means next Figure 2F A cross-sectional view of the manufacturing process of an ultrasonic sensor.

[0023] Figure 2H It means next Figure 2G A cross-sectional view of the manufacturing process of an ultrasonic sensor.

[0024] Figure 2I It means next Figure 2H A cross-sectional view of the manufacturing process of an ultrasonic sensor.

[0025] Figure 3 yes Figure 2D A plan view of a photomask used in the process.

[0026] Figure 4 This is a diagram showing experimental results regarding the relationship between the film stress of the piezoelectric layer and the structure of the piezoelectric layer.

[0027] Figure 5 It is a graph showing the results of X-ray diffraction measurement.

[0028] Figure 6 This is a diagram showing experimental results regarding the relationship between the characteristics of the piezoelectric layer and the structure of the piezoelectric layer.

[0029] Figure 7 It is a cross-sectional view showing a state of ion implantation according to a modification of the first embodiment.

[0030] Figure 8 It is a cross-sectional view showing a state of ion implantation in the second embodiment.

[0031] Figure 9 It is a cross-sectional view of an ultrasonic sensor according to a third embodiment.

[0032] Figure 10 It is a cross-sectional view showing a state of ion implantation in the fourth embodiment.

[0033] Figure 11 This is a schematic diagram showing the stress distribution of the thin layer before ion implantation in the fifth embodiment.

[0034] Figure 12 It is a schematic diagram showing the aperture ratio of the intermediate mask used in the stepper exposure according to the sixth embodiment.

[0035] Figure 13 This is a schematic diagram showing the stress distribution of the thin layer after ion implantation in the seventh embodiment.

[0036] Figure 14A It is a plan view of a photomask according to another embodiment.

[0037] Figure 14B It is a plan view of a photomask according to another embodiment. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be described with the same reference numerals.

[0039] (First embodiment)

[0040] A first embodiment will be described with reference to the accompanying drawings. In this embodiment, an ultrasonic sensor constructed using a manufacturing method of an element forming wafer will be described as an example. First, the structure of the ultrasonic sensor will be described.

[0041] Ultrasonic sensors such as Figure 1 As shown, a semiconductor substrate 10 made of silicon or the like having one surface 10a and another surface 10b is provided. A diaphragm portion 12 is formed by forming a recess 11 in the semiconductor substrate 10. A piezoelectric film 13 and an electrode film 14 are sequentially formed in the diaphragm portion 12.

[0042] The diaphragm portion 12 is not particularly limited. In this embodiment, its planar shape is circular and its diameter is approximately 1 mm. The piezoelectric film 13 is composed of, for example, a piezoelectric ceramic such as aluminum nitride (hereinafter also referred to as AlN), scandium aluminum nitride (hereinafter also referred to as ScAlN), or lead zirconate titanate (PZT). Furthermore, the piezoelectric film 13 is circular in planar shape, has a diameter equivalent to that of the diaphragm portion 12, and has a film thickness of approximately 1 μm. Furthermore, although not specifically shown, the semiconductor substrate 10 is also appropriately formed with a wiring pattern electrically connected to the electrode film 14, a pad portion for connecting the wiring pattern to an external circuit, and a protective film.

[0043] Such ultrasonic sensors can be used, for example, as transmitters and receivers. For example, when the ultrasonic sensor is used as a transmitter, applying a predetermined voltage to the electrode film 14 causes the piezoelectric film 13 to vibrate, thereby vibrating the diaphragm 12. This allows the ultrasonic sensor to transmit a transmission wave. Alternatively, when the ultrasonic sensor is used as a receiver, for example, the diaphragm 12 vibrates in response to the received wave, generating a voltage in the piezoelectric film 13 corresponding to the vibration. The ultrasonic sensor then outputs a detection signal based on the received wave.

[0044] The above is the structure of the ultrasonic sensor of this embodiment. Next, a method for manufacturing the ultrasonic sensor will be described.

[0045] First, if Figure 2AAs shown in FIG. 1 , a semiconductor wafer 100 is prepared. The semiconductor wafer 100 has one surface 100a and another surface 100b and is divided into a plurality of chip forming regions 101 by dicing lines DL. The semiconductor wafer 100 is, for example, a silicon wafer.

[0046] Then, if Figure 2B As shown, a piezoelectric layer 110 is formed on one side 100a of a semiconductor wafer 100 by sputtering or the like. Piezoelectric layer 110 is patterned to form the piezoelectric film 13 and is composed of the piezoelectric ceramic or the like described above. Piezoelectric layer 110 is formed entirely over each chip forming region 101 and along the dicing lines DL. In this embodiment, piezoelectric layer 110 is a thin layer.

[0047] In this case, stress is generated in the piezoelectric layer 110 depending on the film forming device and film forming conditions used to form the piezoelectric layer 110. In addition, the stress is not uniform in the surface direction of the piezoelectric layer 110. That is, a state is formed in which stress is not uniform in the surface direction in the piezoelectric layer 110. For example, it is known that when the piezoelectric layer 110 is formed on a semiconductor wafer 100 having a diameter of 6 inches using an existing film forming device, a stress distribution is formed in the piezoelectric layer 110 in which the difference between the maximum value and the minimum value is about several tens to 100 MPa. Therefore, in this embodiment, the film forming device and various conditions used to form the piezoelectric layer 110 are appropriately changed to pre-understand the stress distribution of the piezoelectric layer 110.

[0048] Next, stress adjustment is performed to bring the stress of the piezoelectric layer 110 to a desired value (i.e., a predetermined value). The following describes the various steps involved in stress adjustment. Furthermore, the following describes an example of uniformizing the stress by reducing the stress difference generated in the piezoelectric layer 110.

[0049] First, if Figure 2C As shown in FIG. 1 , a resist 120 is disposed on the piezoelectric layer 110. In this embodiment, the resist 120 is a positive type. However, the resist 120 may also be a negative type.

[0050] Then, if Figure 2D As shown, a photomask 200 having an opening 201 formed therein is placed on a resist 120. Here, the portion of the piezoelectric layer 110 that becomes the piezoelectric film 13 through patterning is referred to as the piezoelectric film component portion 110a, and the portion of the photomask 200 that adjusts the exposure amount of the resist 120 on the piezoelectric film component portion 110a is referred to as the exposure adjustment portion 200a. In this embodiment, since the piezoelectric film 13 is circular, the piezoelectric film component portion 110a and the exposure adjustment portion 200a are also circular.

[0051] In this embodiment, if Figure 3As shown in FIG. 2 , an opening 201 is formed in the exposure adjustment section 200 a so as to form a dot-shaped dither pattern. Figure 2D The photomask 200 is equivalent to Figure 3 The cross-sectional view of the IID-IID line in FIG. 2 is shown, but in order to make the opening 201 easier to understand, the opening 201 is shown. Figure 3 In terms of the number of openings 201, the width of the openings 201 is increased and the number of openings 201 is decreased. Figure 3 Although not a cross-sectional view, portions of the photomask 200 different from the opening 201 are hatched for easier understanding.

[0052] Furthermore, the ratio of the area where the opening 201 is formed to the entire area of ​​the exposure adjustment section 200a is defined as the aperture ratio of the exposure adjustment section 200a. In this case, the aperture ratio of the exposure adjustment section 200a is adjusted based on the stress distribution of the piezoelectric layer 110. For example, assume that tensile stress is generated throughout the piezoelectric layer 110. Furthermore, regarding the aperture ratio of the exposure adjustment section 200a, based on the stress distribution of the tensile stress, the aperture ratio of the exposure adjustment section 200a that adjusts the exposure amount of the resist 120 on the portion of the piezoelectric film component 110a where the tensile stress is increased is set as follows. That is, this aperture ratio is set to be greater than the aperture ratio of the exposure adjustment section 200a that adjusts the exposure amount of the resist 120 on the portion where the tensile stress is reduced. That is, when exposing the resist 120, the aperture ratio of the exposure adjustment section 200a is adjusted as follows. The aperture ratio of the exposure adjustment unit 200a is adjusted so that the portion of the resist 120 located on the piezoelectric film component 110a, which experiences high tensile stress, has a larger exposed area than the portion located on the piezoelectric film component 110a, which experiences low tensile stress. Furthermore, the photomask 200 is prepared in advance based on the stress distribution of the piezoelectric layer 110, depending on the film formation equipment and film formation conditions.

[0053] Next, in this embodiment, the resist 120 is subjected to aligned exposure (ie, simultaneous exposure) using the above-mentioned photomask 200. In this embodiment, the piezoelectric film component 110a corresponds to the element component.

[0054] Then, if Figure 2EAs shown, by developing the resist 120, an opening 121 is formed in the resist 120. Hereinafter, the ratio of the area in which the opening 121 is formed relative to the entire area of ​​the portion of the resist 120 located on the piezoelectric film component 110a is referred to as the aperture ratio of the resist 120. In this case, the resist 120 is in a state where the aperture ratio of the portion located on the piezoelectric film component 110a, which has a large tensile stress, is greater than the aperture ratio of the portion located on the piezoelectric film component 110a, which has a small tensile stress. Furthermore, in this embodiment, since the diameter of the piezoelectric film 13 (i.e., the piezoelectric film component 110a) is set to approximately 1 mm, the pitch of the openings 121 can be formed in a pattern that is sufficiently small relative to the diameter, such as 1 μm.

[0055] Then, if Figure 2F As shown, ion implantation is performed using the resist 120 as a mask to form an implantation region 130 in the piezoelectric film component 110 a , thereby setting the stress of the piezoelectric film component 110 a to a desired value and forming an element formation wafer 300 .

[0056] In this embodiment, by performing multiple ion implantations while varying the acceleration voltage, multiple implantation regions 130 are formed along the thickness direction of the piezoelectric layer 110. In this case, the implantation regions 130 are formed deeper in the piezoelectric layer 110 as the acceleration voltage increases.

[0057] For example, in the case of ion implantation of Si (silicon), the implantation amount is set to 8.00×10 12 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 25 KeV so that the implantation amount was 1.60×10 13 atoms / cm 3 Then, the ion implantation was performed by setting the acceleration voltage to 50 KeV and making the implantation amount 2.80×10 13 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 100 KeV so that the implantation amount was 7.60×10 13 atoms / cm 3 ion implantation.

[0058] For example, in the case of ion implantation of Mg (magnesium), the implantation amount is set to 5.00×10 12 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 20 KeV so that the implantation amount was 1.70×10 13 atoms / cm3 Then, the ion implantation was performed by setting the acceleration voltage to 40 KeV and making the implantation amount 3.00×10 13 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 80 KeV so that the implantation amount became 9.50×10 13 atoms / cm 3 ion implantation.

[0059] Thus, a plurality of injection regions 130 are formed along the thickness direction in the piezoelectric layer 110. Figure 2F , two implantation regions 130 are shown formed along the thickness direction of the piezoelectric layer 110. However, when ion implantation is performed using four different acceleration voltages as described above, four implantation regions 130 are actually formed along the thickness direction of the piezoelectric layer 110. Furthermore, the acceleration voltage only needs to be changed commonly in each chip formation region 101, and does not need to be changed for each chip formation region 101.

[0060] Here, as Figure 4 As shown in FIG. 1 , it was confirmed that the stress of the piezoelectric layer 110 changes in the compression direction by ion implantation into the piezoelectric layer 110. Figure 4 In the figure, AlN and ScAlN are materials constituting the piezoelectric layer 110 , 100 nm and 200 nm are the film thicknesses of the piezoelectric layer 110 , and Si implantation and Mg implantation indicate the types of elements implanted by ions.

[0061] also, Figure 4 The Si implantation was performed by setting the acceleration voltage to 10 KeV so that the implantation amount was 8.00×10 12 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 25 KeV so that the implantation amount was 1.60×10 13 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 50 KeV so that the implantation amount was 2.80×10 13 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 100 KeV and the implantation amount was 7.60×10 13 atoms / cm 3 The results in the case of ion implantation. Similarly, Figure 4 The Mg implantation was performed by setting the acceleration voltage to 10 KeV so that the implantation amount was 5.00×10 12 atoms / cm 3The ion implantation was performed by setting the acceleration voltage to 20 KeV so that the implantation amount was 1.70×10 13 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 40 KeV so that the implantation amount was 3.00×10 13 atoms / cm 3 The ion implantation was performed by setting the acceleration voltage to 80 KeV so that the implantation amount was 9.50×10 13 atoms / cm 3 The result of ion implantation. Figure 5 and Figure 6 The same conditions apply to Si injection and Mg injection.

[0062] In this case, it was confirmed that when the film thickness was 100nm, the stress in the compressive direction changed by approximately 1.2GPa through ion implantation. It was confirmed that when the film thickness was 200nm, the stress in the compressive direction changed by approximately 600MPa. Therefore, it is assumed that when the film thickness was approximately 1μm, the stress in the compressive direction could change by approximately 100MPa. In other words, when the piezoelectric layer 110 had a film thickness of approximately 1μm, even if a stress distribution with a difference between the maximum and minimum values ​​of approximately tens to 100MPa was generated, the difference between the maximum and minimum values ​​was sufficiently reduced through ion implantation.

[0063] Furthermore, even if ion implantation is performed on the piezoelectric layer 110, as shown in FIG. Figure 5 and Figure 6 As shown, the crystallinity and piezoelectricity are almost unchanged. Figure 5 This is the experimental result obtained by scanning the (0002) plane in X-ray diffraction measurement. Figure 6 The center in FIG. 1 is the result of a portion of the piezoelectric layer 110 located at the center of the semiconductor wafer 100 , and the top is the result of a portion of the piezoelectric layer 110 located at the outer edge of the semiconductor wafer 100 . Figure 6 Where d33 is the piezoelectric constant. And, Figure 6 These are the results when the piezoelectric layer 110 is formed on a 6-inch semiconductor wafer 100 .

[0064] Therefore, by using the resist 120 with the openings 121 formed as described above as a mask, a larger amount of ions is injected into the piezoelectric film component 110a experiencing greater tensile stress than into the piezoelectric film component 110a experiencing less tensile stress, thereby imparting a greater compressive stress. Consequently, the difference between the maximum and minimum stress distributions in the piezoelectric film component 110a can be reduced, resulting in a more uniform stress distribution. Furthermore, when performing ion implantation, there is no need to specifically change the irradiation time, etc., for each piezoelectric film component 110a in the chip formation region 101.

[0065] Furthermore, as described above, even if ion implantation is performed, the crystallinity and piezoelectricity do not change particularly. However, when ion implantation is performed, it is preferable to implant a material of the same group number as the material constituting the piezoelectric layer 110. For example, in the case where the piezoelectric layer 110 is composed of AlN, since Al belongs to the 3B group and N belongs to the 5B group, it is preferable to ion implant an element of the 3B group or the 5B group. Furthermore, for example, in the case where the piezoelectric layer 110 is composed of ScAlN, since Sc belongs to the 3A group, Al belongs to the 3B group, and N belongs to the 5B group, it is preferable to ion implant an element of the 3A group, the 3B group, or the 5B group. Thus, by implanting an element of the same group number as the element constituting the piezoelectric layer 110, changes in conductivity can also be suppressed. Therefore, when ion implantation is performed, it is preferable to implant a material of the same group number as the material constituting the piezoelectric layer 110.

[0066] Next, although not specifically shown, a heat treatment is performed. At this time, the implanted ions diffuse, and the local stress in the piezoelectric film component 110a can be made uniform.

[0067] Then, if Figure 2G As shown, a resist (not shown) is placed on the piezoelectric layer 110 and patterned. Then, dry etching or the like is performed using the resist as a mask to pattern the piezoelectric layer 110 and form the piezoelectric film 13.

[0068] Then, if Figure 2H As shown in FIG. 1 , the electrode layer 140 is formed by sputtering or the like so as to cover the piezoelectric film 13. Figure 2I As shown in FIG. 1 , a resist (not shown) is placed on the electrode layer 140 and patterned. Then, dry etching or the like is performed using the resist as a mask to pattern the electrode layer 140 and form the electrode film 14.

[0069] Thereafter, although not particularly shown, the recess 11 is formed from the other surface 100 b side of the semiconductor wafer 100 to form the diaphragm portion 12 , and the wafer is divided along the dicing lines DL to form the ultrasonic sensor.

[0070] As described above, in this embodiment, the aperture ratio of the resist 120 is varied by varying the aperture ratio of the exposure adjustment portion 200a of the photomask 200. Furthermore, ion implantation is performed using the resist 120 as a mask, with ions corresponding to the aperture ratio of the resist 120 being implanted. This results in uniform stress in the piezoelectric film component 110a of each chip formation region 101. This eliminates the need for detailed control of ion implantation time and other factors, simplifying the manufacturing process.

[0071] Furthermore, in this embodiment, ions are implanted from a material of the same family as that constituting the piezoelectric layer 110. Therefore, changes in the conductivity of the piezoelectric layer 110 can be suppressed.

[0072] Furthermore, in this embodiment, ion implantation is performed only on the piezoelectric film component 110 a , so that a region other than the piezoelectric film component 110 a can also be effectively utilized.

[0073] Furthermore, during ion implantation, multiple ion implantations are performed while changing the acceleration voltage to form multiple implantation regions 130 in the thickness direction of the piezoelectric film component 110a. This can also suppress local stress nonuniformity in the thickness direction of the piezoelectric film component 110a.

[0074] (Modification of the first embodiment)

[0075] A modification of the first embodiment will be described. Figure 2F When the acceleration voltage is changed during the process and multiple ion implantations are performed, the following can also be done: Figure 7 As shown, the pattern of the opening 121 of the resist 120 is made different each time ion implantation is performed. Figure 8 An example of performing two ion implantations with varying acceleration voltages is shown. Specifically, after performing a first ion implantation to form an implantation region 130 below the resist 120 in the figure, a second ion implantation is performed using the resist 120 as a mask. This further reduces local stress nonuniformity in the surface direction of the piezoelectric film component 110a.

[0076] (Second embodiment)

[0077] The second embodiment will be described. This embodiment adds the direction of ion implantation to the first embodiment. The rest is the same as the first embodiment, so the description is omitted here.

[0078] In this embodiment, when performing the above Figure 2F When ion implantation is performed, Figure 8As shown, ion implantation is also performed from a direction oblique to the normal direction of one surface 100a of the semiconductor wafer 100. In this case, the thinner the film thickness of the resist 120, the smaller the area that will be shadowed by the resist 120 and not implanted with ions. Therefore, it is preferable to set the aperture ratio of the resist 120 (i.e., the aperture ratio of the exposure adjustment portion 200a) in consideration of the effect of ion implantation from an oblique direction.

[0079] In addition, Figure 8 In the figure, the injection region 130 formed in the portion of the piezoelectric film component 110a exposed from the opening 121 and the injection region 130 formed at different positions in the thickness direction of the piezoelectric film component 110a are omitted.

[0080] This reduces the number of areas in the piezoelectric film component 110a that are shadowed by the resist 120 and not ion-implanted. Specifically, the implantation region 130 can be formed even in the portion of the piezoelectric film component 110a located below the resist 120. This reduces local stress nonuniformity in the piezoelectric film component 110a.

[0081] (Third embodiment)

[0082] The third embodiment will be described. Compared to the first embodiment, this embodiment has a plurality of diaphragm portions 12 formed therein. The rest is the same as the first embodiment, so description thereof will be omitted here.

[0083] The ultrasonic sensor of this embodiment is as follows Figure 9 As shown in FIG. 1 , two diaphragm portions 12 are formed by forming two recesses 11 in a semiconductor substrate 10. Furthermore, a piezoelectric film 13 and an electrode film 14 are sequentially stacked on each diaphragm portion 12.

[0084] Furthermore, in this embodiment, the stress maintained by the piezoelectric films 13 located on each diaphragm portion 12 is set to a different value. In other words, the resonant frequency of each piezoelectric film 13 is set to a different value. Therefore, for example, when this ultrasonic sensor is used to construct a transmitter, the different resonant frequencies of each piezoelectric film 13 make it easy to construct a transmitter capable of transmitting different transmission waves.

[0085] Such an ultrasonic sensor only needs to be Figure 2D to Figure 2FIn the process, the amount of ions injected into the piezoelectric film constituent portion 110a constituting each piezoelectric film 13 can be adjusted based on the stress distribution of the piezoelectric layer 110. For example, by forming the piezoelectric layer 110, two piezoelectric film constituent portions 110a are formed in one chip forming region 101. Therefore, when the piezoelectric layer 110 is formed, in one chip forming region 101, for example, when the stress of the piezoelectric film constituent portion 110a on one side is the same as that of the piezoelectric film constituent portion 110a on the other side, the amount of ions injected into each piezoelectric film constituent portion 110a can be made different. That is, in Figure 2D In the process, as a photomask 200, a photomask having an aperture ratio of the exposure adjustment portion 200a is prepared so that the exposure amount of the resist 120 on the piezoelectric film component 110a located on one side is different from the exposure amount of the resist 120 on the piezoelectric film component 110a located on the other side.

[0086] Thus, even if an ultrasonic sensor is constructed with a plurality of piezoelectric films 13, the same effects as those of the first embodiment can be obtained. In the above description, an example is described in which the stress of each piezoelectric film 13 is different, but the stress of each piezoelectric film 13 may be the same.

[0087] (Fourth embodiment)

[0088] The fourth embodiment will be described. Compared to the first embodiment, this embodiment performs ion implantation on the electrode layer 140. The rest is the same as the first embodiment, so the description thereof will be omitted here.

[0089] First, in this embodiment, ion implantation is not performed on the piezoelectric layer 110. Figure 10 As shown, after forming the electrode layer 140, ion implantation is performed on the electrode film component portion 140a of the electrode layer 140 that constitutes the electrode film 14, thereby reducing the stress of the electrode film component portion 140a to a desired value. Note that in this embodiment, the electrode layer 140 corresponds to a thin layer, and the electrode film component portion 140a corresponds to a device component.

[0090] Specifically, ion implantation into the electrode film component portion 140a is performed using the same method as described above for ion implantation into the piezoelectric film component portion 110a. Specifically, after forming the electrode layer 140, a resist 150 is placed on the electrode layer 140. Then, using a photomask 200 whose aperture ratio is adjusted based on the stress distribution so that the stress in the electrode film component portion 140a reaches a desired value, an opening 151 is formed in the resist 150. Ion implantation is performed using this resist 150 as a mask to form an implantation region 160.

[0091] In this case, in this embodiment, since ion implantation is not performed on the piezoelectric layer 110, a state of non-uniform stress in the surface direction is generated in the piezoelectric layer 110. Furthermore, in this embodiment, the stress distribution of the piezoelectric layer 110 and the electrode layer 140 as a whole is determined in advance, and the stress of the electrode film component 140a is set to a desired value, thereby achieving the desired stress value in the piezoelectric film component 110a and the electrode film component 140a as a whole.

[0092] In addition, Figure 10 , a diagram showing one implantation region 160 formed along the thickness direction of the electrode layer 140 is shown. However, when the acceleration voltage is changed and ion implantation is performed multiple times, multiple implantation regions 160 are formed along the thickness direction of the electrode layer 140.

[0093] Thus, even if ion implantation is performed on the electrode layer 140 , the same effects as those of the first embodiment can be obtained. In this embodiment, an example is described in which ion implantation is not performed on the piezoelectric layer 110 . However, ion implantation may be performed on the electrode layer 140 after the piezoelectric layer 110 is implanted.

[0094] (Fifth embodiment)

[0095] The fifth embodiment will be described. Compared to the first embodiment, this embodiment performs stepper exposure on the resist 120. The rest is the same as the first embodiment, so the description thereof will be omitted here.

[0096] In the above embodiments, the method of performing alignment exposure while fixing the photomask 200 when exposing the resist 120 has been described. However, stepper exposure may be performed while moving the photomask 200 and the semiconductor wafer 100 when exposing the resist 120.

[0097] For example, Figure 11 As shown, it is assumed that when a piezoelectric layer 110 is formed on one side 100a of a semiconductor wafer 100, a tensile stress is generated in the portion located at the center of the semiconductor wafer 100 and a compressive stress is generated in the portion located at the outer edge of the piezoelectric layer 110. Furthermore, it is assumed that the stress changes smoothly from the portion located at the center of the semiconductor wafer 100 toward the outer edge. Figure 11 Schematic diagram showing the stress generated in the piezoelectric film component 110a of each chip forming region 101 in a continuous manner. Figure 11 The stress distribution in one direction along the surface direction of the piezoelectric layer 110 passing through the portion located at the center of the semiconductor wafer 100 is expressed as follows: Figure 12 Schematic diagram of the stress in each area.

[0098] In this case, for example Figure 12 As shown, in the piezoelectric layer 110 , a circular region including the center of the semiconductor wafer 100 is defined as a first region R1 , and regions concentrically extending from the first region R1 are defined as a second region R2 , a third region R3 , and a fourth region R4 , respectively.

[0099] Moreover, in the above Figure 2D When exposing the resist 120 in the process of the present invention, for example, two intermediate masks with different aperture ratios of the exposure adjustment portion 200a are prepared as intermediate masks used as the photomask 200, and the resist 120 is exposed in a step-by-step manner using the intermediate masks. Specifically, in the first region R1, exposure is performed as it is without using the intermediate mask. That is, by Figure 2E In the process, the resist 120 in the first region R1 is completely removed.

[0100] Furthermore, in the second region R2 and the third region R3, the resist 120 is exposed using an intermediate mask with a gradually decreasing aperture ratio of the exposure adjustment section 200a. That is, the resist 120 is exposed so that the aperture ratio decreases in the order of the portion on the piezoelectric film component 110a in the second region R2 and the portion on the piezoelectric film component 110a in the third region R3. In addition, the fourth region R4 is not particularly exposed in this embodiment. Thus, after the exposure adjustment section 200a is performed, the resist 120 is exposed. Figure 2E During the process, the openings 121 with decreasing aperture ratios are formed in the resist 120 in the order of the first region R1, the second region R2, and the third region R3, and the opening 121 is not formed in the fourth region R4.

[0101] Furthermore, by performing ion implantation using the resist 120, the stress distribution of the piezoelectric layer 110 is as follows: Figure 13 As shown, it becomes a so-called waveform, in other words, a sawtooth shape. Figure 13 1 is a schematic diagram continuously showing stress distribution along one direction in the surface direction, passing through a portion located at the center of the semiconductor wafer 100 , and generating stress in the piezoelectric film component 110 a of each chip formation region 101 .

[0102] Specifically, the piezoelectric layer 110 is in the following state: it has the first to fourth regions R1 to R4 along a direction in the surface direction of the semiconductor chip 100 and through a portion located on the center of the semiconductor chip 100, and a plurality of piezoelectric film constituent parts 110a are arranged in each region R1 to R4. Furthermore, the stress distribution of the plurality of piezoelectric film constituent parts 110a arranged in each region R1 to R4 along one direction is set as follows. That is, the stress distribution has a maximum value and a minimum value of stress in each region R1 to R4, and the stress distribution is set to a shape in which the rate of change (i.e., the slope) between the maximum value and the minimum value of stress in each region R1 to R4 is smaller than the rate of change of stress at the boundary portion of the adjacent region. In addition, the rate of change here is a value derived from the ratio of the stress difference between the maximum value and the minimum value and the distance between the parts that become the maximum value and the minimum value. For example, it was confirmed that: in Figure 13 In region R3, the rate of change between the maximum and minimum stress values ​​is smaller than the rate of change of stress at the boundary with region R2.

[0103] Furthermore, in this embodiment, since the resist 120 is exposed in a stepper manner using two types of reticle, the stress generated in the piezoelectric film component 110 a can be divided into four parts.

[0104] In this manner, the same effects as those of the first embodiment can be achieved by performing stepper exposure on the resist 120. Furthermore, when a plurality of reticles are prepared as the photomask 200, the following effects can also be achieved. Specifically, if a portion of the stress distribution changes due to aging of the film forming apparatus, etc., it is sufficient to simply change the segmentation structure (i.e., shot map) of each region or change the reticles corresponding to the changed portions. This makes it possible to easily cope with aging.

[0105] In addition, while the above description uses an example of using two reticle types, the type of reticle can be appropriately changed. That is, if N is an integer greater than 1, then by using N types of reticle types with different aperture ratios in the exposure adjustment unit 200a, the stress distribution of the piezoelectric layer 110 can be divided into (N+2) parts.

[0106] (Other embodiments)

[0107] While the present invention has been described based on embodiments, it should be understood that the present invention is not limited to such embodiments or configurations. The present invention also encompasses various modifications and variations within the scope of equivalents. Furthermore, various combinations or configurations, including only one element, or combinations or configurations thereof, including more than or less than these elements, also fall within the scope and spirit of the present invention.

[0108] For example, in each of the above embodiments, the diaphragm portion 12 may be polygonal instead of circular. In addition, in each of the above embodiments, the recessed portion 11 may not be formed, and the diaphragm portion 12 may not be provided.

[0109] Furthermore, in the first to third embodiments described above, the case where tensile stress is generated in the piezoelectric layer 110 is described. However, the same applies to the case where compressive stress is generated in the piezoelectric layer 110. When compressive stress is generated in the piezoelectric layer 110, the aperture ratio of the photomask 200 can be reversed. That is, by ion implantation into the piezoelectric layer 110, compressive stress is applied to the piezoelectric layer 110. Therefore, when compressive stress is generated in the piezoelectric layer 110, if it is desired to equalize the compressive stress in each piezoelectric film component 110a, the aperture ratio of the photomask 200 can be adjusted so that a larger amount of ions is implanted into the portion with less compressive stress than into the portion with greater compressive stress. Similarly, in the fourth embodiment described above, the aperture ratio of the photomask 200 can be adjusted based on the stress generated in the electrode layer 140 to adjust the amount of ions implanted into the electrode film component 140a.

[0110] In addition, in each of the above-mentioned embodiments, the shape of the opening 201 of the photomask 200 can be changed as appropriate. Figure 14A As shown in FIG. 2 , the opening 201 of the photomask 200 may also be formed in a concentric circle shape. Figure 14B As shown, the opening portion 201 of the photomask 200 may also be formed by radially extending relative to the center of the exposure adjustment portion 200a. However, the photomask 200 preferably forms a plurality of opening portions 201 in consideration of positional deviation, etc. For example, in the case where the aperture ratio of the exposure adjustment portion 200a is set to 50%, it is preferred that the aperture ratio is 50% not by one opening portion 201 but by a plurality of opening portions 201. In this case, the opening portion 201 is preferably a shape having regularity such as n-fold symmetry (where n is an integer greater than 2) relative to the center of the exposure adjustment portion 200a. In addition, Figure 14A and Figure 14B Although not a cross-sectional view, portions of the photomask 200 other than the opening 201 are hatched for easier understanding.

[0111] Furthermore, in each of the above-described embodiments, heat treatment may not be performed after forming the implantation region 130. This manufacturing method can also provide the piezoelectric layer 110 with a desired stress distribution by performing ion implantation.

[0112] Furthermore, in each of the above embodiments, the thin layer may not be the piezoelectric layer 110 or the electrode layer 140 , but may be made of other materials.

[0113] Furthermore, the above-mentioned embodiments can be combined. For example, the above-mentioned second embodiment can be combined with the above-mentioned third to fifth embodiments, and ion implantation can also be performed from a direction inclined relative to the normal direction. The above-mentioned third embodiment can also be combined with the above-mentioned fourth and fifth embodiments to provide a method for manufacturing an element forming wafer 300 that constitutes an ultrasonic sensor having multiple piezoelectric films 13. The above-mentioned fourth embodiment can also be combined with the above-mentioned fifth embodiment to perform ion implantation on the electrode film component 140a. In addition, the above-mentioned embodiments can be further combined with each other, and the combination method can be appropriately changed.

Claims

1. A method for manufacturing an element-forming wafer having a thin layer formed on a semiconductor wafer, wherein: Follow these steps: preparing the semiconductor wafer having a plurality of chip forming regions; forming the thin layer on the semiconductor wafer; and Assuming that the portion constituting each element in the chip forming region of the thin layer is an element constituting portion, and adjusting the stress so that the stress of the element constituting portion becomes a predetermined value; In the above-mentioned step of adjusting the stress, the following steps are performed: exist A resist is disposed on the thin layer; exposing the resist using a photomask having an opening; developing the resist to form an opening in the resist; and performing ion implantation using the resist as a mask; In the step of exposing the resist, the photomask in which the ratio of the opening is adjusted based on the stress generated in the device constituent portion is used.

2. The method for manufacturing a device-forming wafer according to claim 1, wherein: In the step of exposing the resist, alignment exposure is performed on the resist using the photomask.

3. The method for manufacturing a device-forming wafer according to claim 1, wherein: In the step of exposing the resist, stepper exposure is performed on the resist using the photomask.

4. The method for manufacturing a device-forming wafer according to any one of claims 1 to 3, wherein: In the step of performing ion implantation, ion implantation is also performed from a direction tilted with respect to a normal direction of a surface direction of the semiconductor wafer.

5. The method for manufacturing a device-forming wafer according to any one of claims 1 to 3, wherein: In the above-mentioned step of performing ion implantation, ion implantation is performed a plurality of times so that implantation regions formed by the ion implantation are staggered.

6. The method for manufacturing a device-forming wafer according to any one of claims 1 to 3, wherein: After the above-mentioned ion implantation, heat treatment is performed.

7. The method for manufacturing a device-forming wafer according to any one of claims 1 to 3, wherein: In the step of forming the thin layer, a piezoelectric layer is formed; In the step of performing ion implantation, the ions are implanted with an element of the same group number as that of the element constituting the piezoelectric layer.

8. A device forming wafer having a thin layer formed on a semiconductor wafer, characterized in that: have: The semiconductor wafer has a plurality of chip forming areas; and The thin layer is formed on the semiconductor wafer; The portion constituting each element in the chip forming region of the thin layer is defined as an element constituting portion. The thin layer includes a plurality of regions extending along one direction in the surface direction of the semiconductor wafer and passing through a portion located at the center of the semiconductor wafer. By adjusting the ratio of the opening portion of the photomask used to expose the resist arranged on the above-mentioned thin layer, when a plurality of the above-mentioned element components are respectively arranged in the above-mentioned multiple regions, the stress distribution along the above-mentioned one direction of the above-mentioned element components arranged in the above-mentioned multiple regions has a stress maximum and a stress minimum in each of the above-mentioned regions, and the rate of change of the stress between the above-mentioned maximum and the above-mentioned minimum in the above-mentioned region is smaller than the rate of change of the stress at the boundary portion of the adjacent above-mentioned region.

9. The device forming wafer according to claim 8, wherein: The thin layer is composed of a piezoelectric layer; The piezoelectric layer includes an implantation region implanted with an element having the same group number as that of an element constituting the piezoelectric layer.

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