Semiconductor memory device and operating method thereof

Abstract

A semiconductor memory device and an operating method thereof are disclosed. A semiconductor memory device includes a control circuit adapted to provide an active address inputted with an active command as an input address; a plurality of latches adapted to sequentially store the input address as a latched address according to an input control signal, and output the latched address as a target address according to an output control signal; a plurality of counters corresponding to the latches, respectively, each of the counters being adapted to increase a count value corresponding to the latch when the active address matches the latched address stored in the latch; and a refresh controller adapted to divide the counters and the latches into a plurality of groups based on the count values, and generate a reset signal for initializing the counters included in one of the plurality of groups in response to a refresh command.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0006102, filed on January 15, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor design technology, and more specifically, to a semiconductor memory device that performs a target refresh operation. Background Technology

[0004] A semiconductor memory device's memory cell includes a transistor that acts as a switch and a capacitor that stores charge (or data). The presence or absence of any charge in the capacitor of the memory cell (i.e., whether the voltage across the capacitor is high or low) determines whether the data is a logic high level (logic level 1) or a logic low level (logic level 0).

[0005] Data is stored as charge accumulated in capacitors, theoretically with no power consumption. However, leakage current can occur due to factors such as the PN coupling of transistors, causing the initial charge stored in the capacitor to disappear, resulting in data loss. To prevent this, data is typically read from the memory cell before loss, and the normal amount of charge is recharged back into the cell based on the read data. In this way, data can only be retained if this operation is repeated periodically, and the process of recharging the cell charge is called a refresh operation (hereinafter referred to as a normal refresh operation).

[0006] Recently, in addition to normal refresh operations, additional refresh operations (hereinafter referred to as "target refresh operations") are performed on memory cells of specific word lines that are likely to lose data due to row hammering. Row hammering refers to the phenomenon where data in memory cells coupled to or adjacent to a specific word line is corrupted due to excessive activation of the corresponding word line. To prevent row hammering, target refresh operations are performed on word lines that have been activated more than a predetermined number of times (hereinafter referred to as "target word lines"). Target refresh operations can also be performed on word lines adjacent to the target word line. Summary of the Invention

[0007] Embodiments of the present invention relate to a semiconductor memory device capable of sampling an activation address and storing it in a plurality of latches, and selecting a target address for a target refresh operation from the latched addresses based on the number of repeatedly input activation addresses.

[0008] According to one embodiment of the present invention, a semiconductor memory device includes an input control circuit adapted to provide an active address inputted with an active command as an input address; a plurality of latches adapted to sequentially store the input address as a latched address according to an input control signal and output the latched address as a target address according to an output control signal; a plurality of counters corresponding to the latches, respectively, each of the counters being adapted to increase a count value corresponding to the latch when the active address matches the latched address stored in the latch; and a refresh controller adapted to divide the counters and the latches into a plurality of groups based on the count values and generate a reset signal for initializing the counters included in one of the groups in response to a refresh command.

[0009] According to another embodiment of the present invention, a semiconductor memory device includes a plurality of latches adapted to store an input address as a latched address according to an input control signal and output the latched address as a target address according to an output control signal; a plurality of address comparators adapted to compare an active address with the latched address to generate a plurality of match signals; a plurality of counters adapted to generate a plurality of count signals according to the match signals, respectively, and be initialized according to a plurality of reset signals, respectively; a group decoder adapted to generate a plurality of group signals and first to third group enable signals based on the count signals, each of the group signals being formed of first to third bits respectively representing first to third groups; a latch input control circuit adapted to generate the input control signal according to the match signals and a null signal respectively indicating states of the counters; a latch output control circuit adapted to generate the output control signal corresponding to first and second bits of the group signals according to a refresh command and the first to third group enable signals; and a reset control circuit adapted to generate a reset signal corresponding to a third bit of the group signals according to the refresh command.

[0010] According to another embodiment of the present invention, a method for operating a semiconductor memory device includes generating respective count signals by counting respective match signals generated through comparison between an active address and a latched address stored in respective latches via a plurality of counters when an active command is inputted; dividing the counters and the latches into a first group and a second group based on the count signals; and outputting one of the latched addresses of the latches included in the first group as a target address and initializing the counters included in the second group when a refresh command is inputted.

[0011] According to another embodiment of the present application, a semiconductor memory device includes a row control circuit configured to perform a target refresh operation on an array of memory cells in accordance with a target refresh command and a target address; and a refresh control circuit configured to: latch an active address when the active address is different from any of the latched addresses; increase a count corresponding to a particular address of the latched addresses when the active address is the same as the particular address; provide any one of one or more of the latched addresses corresponding to a count greater than a threshold value to the row control circuit as the target address in response to the target refresh command, and initialize the count corresponding to the provided address; provide any of one or more of the latched addresses corresponding to a count less than the threshold value to the row control circuit as the target address in response to the target refresh command when there is no latched address corresponding to a count greater than the threshold value among the latched addresses; and initialize the count less than the threshold value. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the present application.

[0013] Figure 2 is a detailed circuit diagram illustrating Figure 1 the input control circuit illustrated in FIG. 4.

[0014] Figure 3 is a detailed circuit diagram illustrating Figure 2 the latch circuit illustrated in FIG. 5.

[0015] Figure 4 is Figure 3 an operation waveform diagram of the control signal generation circuit illustrated in FIG. 6.

[0016] Figure 5 is a detailed circuit diagram illustrating Figure 2 the comparison circuit illustrated in FIG. 7.

[0017] Figure 6 is a detailed circuit diagram illustrating Figure 2 the count circuit illustrated in FIG. 8.

[0018] Figure 7 is a detailed circuit diagram illustrating Figure 2 the refresh controller illustrated in FIG. 9.

[0019] Figure 8 is a detailed circuit diagram illustrating Figure 2 the refresh controller illustrated in FIG. 9.

[0020] Figure 9 is a detailed circuit diagram illustrating Figure 2 the refresh controller illustrated in FIG. 9.

[0021] Figure 10 is a detailed circuit diagram illustrating Figure 9A flowchart of the operation of the group decoder shown.

[0022] Figure 11 is a diagram illustrating Figure 9 A detailed circuit diagram of the latch input control circuit shown.

[0023] Figure 12 and Figure 13 is a flowchart describing the operation of a memory device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0024] Embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. Like reference numerals refer to like elements throughout the present disclosure.

[0025] It will be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element or coupled or connected thereto via another element. It will also be understood that the terms "comprise", "comprising", and "comprises", and the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0026] In order to select target word lines to be refreshed during a target refresh operation, the memory device can need to count the number of times an activation address (input together with an activation command) is input. When the number (or type) of repeated (or identical) activation addresses is small, the number of activations per target word line per unit time can increase, thereby increasing the risk of row hammering. In this case, it can be efficient to count all the activation addresses, the number of which is small. On the other hand, when the number (or type) of repeated activation addresses is large, the number of activations per target word line per unit time can be small, which can reduce the risk of row hammering, but the burden on the memory device can increase due to the increase in area occupied by the counting circuit and the latch circuit for the large number of individual activation addresses. The following discloses a scheme for efficiently managing the counting circuit and the latch circuit by counting all the activation addresses when the number (or type) of repeated activation addresses is small, and initializing the counting circuit corresponding to the latch circuit at each target refresh period when the number (or type) of repeated activation addresses is large.

[0027] Figure 1 is a block diagram illustrating a storage system 10 according to an embodiment of the present application.

[0028] Referring to Figure 1 , the storage system 10 can include a semiconductor memory device 100 and a memory controller 200.

[0029] The memory controller 200 can control general operations of the storage system 10, and it can control general data exchange between a host and the semiconductor memory device 100. The memory controller 200 can generate command / address signals C / A according to a request REQ from the host and provide the generated command / address signals C / A to the semiconductor memory device 100. The memory controller 200 can provide a clock CK along with the command / address signals C / A to the semiconductor memory device 100. The memory controller 200 can provide data DQ corresponding to the request REQ provided from the host along with data strobe signals DQS to the semiconductor memory device 100. The memory controller 200 can receive the data DQ (read from the semiconductor memory device 100) along with the data strobe signals DQS and provide the data DQ and the data strobe signals DQS to the host.

[0030] The semiconductor memory device 100 can perform a refresh operation, a write operation, and a read operation according to the clock CK, the command / address signals C / A, the data strobe signals DQS, and / or the data DQ provided from the memory controller 200. The refresh operation can include a normal refresh operation in which the semiconductor memory device 100 sequentially refreshes a plurality of word lines; and / or a target refresh operation in which one or more adjacent word lines disposed adjacent to a word line having a large number of activation times or a high activation frequency are refreshed.

[0031] The semiconductor memory device 100 can generate internal commands I CMD (refer to Figure 2 ) and internal addresses I ADD (refer to Figure 2 ) by buffering the command / address signals C / A, and can generate an activation command ACT (refer to Figure 2 ), a precharge command PCG (refer to Figure 2 ), a normal refresh command REF (refer to Figure 2 ), and a target refresh command TREF (refer to Figure 2 ) related to a row control operation by decoding the I CMD commands. The semiconductor memory device 100 can perform a normal refresh operation according to the normal refresh command REF and a target refresh operation according to the target refresh command TREF. The semiconductor memory device 100 can additionally generate a command (e.g., a read command or a write command) related to a data input / output operation by decoding the I CMD commands.

[0032] Specifically, the semiconductor memory device 100 can include a memory cell array 110 and a refresh control circuit 130. In the memory cell array 110, a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines can be arranged in the form of an array. The refresh control circuit 130 can provide a target address TADD for selecting a word line to be refreshed from among the word lines. The refresh control circuit 130 can sample an active address ACT_ADD according to an active command ACT and output the sampled active address ACT_ADD as the target address TADD.

[0033] Figure 2 is a detailed block diagram of the semiconductor memory device 100 illustrated in Figure 1

[0034] Referring to Figure 2 The semiconductor memory device 100 can include a memory cell array 110, a row control circuit 112, a clock buffer 121, a command / address (CA) buffer 122, a command decoder 123, a control signal generation circuit 124, an address latch 125, and a refresh control circuit 130.

[0035] The memory cell array 110 can include memory cells MC coupled to word lines WL and bit lines. The memory cell array 110 can include a plurality of memory banks. The number of memory banks or the number of memory cells MC can be determined based on the capacity of the semiconductor memory device 100.

[0036] The clock buffer 121 can receive a clock CK from the memory controller 200. The clock buffer 121 can generate an internal clock CLK by buffering the clock CK. According to an embodiment of the present application, the memory controller 200 can transmit system clocks CK_t and CK_c to the semiconductor memory device 100 in a differential manner, and the semiconductor memory device 100 can include clock buffers that receive the differential clocks CK_t and CK_c, respectively.

[0037] The CA buffer 122 can receive a command / address signal C / A from the memory controller 200 based on the clock CK. The CA buffer 122 can sample the command / address signal C / A based on the clock CK and output an internal command ICMD and an internal address IADD. Accordingly, the semiconductor memory device 100 can be synchronized with the clock CK.

[0038] ​The command decoder 123 can decode the internal command I CMD output from the CA buffer 122 to generate an activation command ACT, a precharge command PCG, a normal refresh command REF, a target refresh command TREF, and a sampling enable signal RH EN. The command decoder 123 can additionally generate a read command RD, a write command WT, a mode register command MRS, etc. by decoding the internal command I CMD. Here, the target refresh command TREF can be generated each time the normal refresh command REF is inputted a predetermined number of times. For example, the target refresh command TREF can be generated each time the normal refresh command REF is issued 4096 times.

[0039] The control signal generation circuit 124 can generate first to fourth activation signals ACT0 to ACT3 which are sequentially activated according to the sampling enable signal RH EN, the internal clock CLK, and the activation command ACT. In other words, the control signal generation circuit 124 can generate four activation signals ACT0 to ACT3 which are sequentially activated based on one activation command ACT. The detailed structure and operation of the control signal generation circuit 124 will be described later with reference to FIG. 2. Figure 3 and Figure 4

[0040] The address latch 125 can latch the internal address I ADD as an activation address ACT ADD according to the activation command ACT.

[0041] The refresh control circuit 130 can sample the activation address ACT ADD according to the first to fourth activation signals ACT0 to ACT3 to sequentially store a plurality of latched addresses LADD# (1≤#≤16) (although more than 16 latched addresses can be used), select one latched address from the latched addresses LADD# according to the target refresh command TREF, and output the selected one latched address as a target address TADD. In particular, according to one embodiment of the present application proposed, when the target refresh command TREF is activated, the refresh control circuit 130 can select one latched address from the latched addresses LADD# according to a count value obtained by counting the number of times the activation address ACT ADD is repeatedly inputted, output the selected latched address LADD# as the target address TADD, and initialize the count value corresponding to some of the latched addresses LADD#.

[0042] In detail, the refresh control circuit 130 can include an input control circuit 131, a latch circuit 132, a comparison circuit 134, a count circuit 136, and a refresh controller 138.

[0043] The input control circuit 131 can provide the activation address ACT ADD as an input address ADD IN to the latch circuit 132 according to the activation command ACT.​

[0044] The latch circuit 132 may include multiple latches (such as, for example, Figure 6 LAT1 to LAT16. Latches LAT1 to LAT16 can sequentially store the input address ADD_IN according to the input control signal LAT_IE#, and output the latch address LADD# as the target address TADD according to the output control signal LAT_OE#. In particular, each of latches LAT1 to LAT16 can receive one of the first to fourth activation signals ACT0 to ACT3, and when the received activation signal is activated, it provides the latch address LADD# to the comparator circuit 134. The detailed structure of latch circuit 132 will be referred to later. Figure 6 Describe it.

[0045] Comparator circuit 134 generates multiple match signals HIT# by comparing the latched address LADD# with the active address ACT_ADD. When the active address ACT_ADD matches a specific latched address LADD#, comparator circuit 134 activates the corresponding match signal HIT#. The detailed structure of comparator circuit 134 will be described in [reference needed]. Figure 7 Describe it.

[0046] The counting circuit 136 may include a plurality of counters (such as, for example, corresponding to latches LAT1 to LAT16 respectively) Figure 8 Counters C1 to C16 can receive a match signal HIT# and generate multiple counting signals CNT#. Each of counters C1 to C16 can increment its count value when the activation address ACT_ADD matches the latch address ADD# stored in the corresponding latch and thus the corresponding match signal is activated. Specifically, each of counters C1 to C16 can correspond to one of the first to fourth activation signals ACT0 to ACT3, and increments its count value according to the corresponding match signal HIT# when the corresponding activation signal is activated. Counters C1 to C16 can output multiple counting signals CNT# corresponding to the count values ​​respectively. Each of counters C1 to C16 can be initialized according to a corresponding reset signal among multiple reset signals RST#. In addition, when the count value of counters C1 to C16 is zero, counters C1 to C16 can output multiple empty signals NULL#, indicating that the current state is an empty state with a logic high level. The detailed structure of the counting circuit 136 will be referred to later. Figure 8 Describe it.

[0047] In one embodiment, when it is determined based on the match signal HIT# and the null signal NULL# that the active address ACT_ADD does not match any latched address LADD# and that all of the latches LAT1 to LAT16 are in a full state, the input control circuit 131 can randomly sample the active address ACT_ADD as a shadow address SDW_ADD (refer to Figure 5 ). The input control circuit 131 can provide the shadow address SDW_ADD as the input address ADD_IN in response to the target refresh command TREF. Thus, the shadow address SDW_ADD can be stored in the latches in response to the target refresh command TREF. The detailed structure of the input control circuit 131 will be described later with reference to Figure 5 .

[0048] The refresh controller 138 can divide the counters C1 to C16 and the latches LAT1 to LAT16 into a plurality of groups based on the count signal CNT#. For example, the refresh controller 138 can classify the counters each having a count value equal to or greater than a threshold value as a first group, and classify the counters each having a count value less than the threshold value as a second group. Alternatively, the refresh controller 138 can classify each counter having a count value equal to or greater than a first threshold value as a first group, classify each counter having a count value equal to or greater than a second threshold value and less than the first threshold value as a second group, and classify each counter having a count value less than the second threshold value as a third group.

[0049] The refresh controller 138 can generate a reset signal RST# for initializing only the counters included in one group in response to the target refresh command TREF. In this example, the one group can be the group of the counters each having a count value less than the threshold value. Thus, the counters having a count value less than the threshold value and thus belonging to the one group can be initialized at each target refresh period.

[0050] Further, in response to the target refresh command TREF, the refresh controller 138 can generate an output control signal LAT_OE# to output one of the latch addresses LADD# of the latches LAT1 to LAT16 included in the remaining group as the target address TADD. Here, in the present example, the remaining group can be a group of the counters each having a count value equal to or greater than the threshold value. Thus, one of the latch addresses corresponding to a large count value can be output as the target address of the latch addresses LADD# of the latches. When any of the latches LAT1 to LAT16 does not belong to the remaining group of the counters each having a count value equal to or greater than the threshold value, the output control signal LAT_OE# can be generated to output the latch address LADD# of a specific latch (e.g., the first latch LAT1) as the target address TADD. Further, the refresh controller 138 can generate a reset signal for initializing the counter corresponding to the latch whose latch address LADD# is output as the target address TADD.

[0051] Further, when one of the first to fourth activation signals ACT0 to ACT3 or the target refresh command TREF is activated, the refresh controller 138 can generate an input control signal LAT_IE# to store the input address ADD_IN in one of the latches LAT1 to LAT16 selected based on the match signal HIT# and the null signal NULL#. Here, in the present example, the refresh controller 138 can determine that the activation address ACT_ADD does not match any of the latch addresses LADD# based on the match signal HIT#, and generate the input control signal LAT_IE# to store the input address ADD_IN in one of the latches LAT1 to LAT16 selected based on the null signal NULL#. The detailed structure of the refresh controller 138 will be described later with reference to FIG. 2. Figures 9 to 11

[0052] When the activation command ACT is activated, the row control circuit 112 can activate the word line WL corresponding to the internal address IADD, and pre-charge the activated word line WL when the pre-charge command PCG is activated. To select the word line to be refreshed during the normal refresh operation, a refresh counter for generating sequentially increasing count addresses based on a normal refresh command REF can be additionally provided. The row control circuit 112 can perform a normal refresh operation based on the normal refresh command REF, which sequentially refreshes a plurality of word lines WL corresponding to the count addresses. The row control circuit 112 can perform a target refresh operation based on the target refresh command TREF, which refreshes one or more adjacent word lines corresponding to the target address TADD.

[0053] ​With the above structure, when the target address TADD is selected from the latch addresses LADD# of latches LAT1 to LAT16 by sampling the activation address ACT_ADD, the semiconductor memory device 100 can divide counters C1 to C16 and latches LAT1 to LAT16 into at least two groups based on the count value obtained by counting the number of times the activation address ACT_ADD is repeatedly input. Furthermore, during each target refresh period, the semiconductor memory device 100 can output one of the latch addresses LADD# of the latches belonging to the group of counters that all have large count values ​​as the target address, and initialize the counters belonging to the group of counters that all have small count values. In this way, the semiconductor memory device 100 can prevent unnecessary address comparison operations, thereby improving refresh efficiency.

[0054] In the following text, reference will be made to Figures 3 to 11 The detailed structure of each component is described below. In the following description, the case in which the first to sixteenth latches LAT1 to LAT16 are located in the latch circuit 132 and the first to sixteenth counters C1 to C16 are located in the corresponding counting circuit 136 is used as an example.

[0055] Figure 3 It is a diagram. Figure 2 The detailed circuit diagram of the control signal generation circuit 124 shown is shown. Figure 4 It is a diagram. Figure 3 The diagram shows the operation waveform of the control signal generation circuit 124.

[0056] Reference Figure 3 The control signal generation circuit 124 may include a clock generation unit 210 and a signal generation unit 230.

[0057] When the sampling enable signal RH_EN and the activation command ACT are activated, the clock generation unit 210 can generate the target clock RHCLK based on the internal clock CLK. The clock generation unit 210 can deactivate the target clock RHCLK to a logic low level according to the delay signal ACT4D of the fifth activation signal ACT4.

[0058] Specifically, the clock generation unit 210 may include a set signal generator 212, a delay unit D, an SR latch 214, and a clock generator 216.

[0059] The set signal generator 212 can generate a set signal S when both the sampling enable signal RH_EN and the activation command ACT are activated. According to an embodiment of the present application, the set signal generator 212 can be implemented as a logical AND gate. The delay D can generate a delayed signal ACT4D by delaying the fifth activation signal ACT4. The SR latch 214 can generate a clock enable signal RHCLK_EN which is activated according to the set signal S and deactivated according to the delayed signal ACT4D. When the clock enable signal RHCLK_EN is activated, the clock generator 216 can output an internal clock CLK as the target clock RHCLK. According to an embodiment of the present application, the clock generator 216 can be implemented as a logical AND gate.

[0060] The activation command ACT can be provided to the signal generation unit 230 as the first activation signal ACT0. The signal generation unit 230 can generate the second to fifth activation signals ACT1 to ACT4 by sequentially shifting the activation command ACT according to the target clock RHCLK. For example, the signal generation unit 230 can include four flip-flops 232 to 238 coupled in series to shift the activation command ACT in synchronization with the target clock RHCLK and output the second to fifth activation signals ACT1 to ACT4.

[0061] Referring to Figure 4 , with the above-described structure, the clock generation unit 210 can output the internal clock CLK as the target clock RHCLK when the sampling enable signal RH_EN and the activation command ACT are activated. The signal generation unit 230 can generate the first to fifth activation signals ACT0 to ACT4 by sequentially shifting the bit activation command ACT as the target clock RHCLK is toggled. The clock generation unit 210 can deactivate the target clock RHCLK to a logical low level according to the delayed signal ACT4D of the fifth activation signal ACT4. In other words, when an activation command ACT is input, the control signal generation circuit 124 can output the first to fifth activation signals ACT0 to ACT4 which are sequentially activated.

[0062] Hereinafter, in each of the drawings, the delayed signals ACT0D to ACT3D can be defined as signals in which the first to fourth activation signals ACT0 to ACT3 are delayed by a predetermined time.

[0063] Figure 5 is a detailed block diagram of the input control circuit 131 shown in Figure 2 FIG. 2.

[0064] Referring to Figure 5 , the input control circuit 131 can include an enable signal generation unit 310, a shadow latch unit 320, a selection signal generation unit 330, and an address output unit 340.

[0065] The enable signal generating unit 310 can determine whether the active address ACT_ADD matches all the latched addresses LADD1 to LADD16 and whether all the latches LAT1 to LAT16 are in the full state based on the first to sixteenth match signals HIT1 to HIT16 and the first to sixteenth null signals NULL1 to NULL16. For example, when the first to sixteenth match signals HIT1 to HIT16 are all deactivated to the logic low level and when the first to sixteenth null signals NULL1 to NULL16 are deactivated to the logic low level, the enable signal generating unit 310 can determine that the active address ACT_ADD does not match any of the latched addresses LADD1 to LADD16 and that all the latches LAT1 to LAT16 are in the full state. In this example, the enable signal generating unit 310 can generate the latch enable signal SL_EN according to the fourth active signal ACT3 and the oscillation signal SP_OSC.

[0066] In one embodiment, the enable signal generating unit 310 can include a determinator 312, an oscillator 314, a first combiner 316, and a second combiner 318.

[0067] The determinator 312 can generate a mismatch signal NO_MATCH based on the first to sixteenth match signals HIT1 to HIT16 and the first to sixteenth null signals NULL1 to NULL16. When the first to sixteenth match signals HIT1 to HIT16 and the first to sixteenth null signals NULL1 to NULL16 are all at the logic low level, the determinator 312 can generate the mismatch signal NO_MATCH activated to the logic high level. According to one embodiment of the present application, the determinator 312 can be implemented as a NOR gate performing a logical NOR (NOR) operation on the first to sixteenth match signals HIT1 to HIT16 and the first to sixteenth null signals NULL1 to NULL16. The oscillator 314 can generate an oscillation signal SP_OSC activated at a predetermined period. When the delayed signal ACT3D of the fourth active signal ACT3 and the oscillation signal SP_OSC are all activated, the first combiner 316 can activate and output a first combined signal ACT3D_OSC. When the mismatch signal NO_MATCH is activated, the second combiner 318 can generate the latch enable signal SL_EN according to the first combined signal ACT3D_OSC. According to one embodiment of the present application, the first combiner 316 and the second combiner 318 can be implemented as a logical AND gate.

[0068] The shadow latch unit 320 can store the active address ACT_ADD as the shadow address SDW_ADD according to the latch enable signal SL_EN. According to one embodiment of the present application, the shadow latch unit 320 can include a plurality of latches and can sequentially store a plurality of shadow addresses SDW_ADD.

[0069] The selection signal generating unit 330 can generate a selection signal SR_LOCK which is activated according to the target refresh command TREF and deactivated according to the first activation signal ACT0 (i.e., the activation command ACT). According to one embodiment of the present application, the selection signal generating unit 330 can be implemented as an SR latch.

[0070] The address output unit 340 can select one address from the active address ACT_ADD and the shadow address SDW_ADD according to the selection signal SR_LOCK and output it as the input address ADD_IN.

[0071] With the above-described structure, when the activation command ACT is input, the input control circuit 131 can provide the latch circuit 132 with the active address ACT_ADD as the input address ADD_IN. Here, in this example, when the active address ACT_ADD does not match any of the latched addresses LADD1 to LADD16 and the latches LAT1 to LAT16 are all in a full state, the input control circuit 131 can randomly sample the active address ACT_ADD as the shadow address SDW_ADD. When the target refresh command TREF is activated, the input control circuit 131 can provide the latch circuit 132 with the shadow address SDW_ADD as the input address ADD_IN. In other words, the semiconductor memory device 100 according to one embodiment of the present application can maximize the accuracy of address sampling by sampling the active address ACT_ADD which is not stored in the latches during one target refresh period using the additional shadow latch unit 320.

[0072] Figure 6 is a detailed block diagram of the latch circuit shown in Figure 2 FIG. 1.

[0073] Referring to Figure 6 , the latch circuit 132 can include first through sixteenth latches LAT1 to LAT16. The first through sixteenth latches LAT1 to LAT16 can sequentially store the input address ADD_IN according to respective signals among the first through sixteenth input control signals LAT_IE1 to LAT_IE6, respectively.

[0074] Further, among the first through sixteenth latches LAT1 through LAT16, the first latch LAT1, the fifth latch LAT5, the ninth latch LAT9, and the thirteenth latch LAT13 can receive the first activation signal ACT0. The second latch LAT2, the sixth latch LAT6, the tenth latch LAT10, and the fourteenth latch LAT14 can receive the second activation signal ACT1. The third latch LAT3, the seventh latch LAT7, the eleventh latch LAT11, and the fifteenth latch LAT15 can receive the third activation signal ACT2. The fourth latch LAT4, the eighth latch LAT8, the twelfth latch LAT12, and the sixteenth latch LAT16 can receive the fourth activation signal ACT3. In other words, four latches among the first through sixteenth latches LAT1 through LAT16 can receive the same activation signal.

[0075] Accordingly, the first through sixteenth latches LAT1 through LAT16 can output one of the first through sixteenth latch addresses LADD1 through LADD16 as the target address TADD according to a corresponding signal among the first through sixteenth output control signals LAT_OE1 through LAT_OE16, respectively, and provide the first through sixteenth latch addresses LADD1 through LADD16 to the comparison circuit 134 according to the first through fourth activation signals ACT0 through ACT3. Here, in this example, since the first through fourth activation signals ACT0 through ACT3 are sequentially activated, four latch addresses among the first through sixteenth latch addresses LADD1 through LADD16 can be provided to the comparison circuit 134 at the same time.

[0076] Figure 7 is a detailed block diagram of the comparison circuit 134 shown in Figure 2 FIG. 1.

[0077] Referring to Figure 7 , the comparison circuit 134 can include first through fourth address comparators CMP1 through CMP4. Each of the first through fourth address comparators CMP1 through CMP4 can receive four addresses among the first through sixteenth latch addresses LADD1 through LADD16, and compare the received latch addresses with the activation address ACT_ADD to generate first through sixteenth match signals HIT1 through HIT16. For example, the first address comparator CMP1 can generate first through fourth match signals HIT1 through HIT4 by comparing the first through fourth latch addresses LADD1 through LADD4 with the activation address ACT_ADD. Here, since four latch addresses among the first through sixteenth latch addresses LADD1 through LADD16 are provided at the same time, the first through fourth address comparators CMP1 through CMP4 can independently perform the comparison operation four times.

[0078] In other words, the semiconductor memory device 100 according to this embodiment of the present application can sequentially perform the comparison operation by using the sequentially activated first to fourth activation signals ACT0 to ACT3, thereby reducing the area occupied by the comparison circuit.

[0079] Figure 8 is a detailed block diagram of the count circuit 136 shown in Figure 2

[0080] Referring to Figure 8 , the count circuit 136 can include first to sixteenth counters Cl to C16.

[0081] Among the first to sixteenth counters Cl to C16, the first counter Cl, the fifth counter C5, the ninth counter C9, and the thirteenth counter C13 can receive a delayed signal ACT0D of the first activation signal ACT0. The second counter C2, the sixth counter C6, the tenth counter C10, and the fourteenth counter C14 can receive a delayed signal ACT1D of the second activation signal ACT1. The third counter C3, the seventh counter C7, the eleventh counter C11, and the fifteenth counter C15 can receive a delayed signal ACT2D of the third activation signal ACT2. The fourth counter C4, the eighth counter C8, the twelfth counter C12, and the sixteenth counter C16 can receive a delayed signal ACT3D of the fourth activation signal ACT3. In short, four of the first to sixteenth counters Cl to C16 can receive the same activation signal. Here, in this example, the count circuit 136 can perform the counting operation after the comparison operation of the comparison circuit 134 is completed by receiving the delayed signals of the activation signals.

[0082] When the respective signals among the first to sixteenth match signals HIT1 to HIT16 and the respective activation signals are all activated, the first to sixteenth counters Cl to C16 can increase the count value by one and output the respective first to sixteenth count signals CNT1<0:7> to CNT16<0:7>. Also, when any of the count values is zero, the respective counter among the first to sixteenth counters Cl to C16 can be activated to a logic high level and output the respective one among the first to sixteenth null signals NULL1 to NULL16, which indicates that the current state of the respective counter is a null state. Furthermore, the first to sixteenth counters Cl to C16 can be initialized according to the first to sixteenth reset signals RST1 to RST16, respectively. In Figure 8 In the above, the case where each of the first to sixteenth counters Cl to C16 is implemented as an 8-bit counter is described as an example.

[0083] Figure 9 is a detailed block diagram of the count circuit 136 shown in Figure 2 ​A detailed block diagram of the refresh controller 138 is illustrated. Figure 10 is a flowchart illustrating the operation of the group decoder 410. Figure 9 is a detailed circuit diagram of the latch input control circuit 420. In the following embodiments, a case where the refresh controller 138 divides the counters and the latches into the first to third groups will be described as an example. Figure 11 is a detailed circuit diagram of the latch input control circuit 420. In the following embodiments, a case where the refresh controller 138 divides the counters and the latches into the first to third groups will be described as an example.

[0084] Referring to Figure 9 , the refresh controller 138 can include the group decoder 410, the latch input control circuit 420, the latch output control circuit 430, and the reset control circuit 440.

[0085] The group decoder 410 can generate first to sixteenth group signals CNT_GRP1<1:3> to CNT_GRP16<1:3> and first to third group enable signals GRP_EN1 to GRP_EN3 based on the first to sixteenth count signals CNT1<0:7> to CNT16<0:7>. When the first to sixteenth count signals CNT1<0:7> to CNT16<0:7> are equal to or greater than a first threshold (e.g., 64), the group decoder 410 can classify the corresponding counter as the first group. When the first to sixteenth count signals CNT1<0:7> to CNT16<0:7> are equal to or greater than a second threshold (e.g., 8) and less than the first threshold, the group decoder 410 can classify the corresponding counter as the second group. When the first to sixteenth count signals CNT1<0:7> to CNT16<0:7> are less than the second threshold (e.g., 8), the group decoder 410 can classify the corresponding counter as the third group.

[0086] For example, referring to Figure 10When any of the most significant two bits (e.g., CNT1<6:7>) of the first count signal CNT1<0:7> is a logic high bit (YES in step S1010), the group decoder 410 can define the first counter C1 and the first latch LAT1 corresponding to the first counter C1 as the first group by setting the least significant bit CNT_GRP1<1> of the first group signal CNT_GRP1<1:3> to a logic high level in step S1020. When the most significant two bits (e.g., CNT1<6:7>) are both logic low bits (NO in step S1010) and when any of the middle three bits (e.g., CNT1<3:5>) of the first count signal (CNT1<0:7>) is a logic high bit (YES in step S1040), the group decoder 410 can set the first counter C1 and the first latch LAT1 corresponding to the first counter C1 as the second group by setting the middle bit CNT_GRP1<2> of the first group signal CNT_GRP1<1:3> to a logic high level in step S1050. Further, when the most significant two bits (e.g., CNT1<6:7>) and the middle three bits (e.g., CNT1<3:5>) are both logic low bits (NO in step S1040), the group decoder 410 can define the first counter C1 and the first latch LAT1 corresponding to the first counter C1 as the third group by setting the most significant bit CNT_GRP1<3> of the first group signal CNT_GRP1<1:3> to a logic high level in step S1070. The group decoder 410 can repeat the above operations of steps S1010 to S1070 for the second to sixteenth count signals CNT2<0:7> to CNT16<0:7> in steps S1080 and S1090 to divide the counters C1 to C16 and the latches LAT1 to LAT16 into the first to third groups.

[0087] Referring back to Figure 9When any of the least significant bits CNT_GRP1<1> to CNT_GRP16<1> is a logic high bit, the group decoder 410 can activate the first group enable signal GRP_EN1 to a logic high level. On the other hand, when any of the middle bits CNT_GRP1<2> to CNT_GRP16<2> is a logic high bit in a state in which the first group enable signal GRP_EN1 is at a logic low level (i.e., when all of the least significant bits CNT_GRP1<1> to CNT_GRP16<1> are logic low bits), the group decoder 410 can activate the second group enable signal GRP_EN2 to a logic high level. Also, when both the first group enable signal GRP_EN1 and the second group enable signal GRP_EN2 are deactivated to logic low levels, the third group enable signal GRP_EN3 can be activated to a logic high level.

[0088] When the fourth activation signal ACT3 or the target refresh command TREF is activated, the latch input control circuit 420 can generate first to sixteenth input control signals LAT_IE1 to LAT_IE16 according to the first to sixteenth match signals HIT1 to HIT16 and the first to sixteenth null signals NULL1 to NULL16.

[0089] For example, referring to Figure 11 The latch input control circuit 420 can include a sequence control circuit 422 and a signal output circuit 424.

[0090] The sequence control circuit 422 can control the order of the first to sixteenth null signals NULL1 to NULL16 according to the first to sixteenth match signals HIT1 to HIT16 to generate one of first to sixteenth sequential null signals CNT_NULL1 to CNT_NULL16. For example, when the first to sixteenth match signals HIT1 to HIT16 are all deactivated to logic low levels, the sequence control circuit 422 can activate and output one of the first to sixteenth sequential null signals CNT_NULL1 to CNT_NULL16 corresponding to the first to sixteenth null signals NULL1 to NULL16, respectively, according to a predetermined order (e.g., a sequential order).

[0091] When the fourth activation signal ACT3 or the target refresh command TREF is activated, the signal output circuit 424 can output the first to sixteenth sequential null signals CNT_NULL1 to CNT_NULL16 as the first to sixteenth input control signals LAT_IE1 to LAT_IE16. For example, the signal output circuit 424 can include an OR gate OR1 that generates a latch command signal LAT_CMD by performing an OR operation on the fourth activation signal ACT3D and the target refresh command TREF, and a plurality of AND gates AD1 to AD16 that perform an AND operation on the latch command signal LAT_CMD and the first to sixteenth sequential null signals CNT_NULL1 to CNT_NULL16, respectively.

[0092] Through the above-described structure, when the fourth activation signal ACT3D or the target refresh command TREF is activated, the latch input control circuit 420 can determine that any of the latch addresses LADD1 to LADD16 does not match the activation address ACT_ADD based on the first to sixteenth match signals HIT1 to HIT16, and sequentially output the first to sixteenth input control signals LAT_IE1 to LAT_IE16 corresponding to the first to sixteenth null signals NULL1 to NULL16 according to a predetermined order (e.g., a sequential order).

[0093] Referring back to Figure 9 When the target refresh command TREF is activated, the latch output control circuit 430 can generate the first to sixteenth output control signals LAT_OE1 to LAT_OE16 based on the first to third group enable signals GRP_EN1 to GRP_EN3 and the least significant bits CNT_GRP1<1> to CNT_GRP16<1> and the middle bits CNT_GRP1<2> to CNT_GRP16<2> of the first to sixteenth group signals CNT_GRP1<1:3> to CNT_GRP16<1:3>.

[0094] Specifically, the latch output control circuit 430 can include first to third signal combination units 431 to 433 and first to third latch output control units 434 to 436.

[0095] When the target refresh command TREF and the first group enable signal GRP_EN1 are all activated, the first signal combination unit 431 can activate the first output enable signal OE1. When the target refresh command TREF and the second group enable signal GRP_EN2 are all activated, the second signal combination unit 432 can activate the second output enable signal OE2. When the target refresh command TREF and the third group enable signal GRP_EN3 are all activated, the third combination unit 433 can activate the third output enable signal OE3.

[0096] When the first output enable signal OE1 is activated, the first latch output control unit 434 can output first to sixteenth output control signals LAT_OE1 to LAT_OE16 corresponding to the least significant bits CNT_GRP1<1> to CNT_GRP16<1>, respectively. The first latch output control unit 434 can sequentially select one of the least significant bits CNT_GRP1<1> to CNT_GRP16<1> and output the selected one as a corresponding output control signal each time the first output enable signal OE1 is activated. When the second output enable signal OE2 is activated, the second latch output control unit 435 can output first to sixteenth output control signals LAT_OE1 to LAT_OE16 corresponding to the middle bits CNT_GRP1<2> to CNT_GRP16<2>, respectively. The second latch output control unit 435 can sequentially select one of the middle bits CNT_GRP1<2> to CNT_GRP16<2> and output the selected one as a corresponding output control signal each time the second output enable signal OE2 is activated. When the third output enable signal OE3 is activated, the third latch output control unit 436 can output the first output control signal LAT_OE1. According to an embodiment of the present application, the third latch output control unit 436 can sequentially activate one of the first to sixteenth output control signals LAT_OE1 to LAT_OE16 each time the third output enable signal OE3 is activated.

[0097] With the above-described structure, the latch output control circuit 430 can generate the first to sixteenth output control signals LAT_OE1 to LAT_OE16 so that one of the latch addresses of the latches belonging to the group of the counters each having a large count value (either the first group or the second group) is output as the target address TADD. Here, in this example, when there is no latch belonging to the group of the counters each having a large count value (either the first group or the second group), the latch output control circuit 430 can generate the first output control signal LAT_OE1 so that the latch address LADD1 of the first latch LAT1 is output as the target address TADD.

[0098] When the target refresh command TREF is activated, the reset control circuit 440 can generate a reset signal corresponding to the activated output control signal among the first to sixteenth reset signals RST1 to RST16. Also, after the target refresh command TREF is activated, the reset control circuit 440 can generate the first to sixteenth reset signals RST1 to RST16 corresponding to the most significant bits CNT_GRP1<3> to CNT_GRP16<3> of the first to sixteenth group signals CNT_GRP1<1:3> to CNT_GRP16<1:3>, respectively. In other words, the reset control circuit 440 can generate a reset signal for initializing only the counters included in the third group at each target refresh period.

[0099] Hereinafter, the operation of a memory device according to one embodiment of the present application will be described with reference to the accompanying drawings. Figures 2 to 13 Hereinafter, the operation of a memory device according to one embodiment of the present application will be described with reference to the accompanying drawings.

[0100] Figure 12 is a flowchart illustrating the operation of a semiconductor memory device according to one embodiment of the present application when an activation command ACT is input.

[0101] Referring to Figure 12 When the activation command ACT is input in step S1210, in step S1220, the control signal generating circuit 124 can generate the first to fourth activation signals ACT0 to ACT3 which are sequentially activated, and the address latch 125 can latch the internal address IADD as the activation address ACT_ADD.

[0102] In step S1230, according to the first to fourth activation signals ACT0 to ACT3, the latches LAT1 to LAT16 can provide the latched addresses LADD1 to LADD16 to the comparison circuit 134, and the comparison circuit 134 can generate a plurality of match signals HIT1 to HIT16 by comparing the latched addresses LADD1 to LADD16 with the activation address ACT_ADD. Here, when any one of the match signals HITi is activated (YES in step S1240), in step S1250, the corresponding counter Ci can increase the corresponding count value.

[0103] In one embodiment, when the activation command ACT is input, the input control circuit 131 can provide the activation address ACT_ADD as an input address ADD_IN to the latch circuit 132.

[0104] When all of the match signals HIT1 to HIT16 are deactivated (NO in step S1240), when any one of the null signals NULL1 to NULL16 is activated (YES in step S1260), the latch input control circuit 420 of the refresh controller 138 can generate the input control signals LAT_IE1 to LAT_IE16 corresponding to the null signals NULL1 to NULL16. In this case, the activated signal NULLk among the null signals NULL1 to NULL16 can be provided as the input control signal LAT_IEk in accordance with a predetermined order (e.g., a sequential order). In step S1270, the corresponding latch LATk among the latches LAT1 to LAT16 can store the input address ADD_IN in accordance with the input control signal LAT_IEk.

[0105] In one embodiment, when all of the match signals HIT1 to HIT16 are deactivated (NO in step S1240), when all of the null signals NULL1 to NULL16 are deactivated (NO in step S1260), in step S1290, the input control circuit 131 can determine that all of the latches LAT1 to LAT16 are in the full state and store the activated address ACT_ADD as the shadow address SDW_ADD.

[0106] As described above, when the input activated command ACT is input, it can be determined whether there is a latched address identical to the activated address ACT_ADD, and in accordance with the determination result, the count value indicating the number of times of repeated input of the activated address ACT_ADD can be increased or the activated address ACT_ADD can be stored in the null latch. In one embodiment, the activated address ACT_ADD not stored in the latches during one target refresh period can be stored as another shadow address SDW_ADD.

[0107] Figure 13 is a flowchart illustrating an operation of a semiconductor memory device according to one embodiment of the present application when a target refresh command TREF is input.

[0108] Referring to Figure 13 When the target refresh command TREF is input in step S1310, in step S1320, the latch output control circuit 430 of the refresh controller 138 can generate the output control signals LAT_OE1 to LAT_OE16 so that one of the latched addresses of the latches belonging to the group having a large count value (the first or second group) is output as the target address TADD.

[0109] Specifically, when the first group enable signal GRP_EN1 is activated (YES in step S1321), in step S1322, the first latch output control unit 434 can activate the output control signal LAT_OEx based on one of the activated bit positions of the least significant bit positions CNT_GRPl<1> to CNT_GRP16<1> corresponding to the first group. In step S1323, the latch LATx that receives the output control signal LAT_OEx can output the stored latch address LADDx as the target address TADD. In step S1324, the reset control circuit 440 can generate the reset signal RSTx corresponding to the activated output control signal LAT_OEx, and thus can initialize only the corresponding counter Cx among the counters C1 to C16.

[0110] When the first group enable signal GRP_EN1 is deactivated (NO in step S1321) and the second group enable signal GRP_EN2 is activated (YES in step S1325), in step S1326, the second latch output control unit 435 can activate the output control signal LAT_OEy according to one of the activated bit positions of the middle bit positions CNT_GRPl<2> to CNT_GRP16<2> corresponding to the second group. In step S1327, the latch LATy that receives the output control signal LAT_OEy can output the stored latch address LADDy as the target address TADD. In step S1328, the reset control circuit 440 can generate the reset signal RSTy corresponding to the activated output control signal LAT_OEy, and thus can initialize only the corresponding counter Cy among the counters C1 to C16.

[0111] When the first group enable signal GRP_EN1 is deactivated (NO in step S1321) and the second group enable signal GRP_EN2 is also deactivated (NO in step S1325), the third group enable signal GRP_EN3 can be activated. In step S1329, the third latch output control unit 436 can activate the first output control signal LAT_OE1. In step S1330, the first latch LAT1 can output the stored latch address LADD1 as the target address TADD. In step S1331, the reset control circuit 440 can generate the first reset signal RST1 corresponding to the first output control signal LAT_OE1, and thus can initialize only the first counter C1.

[0112] In step S1340, the reset control circuit 440 can generate first to sixteenth reset signals RST1 to RST16 corresponding to the activated bits of the most significant bits CNT_GRP1<3> to CNT_GRP16<3>. Accordingly, in step S1350, the counters C1 to C16 can be initialized. In other words, the counters included in the third group can be initialized only at each target refresh period.

[0113] The input control circuit 131 can provide the shadow address SDW_ADD as the input address ADD_IN. In step S1360, the latch input control circuit 420 can activate one of the activated signals of the null signals NULL1 to NULL16 according to the predetermined order as the input control signal, and the corresponding one of the latches LAT1 to LAT16 can store the input address ADD_IN according to the input control signal.

[0114] According to the embodiment of the present application, when a target address is selected from the addresses stored in the plurality of latches by sampling the activated address, the semiconductor memory device can divide the counters and the latches corresponding thereto into at least two groups based on the count values obtained by counting the number of times the activated address is repeatedly input, select the target address from the latches belonging to the group of the counters each having a large count value, and initialize only the counters belonging to the group of the counters each having a small count value. In this way, the semiconductor memory device can prevent unnecessary address comparison operations, which improves the refresh efficiency of the semiconductor memory device.

[0115] Further, according to one embodiment of the present application, the semiconductor memory device can maximize the accuracy of address sampling by sampling the activated address not stored in the latches during one target refresh period using an additional shadow latch.

[0116] Further, according to one embodiment of the present application, since the address comparison operations are sequentially performed using a plurality of activated signals generated by shifting one activated command, the area occupied by the address comparison circuit in the semiconductor memory device can be reduced.

[0117] Although the present application has been described with respect to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the application as defined in the following claims.

[0118] For example, the positions and types of the logic gates and transistors exemplified in the above-described embodiments should be differently implemented according to the polarity of the input signal.

Claims

1. A semiconductor memory device, comprising: an input control circuit adapted to provide an activation address inputted with an activation command as an input address; a plurality of latches adapted to sequentially store the input address as a latched address according to an input control signal, and output the latched address as a target address according to an output control signal; a plurality of counters corresponding to the plurality of latches, respectively, each counter adapted to increase a count value corresponding to a corresponding latch when the activation address matches the latched address stored in the corresponding latch; and a refresh controller adapted to divide the counters and the latches into a plurality of groups based on the count values, and generate a reset signal for initializing counters included in one of the plurality of groups in response to a refresh command.

2. The semiconductor memory device of claim 1, wherein the refresh controller divides the counters and the latches into the groups by: classifying counters and corresponding latches each having a count value equal to or greater than a threshold value as a first group, classifying counters and corresponding latches each having a count value less than the threshold value as a second group, and wherein the refresh controller generates the reset signal for initializing counters included in the second group.

3. The semiconductor memory device of claim 1, wherein the refresh controller is further adapted to generate the output control signal to output the latched address as the target address from a selected one of latches included in remaining groups of the plurality of groups other than the one group in response to the refresh command, and wherein the refresh controller generates the reset signal for initializing a counter corresponding to the selected latch.

4. The semiconductor memory device of claim 3, wherein the refresh controller is further adapted to generate the output control signal to output a latched address stored in a preset latch as the target address in response to the refresh command when there is no latch included in the remaining groups of the plurality of groups, and wherein the refresh controller generates the reset signal for initializing a counter corresponding to the preset latch.

5. The semiconductor memory device according to claim 1, wherein, the refresh controller is further adapted to generate the input control signal so that the input address is stored in a latch corresponding to a counter having a zero count value when the activation address does not match any of the latched addresses stored in the corresponding latches.

6. The semiconductor memory device according to claim 1, wherein, the input control circuit is further adapted to randomly sample the activation address as a shadow address when the activation address does not match any of the latched addresses and the latches are each in a full state, and provide the shadow address as the input address in response to the refresh command.

7. The semiconductor memory device of claim 1, further comprising a control signal generation circuit adapted to generate first to fourth activation signals sequentially activated in response to the activation command.

8. The semiconductor memory device of claim 7, further comprising a plurality of address comparators adapted to generate a plurality of match signals by comparing the active address with the latched addresses.

9. The semiconductor memory device according to claim 8, wherein, Each latch is further adapted to: receive one of the first to fourth activation signals, and provide the latched address stored in the latch to a corresponding one of the address comparators when the received activation signal is activated.

10. The semiconductor memory device of claim 8, wherein, Each counter is further adapted to receive one of the first to fourth activation signals, wherein each counter is incremented according to a match signal corresponding thereto when the received activation signal is activated, and wherein each counter is initialized according to a reset signal corresponding thereto.

11. The semiconductor memory device according to claim 1, wherein, The input control circuit comprises: an enable signal generation unit adapted to generate a latch enable signal according to the activation command and an oscillation signal when none of the latched addresses matches the active address and all of the latches are in a full state; a shadow latch unit adapted to store the active address as a shadow address according to the latch enable signal; a selection signal generation unit adapted to generate a selection signal activated according to the refresh command and deactivated according to the activation command; and an address output unit adapted to select one of the active address and the shadow address according to the selection signal and output the selected address as the input address.

12. The semiconductor memory device according to claim 1, wherein, The refresh controller comprises: a bank decoder adapted to generate a plurality of bank signals and first to third bank enable signals based on the count values, each bank signal formed by first to third bits respectively representing first to third banks; a latch input control circuit adapted to generate the input control signals based on a plurality of match signals and a plurality of empty signals in response to the activation command or the refresh command, the match signals respectively indicating whether the active address matches the latched addresses stored in the latches, and the empty signals respectively indicating states of the counters; a latch output control circuit adapted to generate output control signals corresponding to first and second bits of the bank signals based on the refresh command and the first to third bank enable signals; and a reset control circuit adapted to generate a reset signal corresponding to a third bit of the bank signals according to the refresh command.

13. The semiconductor memory device of claim 12, wherein The bank decoder generates the bank signals respectively corresponding to the count values, wherein the bank decoder is further adapted to: set the first bit of the bank signal corresponding to the selected count value to a logic high level when the selected count value is equal to or greater than a first threshold value, set the second bit of the bank signal corresponding to the selected count value to a logic high level when the selected count value is equal to or greater than a second threshold value and less than the first threshold value, and set the third bit of the bank signal corresponding to the selected count value to a logic high level when the selected count value is less than the second threshold value. setting a third bit of a group signal corresponding to the selected count value to a logic high level when the selected count value is less than the second threshold value, and wherein the group decoder is further adapted to: activate the first group enable signal when any of the first bits is a logic high bit, activate a second group enable signal when all of the first bits are logic low bits and any of the second bits is a logic high bit, and activate the third group enable signal when both the first group enable signal and the second group enable signal are deactivated.

14. The semiconductor memory device according to claim 12, wherein, the latch input control circuit includes: a sequential control circuit adapted to generate a plurality of sequential empty signals corresponding to the empty signals, respectively, according to a predetermined order when all of the match signals are deactivated, and a signal output circuit adapted to output the sequential empty signals as the input control signals when the activation command or the refresh command is input.

15. The semiconductor memory device of claim 12, wherein, the latch output control circuit includes: a first latch output control unit adapted to generate an output control signal corresponding to the first bits of the group signals according to the refresh command and the first group enable signal; a second latch output control unit adapted to generate an output control signal corresponding to the second bits of the group signals according to the refresh command and the second group enable signal; and a third latch output control unit adapted to generate a first output control signal of the output control signals according to the refresh command and the third group enable signal.

16. A semiconductor memory device, comprising: a plurality of latches adapted to store an input address as a latched address according to an input control signal, and output the latched address as a target address according to an output control signal; a plurality of address comparators adapted to compare an activation address with the latched address to generate a plurality of match signals; a plurality of counters adapted to generate a plurality of count signals, respectively, according to the match signals, and to be initialized, respectively, according to a plurality of reset signals; a group decoder adapted to generate a plurality of group signals and a first group enable signal to a third group enable signal based on the count signals, each of the group signals being formed of first bits to third bits respectively representing a first group to a third group; a latch input control circuit adapted to generate the input control signals according to the match signals and empty signals respectively indicating states of the counters; a latch output control circuit adapted to generate the output control signals corresponding to the first bits and the second bits of the group signals according to a refresh command and the first group enable signal to the third group enable signal; and a reset control circuit adapted to generate a reset signal corresponding to the third bits of the group signals according to the refresh command.

17. The semiconductor memory device of claim 16, further comprising an input control circuit adapted to: provide the activation address as an input address, and randomly sample the activation address as a shadow address according to the match signals and the empty signals when an activation command is input, and provide the shadow address as the input address when the refresh command is input. ​ 18. The semiconductor memory device of claim 17, wherein, The input control circuit includes: an enable signal generation unit adapted to generate a latch enable signal according to an activation command and an oscillation signal when both the match signal and the empty signal are deactivated; a shadow latch unit adapted to store the activation address as a shadow address according to the latch enable signal; a selection signal generation unit adapted to generate a selection signal activated according to the refresh command and deactivated according to the activation command; and an address output unit adapted to select one of the activation address and the shadow address according to the selection signal and output the selected address as the input address.

19. The semiconductor memory device of claim 17, wherein, the bank decoder generates the bank signals respectively corresponding to the count signals, wherein the bank decoder is further adapted to: set a first bit of the bank signal corresponding to the selected count value to a logic high level when the selected count value is equal to or greater than a first threshold value, set a second bit of the bank signal corresponding to the selected count value to a logic high level when the selected count value is equal to or greater than a second threshold value and less than the first threshold value, and set a third bit of the bank signal corresponding to the selected count value to a logic high level when the selected count value is less than the second threshold value, and wherein the bank decoder is further adapted to: activate the first bank enable signal when any of the first bits is a logic high bit, activate a second bank enable signal when all of the first bits are logic low bits and any of the second bits is a logic high bit, and activate the third bank enable signal when both the first bank enable signal and the second bank enable signal are deactivated.

20. The semiconductor memory device of claim 16, wherein, The latch input control circuit includes: a sequential control circuit adapted to generate a plurality of sequential empty signals respectively corresponding to the empty signals according to a predetermined sequence when all of the match signals are deactivated; and a signal output circuit adapted to output the sequential empty signals as the input control signals when an activation command or the refresh command is input.

21. The semiconductor memory device of claim 16, wherein, The latch output control circuit includes: a first latch output control unit adapted to generate the output control signals corresponding to the first bits of the bank signals according to the refresh command and the first bank enable signal; a second latch output control unit adapted to generate the output control signals corresponding to the second bits of the bank signals according to the refresh command and a second bank enable signal; and a third latch output control unit adapted to generate a first output control signal of the output control signals according to the refresh command and the first bank enable signal.

22. A method for operating a semiconductor memory device, comprising: generating respective count signals by a plurality of counters counting respective match signals generated via a comparison between an activation address and a latched address stored in a respective latch when an activation command is input; dividing the counters and the latches into a first group and a second group based on the count signals; and When a refresh command is input, one of the latched addresses included in the first group is output as a target address and a counter included in the second group is initialized.

23. The method of claim 22, wherein, The dividing includes: classifying counters and corresponding latches each having a count value equal to or greater than a threshold value as a first group, and classifying counters and corresponding latches each having a count value less than the threshold value as a second group.

24. The method of claim 22, further comprising: When there is no latched address included in the first group, a latched address stored in a preset latched address is output as the target address.

25. The method of claim 22, further comprising: when the activation command is input, storing the activation address in one of the latches or randomly sampling the activation address as a shadow address; and when the refresh command is input, storing the shadow address in one of the latches, wherein, when all of the match signals are deactivated and all of the latches are in a full state, the activation address is randomly sampled.

26. A semiconductor memory device, comprising: a row control circuit that performs a target refresh operation on an array of memory cells according to a target refresh command and a target address; and a refresh control circuit that: when an activation address is different from any latched address, latches the activation address; when the activation address is the same as any one of the latched addresses, increases a count corresponding to the any one address; in response to the target refresh command, provides any one of one or more latched addresses each corresponding to a count greater than a threshold value to the row control circuit as the target address and initializes a count corresponding to the provided address; when there is no latched address corresponding to a count greater than the threshold value among the latched addresses, provides any one of one or more latched addresses each corresponding to a count less than the threshold value to the row control circuit as the target address in response to the target refresh command; and initializes a count less than the threshold value.

27. The semiconductor memory device of claim 26, wherein, when the refresh control circuit is full of the latched addresses, the refresh control circuit latches the activation address as a shadow address, and wherein the refresh control circuit further latches the shadow address after the providing.

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