Integrated chip and method of operating a phase change memory

Abstract

An integrated chip has an array of memory cells and a driver circuit arranged over a semiconductor substrate. The driver circuit provides a read voltage to the array that varies with respect to an approximate temperature of the memory array to improve temperature dependence in a read current. The driver circuit can vary the read voltage in an inverse manner with temperature. The read voltage can vary continuously or in steps, and the driver circuit can use a table lookup. Optionally, the driver circuit measures the current and modulates the read voltage until the current is within a target range. The memory cells can be multi-level phase change memory cells that include a plurality of phase change elements disposed between a bottom electrode and a top electrode. Modulating the read voltage to reduce current variation with temperature is particularly useful for multi-level cells.

Description

TECHNICAL FIELD

[0001] Embodiments of the invention relate to integrated chips and methods of operating phase change memory. BACKGROUND

[0002] Many electronic devices contain electronic memory configured to store data. Electronic memory can be volatile or non-volatile. Volatile electronic memory uses a power source to maintain data, while non-volatile memory is able to store data without a power source. Flash memory is a widely used non-volatile memory. However, flash memory is believed to have scaling limitations. For this reason, there has long been a need for alternative types of non-volatile memory. Phase change memory (PCM) is among these alternatives. Phase change memory is a type of non-volatile memory in which the phase of a phase change element is used to represent a data unit. Phase change memory has fast read and write times, non-destructive read, and high scalability. Phase change memory also has the potential to store multiple bits per cell. SUMMARY

[0003] According to one aspect of embodiments of the invention, there is provided an integrated chip, comprising: a semiconductor substrate; an array of resistive random access memory cells formed over the semiconductor substrate; and a driver circuit configured to provide a read voltage to selected cells in the array that is selective of a temperature of the array.

[0004] According to another aspect of embodiments of the invention, there is provided an integrated chip, comprising: a semiconductor substrate; an array of phase change memory cells formed over the semiconductor substrate; a temperature sensor positioned to measure an approximate temperature of the array of phase change memory cells; and a driver circuit formed on the semiconductor substrate and operative to select a read voltage for the phase change memory cells as a function of the approximate temperature.

[0005] According to yet another aspect of embodiments of the invention, there is provided a method of operating a phase change memory, comprising: generating a first read voltage when a phase change memory array is at a first temperature; driving a cell in the phase change memory array with the first read voltage; generating a temperature-compensated read voltage when the phase change memory array is at a second temperature; generating a read current by driving a second cell in the phase change memory array with the temperature-compensated read voltage; and determining a programmed state of the second cell by comparing the read current to one or more thresholds; wherein the temperature-compensated read voltage is increased when a difference between the second temperature and the first temperature causes the resistance of the second cell to be higher, and the temperature-compensated read voltage is decreased when the difference between the second temperature and the first temperature causes the resistance of the second cell to be lower. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present application can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be emphasized that various components are not necessarily drawn to scale and have been rendered in simplified form to facilitate discussion.

[0007] Figure 1 is a block diagram of a phase change memory circuit providing temperature dependent read voltages according to some embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of some components of a phase change memory circuit providing Figure 1 more details according to some embodiments.

[0009] Figure 3A is a graph showing the variation of read current with temperature for four different programmed states when the read voltage is not modulated.

[0010] Figure 3B is a graph showing how the read current varies with temperature for a phase change memory circuit according to some embodiments of the present disclosure as the read voltage is reduced by modulating it. Figure 3A

[0011] Figure 3C is a graph showing how varying the reference current can more effectively distinguish between programmed states reflected by the read voltage of a phase change memory circuit according to some embodiments of the present disclosure. Figure 2

[0012] Figure 4 shows a cross-sectional view of an integrated circuit having a phase change memory cell and to which the present disclosure can be applied according to some embodiments.

[0013] Figure 5 shows a cross-sectional view of an integrated circuit having a multi-level phase change memory cell and to which the present disclosure can be applied according to some embodiments.

[0014] Figure 6 is a flowchart showing a method according to some embodiments of the present disclosure.

[0015] Figure 7 is a flowchart showing a method according to some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] ​​The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Specific embodiments or examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the disclosure can refer to a number of examples using reference numerals and / or letters. This repetition is for simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.

[0017] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] A phase change memory (PCM) cell includes at least one phase change element between a bottom electrode and a top electrode. The phase change element has a crystalline state and an amorphous state with different resistivities. These different resistive states can be used to represent data. For example, the amorphous state in a high resistive state can correspond to a logic "0". The crystalline state in a low resistive state can correspond to a logic "1". These different resistive states can be referred to as the programmed states of the cell. Partially crystalline states with intermediate resistive levels can also be formed. If the resistance can be consistently achieved to fall within the different ranges for the four states, the phase change memory cell can be used to represent two data bits, for example, logic "00", logic "01", logic "10", and logic "11". A cell that can store two or more data bits is referred to as a multi-level cell.

[0019] The programmed state of a memory cell (and thus the data stored in the cell) can be read by applying a predetermined voltage to the cell and comparing the resulting current (read current) to one or more reference currents. In addition to the programmed state, the resistance of the cell is temperature dependent. The temperature dependence can affect the accuracy of reading the programmed state of the cell. The temperature dependence of the current can be addressed by adjusting the reference currents based on temperature. However, the present disclosure teaches reducing the temperature variation in the read current by adjusting the predetermined voltage used for the read operation. This approach can be implemented with relatively simple circuitry and reduces error rates. These advantages are particularly evident for multi-layer phase change memory cells. Although the present disclosure focuses primarily on modulating the read voltage when reading the state of a phase change memory cell, the structures and methods of the present disclosure can be applied to reading other types of memory cells. In some embodiments, in addition to modulating the read voltage based on temperature, one or more threshold currents compared to the read current are also adjusted based on temperature. The combination of these two types of temperature compensation can improve the accuracy of distinguishing between different programmed states.

[0020] Typically, memory cells are arranged in rows and columns within a memory array. Read or write operations are performed on memory cells within the memory array by activating word lines and bit lines to provide a voltage to selected phase change memory cells. Each memory cell in the array can be associated with an access selector device that substantially prevents leakage current from flowing through unselected memory cells.

[0021] An integrated chip according to the present disclosure has an array of memory cells arranged over a semiconductor substrate. In some embodiments, the memory cells are phase change memory cells. A phase change memory cell typically includes a heating element and a phase change element disposed between a bottom electrode and a top electrode. According to the present teachings, a driver circuit for the array of memory cells is configured to provide a temperature-compensated read voltage that is a drive voltage that varies with respect to temperature in a manner that reduces temperature-driven variations in the read current.

[0022] The temperature dependence of the resistance of a cell can vary depending on the programmed state of the cell. In some embodiments, the read voltage is temperature compensated according to the temperature dependence of the resistance of the cell in one particular programmed state. In some embodiments, the read voltage is temperature compensated with respect to the temperature dependence of the resistance of the cell when the cell is in its highest resistance programmed state. In some embodiments, the read voltage is temperature compensated with respect to the temperature dependence of the cell resistance when the cell is in its lowest resistance programmed state. In some embodiments, one or more threshold currents are compared to the read current to distinguish between programmed states that also vary with respect to temperature. Although the latter approach can increase complexity, it can reduce error rates, particularly for multi-layer cells.

[0023] In some of these teachings, the driver circuit continuously varies the read voltage in an inverse relationship to temperature. In some of these teachings, the driver circuit gradually varies the read voltage with respect to an increase or decrease in temperature. In some of these teachings, the driver circuit implements a table lookup that selects a read voltage according to a range in which the temperature falls. In some of these teachings, the driver circuit adjusts the read voltage to modulate a current through a reference phase change memory cell in a known programmed state.

[0024] In some of these teachings, the variation in read voltage is determined based on a measurement of a resistance change of the cell with temperature, where the resistance change of the cell with temperature is obtained for a particular wafer from which the integrated chip is diced. In some of these teachings, the variation in read voltage is determined based on a measurement of a resistance change of the cell with temperature, where the resistance change of the cell with temperature is obtained using a particular integrated chip containing the phase change memory array. These approaches can allow the read voltage to compensate for some variations in manufacturing processes.

[0025] Some aspects of the present teachings relate to methods of selecting a drive voltage to read a programmed state of a cell in a phase change memory array. According to the method, the drive voltage is modulated with respect to temperature to reduce temperature-related variations in a read current, which is a current through a cell of the phase change memory during a read operation in which the cell is in some particular programmed state. In some embodiments, the drive voltage is adjusted in a manner that results in an increase in the drive voltage if the temperature of the phase change memory array decreases, and results in a decrease in the drive voltage if the temperature of the phase change memory array increases. In some embodiments, the method includes measuring the temperature of the phase change memory array and adjusting the drive voltage based on the measurement. In some embodiments, the method includes detecting temperature-related variations in a current through a device, and adjusting the drive voltage to reduce those variations. In some embodiments, the device is a PCM memory cell that is used as a reference cell.

[0026] Figure 1 A block diagram showing portions of an integrated chip 100 according to some embodiments of the present disclosure is shown. The integrated chip 100 includes a memory array 101 having a plurality of memory cells 103 a，1 -103 d，4 The memory cells 103 a，1 -103 d，4 are arranged within the memory array 101 in rows and / or columns. For example, a first row includes memory cells 103 a，1 -103 d，1 and a first column includes memory cells 103 a，1 -103 a，4Although memory array 101 is shown as having 4 rows and 4 columns, memory array 101 can have any number of rows and any number of columns. Each memory cell 103 a，1 -103 d，4 may include a phase change memory element 105 coupled to an access selection device 107. Access selection device 107 is configured to selectively provide access to phase change memory element 105 while suppressing leakage current through unselected memory cells 103 a，1 -103 d，4 .

[0027] Memory cells 103 a，1 -103 d，4 may be controlled by bit lines BL1-BL4, word lines WL1-WL4, and source lines SL1-SL4. Word lines WL1-WL4 can be used to operate access selection devices 107 corresponding to memory cells 103 a，1 -103 d，4 . When access selection devices 107 for memory cells 103 a，1 -103 d，4 are turned on, a voltage can be applied to the cell. It should be understood that the effective voltage is the absolute value of the potential difference across phase change memory element 105. For integrated chip 100, applying a voltage to a selected memory cell 103a,1-103d,4 means operating word lines WL1-WL4 to turn on access selection devices 107 corresponding to that memory cell, and using driver circuit 121 to make the absolute value of the potential difference between source lines SL1-SL4 and bit lines BL1-BL4 corresponding to that cell equal to that voltage. In some embodiments, applying the voltage to a memory cell 103 a，1 -103 d，4 is accomplished by coupling the corresponding bit line BL1-BL4 to the voltage while holding the corresponding source line SL1-SL4 at ground potential. Of course, the source lines SL1-SL4 can be held at other potentials, and the roles of bit lines BL1-BL4 and source lines SL1-SL4 can be reversed.

[0028] Driver circuit 121 can be a read / write driver configured to select a voltage to be applied to a selected memory cell 103 a，1 -103 d，4voltage to perform read, write, and write verify operations. Driver circuit 121 receives input from temperature sensing circuit 123 and uses this data to select a read voltage for a read operation. Bit line decoder 119 applies the read voltage to one of bit lines BL1-BL4 under direction from control circuit 125. Word line decoder also applies another voltage to one of word lines WL1-WL4 under direction from control circuit 125, which turns on the memory cells 103 a，1 -103 d，4 of the access selector device 107. These operations together cause the read voltage to be applied to a selected one of memory cells 103 a，1 -103 d，4 .

[0029] Applying a voltage to the selected memory cell 103 a，1 -103 d，4 results in a current. During a read operation, sense amplifier 117 determines the program state of the selected memory cell 103 a，1 -103 d，4 based on the current. Sense amplifier 117 can be connected to source lines SL1-SL4. Alternatively, sense amplifier 117 can be connected to bit lines BL1-BL4. Sense amplifier 117 can determine the program state of memory cell 103 a，1 -103 d，4 based on the current. In some embodiments, sense amplifier 117 determines the program state of memory cell 103 a，1 -103 d，4 by comparing the current to one or more reference currents. In some embodiments, the one or more reference currents are also adjusted based on temperature. Sense amplifier 117 can communicate the program state determination to I / O buffer 115, which can also be coupled to driver circuit 121 to enable write and write verify operations.

[0030] Figure 2 is a block diagram showing some details of some portions of example integrated chip 100, in particular some details of some components in sense amplifier 117 and driver circuit 121. These circuits can have other components not shown. For example, driver circuit 121 includes components not shown that provide write voltages.

[0031] As shown in this example, the driver circuit 121 can include a read voltage selection circuit 227 that can use input from the temperature sensing circuit 123 to pre-determine a read voltage. The temperature sensing circuit 123 can be activated by the driver circuit 121 to query the temperature. Alternatively, the temperature sensing circuit 123 can operate asynchronously and can store temperature data that can be accessed by the read voltage selection circuit 227. In the case that the temperature sensing circuit 123 operates asynchronously, it can periodically update the stored temperature. The period of the update can be in the order of tenths of a second, tenths of a second, seconds, minutes, or any other suitable time. In some embodiments, the temperature sensing circuit 123 includes an on-chip temperature sensor. Alternatively, the temperature sensing circuit 123 is from an off-chip temperature sensor. The integrated chip 100 can have one temperature sensor, or can also have more temperature sensors to provide more local measurements.

[0032] The read voltage selection circuit 227 can use any suitable structure or algorithm to select a temperature-compensated read voltage. After the temperature-compensated read voltage is selected, it can be generated by a read voltage generation circuit 229. The read voltage generation circuit can have components to generate the temperature-compensated read voltage according to the signal received from the read voltage selection circuit 227. The resulting read voltage can then be used to drive any of the memory cells 103 selected by the bit line decoder 119 and the word line decoder 127 to provide a read voltage that is processed by the sense amplifier 117. a，1 -103 d，4

[0033] The example sense amplifier 117 is configured to distinguish between four program states. To distinguish between the four program states, the sense amplifier 117 uses a current mirror circuit 201 to copy the read current to three different current comparators 213A-213C. Each current comparator 213A-213C receives a different reference current from a corresponding reference current generator 203A-203C and generates a binary output that reflects whether the corresponding reference current is higher or lower than the read current. These binary outputs can be processed by a combinational logic circuit 219 to determine the values of two different bits, Bit 0 and Bit 1, which can then be stored in the I / O buffer 115.

[0034] ​In some embodiments, each reference current generator 203A-203C generates a reference current that is independent of temperature. Thus, reference current generators 203A-203C can each be structured to provide a fixed current, although the magnitude of that current will differ among reference current generators 203A-203C. In some other embodiments, one or more of reference current generators 203A-203C generates a reference current that is dependent on temperature. In this example, reference current generator 203B is operable to generate a reference current that varies according to a signal received from reference current selector 211. Reference current selector 211 can include circuitry that selects a reference current according to an input from temperature sensing circuit 123. The reference current can be selected to improve the reliability of distinguishing between two programmed states.

[0035] Figure 3A A plot is shown of the variation in temperature of the read current that will be received by sense amplifier 117 if a fixed read voltage is applied to one of memory cells 103 a，1 -103 d，4 A plot is shown of the variation in temperature of the read current that will be received by sense amplifier 117 if a fixed read voltage is applied to one of memory cells 103

[0036] According to the present teachings, driver circuit 121 provides a read voltage that improves temperature compensation of the current variation with temperature. Figure 3B An example is provided in which the read voltage is modulated taking into account the temperature dependence of the resistance of the highest resistance programmed state. The result of this modulation is that the current 301B of the lowest resistance programmed state remains constant over the entire temperature range. For the other three programs shown by plots 303B, 305B, and 307B, the modulation also substantially reduces the variation of the read current with temperature. The modulation is sufficient to distinguish the four programmed states using three fixed reference currents: reference current 311, reference current 313, and reference current 315 over the entire temperature range.

[0037] In some embodiments, the read voltage is modulated such that for every 1 °C increase in temperature, the read voltage decreases by 0.1 mV or more. In some embodiments, the read voltage is modulated such that for every 1 °C increase in temperature, the read voltage decreases by 0.5 mV or more. In some embodiments, the read voltage is modulated such that for every 1 °C increase in temperature, the read voltage will decrease by about 1 mV. These trends can be reversed for decreases in temperature.

[0038] In some embodiments, the read voltage varies linearly with temperature. In some embodiments, the voltage varies continuously, whereby the read voltage V approximately follows the formula:

[0039] V = V0+ x(T - T0)

[0040] where V0is a reference voltage, T0is a reference temperature, T is the current temperature, and x is the amount of voltage decrease per unit change in temperature.

[0041] In some embodiments, the read voltage is decreased or increased in fixed increments. For example, for every 6 °C increase in temperature, the voltage can be decreased by 0.6 mV. Effectively, the temperature range is divided into 6 °C intervals, and a different voltage is applied for each interval. In some embodiments, the temperature interval size is between 0.1 °C and 20 °C. In some embodiments, the temperature interval size is between 0.5 °C and 10 °C. In some embodiments, the temperature interval size is between 2 °C and 10 °C. In some embodiments, the increment of temperature increase or decrease is between 0.01 mV and 10 mV. In some embodiments, the increment of temperature increase or decrease is between 0.1 mV and 2 mV. The stepwise approach can simplify the circuitry of the driver circuit 121.

[0042] In some embodiments, the read voltage is decreased or increased according to a table lookup. For example, a different voltage can be assigned for each 6 °C temperature interval. If the interval sizes are all equal, and the voltage varies in unit increments between intervals, this is effectively a stepwise approach. However, the table lookup allows the interval sizes to be varied. The table lookup also allows for non-linear variation of the voltage with temperature. In some embodiments, the table has 2 rows to 1000 rows. In some embodiments, the table has 5 rows to 200 rows. In some embodiments, the table has 10 rows to 100 rows. Using a table lookup or varying in unit increments, the read voltage is selected from among a plurality of discrete values.

[0043] Although the read currents of plots 301B, 303B, 305B, and 307B are shown as single-valued functions, these currents are actually averages. Due to manufacturing and programming variations, the actual read currents can show some degree of scatter around these averages. This scatter can cause errors, particularly when the threshold current is close to the read current. For example, the read current of plot 305B reaches a minimum distance 331B to the threshold current 313 at the low end of the temperature range, and the read current of plot 303B reaches a minimum distance 333B to the threshold current 313 at the high end of the temperature range. As shown, by replacing the threshold current 317 with a first value having the lower end of the temperature range and a second value having the upper end of the temperature range, the minimum distance 331B can be increased significantly to a minimum distance 331C, and the minimum distance 333B can be increased to a minimum distance 333C. Figure 3C

[0044] The driver circuit 121 can be a read driver and a write driver. The driver circuit 121 can support read operations, write operations, and write verify operations. The write verify operations can be substantially the same as the read operations, except that the write verify operations are applied automatically after a write operation to verify whether the operation was successful. A write operation is an operation that sets the program state of one of the memory cells 103 a，1 -103 d，4 For each program state, there is a different temperature program (temperature profile over time period) used to achieve the state. The temperature can be achieved by applying appropriate voltages to the memory cells 103 a，1 -103 d，4

[0045] Figure 4 A cross-sectional view showing a portion of an integrated chip 400 having a phase change memory array is shown, in accordance with some embodiments of the present disclosure. The integrated chip 400 can be an embodiment of the integrated chip 100. The integrated chip 400 includes a metal interconnect structure 443 over a semiconductor substrate 439. A phase change memory cell 405A is formed within the metal interconnect structure 443. The metal interconnect structure 443 includes a plurality of conductive vias 403 and a plurality of conductive lines 401 disposed within a dielectric structure 441. An access selector device 427 of the phase change memory cell 405A can be formed on the semiconductor substrate 439. The access selector device 427 can correspond to one of the memory cells 103 a，1 -103 d，4

[0046] ​​​Phase change memory cell 405A includes a bottom electrode 411, a top electrode 407, and a phase change element 409A disposed between bottom electrode 411 and top electrode 407. In some embodiments, bottom electrode 411 has a via. Bottom electrode 411 can include a conductor 413 laterally surrounded by a conductive liner 415. In some embodiments, bottom electrode 411 functions as a heater to increase the temperature of phase change element 409A for write and erase operations.

[0047] In some embodiments, phase change element 409A is or includes a chalcogenide glass. The chalcogenide glass can be or can include, for example, at least one chalcogenide (a chemical element from group 16 of the periodic table) or chalcogenide compound, such as sulfur (S), selenium (Se), tellurium (Te), selenium sulfide (SeS), germanium antimony telluride (GeSbTe), silver indium antimony telluride (AgInSbTe), etc. In some embodiments, phase change element 409A is or includes a germanium telluride compound (GeTeX), an arsenic telluride compound (AsTeX), or an arsenic selenium compound (AsSeX), where X can be, for example, germanium (Ge), silicon (Si), gallium (Ga), a lanthanide (Ln), phosphorus (P), boron (B), carbon (C), nitrogen (N), oxygen (O), combinations of the foregoing, etc.

[0048] Conductor 413 and top electrode 407 can be or can include, for example, titanium, tantalum, tungsten, a nitride of the foregoing (e.g., titanium nitride), combinations of the foregoing, etc. Conductor 413 and top electrode 407 can be the same material or different materials. In some embodiments, conductive liner 415 can be or can include, for example, titanium, tantalum, tungsten, hafnium, a nitride of the foregoing (such as titanium nitride), combinations of the foregoing, etc. Conductive liner 415 can function as an adhesion layer to maintain physical and electrical coupling between conductor 413 and the underlying conductive line 401.

[0049] In some embodiments, access selector device 427 is a metal-oxide-semiconductor field-effect transistor (MOSFET). Access selector device 427 can include a source / drain region 421 formed in or on a semiconductor substrate 437, a gate dielectric 429, a gate electrode 425, and a sidewall spacer 423. Gate dielectric 429 can be or can include, for example, an oxide (such as silicon dioxide), a high-k dielectric material, another suitable dielectric material, etc. Gate electrode 425 can be or can include, for example, polysilicon, a metallic material (such as aluminum, tungsten, titanium), or another suitable conductive material. Sidewall spacer can be or can include, for example, silicon nitride, silicon carbide, etc. Source / drain region 421 can be of a first doping type (n-type or p-type) and can be formed in a well 437 of a second doping type opposite the first doping type.

[0050] The semiconductor substrate 439 can include any type of semiconductor body (e.g., silicon, SiGe, SOI), such as a semiconductor wafer and / or one or more dies on a wafer, or any other type of semiconductor and / or epitaxial layers associated therewith. The dielectric structure 441 can include one or more interlayer dielectric (ILD) layers separated by etch stop layers and surrounding the conductive lines 401, conductive vias 403, etc. The ILD layers can include one or more dielectric materials, such as silicon dioxide (SiO2), low-k dielectric materials (such as carbon-doped oxides of silicon (SiCOH)), fluorosilicate glass, phosphosilicate glass (e.g., borophosphosilicate glass), etc. The conductive material forming the conductive lines 401, conductive vias 403, etc. can be or can include a metal (e.g., aluminum, copper, tungsten, etc.).

[0051] The first conductive line 401 coupled to the first source / drain region 421 can provide a source line (SL). The bottom electrode 411 of the phase change memory cell 405A can be coupled to the second source / drain region 421. The top electrode 407A of the phase change memory cell 405A can be coupled to the second conductive line 401, which provides a bit line (BL). The gate electrode 425 can provide a word line (WL). In some embodiments, the SL is in the second metal interconnect level, although the SL can alternatively be in another metal interconnect level. In some embodiments, the phase change memory cell 405A is disposed between the fourth and fifth metal interconnect levels, although the phase change memory cell 405A can alternatively be disposed at a higher or lower position within the metal interconnect structure 443. In some embodiments, the BL is disposed in a metal interconnect level above the phase change memory cell 405A. Many other arrangements of these structures can also be used within the scope of the present disclosure.

[0052] Although the integrated chip 400 uses MOSFETs as the access selector devices 427, many other types of access selector devices can be used. In some embodiments, the access selector devices 427 are different types of transistors, such as bipolar junction transistors, etc. In some embodiments, the access selector devices 427 are unipolar selectors, which reduce the number of connections required per memory cell 103 a，1 -103 d，4 In some embodiments, the unipolar selectors are diodes (e.g., PN diodes, PiN diodes, Schottky diodes, oxide semiconductor-oxide diodes, etc.). In such embodiments, the access selector devices 427 are formed by doping the semiconductor substrate 439 to form a p-type region and an n-type region, and by depositing a metal layer on the p-type region and the n-type region to form a Schottky diode, etc. a，1 -103 d，4A voltage greater than the threshold of the diode is applied to access the phase change memory cell 109 for read and write operations. In other embodiments, the unipolar selector is a filament-based selector, a rectifier, a varistor-type selector, an ohmic threshold switch (OTS), a doped chalcogenide-based selector, a Mott effect-based selector, a mixed ionic electronic conductor (MIEC)-based selector, a field assisted superlinear threshold (FAST) selector, etc.

[0053] The phase change element 409A has crystalline and amorphous states with completely different resistivity values. The crystalline and amorphous states can be used to represent different data states. More specifically, the phase change element 409A can be heated to a high temperature (e.g., over 600°C) at which it loses crystallinity. The phase change element 409A can then be rapidly cooled or "quenched" to "freeze" the phase change element in the amorphous state (high resistance state), which can correspond to, for example, a "0" data state (e.g., a "reset" operation). Conversely, by heating the phase change element 409A to a lower temperature (e.g., about 100-150 degrees Celsius), where the lower temperature is above the crystallization point of the phase change element 409A but below its melting point, the phase change element can be transitioned to a low resistance state (i.e., crystalline state), which can correspond to, for example, a "1" state (e.g., program or "SET" the phase change memory cell). The temperature and time can also be controlled to provide partial crystallization, which can be used to represent additional different data states, so that the phase change element 409A can provide a multi-level cell.

[0054] Figure 5 A cross-sectional view of a portion of an integrated chip 500 is shown, which is identical to the integrated chip 400 except that the integrated chip 500 has a phase change memory cell 405B instead of the phase change memory cell 405A. The phase change memory cell 405B differs from the phase change memory cell 405A in that it has a first phase change element 409B, a second phase change element 409C, and a third phase change element 409D. Like the phase change element 409A, the phase change elements 409B-409D can each be or include a chalcogenide glass. They can be the same chalcogenide glass or different chalcogenide glasses. Differences in composition, thickness, and distance from the bottom electrode 411 can be exploited to allow programming to leave none, one, two, or all three of the phase change elements 409B-409D in a crystalline state to represent four different configurations that provide two bits of data. Regardless of which configuration is employed, a multi-level cell with n bits of data has 2n different resistance levels that can be distinguished according to 2n-1 threshold values. According to the present disclosure, reliable reading of the programmed states (resistance levels) can be enhanced by temperature modulation of the read voltage.

[0055] The temperature sensing circuit 123 can obtain the temperature from any suitable type of temperature sensor at any suitable location. In some embodiments, the temperature sensing circuit 123 includes a temperature sensor that includes a first doped region (not shown) of the semiconductor substrate 439 and a second doped region (not shown) of the semiconductor substrate 439. The first and second doped regions are of different types and in contact with each other to define a PN junction. In some embodiments, the first and second doped regions can extend from a top surface of the semiconductor substrate 439 to a bottom surface of the semiconductor substrate 439. In some other embodiments, the temperature sensor includes a layer (not shown) of material whose resistance predictably changes in response to a change in temperature, such as a layer of doped polysilicon or the like.

[0056] While the examples focus on phase change random access memory (PcRAM), the structures and methods of the present disclosure can be applied to other types of memory, for example, including but not limited to resistive random access memory (ReRAM), oxygen- displacement memory (OxRAM), conductive-bridge random access memory (CBRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), carbon nanotube random access memory (NRAM), and the like.

[0057] Figure 6 A method 600 of operating an integrated chip 100, 400, 500 according to the present disclosure is shown. The method 600 includes an act 601 of measuring a temperature that is an approximate temperature of the memory array 101, an act 603 of selecting a read voltage based on the measured temperature, and an act 605 of reading a programmed state of one or more memory cells 103a,1-103d,4 using the selected read voltage. When the memory cell 103 a，1 -103 d，4 is in a certain particular resistance state, the read voltage is selected to improve temperature-dependent variations in current flow through the one of the memory cells 103 a，1 -103d,4. Reading the programmed state of the one of the memory cells 103 a，1 -103 d，4 may include applying the selected voltage to the memory cell 103 a，1 -103 d，4 and comparing a resulting current through the memory cell 103 a，1 -103 d，4 to one or more thresholds. In some embodiments, one or more of the one or more thresholds are also adjusted based on the temperature.

[0058] The temperature sensor can be any device whose resistance systematically changes with temperature. A phase change memory cell in a fixed programmed state is such a device. A phase change memory cell can maintain its programmed state for over 100 years. Thus, the integrated chip 100 can include a phase change memory cell that is programmed at the end of the manufacturing process and then used as a reference cell to determine a read voltage that can improve temperature related variations in the read current. The reference cell or similar device can be used to sense temperature variations and adjust the read voltage to improve temperature related variations in the current without specifically determining a temperature value or measuring temperature in a narrow sense.

[0059] Figure 7 An example method 700 is provided that uses a phase change memory reference cell to adjust a read voltage in response to temperature variations without making a specific temperature measurement. The method 700 can begin at act 701 by applying an initial value of a read voltage to a reference phase change memory cell. Act 703 is to measure a resulting current through the reference phase change memory cell. Act 705 is to determine whether the current is within a predetermined target range. If the current is outside the target range, the method 700 proceeds to act 707 to adjust the read voltage. If the current is above the target range, act 707 decreases the read voltage. If the current is below the target range, act 707 increases the read voltage. After adjusting the read voltage in act 707, the method 700 returns to act 701. Acts 701-707 constitute a feedback control loop that continues until the current is within the target range. Once the current is within the target range, the method continues with act 709 to apply the read voltage to read the programmed state of one or more memory cells 103 a，1 -103 d，4 .

[0060] Some aspects of the present teachings relate to an integrated chip having a semiconductor substrate, a driver circuit, and an array of resistive random access memory cells formed over the semiconductor substrate. The driver circuit is configured to provide a read voltage to selected cells in the array that selectively varies with respect to a temperature of the array. The memory cells can be multi-level phase change memory cells.

[0061] Some aspects of the present teachings relate to an integrated chip having a semiconductor substrate, an array of phase change memory cells formed over the semiconductor substrate, and a temperature sensor positioned to measure an approximate temperature of the array of phase change memory cells. Circuitry disposed on the semiconductor substrate is to select a read voltage for the phase change memory cells as a function of the approximate temperature.

[0062] Some aspects of the present teachings relate to a method of operating a phase change memory. The method includes selecting a voltage for reading a state of a cell in a phase change memory array, and applying the voltage to read the state of the cell in the phase change memory array. The method also includes adjusting the voltage in a manner that causes the voltage to increase if a temperature of the phase change memory array decreases, and causes the voltage to decrease if the temperature of the phase change memory array increases.

[0063] Some aspects of the present teachings relate to a method of operating a phase change memory. The method includes generating a first read voltage when the phase change memory is at a first temperature, and then driving a cell in a phase change memory array with the first read voltage. Subsequently, when the phase change memory is at a second temperature, a temperature-compensated read voltage is selected. A read current is generated by driving a second cell in the phase change memory array with the temperature-compensated read voltage. A programmed state of the second cell is determined by comparing the read current to one or more thresholds. In the method, the temperature-compensated read voltage is made higher when a difference between the second temperature and the first temperature causes the resistance of the second cell to be higher, and the temperature-compensated read voltage is made lower when the difference between the second temperature and the first temperature causes the resistance of the second cell to be lower. The first temperature decreases the resistance of the second cell.

[0064] Some aspects of the present teachings also relate to an integrated chip comprising: a semiconductor substrate; an array of resistive random access memory cells formed above the semiconductor substrate; and a driver circuit configured to provide a read voltage to a selected cell in the array that selectively varies with a temperature of the array.

[0065] In the above integrated chip, the driver circuit is configured to select the read voltage from one of a plurality of discrete read voltages as a function of the temperature.

[0066] In the above integrated chip, the driver circuit is configured to increase the read voltage in response to a decrease in the temperature, and to decrease the read voltage in response to an increase in the temperature.

[0067] In the above integrated chip, further comprising a sense amplifier structured to distinguish between four or more different programmed states of the selected cell by comparing a read current driven by the driver circuit to a plurality of reference currents.

[0068] In the above integrated chip, further comprising a temperature sensor that provides the temperature.

[0069] In the above integrated chip, the driver circuit is configured to continuously vary the read voltage based on the temperature.

[0070] In the above integrated chip, the resistive random access memory cells are phase change memory cells that include a chalcogenide glass.

[0071] In the above integrated chip, the resistive random access memory cells include a plurality of chalcogenide glass layers.

[0072] In the above integrated chip, further comprising: a reference phase change memory cell; wherein the driver circuit is operable to use the reference phase change memory cell to determine the selection of the read voltage.

[0073] Some aspects of the present teachings also relate to an integrated chip, comprising: a semiconductor substrate; an array of phase change memory cells formed above the semiconductor substrate; a temperature sensor positioned to measure an approximate temperature of the array of phase change memory cells; and a driver circuit formed on the semiconductor substrate and operable to select a read voltage for the phase change memory cells as a function of the approximate temperature.

[0074] In the above integrated chip, the driver circuit is configured to select the read voltage from a plurality of discrete voltages.

[0075] In the above integrated chip, the driver circuit is configured to select the read voltage as a function of a temperature range into which the approximate temperature falls.

[0076] In the above integrated chip, further comprising a sense amplifier structured to distinguish between four or more different resistance states of one of the phase change memory cells.

[0077] In the above integrated chip, further comprising: a sense amplifier operable to compare a current through one of the phase change memory cells to a reference current to distinguish between different resistance states of the phase change memory cells; wherein the sense amplifier is operable to select the reference current based on the approximate temperature.

[0078] Some aspects of the present teachings also relate to a method of operating a phase change memory, comprising: generating a first read voltage when a phase change memory array is at a first temperature; driving a cell in the phase change memory array with the first read voltage; generating a temperature-compensated read voltage when the phase change memory array is at a second temperature; generating a read current by driving a second cell in the phase change memory array with the temperature-compensated read voltage; and determining a programmed state of the second cell by comparing the read current to one or more thresholds; wherein the temperature-compensated read voltage is raised when a difference between the second temperature and the first temperature causes the resistance of the second cell to be higher, and the temperature-compensated read voltage is lowered when the difference between the second temperature and the first temperature causes the resistance of the second cell to be lower.

[0079] In the above method, the temperature-compensated read voltage is raised or lowered from the first read voltage in predetermined increments.

[0080] In the above method, the temperature-compensated read voltage is selected based on one or more temperature measurements.

[0081] In the above method, the temperature-compensated read voltage is selected from a plurality of discrete voltages.

[0082] In the above method, each of the discrete voltages corresponds to a different range of second temperatures.

[0083] In the above method, further comprising: applying a second read voltage to a cell in the phase change memory array or a phase change memory cell external to the phase change memory array; comparing a resulting current through the cell to a target current range; selecting the temperature-compensated read voltage to be lower than the second voltage if the resulting current is above the target current range; and selecting the temperature-compensated read voltage to be higher than the second voltage if the resulting current is below the target current range.

[0084] One skilled in the art will readily appreciate that one or more of the disclosed embodiments can be realized without realizing the other specified advantages in whole or in part. From the foregoing detailed description, one skilled in the art will appreciate that various changes can be made without departing from the scope of the present disclosure. Accordingly, it is intended by the appended claims, their equivalents, and the foregoi ng description to encompass all such changes and modifications.

Claims

1. An integrated chip, comprising: Semiconductor substrate; An array of resistive random access memory cells is formed above the semiconductor substrate; as well as The driver circuit is configured to provide a read voltage to a selected cell in the array regarding temperature-selective changes in the array; The sensing amplifier is configured to distinguish between four or more different programming states of the selected cell by comparing a read current driven by the driver circuit with a plurality of reference currents. The magnitude of at least one of the plurality of reference currents varies with the temperature of the array.

2. The integrated chip according to claim 1, wherein, The driver circuit is configured to select one of a plurality of discrete read voltages as the read voltage based on the temperature.

3. The integrated chip according to claim 1, wherein, The driver circuit is configured to increase the read voltage in response to a decrease in temperature and decrease the read voltage in response to an increase in temperature.

4. The integrated chip of claim 1, further comprising a plurality of reference current generators, one or more of the plurality of reference current generators generating at least one of the plurality of reference currents related to the temperature.

5. The integrated chip according to claim 1, further comprising a temperature sensor providing the temperature.

6. The integrated chip according to claim 1, wherein, The driver circuit is configured to continuously change the read voltage based on the temperature.

7. The integrated chip according to claim 1, wherein, The resistive random access memory unit is a phase change memory unit comprising chalcogenide glass.

8. The integrated chip according to claim 7, wherein, The resistive random access memory cell includes multiple chalcogenide glass layers.

9. The integrated chip according to claim 1, further comprising: Reference phase-change memory cell; The driver circuit is operable to use the reference phase-change memory cell to determine the selection of the read voltage.

10. An integrated chip, comprising: Semiconductor substrate; An array of phase-change memory cells is formed above the semiconductor substrate; A temperature sensor is positioned to measure the temperature of the array of phase-change memory cells; as well as A driver circuit is formed on the semiconductor substrate and operates to select the read voltage of the phase change memory cell according to the temperature; A sensing amplifier operable to compare a current passing through one of the phase-change memory cells with a reference current to distinguish different resistance states of the phase-change memory cells; The sensing amplifier is operable to select the reference current based on the temperature.

11. The integrated chip according to claim 10, wherein, The driver circuit is configured to select the read voltage from a plurality of discrete voltages.

12. The integrated chip according to claim 10, wherein, The driver circuit is configured to select the read voltage based on the temperature range into which the temperature falls.

13. The integrated chip according to claim 10, wherein, The sensing amplifier is configured to distinguish between four or more different resistance states of one of the phase-change memory cells.

14. The integrated chip according to claim 10, further comprising: A reference current generator that generates a reference current that is related to the temperature.

15. A method of operating a phase-change memory, comprising: When the phase-change memory array is at a first temperature, a first read voltage is generated; The cells in the phase-change memory array are driven using the first read voltage; When the phase-change memory array is at the second temperature, a temperature-compensated read voltage is generated; A read current is generated by driving a second cell in the phase-change memory array using the temperature-compensated read voltage; as well as The programming state of the second cell is determined by comparing the read current with one or more thresholds, wherein the magnitude of at least one of the one or more thresholds varies with the temperature of the phase change memory array; Specifically, when the difference between the second temperature and the first temperature causes the resistance of the second unit to be high, the temperature-compensated read voltage is increased; and when the difference between the second temperature and the first temperature causes the resistance of the second unit to be low, the temperature-compensated read voltage is decreased.

16. The method according to claim 15, wherein, The temperature-compensated read voltage increases or decreases the first read voltage by a predetermined increment.

17. The method according to claim 15, wherein, The temperature compensation reading voltage is selected based on one or more temperature measurements.

18. The method according to claim 15, wherein, The temperature compensation read voltage is selected from a plurality of discrete voltages.

19. The method according to claim 18, wherein, Each of the discrete voltages corresponds to a different range of the second temperature.

20. The method of claim 15, further comprising: A second read voltage is applied to a cell in the phase change memory array or a phase change memory cell outside the phase change memory array; The current obtained through the unit is compared with the target current range; If the obtained current is higher than the target current range, the temperature-compensated reading voltage is selected to be lower than the second reading voltage; as well as If the obtained current is lower than the target current range, the temperature-compensated reading voltage is selected to be higher than the second reading voltage.

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