Semiconductor chip including through electrode and semiconductor package including the same

Abstract

The present application relates to a semiconductor chip including a through electrode and a semiconductor package including the same. The semiconductor chip according to an embodiment includes a main body part having a front surface and a rear surface, the main body part being oriented in a manner that the rear surface is above the front surface; a first through electrode and a second through electrode penetrating the main body part, the first and second through electrodes having protrusions protruding above the rear surface of the main body part; a wiring part formed below the front surface of the main body part; a power supply pattern formed above the rear surface of the main body part and spaced apart from the protrusions; an interlayer insulation layer filling a space between the power supply pattern and the protrusions; and a first rear connection electrode and a second rear connection electrode formed above the interlayer insulation layer and connected to the first and second through electrodes, respectively, wherein the first rear connection electrode is connected to both the first through electrode and a portion of the power supply pattern adjacent to the first through electrode.

Description

TECHNICAL FIELD

[0001] The present patent document relates to semiconductor technology, and more particularly, to a semiconductor chip including a through electrode and a semiconductor package including the same. BACKGROUND

[0002] Electronic products need a large amount of data processing even as their size gradually becomes smaller. Accordingly, the size of semiconductor chips used in these electronic products also needs to be thin and small. In addition, semiconductor packages in which a plurality of semiconductor chips are embedded have been manufactured.

[0003] A plurality of semiconductor chips can be stacked in a vertical direction and can be electrically connected to each other using through electrodes that pass through the semiconductor chips. SUMMARY

[0004] In an embodiment, a semiconductor chip can include a body portion having a front surface and a rear surface, the body portion being oriented in a manner that the rear surface is above the front surface, a first through electrode and a second through electrode penetrating the body portion and having protrusions protruding above the rear surface of the body portion, a power pattern formed above the rear surface of the body portion and spaced apart from the protrusions, an interlayer insulating layer filling a space between the power pattern and the protrusions, and a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and connected to the first through electrode and the second through electrode, respectively, wherein the first rear connection electrode is connected to the first through electrode and a portion of the power pattern adjacent to the first through electrode at the same time.

[0005] In another embodiment, a semiconductor package can include a first semiconductor chip including a main part having a front surface and a rear surface, a first through electrode and a second through electrode penetrating the main part and having a protrusion protruding above the rear surface of the main part, a power pattern formed above the rear surface of the main part and spaced apart from the protrusion, an interlayer insulating layer filling a space between the power pattern and the protrusion, a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and connected to the first through electrode and the second through electrode, respectively, and a rear insulating layer formed above the interlayer insulating layer and the power pattern and filling a space between the first rear connection electrode and the second rear connection electrode, the main part being oriented in a manner that the rear surface is above the front surface, wherein the first rear connection electrode is connected to the first through electrode and a portion of the power pattern adjacent to the first through electrode at the same time; and a second semiconductor chip including a plurality of front connection electrodes directly bonded to the first rear connection electrode and the second rear connection electrode, respectively, and a front insulating layer directly bonded to the rear insulating layer while filling a space between the plurality of front connection electrodes.

[0006] In another embodiment, a semiconductor chip can include a main part having a front surface and a rear surface, the main part being oriented in a manner that the rear surface is above the front surface; a first through electrode and a second through electrode penetrating the main part; a power pattern formed above the rear surface of the main part and spaced apart from the first through electrode and the second through electrode; a first connection pattern and a second connection pattern formed above the rear surface of the main part and connected to the first through electrode and the second through electrode, respectively; an interlayer insulating layer filling a space between the power pattern and the first connection pattern and the second connection pattern; and a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and connected to the first connection pattern and the second connection pattern, respectively, wherein the first rear connection electrode is connected to the first connection pattern and a portion of the power pattern adjacent to the first connection pattern at the same time.

[0007] In another embodiment, a semiconductor package can include a first semiconductor chip including a main body portion having a front surface and a rear surface, a first through electrode and a second through electrode penetrating the main body portion, a power pattern formed above the rear surface of the main body portion and spaced apart from the first through electrode and the second through electrode, a first connection pattern and a second connection pattern formed above the rear surface of the main body portion and connected to the first through electrode and the second through electrode, respectively, an interlayer insulating layer filling a space between the power pattern and the first connection pattern and the second connection pattern, a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and connected to the first connection pattern and the second connection pattern, respectively, and a rear insulating layer formed above the interlayer insulating layer and the power pattern and filling a space between the first rear connection electrode and the second rear connection electrode, the main body portion being oriented in a manner that the rear surface is above the front surface, wherein the first rear connection electrode is connected to the first through electrode and a portion of the power pattern adjacent to the first through electrode at the same time; and a second semiconductor chip including a plurality of front connection electrodes directly bonded to the first rear connection electrode and the second rear connection electrode, respectively, and a front insulating layer directly bonded to the rear insulating layer while filling a space between the plurality of front connection electrodes. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1A and FIG. 1B is a diagram illustrating a semiconductor chip according to an embodiment of the present disclosure.

[0009] FIG. 2 is a cross-sectional view illustrating a stacked semiconductor chip according to an embodiment of the present disclosure.

[0010] FIGS. 3A-3F is a cross-sectional view illustrating a manufacturing method of a semiconductor chip according to an embodiment of the present disclosure.

[0011] FIGS. 4A-4D is a cross-sectional view illustrating a manufacturing method of a semiconductor chip according to another embodiment of the present disclosure.

[0012] FIG. 5A and FIG. 5B is a diagram illustrating a semiconductor chip according to another embodiment of the present disclosure.

[0013] FIGS. 6A-6D is a cross-sectional view illustrating a manufacturing method of a semiconductor chip according to another embodiment of the present disclosure.

[0014] FIGS. 7A-7C is a cross-sectional view illustrating a manufacturing method of a semiconductor chip according to another exemplary embodiment of the present disclosure.

[0015] FIG. 8A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0016] FIG. 9 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0017] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0018] The accompanying drawings are not necessarily drawn to scale. In some instances, at least some of the structures in the drawings can have been exaggerated for the sake of clarity. In presenting a particular example in an accompanying drawing or description, the relative positioning relationship of the layers as shown or the order of arranging the layers reflects a particular implementation of the example described or shown, and different relative positioning relationship or order of arranging the layers can be possible. In addition, the example described or shown of a multi-layer structure can not reflect all layers present in the particular multi-layer structure (e.g., one or more additional layers can be present between the two shown layers). As a particular example, when a first layer in a described or shown multi-layer structure is referred to as being "on" or "over" a second layer or a substrate, the first layer can be formed directly on the second layer or substrate, but can also indicate a structure in which one or more other intervening layers can be present between the first layer and the second layer or substrate.

[0019] In the description of the following embodiments, when a parameter is referred to as being "predetermined", it can be intended to mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter can be set at the start of the process or algorithm, or can be set during the period of executing the process or algorithm.

[0020] FIG. 1A and FIG. 1B is a diagram illustrating a semiconductor chip according to an embodiment of the present disclosure. FIG. 1A is a plan view of the semiconductor chip of the present embodiment as viewed from above, FIG. 1B is a cross-sectional view taken along the line A-A' of FIG. 1A In FIG. 1A , for the sake of convenience of description, the through electrode and the power supply pattern provided below the back connection electrode are shown in dotted lines together with the back connection electrode provided at the uppermost portion of the semiconductor chip.

[0021] Referring to FIG. 1A and FIG. 1BThe semiconductor chip 100 of the present embodiment can include a main body part 110, a wiring part 120, a front connection electrode 130, a front insulating layer 140, a through electrode 150, a power supply pattern 160, an interlayer insulating layer 170, a rear connection electrode 180, and a rear insulating layer 190.

[0022] The main body part 110 can be formed of a semiconductor material such as silicon or germanium, and can have a front surface 111, a rear surface 112, and side surfaces connecting them to each other. The front surface 111 of the main body part 110 can refer to an active surface provided with the wiring part 120, and the rear surface 112 of the main body part 110 can refer to a surface located on the opposite side of the front surface 111.

[0023] The wiring part 120 can be formed under the front surface 111 of the main body part 110. The wiring part 120 can include a circuit / wiring structure electrically connected to the through electrode 150. For the convenience of description, the circuit / wiring structure is simply shown as a line in the wiring part 120, but is not limited to the illustrated case. In this case, the circuit / wiring structure can be implemented differently depending on the type of the semiconductor chip 100. For example, when the semiconductor chip 100 includes a volatile memory such as a dynamic random access memory (DRAM) and a static random access memory (SRAM) or a non-volatile memory such as a NAND flash, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), and a ferroelectric random access memory (FRAM), the circuit / wiring structure can include a memory cell array having a plurality of memory cells.

[0024] The front connection electrode 130 can be formed under the wiring part 120. The front connection electrode 130 can be used to electrically connect the semiconductor chip 100 to another component (not shown) such as another semiconductor chip or a substrate that will face the front surface 111. The front connection electrode 130 can include a metal such as copper (Cu), nickel (Ni), tin (Sn), gold (Au), silver (Ag), or a combination thereof or a compound of the metal, and can have a single-layer structure or a multi-layer structure. In particular, when the front connection electrode 130 is directly bonded to a rear connection electrode of another semiconductor chip (not shown) to form a hybrid bonding structure, the front connection electrode 130 can include a metal material that can be bonded to the rear connection electrode by interdiffusion of metals through a high-temperature annealing process.

[0025] The front connection electrode 130 can be electrically connected to the wiring part 120. In addition, the front connection electrode 130 can be electrically connected to the through electrode 150 through the wiring part 120.

[0026] The front insulating layer 140 can be formed under the wiring portion 120 to fill spaces between the front connection electrodes 130. The front insulating layer 140 can include various insulating materials. In particular, when the front insulating layer 140 is directly bonded to a rear insulating layer of another semiconductor chip (not shown) to form a hybrid bonded structure, the front insulating layer 140 can include an insulating material that can be bonded to the rear insulating layer through covalent bonding between insulating materials. For example, the front insulating layer 140 can include silicon oxide or silicon nitride. One surface of the front connection electrodes 130 not facing the wiring portion 120 and one surface of the front insulating layer 140 can be substantially coplanar.

[0027] The through electrode 150 can have a columnar shape extending from the front surface 111 of the body portion 110 to the rear surface 112 and penetrating the body portion 110. In addition, the through electrode 150 can protrude above the rear surface 112 of the body portion 110 to further penetrate the interlayer insulating layer 170 formed above the rear surface 112 of the body portion 110. As an example, the through electrode 150 can include a TSV (Through Silicon Via). The through electrode 150 can include various conductive materials. As an example, the through electrode 150 can include a metal such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), or a combination thereof, or a compound of the metal. One end of the through electrode 150 can be connected to a portion of the circuit / wiring structure of the wiring portion 120, and the other end of the through electrode 150 can be connected to the rear connection electrode 180. In a plan view, the width of each through electrode 150 is indicated by the reference numeral W1.

[0028] The through electrode 150 can include a first through electrode 150A electrically connected to the power supply pattern 160 and a second through electrode 150B not electrically connected to the power supply pattern 160. A power supply (e.g., a power supply voltage or a ground voltage of various levels) can be supplied through the first through electrode 150A. In this case, the power supply applied to the first through electrode 150A can be the same as the power supply applied to the power supply pattern 160. In addition, various levels of power supply can be supplied through the second through electrode 150B, or various signals required to drive the semiconductor chip 100 can be transmitted through the second through electrode 150B. In this case, the power supply applied to the second through electrode 150B can be different from the power supply applied to the first through electrode 150A and the power supply pattern 160. For example, the potential value applied to the second through electrode 150B can be different from the potential value applied to the first through electrode 150A and the power supply pattern 160.

[0029] The power supply pattern 160 can be formed over the rear surface 112 of the body portion 110 to be spaced apart from the through electrode 150 in a horizontal direction. The power supply pattern 160 can be electrically connected to the first through electrode 150A by the first rear connection electrode 180A and can be electrically insulated from the second through electrode 150B. The power supply pattern 160 can include various conductive materials. As an example, the power supply pattern 160 can include a metal such as copper (Cu), nickel (Ni), tin (Sn), gold (Au), silver (Ag), or a combination thereof, or a compound of the metal.

[0030] In the present embodiment, in a plan view, the power supply pattern 160 can include a plurality of line patterns 160A arranged in one direction and an extension pattern 160B connecting end portions of the plurality of line patterns 160A to each other. The interlayer insulating layer 170 can fill spaces between the plurality of line patterns 160A. That is, the plurality of line patterns 160A can be alternately arranged with the interlayer insulating layer 170. In this case, compared to a case where a power supply pattern having a flat plate shape is formed, an area in which the interlayer insulating layer 170 is formed can be increased, so that an adhesion property between a layer in which the power supply pattern 160 is formed and a layer formed thereon (for example, a layer in which the rear connection electrode 180 and the rear insulating layer 190 are formed) can be improved. However, the present disclosure is not limited thereto, and the power supply pattern 160 can have various planar shapes, provided that it is spaced apart from the through electrode 150.

[0031] Two or more first through electrodes 150A can be electrically connected to each other by the power supply pattern 160A to form a power distribution network (PDN), and thus, stable power supply can be made through the first through electrode 150A.

[0032] The interlayer insulating layer 170 can be formed over the rear surface 112 of the body portion 110 to fill spaces between the through electrode 150 and the power supply pattern 160. The interlayer insulating layer 170 can include various insulating materials such as silicon oxide, silicon nitride, or a combination thereof. In addition, the interlayer insulating layer 170 can have a single layer structure or a multi-layer structure. One surface of the through electrode 150, one surface of the power supply pattern 160, and one surface of the interlayer insulating layer 170, which do not face the rear surface 112 of the body portion 110, can form a substantially flat surface.

[0033] The back connection electrodes 180 can be formed over a flat surface formed based on one surface of the through electrodes 150, one surface of the power source pattern 160, and one surface of the interlayer insulation layer 170. The back connection electrodes 180 can be used to electrically connect the semiconductor chip 100 to another component (not shown) such as another semiconductor chip that will face the back surface 112. The back connection electrodes 180 can include a metal such as copper (Cu), nickel (Ni), tin (Sn), gold (Au), silver (Ag), or a combination thereof, or a compound of the metal, and can have a single layer structure or a multi-layer structure. The back connection electrodes 180 can be formed of the same material as the front connection electrodes 130. Specifically, when the back connection electrodes 180 are directly bonded to the front connection electrodes of another semiconductor chip (not shown) to form a hybrid bonding structure, the back connection electrodes 180 can include a metal material that can be bonded to the front connection electrodes by interdiffusion of metals through a high-temperature annealing process. In a plan view, the width of each back connection electrode 180 is indicated by the reference numeral W2.

[0034] The back connection electrodes 180 can include first back connection electrodes 180A connected to the first through electrodes 150A, second back connection electrodes 180B connected to the second through electrodes 150B, and third back connection electrodes 180C not connected to the through electrodes 150.

[0035] The first back connection electrodes 180A can be formed to overlap and be connected with the respective first through electrodes 150A. The first back connection electrodes 180A can correspond one-to-one to the first through electrodes 150A. In addition, the first back connection electrodes 180A can overlap and be connected with the portions of the power source pattern 160 adjacent to the first through electrodes 150A at the same time (see P1). To this end, the value of the width W2 of the first back connection electrodes 180A can be greater than the sum of the width W1 of the first through electrodes 150A and the minimum distance D1 between the first through electrodes 150A and the power source pattern 160 adjacent thereto. As a result, the first back connection electrodes 180A can electrically connect the first through electrodes 150A to the power source pattern 160, and a power source applied to the first through electrodes 150A and the power source pattern 160 can be supplied to the first back connection electrodes 180A.

[0036] The second back connection electrode 180B can be formed to overlap and be connected with each of the second through electrodes 150B. The second back connection electrode 180B can correspond one-to-one with the second through electrodes 150B. The second back connection electrode 180B can not overlap / connect with the power supply pattern 160 around the second through electrode 150B. To this end, the power supply pattern 160 can be arranged such that a minimum distance D2 between the second through electrode 150B and the power supply pattern 160 adjacent thereto is greater than a minimum distance D1 between the first through electrode 150A and the power supply pattern 160 adjacent thereto. That is, a value of a width W2 of the second back connection electrode 180B can be less than a sum of a width W1 of the second through electrode 150B and the minimum distance D2 between the second through electrode 150B and the power supply pattern 160 adjacent thereto. A power supply or a signal applied to the second through electrode 150B can be supplied or transmitted to the second back connection electrode 180B.

[0037] The third back connection electrode 180C can be formed to be spaced apart from the first back connection electrode 180A and the second back connection electrode 180B without overlapping or being connected with the through electrode 150. The third back connection electrode 180C can be a dummy that is not used for signal transmission or power supply. In the present embodiment, the third back connection electrode 180C can be applied with the same power supply as the power supply pattern 160 by overlapping and being connected with the power supply pattern 160. However, if the third back connection electrode 180C is in a floating state not electrically connected to other wiring except the power supply pattern 160, the third back connection electrode 180C can not perform a function of signal transmission or power supply. Further, as described later, even if the third back connection electrode 180C is connected to a front connection electrode (see 130 in FIG. 1) of another semiconductor chip, in a case where the third back connection electrode 180C is in a floating state not electrically connected to other wiring except the power supply pattern 160, the third back connection electrode 180C can not perform a function of signal transmission or power supply. FIG. 2 In another embodiment, unlike the example, the third back connection electrode 180C can not overlap / connect with the power supply pattern 160. That is, the third back connection electrode 180C can be formed in a region in which the power supply pattern 160 is not present, and thus can have an electrically floating state. The third back connection electrode 180C can perform various functions. As an example, the third back connection electrode 180C can function to facilitate a process, for example, serving as a stop layer during a planarization process when a plurality of semiconductor chips 100 are stacked. As another example, the third back connection electrode 180C can function to improve a heat dissipation characteristic in a semiconductor package having a plurality of semiconductor chips 100. The third back connection electrode 180C can be omitted.

[0038] The front connection electrodes 130 and the rear connection electrodes 180 can have the same arrangement. That is, in a plan view, the plurality of front connection electrodes 130 and the plurality of rear connection electrodes 180 can overlap each other.

[0039] The rear insulating layer 190 can be formed above a flat surface formed based on one surface of the through electrode 150, one surface of the power supply pattern 160, and one surface of the interlayer insulating layer 170, to fill a space between the rear connection electrodes 180. The rear insulating layer 190 can include various insulating materials. The rear insulating layer 190 can be formed of the same material as the front insulating layer 140. Specifically, when the rear insulating layer 190 is directly bonded to a front insulating layer of another semiconductor chip (not shown) to form a hybrid bonding structure, the rear insulating layer 190 can include an insulating material that can be bonded to the front insulating layer through covalent bonding between insulating materials. For example, the rear insulating layer 190 can include silicon oxide or silicon nitride. One surface of the rear connection electrode 180 not facing the above-described flat surface and one surface of the rear insulating layer 190 can be substantially coplanar.

[0040] According to the above-described semiconductor chip 100, the first rear connection electrode 180A can be connected to the corresponding first through electrode 150A and the power supply pattern 160 adjacent thereto at the same time. Also, the first rear connection electrode 180A can directly contact the corresponding first through electrode 150A and the power supply pattern 160 adjacent thereto. Thus, since two or more first through electrodes 150A form a PDN through the first rear connection electrode 180A and the power supply pattern 160, the power supply can be easily and stably supplied. Specifically, when a plurality of semiconductor chips 100 are stacked in a vertical direction, power supply through the plurality of semiconductor chips 100 can be more efficiently performed.

[0041] In addition, when a plurality of semiconductor chips 100 are stacked in a vertical direction, a hybrid bonding structure that firmly bonds the semiconductor chips 100 adjacent in the vertical direction can be provided. This will be described in more detail below with reference to FIG. 2 in more detail.

[0042] FIG. 2 is a cross-sectional view illustrating a stacked semiconductor chip according to an embodiment of the disclosure. FIG. 2 shows a case where two semiconductor chips are stacked in a vertical direction.

[0043] Referring to FIG. 2 , the first semiconductor chip 100 can be substantially the same as the above-described FIG. 1A and FIG. 1B semiconductor chip 100. Thus, the same reference numerals as those of FIG. 1A and FIG. 1B are used.

[0044] The second semiconductor chip 200 can also be substantially the same as the above-describedFIG. 1A and FIG. 1B The semiconductor chip 100 is substantially the same as the first semiconductor chip 100. That is, the second semiconductor chip 200 can include a main body portion 210 having a front surface 211 and a rear surface 212, the main body portion being oriented in an embodiment in a manner that the rear surface 212 is above the front surface 211, a wiring portion 220 disposed above the front surface 211 of the main body portion 210, front connection electrodes 230 disposed above the wiring portion 220 and electrically connected to the through electrodes 250 through the wiring portion 220, a front insulating layer 240 disposed above the wiring portion 220 and filling spaces between the front connection electrodes 230, through electrodes 250 penetrating the main body portion 210 and protruding above the rear surface 212 of the main body portion 210, a power supply pattern 260 disposed above the rear surface 212 of the main body portion 210, an interlayer insulating layer 270 disposed above the rear surface 212 of the main body portion 210 and filling spaces between the through electrodes 250 and the power supply pattern 260, rear connection electrodes 280 disposed above the interlayer insulating layer 270, and a rear insulating layer 290 disposed above the interlayer insulating layer 270 and filling spaces between the rear connection electrodes 280. The through electrodes 250 can include first through electrodes 250A electrically connected to the power supply pattern 260 and second through electrodes 250B not electrically connected to the power supply pattern 260. The rear connection electrodes 280 can include first rear connection electrodes 280A connected to both the first through electrodes 250A and the power supply pattern 260, second rear connection electrodes 280B connected to the second through electrodes 250B and not connected to the power supply pattern 260, and third rear connection electrodes 280C not connected to the through electrodes 250.

[0045] The second semiconductor chip 200 can be stacked above the first semiconductor chip 100, and the front surface 211 of the second semiconductor chip 200 faces the rear surface 112 of the first semiconductor chip 100. In this case, the rear connection electrode 180 of the first semiconductor chip 100 can be directly bonded to the front connection electrode 230 of the second semiconductor chip 200, and the rear insulating layer 190 of the first semiconductor chip 100 can be directly bonded to the front insulating layer 240 of the second semiconductor chip 200. This can be achieved by performing a high-temperature annealing process in a state in which the rear connection electrode 180 and the rear insulating layer 190 of the first semiconductor chip 100 are in contact with the front connection electrode 230 and the front insulating layer 240 of the second semiconductor chip 200, respectively. During the high-temperature annealing process, the metals used to form the rear connection electrode 180 of the first semiconductor chip 100 and the front connection electrode 230 of the second semiconductor chip 200 can be bonded to each other through mutual diffusion of the metals (for example, mutual diffusion of copper). At this time, the insulating materials used to form the rear insulating layer 190 of the first semiconductor chip 100 and the front insulating layer 240 of the second semiconductor chip 200 can be bonded to each other through covalent bonding of the insulating materials (for example, covalent bonding formed between silicon oxide or silicon nitride). Accordingly, hybrid bonding between the first semiconductor chip 100 and the second semiconductor chip 200 can be performed. That is, bonding of the metal to the metal and bonding of the insulating layer to the insulating layer can be performed in situ.

[0046] Each of the first to third back connection electrodes 180A, 180B, and 180C of the first semiconductor chip 100 can be bonded to a corresponding front connection electrode 230 of the second semiconductor chip 200. In this case, the arrangement of the first to third back connection electrodes 180A, 180B, and 180C can be substantially the same as the arrangement of the front connection electrodes 230. In a plan view, each of the first to third back connection electrodes 180A, 180B, and 180C can overlap the corresponding front connection electrode 230. The third back connection electrode 180C of the first semiconductor chip 100 can be omitted. In this case, the front connection electrode 230 of the second semiconductor chip 200 corresponding to the third back connection electrode 180C can also be omitted. According to embodiments, power is supplied to the first semiconductor chip 100 and the second semiconductor chip 200 through the first through electrode 150A, the power supply pattern 160, the first back connection electrode 180A, and the front connection electrode 230 connected to the first back connection electrode 180A, and a signal is transmitted to the first semiconductor chip 100 and the second semiconductor chip 200 through the second through electrode 150B, the second back connection electrode 180B, and the front connection electrode 230 connected to the second back connection electrode 180B. According to embodiments, the power supplied to the first semiconductor chip 100 and the second semiconductor chip 200 through the first through electrode 150A, the power supply pattern 160, the first back connection electrode 180A, and the front connection electrode 230 connected to the first back connection electrode 180A is different from the power supplied to the first semiconductor chip 100 and the second semiconductor chip 200 through the second through electrode 150B, the second back connection electrode 180B, and the front connection electrode 230 connected to the second back connection electrode 180B.

[0047] According to the above-described embodiments, firm bonding between the first semiconductor chip 100 and the second semiconductor chip 200 can be performed by forming a hybrid bonding structure. In addition, since electrical connection between the first semiconductor chip 100 and the second semiconductor chip 200 is achieved without connection bumps, a power supply path or a signal transmission path therebetween can be shortened. As a result, power supply delay or signal transmission delay can be reduced, thereby improving the operating characteristics of the first semiconductor chip 100 and the second semiconductor chip 200. In addition, since a space for arranging bumps between the first semiconductor chip 100 and the second semiconductor chip 200 is not needed, a reduction in heat transfer efficiency caused by filling the space with an insulating material can be reduced.

[0048] Furthermore, by not setting the power patterns 160 and 260 on the surface, the impact on the interfacial bonding strength of the hybrid bonding structure can be minimized. The interfacial bonding strength of the hybrid bonding structure can be defined as the sum of the covalent bonding strength between insulating layers and the intermetallic bonding strength between metals. Since covalent bonding strength is stronger than intermetallic bonding strength, the total interfacial bonding strength can also be reduced when the area occupied by the insulating layer at the bonding interface is reduced. If the power pattern is formed at the same height as the rear connecting electrode (i.e., in the rear insulating layer), the contact area between the rear insulating layer of the lower semiconductor chip and the front insulating layer of the upper semiconductor chip can be reduced, thus reducing the interfacial bonding strength between them.

[0049] FIGS. 3A-3F This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to an embodiment of the present disclosure.

[0050] Reference FIG. 3A A structure can be formed above a carrier substrate (not shown), the structure having: an initial body portion 310 having a front surface 311 and an initial rear surface 312 therein, wherein an initial through electrode 350 is formed; a wiring portion 320 formed below the front surface 311 of the initial body portion 310; and a front connecting electrode 330 and a front insulating layer 340 formed below the wiring portion 320. The initial through electrode 350 may include an initial conductive post 352 and initial spacers 354 surrounding the side and top surfaces of the initial conductive post 352. The method of forming this structure will be described in more detail below.

[0051] First, an initial body portion 310 with a front surface 311 and an initial rear surface 312 can be provided. The distance between the initial rear surface 312 and the front surface 311 is comparable. FIG. 1B The rear surface 112 is large, therefore, the initial main body portion 310 can have a larger size than the rear surface 112. FIG. 1B The main body has a thickness of 110.

[0052] Subsequently, the initial body portion 310 may be etched to form a hole 313 in the initial body portion 310. The hole 313 may be formed from the front surface 311 of the initial body portion 310 toward the initial rear surface 312 at a predetermined depth. The depth of the hole 313 may be less than the thickness of the initial body portion 310.

[0053] Subsequently, an initial spacer 354 can be formed along the inner wall of the hole 313, and the hole 313 with the initial spacer 354 can be filled with a conductive material to form an initial conductive post 352. Thus, an initial through electrode 350 can be formed. The initial conductive post 352 may include a metal or a metal compound, and the initial spacer 354 may include silicon oxide, silicon nitride, metal nitride, etc.

[0054] Subsequently, the wiring portion 320 can be formed under the front surface 311 of the initial main body portion 310 in which the initial through electrode 350 is formed, and the front connection electrode 330 and the front insulating layer 340 can be formed under the wiring portion 320. Thus, the structure of FIG. 3A

[0055] Referring to FIG. 3B A portion of the initial main body portion 310 can be removed to form the main body portion 310A which is thinner than the initial main body portion 310. That is, a thinning process can be performed.

[0056] The thinning process can be performed on the initial rear surface 312 of the initial main body portion 310. Thus, the main body portion 310A can have the front surface 311 and the rear surface 312A. The distance between the front surface 311 and the rear surface 312A of the main body portion 310A can be smaller than the distance between the front surface 311 and the initial rear surface 312. The thinning process can be performed by grinding, chemical mechanical polishing (CMP), and / or etch-back. Further, the thinning process can be performed such that a portion of the initial through electrode 350 can protrude from the rear surface 312A of the main body portion 310A. The portion of the initial through electrode 350 which protrudes from the rear surface 312A of the main body portion 310A will be referred to as a protrusion of the initial through electrode 350 (see P2).

[0057] Referring to FIG. 3C The initial first interlayer insulating layer 372 can be conformally formed along its lower profile. As an example, the initial first interlayer insulating layer 372 can include silicon nitride.

[0058] Subsequently, a stack structure of the initial second interlayer insulating layer 374 and the initial third interlayer insulating layer 376 can be formed over the initial first interlayer insulating layer 372 along its lower profile. The stack structure can have an opening OP which provides a space in which a power pattern is to be formed. The stack structure can be formed by depositing layers of insulating materials for forming the initial second interlayer insulating layer 374 and the initial third interlayer insulating layer 376 over the initial first interlayer insulating layer 372 along its lower profile and removing the layers of insulating materials in regions corresponding to the opening OP by a mask and etching process. During the mask and etching process, the initial first interlayer insulating layer 372 can function as an etch stop layer. As an example, the initial second interlayer insulating layer 374 and the initial third interlayer insulating layer 376 can include silicon oxide and silicon nitride, respectively.

[0059] Referring to FIG. 3D The initial first interlayer insulating layer 372 can be conformally formed along its lower profile. As an example, the initial first interlayer insulating layer 372 can include silicon nitride. FIG. 3C ​An initial metal-containing thin film layer 362 is formed over the resulting structure. The initial metal-containing thin film layer 362 may include a metal or a metal compound and may have a single-layer or multi-layer structure. The initial metal-containing thin film layer 362 may be formed by deposition or the like and may be formed to a thin thickness with incomplete filling of the opening OP. The initial metal-containing thin film layer 362 may serve to improve the properties and / or formation process of the metal-containing layer 364, which will be described later.

[0060] Subsequently, an initial metal-containing layer 364 may be formed over the initial metal-containing thin film layer 362. The initial metal-containing layer 364 may include a metal or a metal compound and may have a single-layer structure or a multi-layer structure. The initial metal-containing layer 364 may be formed by deposition, electroplating, etc., and may be formed to have a thickness that sufficiently fills the opening OP on which the initial metal-containing thin film layer 362 is formed.

[0061] Reference FIG. 3E , can be FIG. 3D The resulting structure undergoes a planarization process. The planarization process can be performed by methods such as chemical mechanical polishing. Additionally, a planarization process can be performed such that, apart from the initial third interlayer insulating layer 376 present above the initial through electrode 350, the upper surface of the initial third interlayer insulating layer 376 (see [reference]) is planarized. FIG. 3D The arrow ① in the image is exposed.

[0062] As a result of this process, a metal thin film layer 362A, a metal layer 364A, a first interlayer insulating layer 372A, a second interlayer insulating layer 374A, a third interlayer insulating layer 376A, and a through electrode 350A having a conductive pillar 352A and a spacer 354A can be formed. The metal thin film layer 362A, the metal layer 364A, the first interlayer insulating layer 372A, the second interlayer insulating layer 374A, the third interlayer insulating layer 376A, and the through electrode 350A can form a flat surface. The shape and function of the metal thin film layer 362A, the metal layer 364A, the first interlayer insulating layer 372A, the second interlayer insulating layer 374A, the third interlayer insulating layer 376A, and the through electrode 350A will be described in more detail below.

[0063] The through electrode 350A having conductive pillar 352A and spacer 354A can substantially correspond to FIG. 1B The through electrode 150. The conductive post 352A can be used as a path for signal transmission / power supply. The spacer 354A can surround the sidewall of the conductive post 352A to electrically insulate the body portion 310A and the conductive post 352A and / or prevent metal diffusion from the conductive post 352A to the body portion 310A.

[0064] Metal thin film layer 362A and metal layer 364A can correspond to FIG. 1BThe power supply pattern 160. Therefore, the metal thin film layer 362A and the metal layer 364A will be referred to as power supply pattern 360. The metal thin film layer 362A may be along the above-mentioned opening (see... FIG. 3C The side and bottom surfaces of the OP (intercalation layer 364A) are formed, and a metal-containing layer 364A can be provided to fill the opening where the metal-containing thin film layer 362A is formed. Therefore, the side and bottom surfaces of the metal-containing layer 364A can be surrounded by the metal-containing thin film layer 362A. As described above, the metal-containing thin film layer 362A can be used to improve the properties and / or formation process of the metal-containing layer 364A. As an example, although not shown, the metal-containing thin film layer 362A can have a multilayer structure having a barrier layer and a seed layer disposed above the barrier layer. The barrier layer can include a metal or metal compound such as titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel vanadium (NiV), etc., and the seed layer can include a metal such as copper (Cu). In this case, the barrier layer can prevent metal diffusion between the power patterns 360 that can occur through the second interlayer insulating layer 374A, and the seed layer can be used as a seed during electroplating for forming the metal-containing layer 364A.

[0065] The second interlayer insulation layer 374A and the third interlayer insulation layer 376A can essentially correspond to FIG. 1B Interlayer insulation layer 170. First interlayer insulation layer 372A is not shown. FIG. 1B In, but can be added FIG. 1B The semiconductor chip. A first interlayer insulating layer 372A is formed along the rear surface 312A of the main body portion 310A and the side surface of the protrusion of the through electrode 350A. The first interlayer insulating layer 372A serves to prevent metal diffusion between the protrusions of the through electrode 350A or to prevent contamination by external metals. A second interlayer insulating layer 374A and a third interlayer insulating layer 376A are used to insulate the power pattern 360 from each other and to provide space for the power pattern 360 to be formed. In addition, the third interlayer insulating layer 376A serves to prevent metal diffusion between the power patterns 360 that can occur through the second interlayer insulating layer 374A.

[0066] Reference FIG. 3F , can FIG. 3E A rear insulating layer 390 is formed above the resulting structure, and the rear insulating layer 390 has an opening 392 providing space for the formation of the rear connection electrode. Although not shown, it can be achieved by... FIG. 3E An insulating material layer is deposited over the resulting structure, and the insulating material layer in the area where the back connection electrode is to be formed is removed by a masking and etching process to form a back insulating layer 390. The back insulating layer 390 may include an insulating material such as silicon oxide.

[0067] Subsequently, the back connection electrode 380 filling the opening 392 can be formed. The back connection electrode 380 can include a metal-containing thin film layer 382 formed along the side surface and the lower surface of the opening 392 and a metal-containing layer 384 filling the opening 392 in which the metal-containing thin film layer 382 is formed. Although not shown, the back connection electrode 380 can be formed by depositing a thin metal material layer for forming the metal-containing thin film layer 382 along the upper surface of the back insulating layer 390 and the side surface and the lower surface of the opening 392, depositing another metal material layer having a thickness sufficient to fill the opening 392 over the thin metal material layer by deposition or plating, and performing a planarization process until the upper surface of the back insulating layer 390 is exposed.

[0068] Accordingly, a semiconductor chip substantially the same as FIG. 1B the semiconductor chip 100 can be manufactured.

[0069] Further, in the embodiment of FIGS. 3A-3F the power supply pattern 360 and the back connection electrode 380 can be formed by patterning the insulating layer to form spaces in which the power supply pattern 360 and the back connection electrode 380 are to be formed, and then filling the spaces with a conductive material forming the power supply pattern 360 and the back connection electrode 380. However, the present disclosure is not limited thereto, and a method of forming a power supply pattern and / or a back connection electrode by patterning a conductive layer and then filling spaces between the patterned conductive layers with an insulating material can be used. This will be exemplarily described below with reference to FIGS. 4A-4D .

[0070] FIGS. 4A-4D is a cross-sectional view illustrating a method of manufacturing a semiconductor chip according to another embodiment of the present disclosure. A description will be focused on the differences from FIG. 3A and FIG. 3B .

[0071] Referring to FIG. 4A , a structure having a main body portion 410 having a front surface 411 and a back surface 412, an initial through electrode 450 penetrating the main body portion 410 and protruding above the back surface 412 of the main body portion 410, a wiring portion 420 formed below the front surface 411 of the main body portion 410, and a front connection electrode 430 and a front insulating layer 440 formed below the wiring portion 420 can be formed over a carrier substrate (not shown). The initial through electrode 450 can include an initial conductive pillar 452 and an initial spacer 454 surrounding the side surface and the upper surface of the initial conductive pillar 452.

[0072] Subsequently, a power supply pattern 460 in which a metal-containing thin film layer 462 and a metal-containing layer 464 are stacked can be formed over the back surface 412 of the body portion 410. Although not shown, the power supply pattern 460 can be formed by depositing a material layer for forming the metal-containing thin film layer 462 and the metal-containing layer 464 over the back surface 412 of the body portion 410, and patterning the material layer using a mask and an etching process. Alternatively, although not shown, the power supply pattern 460 can be formed by depositing a material layer for forming the metal-containing thin film layer 462 over the back surface 412 of the body portion 410, forming a photoresist pattern that provides spaces in which the metal-containing layer 464 is to be formed, forming the metal-containing layer 464 in the spaces provided by the photoresist pattern by electroplating, removing the photoresist pattern, and removing the material layer exposed by the metal-containing layer 464. In this case, unlike the power supply pattern (see 360 in FIG. 3E

[0073] Referring to FIG. 4B A first initial interlayer insulating layer 472 can be formed over the power supply pattern 460, the back surface 412 of the body portion 410, and the protrusions of the initial through electrode 450 along the lower profile thereof. As an example, the first initial interlayer insulating layer 472 can include silicon nitride.

[0074] Subsequently, a second initial interlayer insulating layer 474 can be formed over the first initial interlayer insulating layer 472 to a thickness sufficient to cover the power supply pattern 460 and the protrusions of the initial through electrode 450. As an example, the second initial interlayer insulating layer 474 can include silicon oxide.

[0075] Referring to FIG. 4C A planarization process can be performed on the resulting structure of FIG. 4B The planarization process can be performed until the upper surface of the power supply pattern 460 is exposed.

[0076] As a result, a first interlayer insulating layer 472A and a second interlayer insulating layer 474A that fill the spaces between the power supply patterns 460, and a through electrode 450A having a conductive pillar 452A and a spacer 454A can be formed. The first interlayer insulating layer 472A can be formed along the back surface 412 of the body portion 410, the side surfaces of the power supply patterns 460, and the side surfaces of the protrusions of the through electrode 450A. The first interlayer insulating layer 472A can function to prevent metal diffusion between the protrusions of the through electrode 450A and the power supply patterns 460.

[0077] Referring to FIG. 4D A planarization process can be performed on the resulting structure of FIG. 4C ​A back connection electrode 480 is formed over the resultant structure of the semiconductor chip 100. The back connection electrode 480 can include a laminated structure of a metal-containing thin film layer 482 and a metal-containing layer 484. Although not shown, the back connection electrode 480 can be formed by depositing a material layer for forming the metal-containing thin film layer 482 and the metal-containing layer 484 over the resultant structure of the semiconductor chip 100, and patterning the material layer by a mask and etching process. Alternatively, although not shown, the back connection electrode 480 can be formed by depositing a material layer for forming the metal-containing thin film layer 482 over the resultant structure of the semiconductor chip 100, forming a photoresist pattern which provides a space where the metal-containing layer 484 is to be formed, forming the metal-containing layer 484 in the space provided by the photoresist pattern by electroplating, removing the photoresist pattern, and removing the material layer exposed by the metal-containing layer 484. In this case, unlike the back connection electrode (see 380 in FIG. 3) of the above-described embodiment, the metal-containing thin film layer 482 can contact only a lower surface of the metal-containing layer 484. FIG. 4C FIG. 4C FIG. 3F

[0078] Subsequently, a back insulating layer 490 can be formed to fill spaces between the back connection electrodes 480. Although not shown, the back insulating layer 490 can be formed by depositing an insulating material layer having a thickness sufficient to cover the back connection electrodes 480 over the resultant structure of the semiconductor chip 100, and performing a planarization process until the upper surfaces of the back connection electrodes 480 are exposed. FIG. 4C

[0079] Thus, a semiconductor chip substantially identical to the semiconductor chip 100 of FIG. 1B can be manufactured.

[0080] FIG. 5A and FIG. 5B is a diagram illustrating a semiconductor chip according to another embodiment of the present disclosure. FIG. 5A is a plan view of the semiconductor chip of the present embodiment when viewed from above, FIG. 5B is a cross-sectional view taken along the line B-B' of FIG. 5A In FIG. 5A , for convenience of description, through electrodes, connection patterns, and power supply patterns disposed below the back connection electrodes are shown in dotted lines together with the back connection electrodes disposed at the uppermost portion of the semiconductor chip. Focus will be placed on differences from the above-described FIG. 1A and FIG. 1B embodiments.

[0081] Referring to FIG. 5A and FIG. 5B ​​​​The semiconductor chip 500 of the present embodiment can include a main body portion 510, a wiring portion 520, a front connection electrode 530, a front insulating layer 540, a through electrode 550, a power supply pattern 560, a connection pattern 565, an interlayer insulating layer 570, a rear connection electrode 580, and a rear insulating layer 590.

[0082] The main body portion 510 can have a front surface 511 and a rear surface 512. The wiring portion 520 can be formed below the front surface 511 of the main body portion 510. The front connection electrode 530 and the front insulating layer 540 can be formed below the wiring portion 520.

[0083] The through electrode 550 can have a columnar shape extending from the front surface 511 to the rear surface 512 of the main body portion 510 to penetrate the main body portion 510. One end of the through electrode 550 can be connected to the wiring portion 520, and the other end of the through electrode 550 can be connected to the connection pattern 565. In a plan view, the width of each through electrode 550 is indicated by reference numeral W1. The through electrode 550 can include a first through electrode 550A electrically connected to the power supply pattern 560 and a second through electrode 550B not electrically connected to the power supply pattern 560.

[0084] The power supply pattern 560 can be formed above the rear surface 512 of the main body portion 510 to be spaced apart from the through electrode 550 in a horizontal direction. The power supply pattern 560 can be electrically connected to the first through electrode 550A by a first rear connection electrode 580A and can be electrically insulated from the second through electrode 550B.

[0085] The connection pattern 565 can be formed at the same height as the power supply pattern 560 in a vertical direction. That is, the connection pattern 565 can be formed above the rear surface 512 of the main body portion 510. The connection pattern 565 can be formed to overlap and connect with each through electrode 550. The connection pattern 565 and the through electrode 550 can correspond to each other one-to-one. The connection pattern 565 can include a first connection pattern 565A connected to the first through electrode 550A and a second connection pattern 565B connected to the second through electrode 550B.

[0086] The width W3 of the connection pattern 565 can be greater than the width W1 of the through electrode 550 and can be less than the width W2 of the back connection electrode 580. In the present embodiment, the first connection pattern 565A can be spaced apart from the power supply pattern 560 adjacent thereto by a predetermined minimum distance D3, but the present disclosure is not limited thereto, and the side surface of the first connection pattern 565A and the side surface of the power supply pattern 560 adjacent thereto can be in contact with each other. On the other hand, the second connection pattern 565B can be spaced apart from the power supply pattern 560 adjacent thereto. That is, the side surface of the second connection pattern 565B and the side surface of the power supply pattern 560 adjacent thereto can not be in contact. The connection pattern 565 can be formed of the same metal or metal compound as the power supply pattern 560.

[0087] The interlayer insulating layer 570 can be formed over the back surface 512 of the body portion 510 to fill the space between the power supply pattern 560 and the connection pattern 565.

[0088] The back connection electrode 580 can include a first back connection electrode 580A connected to the first connection pattern 565A, a second back connection electrode 580B connected to the second connection pattern 565B, and a third back connection electrode 580C not connected to the connection pattern 565.

[0089] The first back connection electrode 580A can be formed to overlap and be connected to each of the first connection patterns 565A. Accordingly, the first through electrode 550A can be electrically connected to the first back connection electrode 580A through the first connection pattern 565A. Further, the first back connection electrode 580A can overlap and be connected to a portion of the first connection pattern 565A and the power supply pattern 560 adjacent thereto at the same time. To this end, the value of the width W2 of the first back connection electrode 580A can be greater than the sum of the width W3 of the first connection pattern 565A and the minimum distance D3 between the first connection pattern 565A and the power supply pattern 560 adjacent thereto. As a result, the first back connection electrode 580A can electrically connect the first connection pattern 565A to the power supply pattern 560.

[0090] The second back connection electrode 580B can be formed to overlap and be connected to each of the second connection patterns 565B. Accordingly, the second through electrode 550B can be electrically connected to the second back connection electrode 580B through the second connection pattern 565B. The second back connection electrode 580B can be electrically insulated from the power supply pattern 560 by not overlapping / being connected to the power supply pattern 560 around the second connection pattern 565B.

[0091] The third back connection electrode 580C can be formed to be spaced apart from the first back connection electrode 580A and the second back connection electrode 580B without overlapping or being connected to the connection pattern 565. That is, the third back connection electrode 580C can be a dummy not used for signal transmission or power supply.

[0092] The back insulating layer 590 can be formed over a flat surface formed based on one surface of the connection pattern 565, one surface of the power supply pattern 560, and one surface of the interlayer insulating layer 570, to fill spaces between the back connection electrodes 580.

[0093] Even with the semiconductor chip 500 described above, the effects of the semiconductor chip (see FIG. 1A and FIG. 1B 100) of the above-described embodiments can be obtained. That is, since the first back connection electrode 580A is connected to the corresponding first connection pattern 565A and the power supply pattern 560 adjacent thereto at the same time, power supply through these elements can be easily and stably performed.

[0094] In addition, when a plurality of semiconductor chips 500 are stacked in the vertical direction, a hybrid bonding structure for firmly bonding the semiconductor chips 500 adjacent in the vertical direction can be provided. That is, since the power supply pattern 560 and the connection pattern 565 are disposed under the back connection electrode 580, in a case where the back connection electrode 580 and the back insulating layer 590 are bonded to the front connection electrode and the front insulating layer of another semiconductor chip (not shown), respectively, the power supply pattern 560 and the connection pattern 565 do not adversely affect the bonding.

[0095] FIGS. 6A-6D is a cross-sectional view illustrating a manufacturing method of a semiconductor chip according to another embodiment of the disclosure.

[0096] Referring to FIG. 6A , a structure having a body portion 610 having a front surface 611 and a back surface 612, a wiring portion 620 formed under the front surface 611 of the body portion 610, a front connection electrode 630 and a front insulating layer 640 formed under the wiring portion 620, and an initial through electrode 650 penetrating the body portion 610 and protruding above the back surface 612 of the body portion 610 while being connected to the wiring portion 620 can be formed over a carrier substrate (not shown). The initial through electrode 650 can include an initial conductive pillar 652 and an initial spacer 654.

[0097] Subsequently, an initial first interlayer insulating layer 672 can be formed over the back surface 612 of the body portion 610 and the protrusion of the initial through electrode 650 along the lower profile thereof. As an example, the initial first interlayer insulating layer 672 can include silicon nitride.

[0098] Referring to FIG. 6B , by performing a planarization process so that an upper surface of the initial first interlayer insulating layer 672 present above the back surface 612 of the initial body portion 610 is exposed, a through electrode 650A having a conductive pillar 652A and a spacer 654A and a first interlayer insulating layer 672A can be formed.

[0099] As a result of this process, the through electrode 650A can have a columnar shape that penetrates the body portion 610 and the first interlayer insulating layer 672A. The upper surface of the first interlayer insulating layer 672A and one surface of the through electrode 650A can form a flat surface.

[0100] Subsequently, a laminated structure of a second interlayer insulating layer 674 and a third interlayer insulating layer 676 having openings OP that provide spaces in which a power supply pattern and a connection pattern are to be formed can be formed over the first interlayer insulating layer 672A. As an example, the second interlayer insulating layer 674 and the third interlayer insulating layer 676 can include silicon oxide and silicon nitride, respectively.

[0101] Referring to FIG. 6C A power supply pattern 660 and a connection pattern 665 can be formed filled in the openings of the second interlayer insulating layer 674 and the third interlayer insulating layer 676. The power supply pattern 660 can include a metal-containing thin film layer 662 and a metal-containing layer 664, and the metal-containing thin film layer 662 can surround the side surface and the lower surface of the metal-containing layer 664. The connection pattern 665 can include a metal-containing thin film layer 666 and a metal-containing layer 668, and the metal-containing thin film layer 666 can surround the side surface and the lower surface of the metal-containing layer 668.

[0102] Referring to FIG. 6D A back insulating layer 690 having openings that provide spaces for forming a back connection electrode 680 and the back connection electrode 680 formed in the openings of the back insulating layer 690 can be formed over the resulting structure of FIG. 6C The back connection electrode 680 can include a metal-containing thin film layer 682 and a metal-containing layer 684, and the metal-containing thin film layer 682 can surround the side surface and the lower surface of the metal-containing layer 684.

[0103] Thus, a semiconductor chip substantially identical to the semiconductor chip 100 of FIG. 5B can be manufactured.

[0104] FIGS. 7A-7C is a cross-sectional view illustrating a manufacturing method of a semiconductor chip according to another exemplary embodiment of the present disclosure.

[0105] Referring to FIG. 7AA structure can be formed over a carrier substrate (not shown) having a main body portion 710 having a front surface 711 and a back surface 712, a wiring portion 720 formed under the front surface 711 of the main body portion 710, a front connection electrode 730 and a front insulating layer 740 formed under the wiring portion 720, a first interlayer insulating layer 772 formed over the back surface 712 of the main body portion 710, and a through electrode 750 penetrating the main body portion 710 and the first interlayer insulating layer 772. The through electrode 750 can include a conductive pillar 752 and a spacer 754.

[0106] Subsequently, a power pattern 760 in which a metal-containing thin film layer 762 and a metal-containing layer 764 are stacked and a connection pattern 765 in which a metal-containing thin film layer 766 and a metal-containing layer 768 are stacked can be formed over the back surface 712 of the main body portion 710.

[0107] Referring to FIG. 7B A second interlayer insulating layer 774 and a third interlayer insulating layer 776 can be formed to fill spaces between the power pattern 760 and the connection pattern 765. The second interlayer insulating layer 774 can include, for example, silicon nitride, and can be formed along side surfaces of the power pattern 760, side surfaces of the connection pattern 765, and an upper surface of the first interlayer insulating layer 772. The third interlayer insulating layer 776 can include, for example, silicon oxide, and can have side surfaces and a lower surface surrounded by the second interlayer insulating layer 774.

[0108] Referring to FIG. 7C A back connection electrode 780 can be formed over the resulting structure of FIG. 7B The back connection electrode 780 can include a stacked structure of a metal-containing thin film layer 782 and a metal-containing layer 784.

[0109] Subsequently, a back insulating layer 790 filling spaces between the back connection electrodes 780 can be formed.

[0110] Accordingly, a semiconductor chip substantially the same as the semiconductor chip 500 of FIG. 5B can be manufactured.

[0111] According to the above-described embodiments of the present disclosure, a semiconductor chip capable of improving operational characteristics and facilitating a manufacturing process and a semiconductor package including the same can be provided.

[0112] FIG. 8A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to embodiments is shown. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 can include at least one of the semiconductor packages according to the described embodiments.

[0113] The memory 7810 can include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 can control the memory 7810 so that stored data is read out or data is stored in response to a read / write request from a host 7830.

[0114] FIG. 9 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 can include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 can be coupled to each other through a bus 8715 that provides a path for data movement.

[0115] In embodiments, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 can include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 can include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 can store data and / or commands to be executed by the controller 8711, etc.

[0116] The memory 8713 can include a volatile memory device such as a DRAM and / or a nonvolatile memory device such as a flash memory. For example, a flash memory can be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory can constitute a solid state disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

[0117] The electronic system 8710 can further include an interface 8714 configured to transmit and receive data to and from a communication network. The interface 8714 can be of a wired or wireless type. For example, the interface 8714 can include an antenna or a wired or wireless transceiver.

[0118] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system can be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0119] If the electronic system 8710 represents a device capable of performing wireless communication, the electronic system 8710 can be used in a communication system using a technology of CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0120] Although various embodiments are described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined in the following claims.

[0121] Cross Reference to Related Applications

[0122] This application claims priority to Korean Patent Application No. 10-2020-0186907, filed December 30, 2020, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor chip, the semiconductor chip comprising: The main body portion has a front surface and a rear surface, and the main body portion is oriented such that the rear surface is above the front surface; A first through electrode and a second through electrode penetrate the main body portion and have protrusions extending above the rear surface of the main body portion; A power pattern is formed above the rear surface of the body portion and spaced apart from the protrusion; An interlayer insulating layer that fills the space between the power pattern and the protrusion; as well as A first rear connection electrode and a second rear connection electrode are formed above the interlayer insulating layer and are respectively connected to the first through electrode and the second through electrode. Wherein, the first post-connection electrode is simultaneously connected to both the first through-electrode and a portion of the power pattern adjacent to the first through-electrode. The second rear connection electrode is not connected to the power supply pattern.

2. The semiconductor chip according to claim 1, wherein, The width of the first connecting electrode is greater than the sum of the width of the first through electrode and the minimum distance between the first through electrode and the power pattern adjacent to the first through electrode.

3. The semiconductor chip according to claim 1, wherein, The width of the second connecting electrode is less than the sum of the width of the second through electrode and the minimum distance between the second through electrode and the power pattern adjacent to the second through electrode.

4. The semiconductor chip according to claim 1, further comprising: A third post-connection electrode is formed above the interlayer insulating layer and is not connected to the first through electrode and the second through electrode.

5. The semiconductor chip according to claim 1, further comprising: A rear insulating layer is formed above the interlayer insulating layer and the power pattern, and the rear insulating layer fills the space between the first rear connection electrode and the second rear connection electrode.

6. The semiconductor chip according to claim 1, further comprising: A wiring portion formed below the front surface of the main body portion; A plurality of front connection electrodes are formed below the wiring portion and are respectively connected to the first through electrode and the second through electrode through the wiring portion; as well as A front insulating layer is formed below the wiring portion, and the front insulating layer fills the space between the plurality of front connection electrodes.

7. The semiconductor chip according to claim 1, wherein, The power pattern includes a metal layer and a metal thin film layer surrounding the side and bottom surfaces of the metal layer.

8. The semiconductor chip according to claim 1, wherein, The power pattern includes a metal thin film layer and a metal layer formed on top of the metal thin film layer.

9. The semiconductor chip according to claim 1, wherein, Each of the first and second rear connection electrodes includes a metal-containing layer and a metal-containing thin film layer surrounding the side and lower surfaces of the metal-containing layer.

10. The semiconductor chip according to claim 1, wherein, Each of the first and second rear connection electrodes includes a metal-containing thin film layer and a metal-containing layer formed above the metal-containing thin film layer.

11. The semiconductor chip according to claim 1, wherein, The interlayer insulating layer includes a silicon oxide layer and a silicon nitride layer formed on top of the silicon oxide layer.

12. The semiconductor chip according to claim 1, further comprising: A silicon nitride layer is disposed below the interlayer insulating layer and the power pattern, and is formed along the rear surface of the body portion and the side surface of the protrusion.

13. The semiconductor chip according to claim 1, wherein, The interlayer insulating layer includes a silicon nitride layer formed along the side surface of the power pattern, the side surface of the protrusion, and the rear surface of the body portion, and the interlayer insulating layer includes a silicon oxide layer having a side surface and a lower surface surrounded by the silicon nitride layer.

14. The semiconductor chip according to claim 1, wherein, The first post-connection electrode is in direct contact with the first through electrode and the power pattern.

15. The semiconductor chip according to claim 1, wherein, The power pattern includes multiple line patterns and extended patterns connecting the multiple line patterns to each other, and The plurality of line patterns are arranged alternately with the interlayer insulation layer.

16. A semiconductor package comprising: A first semiconductor chip includes a body portion having a front surface and a rear surface; a first through electrode and a second through electrode penetrating the body portion and having protrusions extending above the rear surface of the body portion; a power pattern formed above the rear surface of the body portion and spaced apart from the protrusions; an interlayer insulating layer filling the space between the power pattern and the protrusions; a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and respectively connected to the first through electrode and the second through electrode; and a rear insulating layer formed above the interlayer insulating layer and the power pattern and filling the space between the first rear connection electrode and the second rear connection electrode. The body portion is oriented such that the rear surface is above the front surface, wherein the first rear connection electrode is simultaneously connected to the first through electrode and a portion of the power pattern adjacent to the first through electrode. A second semiconductor chip includes a plurality of front connecting electrodes that are directly bonded to the first and second rear connecting electrodes, and a front insulating layer that is directly bonded to the rear insulating layer while filling the space between the plurality of front connecting electrodes. The second rear connection electrode is not connected to the power supply pattern.

17. The semiconductor package of claim 16, wherein, Power is supplied to the first semiconductor chip and the second semiconductor chip through the first through electrode, the power pattern, the first rear connection electrode, and the front connection electrode connected to the first rear connection electrode. The signal is transmitted to the first semiconductor chip and the second semiconductor chip through the second through electrode, the second rear connection electrode and the front connection electrode connected to the second rear connection electrode.

18. The semiconductor package of claim 16, wherein, The power supplied to the first semiconductor chip and the second semiconductor chip through the first through electrode, the power pattern, the first rear connection electrode, and the front connection electrode connected to the first rear connection electrode is different from the power supplied to the first semiconductor chip and the second semiconductor chip through the second through electrode, the second rear connection electrode, and the front connection electrode connected to the second rear connection electrode.

19. The semiconductor package of claim 16, wherein, The first rear connection electrode, the second rear connection electrode, and the front connection electrode are formed of the same material, and The rear insulating layer and the front insulating layer are formed of the same material.

20. A semiconductor chip, the semiconductor chip comprising: The main body portion has a front surface and a rear surface, and the main body portion is oriented such that the rear surface is above the front surface; A first through electrode and a second through electrode, the first through electrode and the second through electrode penetrating the main body portion; A power pattern is formed above the rear surface of the main body portion and spaced apart from the first through electrode and the second through electrode. A first connecting pattern and a second connecting pattern are formed above the rear surface of the main body portion and are respectively connected to the first through electrode and the second through electrode. An interlayer insulating layer that fills the space between the power supply pattern and the first connection pattern and the second connection pattern; as well as A first rear connection electrode and a second rear connection electrode are formed above the interlayer insulating layer and are respectively connected to the first connection pattern and the second connection pattern. Wherein, the first rear connection electrode is simultaneously connected to a portion of both the first connection pattern and the power supply pattern adjacent to the first connection pattern. The second connection pattern is spaced apart from the power supply pattern.

21. The semiconductor chip according to claim 20, wherein, The width of each of the first connection pattern and the second connection pattern is greater than the width of each of the first through electrode and the second through electrode, and Wherein, the width of each of the first connection pattern and the second connection pattern is smaller than the width of each of the first rear connection electrode and the second rear connection electrode.

22. The semiconductor chip according to claim 20, wherein, The width of the first rear connection electrode is greater than the sum of the width of the first connection pattern and the minimum distance between the first connection pattern and the power supply pattern adjacent to the first connection pattern.

23. The semiconductor chip according to claim 20, further comprising: A third post-connection electrode is formed above the interlayer insulating layer and is not connected to the first connection pattern or the second connection pattern.

24. The semiconductor chip according to claim 20, further comprising: A rear insulating layer is formed above the interlayer insulating layer and the power pattern, and the rear insulating layer fills the space between the first rear connection electrode and the second rear connection electrode.

25. The semiconductor chip according to claim 20, further comprising: A wiring portion formed below the front surface of the main body portion; A plurality of front connection electrodes are formed below the wiring portion and are respectively connected to the first through electrode and the second through electrode through the wiring portion; as well as A front insulating layer is formed below the wiring portion, and the front insulating layer fills the space between the plurality of front connection electrodes.

26. The semiconductor chip according to claim 20, wherein, Each of the power supply pattern and the first connection pattern and the second connection pattern includes a metal-containing layer and a metal-containing thin film layer surrounding the side and bottom surfaces of the metal-containing layer.

27. The semiconductor chip according to claim 20, wherein, Each of the power supply pattern and the first connection pattern and the second connection pattern includes a metal-containing thin film layer and a metal-containing layer formed on top of the metal-containing thin film layer.

28. The semiconductor chip according to claim 20, wherein, Each of the first and second rear connection electrodes includes a metal-containing layer and a metal-containing thin film layer surrounding the side and lower surfaces of the metal-containing layer.

29. The semiconductor chip according to claim 20, wherein, Each of the first and second rear connection electrodes includes a metal-containing thin film layer and a metal-containing layer formed above the metal-containing thin film layer.

30. The semiconductor chip according to claim 20, wherein, The interlayer insulating layer includes a silicon oxide layer and a silicon nitride layer formed on top of the silicon oxide layer.

31. The semiconductor chip according to claim 20, further comprising: A silicon nitride layer is disposed below the interlayer insulating layer, the power supply pattern, and the first and second connection patterns, and is formed above the rear surface of the main body portion. The first through electrode and the second through electrode further penetrate the silicon nitride layer.

32. The semiconductor chip according to claim 20, wherein, The interlayer insulating layer includes a silicon nitride layer formed along the side surfaces of the power pattern, the side surfaces of the first connection pattern and the second connection pattern, and the rear surface of the body portion, and the interlayer insulating layer includes a silicon oxide layer having a side surface and a lower surface surrounded by the silicon nitride layer.

33. The semiconductor chip according to claim 20, wherein, The first rear connection electrode is in direct contact with the first connection pattern and the power supply pattern.

34. The semiconductor chip according to claim 20, wherein, The power pattern includes multiple line patterns and extended patterns connecting the multiple line patterns to each other, and The plurality of line patterns are arranged alternately with the interlayer insulation layer.

35. A semiconductor package comprising: A first semiconductor chip includes a body portion having a front surface and a rear surface; a first through electrode and a second through electrode penetrating the body portion; a power pattern formed above the rear surface of the body portion and spaced apart from the first through electrode and the second through electrode; a first connection pattern and a second connection pattern formed above the rear surface of the body portion and respectively connected to the first through electrode and the second through electrode; an interlayer insulating layer filling the space between the power pattern and the first connection pattern and the second connection pattern; a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and respectively connected to the first connection pattern and the second connection pattern; and a rear insulating layer formed above the interlayer insulating layer and the power pattern and filling the space between the first rear connection electrode and the second rear connection electrode. The body portion is oriented such that the rear surface is above the front surface, wherein the first rear connection electrode is simultaneously connected to the first through electrode and a portion of the power pattern adjacent to the first through electrode. A second semiconductor chip includes a plurality of front connecting electrodes that are directly bonded to the first and second rear connecting electrodes, and a front insulating layer that is directly bonded to the rear insulating layer while filling the space between the plurality of front connecting electrodes. The second rear connection electrode is not connected to the power supply pattern.

36. The semiconductor package of claim 35, wherein, Power is supplied to the first semiconductor chip and the second semiconductor chip through the first through electrode, the first connection pattern, the power pattern, the first rear connection electrode, and the front connection electrode connected to the first rear connection electrode. The signal is transmitted to the first semiconductor chip and the second semiconductor chip through the second through electrode, the second connection pattern, the second rear connection electrode and the front connection electrode connected to the second rear connection electrode.

37. The semiconductor package of claim 35, wherein, The power supplied to the first semiconductor chip and the second semiconductor chip through the first through electrode, the first connection pattern, the power pattern, the first rear connection electrode, and the front connection electrode connected to the first rear connection electrode is different from the power supplied to the first semiconductor chip and the second semiconductor chip through the second through electrode, the second connection pattern, the second rear connection electrode, and the front connection electrode connected to the second rear connection electrode.

38. The semiconductor package of claim 35, wherein, The first rear connection electrode, the second rear connection electrode, and the front connection electrode are formed of the same material, and The rear insulating layer and the front insulating layer are formed of the same material.

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