Self-latching sensing timing in one-time programmable memory architecture

Abstract

The present invention relates to a self-latching sensing sequence in a single-time programmable memory architecture. A programmable memory (19) includes a self-latching read data path. A sense amplifier (28) senses a voltage level at a bit line that conveys the data state of a selected memory cell (32) in its associated column. A data latch (30) coupled to the output of the sense amplifier (28) transmits the sensed data state. Set-reset logic (34) is provided in the read data path that receives the output of the data latch (30), and the set-reset logic (34) latches the data latch (30) and isolates it from the sense amplifier (28) in response to a transition of the data state in a read cycle. The set-reset logic (34) resets the data latch (30) at the beginning of the next read cycle. In some embodiments, a timer (27) is provided so that the latch (30) is reset after a timeout period in a longer read cycle in which no data transition occurs.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the application date of December 16, 2016, application number "201611168426.3", and invention name "Self-latching sensing timing in a one-time programmable memory architecture".

[0003] Cross-reference to related applications

[0004] This application claims priority under 35 USC §119(e) to Provisional Application No. 62 / 269,737, filed December 18, 2015, which is incorporated herein by reference.

[0005] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0006] not applicable. Technical Field

[0007] The present invention relates to the field of solid-state memory. More particularly, embodiments of the present invention relate to sensing the state of data stored in a one-time programmable non-volatile memory. Background Art

[0008] Non-volatile solid-state read / write memory devices are common in many modern electronic systems, particularly portable electronic devices and systems. A common type of non-volatile solid-state memory device includes a memory device known as an electrically programmable read-only memory (EPROM) device. Modern EPROM memory cells include one or more "floating gate" transistors that store data states. In a general sense, these floating gate transistors are "programmed" by applying a bias voltage that causes holes or electrons to tunnel or be injected through a relatively thin dielectric film onto an electrically isolated transistor gate element that serves as the transistor's floating gate. This charge trapped on the floating gate modulates the apparent threshold voltage of the memory cell transistor compared to the threshold voltage without charge trapped on the floating gate. This difference in threshold voltage can be detected by sensing the resulting difference in source-drain conduction between the programmed and unprogrammed states under normal transistor bias conditions. Some EPROM devices are "erasable," in that trapped charge can be removed from the floating gate, for example, by exposing the memory cell to ultraviolet light (such memories are referred to as "UV EPROM") or by applying specific electrical bias conditions that cause tunneling of charge from the floating gate (such memories are referred to as electrically erasable or electrically alterable, i.e., EEPROM or EAPROM, respectively). "Flash" memory devices are typically implemented by EEPROM memory arrays, in which an erase operation is applied to a "block" of memory cells simultaneously.

[0009] Because of the convenience and efficiency of modern EPROM and EEPROM functionality, nonvolatile memory arrays are now commonly embedded within larger integrated circuits, such as modern complex microprocessors, digital signal processors, and other large logic circuits. This type of embedded nonvolatile memory can be used as nonvolatile program memory for software routines that can be executed by the processor, and can also be used as a nonvolatile data storage device. On a smaller scale, nonvolatile memory cells can implement control registers that can be used to configure larger logic circuits, or they can be used to "trim" analog levels after electrical measurements.

[0010] As is known in the art, "single-time programmable" ("OTP") memory is also popular, particularly in embedded non-volatile memory applications such as those described above. The memory cells of OTP memory are constructed similarly or identically to UV EPROM cells and, therefore, are not electrically erasable. However, when mounted in an opaque package without a window through which the memory can be exposed to UV light, UV EPROM cells can be programmed once, and only once. In embedded applications, OTP memory can be used to store program code to be executed by an embedded microcontroller or microprocessor.

[0011] In any type of solid-state semiconductor memory, the data path timing of read operations is critical to the performance of the memory device. As is fundamental to the art, memory cells in conventional OTP and other solid-state memories are typically accessed by selecting a row of cells in the array according to a row address, coupling the storage devices in each of those cells to corresponding bit lines to establish a voltage or current on each bit line based on the data state stored in its corresponding cell. Sense amplifiers sense the state of the bit lines to determine the data state of the accessed cell, and then latch these sensed data states and transmit them along the memory's output data path. Accurate sensing of the stored memory cell state must be maintained under varying voltage and temperature conditions, variations in manufacturing parameters, and in the presence of system noise. As is known in the art, the noise margin of the read operation, which depends on the timing accuracy in the read circuitry, largely determines the minimum memory cell size required to provide the necessary read current, and therefore the memory density in bits per cell "chip" area.

[0012] This accuracy of the sensing circuitry is largely due to the timing with which the sense amplifiers operate to amplify and latch the data states represented by the bit line signals. In each cycle, time must be allowed for the accessed cells to develop voltages or currents on those bit lines before the bit line levels are amplified and latched as the data states read from the accessed memory cells. On the one hand, if data is latched too early in the cycle, the data read before the bit line signals have fully developed is susceptible to errors from noise. On the other hand, latching data later than required for reliable sensing will excessively extend the read cycle time and, therefore, limit the performance of the device.

[0013] It has been observed that optimizing the data path timing of a read cycle can be quite difficult in modern memory architectures. One conventional technique for setting the read path timing is to generate the sense amplifier enable signal from the row enable control signal that gates the word line driver, but employing a delay element (e.g., a chain of logic inverters) to establish the desired delay time after the selected word line is driven and before the sense amplifier is enabled or the sensed data is latched. However, it has been observed that the construction, and therefore the electrical characteristics, of the memory cell transistors often differ from the construction and electrical characteristics of the logic transistors that comprise the delay elements. Significant device mismatch, along with local variations in the device behavior of these minimum-sized cell transistors, can necessitate building additional design margin (i.e., an extended delay between the word line drive and the sense amplifier enable signal) into the timing circuit. This additional margin adversely impacts the read cycle time.

[0014] Another conventional method for determining sense amplifier timing in modern solid-state memories uses a "tracking" circuit based on replica or "dummy" memory cells constructed using the same transistor size as the cell transistors. This method is particularly common in those memory technologies where the replica cells can closely match the cell transistors in the main array, such as static random access memory (SRAM). Arslan et al., "Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines," Custom Integrated Circuits Conference (IEEE, 2008), pp. 415-418, describes the incorporation of replica columns of memory cells implemented in or adjacent to a main memory array, where the replica bit lines are discharged by a configurable number of dummy memory cells, with the columns driving the sense amplifier enable signal. Amrutur et al., “A Replica Technique for Wordline and Sense Control in Low-Power SRAMs,” J. Solid State Circuits, Vol. 33, No. 8 (IEEE, 1998), pp. 1208-1219, describes a row of replica cells implemented in or adjacent to a main memory array in which a dummy global word line is driven along with the global word line for the main array.

[0015] In some memory architectures, such as those used in conventional one-time programmable (OTP) memories, a tracking circuit determines when a data latch that receives the output of a sense amplifier is enabled. In one conventional OTP architecture, the sense amplifier responds asynchronously to the bit line level to produce an output level that is latched into the read data latch at a point in the cycle determined by the tracking circuit.

[0016] FIG1 illustrates the functional architecture of a conventional OTP memory including tracking circuitry for timing the latching of data sensed by a sense amplifier. In this conventional architecture, OTP bit cells are arranged in rows and columns in a main array 2, where cells in the same row share a word line and cells in the same column share a bit line BL. The main array 2 is coupled to a corresponding one of the main sense amplifiers 4. Control logic 5 represents the timing logic circuitry that generates a word line enable signal WL_EN, which gates a row decoder and word line driver (not shown) to energize the selected word line in the main array 2 in response to a clock signal CLK at the appropriate time during a read cycle (indicated by a read enable signal READ). The main sense amplifier 4 asynchronously senses the state of the bit line BL in the manner discussed above and presents a corresponding output signal indicating the sensed data state to a read data latch 6. In this conventional OTP architecture, the read data latch 6 latches the output data D_OUT presented by the main sense amplifier 4 in response to the LATCH_DATA signal. The tracking circuit 8 also generates a reset signal RESET to the control logic 5 at this time to allow the memory to prepare for the next cycle immediately after the output data is latched from the read data latch 6 at interval t2-t1.

[0017] According to this conventional OTP architecture, the timing of the LATCH_DATA signal is derived from a tracking circuit 8 that tracks the sense of the data level stored at one or more replica memory cells 2R after energizing the word line enable signal WL_EN. Each replica cell 2R is typically hardwired to a specific data state and is coupled to a replica bit line RBL when the word line enable signal WL_EN is energized. If multiple replica cells 2R are used, they are typically grouped together along one or more replica bit lines RBL to minimize the effects of local device variations. The replica sense amplifier 4R issues a signal to the tracking circuit 8 in response to transitions on the replica bit line RBL. The tracking circuit 8, in turn, generates the LATCH_DATA signal, which (theoretically) occurs at the time when the replica sense amplifier 4R generates a stable D_OUT state based on the level on the replica bit line RBL (plus an additional time margin to allow for variations within the main array 2). For the reasons discussed above, the timing of this LATCH_DATA signal is critical to the overall performance of this OTP memory. If the LATCH_DATA signal is applied to the latch 6 too early in the cycle, the noise margin of the read operation is poor; if it is applied too late in the cycle, the cycle time of the memory is degraded.

[0018] However, it has been observed that conventional tracking circuit approaches are limited in the accuracy with which sense amplifier or data latch timing can be achieved in one-time programmable (OTP) memories. As is known in the art, the electrical behavior of OTP memory cells changes over the lifetime of the device, for example, because the charge stored at the floating gate of the bit cell transistor leaks or is otherwise weakened. This change in behavior is typically reflected in a degradation in the read performance of programmed (i.e., "1" data state) cells over time. Unfortunately, referring to FIG1 , replica OTP cell 2R will degrade over time differently than the average cell in main array 2, if for no other reason than because replica cell 2R is accessed in every read cycle, whereas cells in main array 2 are, on average, accessed much less frequently.

[0019] To avoid the resulting changes in read performance over time, many conventional OTP memories implement replica cell 2R as a non-programmable transistor, for example, as a p-channel MOS load transistor, so that the timing of the LTCH_DATA signal does not change over the lifetime of the device. However, using a different transistor type and arrangement for replica cell 2R than for the cells in main array 2 causes the tracking circuit and the actual data path to exhibit different behavior with changes in power supply voltage, temperature, and process parameters. FIG2 a qualitatively illustrates the effect of changes in these parameters on the timing determination in the OTP memory of FIG1 . In this example of FIG2 a , plot VBL is plotted. BC Bit line voltage VBL for a “0” to “1” transition after energizing the selected word line in the main array 2 is shown for “best case” conditions for power supply voltage, temperature, and process parameters. BC As shown in Figure 2a, the bit line voltage VBL BC At time t0, the trip voltage Vtrip is reached, at which time the LATCH_DATA signal can be issued to the read data latch 6 to accurately latch the output D_OUT of the sense amplifier 4. WC Showing the "worst case" conditions for voltage, temperature, and process in generating the bit line voltage in this OTP memory, plot VBL WC At a later time t1 the trip voltage Vtrip is reached.

[0020] While the tracking circuitry can be arranged to issue the LATCH_DATA signal at any time after the worst-case time t1, the construction of replica cell 2R, which is made of different transistors than the memory cells in main array 2, necessitates the implementation of some timing margins, given the eventual degradation of the main array cells over the lifetime of the system. Consequently, the arrangement of replica cell 2R, replica sense amplifier 4R, and tracking circuitry 8 in this conventional OTP memory is typically arranged so that the reference bit line voltage VRBL reaches the trip voltage Vtrip later than the worst-case time t1 for main array 2. FIG2 a shows an example of this slower generation of reference bit line voltage VRBL, which reaches the trip voltage Vtrip at time t2.

[0021] This margin provided by the interval t2-t1 directly impacts the memory's cycle time. FIG2 b illustrates the generation of a stable "1" level at the output D_OUT of the sense amplifier 4 after the clock signal CLK is issued to the control logic 5 in this architecture. The timing margin indicated by the time interval t2-t1 after the worst-case time (when the reference bit line voltage VRBL reaches the trip voltage Vtrip) accounts for degradation of the main array cells over the device's lifetime. In current OTP memories, this t2-t1 margin can vary from 30 nsec to as much as 100 nsec, depending on the memory size. This margin interval t2-t1 can be a significant portion of the memory's overall cycle time Tcyc and, therefore, can impact the device's overall performance. Summary of the Invention

[0022] The disclosed embodiments provide a timing architecture for a read data path in a one-time programmable (OTP) memory in which memory cycle time is minimized.

[0023] The disclosed embodiments provide such a memory architecture in which the timing of the read data path adjusts as bitcell performance changes over the operational lifetime of the memory.

[0024] The disclosed embodiments provide such a memory architecture that requires minimal timing margin to account for cell degradation.

[0025] The disclosed embodiments provide such a memory architecture in which read power consumption is reduced.

[0026] The disclosed embodiments provide such a memory architecture that can be implemented with simpler circuitry than in conventional memories.

[0027] Other objects and advantages of the disclosed embodiments will become apparent to those of ordinary skill in the art upon reference to the following description taken in conjunction with the drawings.

[0028] According to certain embodiments, a programmable memory includes a read data path, wherein transitions in the data path itself are used to latch the data state sensed from the accessed memory cell. Latch set reset logic is provided such that, during a read operation, a transition at the output of a sense amplifier caused by a selected memory cell storing a programmed cell state clocks a data latch to store that data state and isolate its input from the sense amplifier. The latch set reset logic resets the data latch at the beginning of the next read cycle. In some embodiments, a timer is provided such that the latch is reset after a timeout period during longer read cycles in which no data transitions occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG. 1 is a circuit diagram of the functional architecture of a conventional one-time programmable (OTP) memory in block diagram form.

[0030] FIG. 2 a is a plot illustrating the response of a sense amplifier to a bit line voltage in a conventional OTP memory.

[0031] 2b is a timing diagram illustrating sense amplifier and data latch timing in a conventional OTP memory.

[0032] Figure 3 is a circuit diagram in block diagram form of a large integrated circuit including an OTP memory constructed according to an embodiment.

[0033] Figure 4 The embodiment is constructed in the form of a block diagram Figure 3 Circuit diagram of the OTP memory in the integrated circuit.

[0034] Figure 5 is in the form of a block diagram according to that embodiment Figure 4 Circuit diagram of the functional architecture of the OTP memory.

[0035] Figure 6 In block diagram and schematic form according to that embodiment Figure 5 Circuit diagram of the OTP memory data path.

[0036] Figure 7a and 7b is a schematic diagram according to an embodiment Figure 5 Circuit diagram of the sense amplifier, data latch, and logic circuit in the OTP memory.

[0037] Figure 8 It is an explanation according to the embodiment Figure 5 The timing diagram of the sense amplifier and data latch timing of the OTP memory. DETAILED DESCRIPTION

[0038] One or more embodiments described in this specification are implemented in a one-time programmable (OTP), electrically programmable read-only memory, such as may be implemented in a microcontroller or other large integrated circuit, and as expected, such implementation is particularly advantageous in that context. However, it is also expected that the concepts of the present invention may be beneficially applied to other applications, such as stand-alone OTP memory devices, as well as other memory technologies, particularly those in which the tracking unit may not match the main memory unit in terms of electrical characteristics and performance. Therefore, it should be understood that the following description is provided by way of example only and is not intended to limit the true scope of the invention as claimed.

[0039] Figure 3 An example of a large integrated circuit 10 in the form of a so-called "system on a chip" ("SoC"), as is now popular in many electronic systems, is described. Integrated circuit 10 is a single-chip integrated circuit into which an entire computer architecture is implemented. Thus, in this example, integrated circuit 10 includes a microprocessor 12, which is connected to a system bus (SBUS) and serves as the central processing unit of the device. Various memory resources, including random access memory (RAM) 18 and single-time programmable read-only memory (OTP) 19, reside on system bus (SBUS) and are therefore accessible to microprocessor 12.

[0040] In this example, the OTP 19 is of a type that can be erased by exposure to ultraviolet light, i.e., a UV EPROM. In this example, if the integrated circuit 10 is packaged in a conventional opaque package, then the OTP 19 can be programmed but not erased once it has been packaged. Alternatively, as will be mentioned below, if the integrated circuit 10 is packaged with a window through which the memory array of the OTP 19 is visible, then the OTP 19 can be used as a UV EPROM. Figure 3 Other implementations of this nonvolatile memory, shown as OTP 19, include electrically erasable and flash implementations. In any case, it is contemplated that Figure 3 The OTP 19 in the integrated circuit 10 is typically used as program memory for storing program instructions executable by the microprocessor 12, while the RAM 18 is used as data memory. In some cases, program instructions may reside in the RAM 18 for recall and execution by the microprocessor 12. Other system functions in the integrated circuit 10 are generally shown by the system control 14 and the input / output interface 17.

[0041] Those skilled in the art will recognize, with reference to this specification, that the integrated circuit 10 may include other components besides Figure 3 In addition to or in place of those shown in Figure 3 The functions shown in the Figure 3Thus, the architecture and functionality of integrated circuit 10 are provided by way of example only and are not intended to limit the scope of the claims.

[0042] Figure 4 An example of the architecture of the OTP 19 according to an embodiment of the present invention is illustrated. Although FIG. 2 illustrates the OTP 19 as an embedded memory within a larger integrated circuit 10, the OTP 19 may alternatively correspond to a stand-alone memory integrated circuit. Persons skilled in the art will also understand with reference to this description that the description is provided by way of example only. Figure 3 The memory architecture of the OTP 19 in the embodiment of the present invention can be the same as that of the OTP 19 in the embodiment of the present invention. Figure 3 The architecture shown in is significantly different.

[0043] In this example, the OTP 19 includes a memory array 20 containing programmable read-only memory cells arranged in rows and columns. Figure 3 A single instance of a memory array 20 is shown in FIG, but it should be understood that the OTP 19 may include multiple memory arrays 20, each corresponding to a memory block within the address space of the OTP 19. Figure 3 , memory array 20 includes m rows and n columns of floating gate memory cells, each of which stores one data bit. In these embodiments, cells in the same column share a single bit line BL[n-1:0], and cells in the same row share one of the word lines WL[m-1:0]. Memory array 20 may alternatively be arranged to include multiple cell array blocks or sub-arrays, depending on the addressing space or memory architecture. Pre-decoder and control logic 25 includes decoder logic and other control logic for controlling access to selected cells in memory array 20. In this embodiment, pre-decoder and control logic 25 receives a memory address from outside OTP 19, for example, via bus SBUS ( Figure 3 ) receives a memory address from the microprocessor 12 along with a clock signal CLK and one of the enable signals READ or PROG, indicating whether a read operation or a program operation is to be performed, respectively. The clock signal CLK may be provided by a clock generator circuit (not shown) in the integrated circuit 10, while the applicable READ and PROG signals are typically provided by the specific function in the integrated circuit 10 that accesses the OTP 19 (e.g., the microprocessor 12). In a general sense, the pre-decoder and control logic 25, after receiving an instance of the clock signal CLK, operates to at least partially decode the row and column portions of the received memory address and controls various functions within the OTP 19 to implement the desired read or program function.

[0044] In a read cycle, word line driver 24 receives a row address signal from pre-decoder and control logic 25, which, along with appropriate timing signals, indicates the particular row of memory array 20 to be accessed. In response, word line driver 24 energizes one of word lines WL[m-1:0] corresponding to the decoded row address value, which causes the cells in that corresponding row to present a voltage or current to their corresponding bit lines BL[n-1:0] of their column, depending on the data state stored in each of those cells.

[0045] exist Figure 4 In the architecture of FIG, column select circuitry 26 is essentially constructed as a multiplexer to select one or more of the bit lines BL[n-1:0] for coupling to sense amplifiers 28 in response to a column address (as at least partially decoded by predecoder and control logic 25). The number of sense amplifiers 28 generally corresponds to the width of the output data word. Sense amplifiers 28 essentially digitize the voltage or current on the selected bit line BL[n-1:0] and forward the result to data latches 30 for ultimate buffering and presentation on data output line Q_OUT. As will be described in further detail below, the enabling and timing of sense amplifiers 28 and data latches 30 will be largely based on the data transitions along the data path itself.

[0046] A write circuit (not shown) will also be provided in the OTP 19 to program the selected memory cells using the data present on the data input bus D_IN in a conventional manner, specifically by selectively applying appropriate programming voltages to the selected bit lines BL[n-1:0]. It is contemplated that such write circuitry and programming operations may be implemented using any of several conventional techniques known in the art for electrically programmable memories. As will be understood by those skilled in the art with reference to this specification, other circuitry, including pre-charge and bias circuitry for pre-charging and biasing the bit lines BL[n-1:0], generating programming voltages, control signals, and the like, will be included within the OTP 19, as is typical for electrically programmable memories.

[0047] Figure 5The functional architecture of OTP 19 is illustrated, in conjunction with the timing of latching data sensed in its read data path. According to these embodiments, OTP bit cells are conventionally arranged in rows and columns in main array 22, with cells in the same row sharing a word line and cells in the same column sharing a bit line BL. At the beginning of each read cycle, bit line BL is initialized to a particular logic level, such as that exhibited by a bit cell in its unprogrammed state. Control logic 25 represents sequential logic circuitry that generates word line enable signal WL_EN at the appropriate time in a read cycle (indicated by read enable signal READ) and in response to clock signal CLK. This word line enable signal WL_EN, in turn, causes the selected word line in main array 22 to be energized. The cells in the selected row apply their data states to the corresponding bit line BL in the conventional manner, with the selected one being applied to the corresponding sense amplifier 28. Sense amplifier 28 senses the level at the selected bit line BL and presents the sensed data state to the corresponding data latch 30 on line SA_OUT. According to this embodiment, each data latch 30 latches the sensed data state in response to a transition at its output D_OUT (e.g., a low-to-high transition indicating that the corresponding cell is programmed to a "1" data state). Additionally, according to these embodiments, the same transition at the output of each data latch 30 also operates to isolate its input from its corresponding sense amplifier 28. The output data state on the corresponding output line D_OUT is forwarded to the destination, for example, via an output buffer.

[0048] Conversely, according to these embodiments, if no transition occurs at output D_OUT (i.e., the corresponding memory cell selected in main array 22 is in its unprogrammed state), data latch 30 does not latch its data state but remains in its initialized condition. In any case, control logic 25 resets sense amplifier 28 and data latch 30 in response to the rising edge of clock signal CLK before the next read operation, for example, at the beginning of the next cycle. In those instances where the selected cell in a read cycle is in its unprogrammed state such that no transition occurs at the output of sense amplifier 28, leakage current may flow from the bit cell through its sense amplifier 28. According to some of these embodiments, a timer 27 is provided in the OTP memory 19 to measure a timeout period from the initialization of the previous cycle and, after reaching the end of that cycle without starting a new cycle, causes the control logic 25 to issue a sense amplifier reset signal on the line SA_RST and also to issue a reset signal to the data latches 30; this timeout ensures the reset of those sense amplifiers 28 that did not sense a data level transition in the previous cycle, thereby eliminating this leakage path and undesirable power consumption.

[0049] As a result of this operation, the latching of data in the read data path is essentially "self-timed" in the sense that data transitions in the data path itself time the latching of the output data. No tracking circuitry or replica cells are required, thereby avoiding the timing inaccuracies found in single-time programmable memories, where replica cells do not match the actual cells in electrical characteristics at the time of manufacture or degrade differently than the actual cells over the operating life of the device. In fact, given that the additional timing margin necessitated by the differences in replica cells (t2-t1 margin in Figure 2b) is not required, the self-timing of the data path results in faster read cycle times than conventional memories utilizing tracking circuitry.

[0050] The following will now focus on four representative bit cells 32 in array 22 (i.e., Figure 6 The bit cell 32 shown in 0,0 , 32 0,1 , 32 1,0 , 32 1,1 ) Figure 6 The construction of the OTP 19 according to an embodiment is described in further detail. It is of course contemplated that a given instance of the array 22 will typically contain more bit cells 32 as is appropriate for the program code or other contents of that memory resource in the integrated circuit 10. Additionally, although Figure 6 The arrangement of FIG. 1 illustrates a single instance of a sense amplifier 28 and a data latch 30 in this read data path by way of example, but it is of course contemplated that multiple sense amplifiers 28 and data latches 30 will operate simultaneously and in the same manner in those memories in which the data word width is greater than a single bit. Those skilled in the art will understand with reference to this specification that Figure 6 The construction shown in will represent the construction of each of the multiple instances of that circuit.

[0051] In this embodiment, each bit unit 32 j,k The MOS transistor 31 includes a p-channel floating gate MOS transistor 31, wherein its source / drain path is connected in series with the source / drain path of the p-channel MOS select transistor 33 to the power supply voltage (eg, V dd Power supply voltage) and its corresponding bit line BL k Between. Each unit 32 j,k The gate of the select transistor 33 receives the word line WL for its row j In this example, because the select transistor 33 is a p-channel MOS device, when the word line driver 24 is the word line WL j When driven to a low logic level, the word line WL j The word line driver 24 responds to the row address signal X_DEC to enable the selected word line WL jAt power-up, the row address signal X_DEC has been at least partially decoded by the pre-decoder 37 .

[0052] Positioning unit 32 j,k The data state of bit cell 32 depends on whether its floating gate transistor 31 is programmed to have a charge trapped on its floating gate electrode. j,k The unprogrammed state of bit cell 32 is that state in which its floating gate transistor 31 is non-conductive, and the programmed state is that state in which sufficient electrons are trapped on the floating gate electrode to render transistor 31 conductive upon application of a sufficient source-drain voltage. j,k The state of the floating gate transistor 31 is determined when its word line WL j When the bit line BL is energized to turn on the select transistor 33 k If the voltage at unit 32 j,k is programmed, then conduction through transistor 31 will be on word line WL j is powered on and its select transistor 33 is turned on to turn the high voltage (V cc ) is applied to the bit line BL j On the contrary, if unit 32 j,k Unprogrammed and therefore selected transistor 33 is connected to word line WL j When it is not conducting, V cc Voltage will not be applied to that bit line BL j In this unprogrammed state, the selected bit cell 32 j,k Therefore no power other than that due to the leakage current will be consumed; in this embodiment, it is advantageous to use this effect.

[0053] Bit line B Lk is coupled to the column selection circuit 26, which receives the decoded column address signal Y_DEC from the pre-decoder 37 and selects those bit lines BL k Sense amplifier 28 compares the voltage or read current at the selected bit line BL_OUT with a reference level and presents the corresponding data state on line SA_OUT to the sense amplifier 28 as described above with respect to FIG. Figure 5 The data latch 30 is described. In this embodiment, the data latch 30 is j,k OUT is transparent during the sensing period, and thus, the data level sensed at line SA_OUT is transferred to its output on line D_OUT through data latch 30. Output buffer 38, in turn, presents that data state at its output Q_OUT for transfer to the appropriate destination in integrated circuit 10.

[0054] like Figure 6 As shown in FIG, the predecoder and control logic 25 includes a clock generator 36 that generates an internal clock signal for the OTP 19 based on the clock signal CLK. The clock signal CLK may be generated by a clock circuit (not shown) elsewhere in the integrated circuit 10. In the read circuit of the OTP 19 according to this embodiment, the internal clock signals generated by the clock generator 36 include a clock signal ACLK applied to the predecoder 37 and the control logic 35, and a reset signal RESET applied to the timer 27, both of which are (for example) generated at a suitable time after the rising edge of the clock signal CLK. As described above, the predecoder 37 (for example, via Figure 3 The memory address is received from a request function in the integrated circuit 10 in response to a clock signal ACLK from a clock generator 36, and that memory address is at least partially decoded for use by the word line driver 24 and the column select circuit 26.

[0055] In this embodiment, timer 27 is a conventional timer circuit that measures the maximum cycle time from the reset signal RESET from clock generator 36 at the beginning of the cycle. As will be described below in conjunction with its operation, OTP 19 according to these embodiments is initialized at the beginning of a read cycle, rather than at the end of a read cycle, as might be indicated by a tracking circuit in a conventional memory. Because data latch timing is based on a unidirectional transition in the read path according to a self-timed operation, a reset will not otherwise occur in a read cycle in which no data transition is detected, especially if that cycle is not immediately followed by another read operation. Thus, the operation of timer 27 ensures the reset of sense amplifier 28 and the initialization of bit lines BL in array 22 after a specified maximum timeout period. For example, if the normal read cycle period of OTP 19 is approximately 50 nsec, a suitable timeout period measured by timer 27 may be approximately 200 nsec or longer. After the timeout period expires, timer 27 issues signal EOC to control logic 35.

[0056] The control logic 35 is constructed as a logic circuit that issues control signals to various circuits in the read path according to these embodiments. As described above, the control logic 35 receives the internal clock signal ACLK from the clock generator 36, the cycle end signal EOC from the timer 27, and the read control signal READ and the program control signal PRGM, which respectively indicate the type of cycle to be performed by the OTP 19, from the microprocessor 12 or another function in the integrated circuit 10. Figure 6In the embodiment of the present invention, the control logic 35 issues an enable signal ENSAZ to the latch set reset logic 34 and the sense amplifier 28 in response to the internal clock signal ACLK at the beginning of a read cycle (as indicated by the READ control signal); the enable signal ENSAZ is also issued by the control logic 35 in response to the end-of-cycle signal EOC from the timer 27. According to this embodiment, and as will be described in further detail below, the enable signal ENSAZ operates to reset the sense amplifier 28 and initialize the reset of the data latch 30.

[0057] In addition to the enable signal ENSAZ, line D_OUT from the output of the data latch 30 is also conveyed to the latch set reset logic 34. As discussed above, and as will be described in further detail below, the latch set reset logic 34 issues the latch signal LAT to the data latch 30 in response to a transition at line D_OUT, thereby latching that data state into the data latch 30 to allow the sense amplifier 28 and the remainder of the upstream circuitry to be reset in the next cycle. Figure 6 As shown in , latch signal LAT is also applied to sense amplifier 28 to disable sense amplifier 28 in response to a transition at line D_OUT.

[0058] Figure 7a and 7b Further details according to Figure 6 The data path circuit of the OTP 19 of the embodiment. Figure 7a In the example, a single bit cell 32 is illustrated for clarity. j,k It should be understood, of course, that the particular bit cell 32 of this example coupled to the sense amplifier 28 j,k will be the bit location corresponding to the decoded memory address. Figure 7a As shown in FIG, the bit line BL k The corresponding precharge transistor 42 k Associated, precharge transistor 42 k Its source / drain path is connected to the bit line BL k and ground, and its gate receives a control signal BLDIS from the control logic 35 or other appropriate circuit in the OTP 19. According to this embodiment, each bit line BL k Prior to the initiation of the read operation, the associated precharge transistor 42 k is initialized to a voltage corresponding to the unprogrammed state of the bit cell 32. Thus, if the bit line BL k The selected bit cell 32 j,k In the unprogrammed state, the bit line BL k Conversely, if the selected bit cell 32 j,kIn its programmed state, the bit line BL k will make a transition based on its precharged level, in this embodiment, from ground to a high voltage (e.g., close to V cc ).

[0059] Column select transistor 26 k Its source / drain path is connected to the bit line BL k between its associated sense amplifier 28 and receiving the decoded column select signal CSEL at its gate k If the bit line BL k Corresponding to the column indicated by the received column address, the decoded signal CSEL is then k Power is applied, thereby turning on transistor 26 k The bit line BL is connected to the sensing node SN. k Connected to sense amplifier 28.

[0060] In this embodiment, the sense amplifier 28 is essentially a current comparator that compares the current flowing from the bit line BL. k The reference current conducted by transistors 45 and 46 during a read cycle is established by a reference transistor 45 having its source / drain path connected in series with the source / drain path of transistor 46 between sense node SN and ground. The gate of reference transistor 45 receives a bias voltage NBIAS from a reference circuit in OTP 19 or elsewhere in integrated circuit 10, while transistor 46 receives a latch signal LAT from latch set reset logic 34, as will be described below. Bias voltage NBIAS establishes the reference current conducted by transistors 45 and 46 during a read cycle, such that the voltage at sense node SN depends on the voltage from the selected cell 32. j,k The bit line BL k Whether the current exceeds the reference current. For the bit cell 32 in the unprogrammed state j,k , bit line BL k The most leakage current will be conducted, and transistors 45 and 46 will pull the sense node SN to ground. For bit cell 32 in its programmed (ie, conductive) state j,k , the bit line current will be sufficient to overcome the smaller reference current established by reference transistor 45, and the voltage of sense node SN will move toward V cc Inverters 40a, 40b connected in series between the sense node SN and the data latch 30 generate a voltage at the output SA_OUT of the sense amplifier 28 that corresponds to the voltage at the sense node SN and therefore to the selected bit cell 32. j,k The logic level of the state.

[0061] According to this embodiment, data latch 30 includes a first transmission gate 50a, which is coupled to the output SA_OUT of sense amplifier 28 and controlled by a latch signal LAT from latch set reset logic 34. Transmission gate 50a can be constructed as a pair of complementary MOS transistors, with their source / drain paths connected in parallel and receiving complementary signals (i.e., latch signal LAT and its complement LATZ in this example) at their respective gates, as is known in the art. Alternatively, transmission gate 50a can be a single pass transistor. The opposite side of transmission gate 50a is connected to the input of inverter 52a, which has its output connected to the input of each of inverters 52b and 52c. Transmission gate 50b connects the output of inverter 52b to the input of inverter 52a to form a latch when transmission gate 50b is conductive. In this embodiment, transmission gate 50b receives the complementary latch signal LATZ generated by inverter 49 based on latch signal LAT. Thus, transmission gate 50b is off when transmission gate 50a is on (where latch signal LAT is at a high logic level), and transmission gate 50a is off when transmission gate 50b is on (where latch signal LAT is at a low logic level). The latch output D_OUT at the output of inverter 52c is applied to output buffer 38 and latch set reset logic 34.

[0062] Figure 7b The configuration of the latch set reset logic 34 according to this embodiment is described. The latch set reset logic 34 includes a pair of cross-coupled NAND gates 54a, 54b, each having an input receiving the output of the other. The other input of the NAND gate 54a is received (via an inverter 55a) from the control logic 35 ( Figure 6 ) receives the logic complement of the enable signal ENSAZ. The other input of the NAND gate 54b receives the logic complement of the latch output D_OUT (via inverter 55b). Thus, the latch set reset logic 34 is operable to assert the latch signal LAT in response to a high logic level at the enable signal ENSAZ or the latch output D_OUT.

[0063] Of course, latch set reset logic 34 may be implemented by other logic circuit arrangements to perform the functions of control logic 25 according to these embodiments. Figure 7a, the latch signal LAT from the latch set reset logic 34 is applied to the gate of the transistor 46 in the sense amplifier 28, thereby amplifying the logic arrangement of this circuit for efficient implementation. Alternatively, the control logic 25 can be arranged to disable the sense amplifier 28 (e.g., by turning off its transistor 46) separately from the setting and resetting of the data latch 30. It is expected that those skilled in the art will be able to readily implement the specific arrangement of the control logic 25 including the latch set reset logic 34 in the manner desired for each specific implementation of these embodiments.

[0064] Reference Figure 8 , now we will focus on OTP 19 unit 32 j,k The case where the transistor 31 is programmed to a "1" data state (ie, has charge trapped at the floating gate of the transistor 31 to render it conductive) is described in terms of Figure 6 、 7a 7b is an example of the operation of the read path architecture of the OTP 19 in performing a read cycle. As will be apparent from this description, in the previous read cycle, and therefore before the start of the read cycle at time t0, the latch set reset logic 34 has already issued the latch signal LAT at a logic low level. In the data latch 30, the pass transistor 50a is therefore turned off, and the pass transistor 50b is turned on, so that the data latch 30 retains the previous data state D_OUT and presents a corresponding logic level at its output D_OUT.

[0065] In this example, the read cycle applies the rising edge of the clock signal CLK to the clock generator 36 ( Figure 6 ) begins, in response to the application, the clock generator 36 issues the trailing edge of the internal clock signal ACLK to the pre-decoder 37 and the control logic 35 to initialize the cycle. Figure 7a As described, the bit line BL k Each is precharged to ground, for example, by the control circuit briefly asserting signal BLDIS to turn on transistor 42 in response to this transition of internal clock signal ACLK. k The high-to-low transition of the internal clock signal ACLK also causes the pre-decoder 37 to begin decoding the row and column addresses received, for example, from the system bus SBUS for application to the word line drivers 24 and column select circuits 26, which in turn initialize access to the selected row of cells and to those bit lines BL to be sensed, respectively. k In this example, the selected cell 32 in row j and column k j,k is in its programmed ("1") state and thus its selected bit line BL k Pulled to a high voltage for sensing.

[0066] In a read cycle (i.e., when the read signal READ is asserted) and in response to the internal clock signal ACLK, the control logic 35 issues a pulse of the enable signal ENSAZ to the sense amplifiers 28 and the latch set reset logic 34. In this embodiment of the present invention, this enable signal ENSAZ pulse initializes each sense node SN to a low level by turning on the transistor 44 in each sense amplifier 28. In addition, according to this embodiment, as Figure 8 , the rising edge of the ENSAZ pulse causes the latch set reset logic 34 to issue a rising edge of the latch signal LAT to the sense amplifier 28 and the data latch 30. The high level of the latch signal LAT turns on the transistor 46 in the sense amplifier 28, thereby allowing the reference current from the sense node SN to be conducted through the transistor 45 under the control of the bias voltage NBIAS. In addition, the latch signal LAT "resets" the data latch 30 by turning on its transmission gate 50a and opening its transmission gate 50b. In this "reset" state, the previous state stored in the data latch 30 is no longer latched, and the current level at the sense amplifier output SA_OUT is passed through the data latch 30 via inverters 52a, 52c.

[0067] At the end of the pulse of the enable signal ENSAZ as determined by the control logic 35, the transistor 44 turns off so that the sense node SN is no longer held at ground except through the reference transistor 45. Thus, as determined by the selected cell 32 j,k The data state of the selected bit line BL is determined by k The voltage at will be reflected at the sensing node SN to some extent: j,k The read current exceeds the reference current through transistor 45. For the "1" state, as described above, the read current will exceed the reference current and the bit line BL will be used. k Raise the sensing node SN to a high level. Figure 8 , in response to the bit line BL k When the sense amplifier 28 (and therefore the sense node SN) reaches the trip voltage Vtrip of the inverter 40a of the sense amplifier 28, the sense amplifier output SA_OUT makes a transition to a high logic level as driven by the inverter 40b. With the transmission gate 50a in the data latch 30 turned on (at this time, the latch signal LAT is high), the high logic level at the sense amplifier SA_OUT is reflected at the latch output D_OUT after a propagation delay through the inverters 52a and 52c. Figure 8The access time Tacc shown in FIG refers to the time interval between the rising edge of the clock signal CLK and the low-to-high transition at the latch output D_OUT. Because the data latch 30 is transparent during the sensing operation, this access time Tacc is essentially dependent on the number of memory cells 32 being addressed that are in their "1" data state. j,k The buffer 38 then presents that high logic level on line Q_OUT in the data path of the OTP 19.

[0068] According to this embodiment, latch set reset logic 34 terminates the pulse of latch signal LAT in response to a low-to-high transition at latch output D_OUT. Specifically, the trailing edge of latch signal LAT "sets" data latch 30 by turning off transmission gate 50a and turning on transmission gate 50b, coupling the output of inverter 52b to the input of inverter 52a. The sensed "1" data state is latched into and retained by data latch 30 in this "set" state, and is no longer affected by the level at sense amplifier output SA_OUT. Additionally, according to this embodiment, transistor 46 in sense amplifier 28 turns off, thereby ending this cycle of sensing operations.

[0069] In this state, the low level of latch signal LAT keeps sense amplifier 28 off and keeps data latch 30 decoupled from sense amplifier SA_OUT, as described above. k Turned on to initialize the bit line BL in the next cycle k , and thus, the selected programmed cell 32 j,k No current is drawn except for leakage current. Data latch 30 maintains the "1" data state at data output line Q for the remainder of the cycle. This state is maintained until the next rising edge of clock signal CLK, which is when OTP 19 begins the next cycle.

[0070] For unprogrammed (“0”) cells 32 j,k In the case of Figure 8The operation is described, except that no transition occurs at the sense amplifier output SA_OUT, and therefore no transition occurs at the latch output D_OUT. Therefore, the latch set reset logic 34 does not generate a pulse of the latch signal LAT. In this case, the data latch 30 remains unlatched (the transmission gate 50b remains open), and the data latch 30 simply passes the low logic level at the sense amplifier output SA_OUT to the buffer 38 for presentation at the data output Q_OUT. Because the pulse of the latch signal LAT is not terminated for this "0" data state case, the transistor 46 remains on and therefore the sense amplifier 28 remains on for the duration of the cycle. Therefore, the data latch 30 is not latched by the "0" state cell 32. j,k Any leakage current will flow along the bit line BL k The selected cell 32 is not connected to the ground because the hard gate voltage is applied. j,k If the floating gate transistors 33 in the array 22 are kept off, it is expected that some leakage current may occur from some cells 32 in the array 22. Although this leakage occurs over relatively short cycle times (i.e., Figure 8 While the leakage power consumed may be less noticeable during the period between rising edges of the clock signal CLK (shown as Tcyc in FIG), the leakage power consumed may be more noticeable during longer cycle times, which, given its static nature, may occur frequently for the OTP 19. For example, the last cycle in a burst read of the OTP 19 may be quite long, extending from the end of one burst to the beginning of the next.

[0071] According to this embodiment, a timer 27 is provided within the control logic 25 to initialize the reset of the sense amplifier 28 and the data latch 30 if a reset of the sense amplifier 28 and the data latch 30 does not occur in response to a data transition after the maximum allowable cycle time interval has elapsed. The timer 27 may be constructed in a conventional manner, for example, as a count-down (or count-up) timer whose stored contents advance with each cycle of the periodic clock signal. Figure 6In the embodiment of the present invention, timer 27 receives a reset clock RESET from clock generator 36 in response to each rising edge of clock signal CLK. This transition of reset clock RESET causes timer 27 to begin measuring a time interval corresponding to a maximum cycle time, for example, by performing a countdown (or countup) of clock pulses. An example of a maximum cycle time may be approximately 200 nsec; a typical cycle time in normal operation of the OTP is generally greater than 50 nsec or less. Typically, timer 27 is clocked by a higher frequency clock, such as may be generated by clock generator 36, for example. After reaching a pre-programmed or selected maximum time interval, timer 27 then issues an end-of-cycle signal EOC to control logic 35, which in turn issues a pulse of enable signal ENSAZ to latch set reset logic 34. In response to the ENSAZ pulse, as described above, the latch set reset logic 34 issues a pulse of the latch signal LAT, thereby setting the data latch 30 to store a "0" data state at the sense amplifier output SA_OUT and turning off the sense amplifier 28 by turning off the transistor 46. With the sense amplifier 28 disabled in this manner, the unprogrammed "0" cell 32 will be blocked by the off-state transistor 46. j,k Any leakage current is transferred to ground and additional power consumption will be minimized.

[0072] Thus, these embodiments operate to "self-latch" the sensed data state of a selected OTP cell at a timing corresponding to the transition of the sensed data state itself. As in conventional OTP memory, no tracking circuitry or replica cells are required to control the timing of the data latches. Consequently, the self-timing of the data latches can be substantially as fast as the operation of the memory itself, without the additional timing margins of conventional tracking circuits that must accommodate variations between replica cells or other delay circuits with OTP cell performance over the operating lifetime of the device. Rather, as OTP cell performance may degrade over its operating lifetime, the self-latching operation according to these embodiments will accurately track any such degradation. Referring to FIG. 2 a , the cycle time Tcyc of the OTP 19 according to these embodiments can be minimized because the need to include a "t2-t1 margin" as shown in FIG. 2 a and 2 b is eliminated. Furthermore, these embodiments implement the self-latching read data path in a manner that minimizes excess power consumption and can be efficiently implemented in modern integrated circuits from a chip area and circuit complexity perspective.

[0073] Although one or more embodiments have been described in this specification, it is contemplated that modifications and alternatives to these embodiments will become apparent to those skilled in the art upon reference to this specification and its accompanying drawings, which modifications and alternatives will achieve one or more of the advantages and benefits of the present invention. It is contemplated that such modifications and alternatives are within the scope of the present invention as subsequently claimed herein.

Claims

1. A method of reading data stored in a memory element of a memory device, comprising: receiving a signal corresponding to the data stored in the memory element at an input of a sense amplifier; outputting a sense output signal at an output of the sense amplifier that indicates a logic state of the data stored in the memory element in response to a sense amplifier enable signal; operating a data latch having an input in a reset state in response to a latch signal indicating a first value to pass the sense output signal of the sense amplifier to an output of the data latch, wherein the input of the data latch is coupled to the output of the sense amplifier to receive the sense output signal; and operating the data latch in a set state in response to the latch signal indicating a second value to store a data state of the sense output signal and to isolate the input of the data latch from the output of the sense amplifier; wherein the latch signal is generated using a set-reset control circuit having an input receiving the sense amplifier enable signal, and the generation of the latch signal is at least partially responsive to the sense amplifier enable signal. 2 . The method of claim 1 , wherein the data latch is operated in the set state in response to the sense output signal indicating the logic state of the data stored in the memory element corresponding to a programmed state. 3 . The method of claim 2 , wherein the data latch is operated in the reset state in response to the sense output signal indicating the logic state of the data stored in the memory element corresponding to an unprogrammed state. 4 . The method of claim 3 , wherein the programmed state has a logical value of 1 and the unprogrammed state has a logical value of 0.

5. The method of claim 1 , wherein operating the data latch in the reset state comprises: closing a first transmission gate coupled between the input of the data latch and the output of the data latch; and A second transmission gate coupled between an output of the data latch and a storage element of the data latch is opened.

6. A method of reading data from a programmable solid-state memory having a memory cell to store data in a first data state or a second data state, the method comprising: At the beginning of a read cycle, resetting each of a plurality of bit lines of the programmable solid-state memory to a first level; applying the data state of a selected one of the memory cells to a bit line after resetting the plurality of bit lines to the first level, the bit line being one of the plurality of bit lines, wherein when the data state of the selected memory cell is the first data state, applying the first data state of the selected memory cell to the bit line causes the bit line to remain at the first level, and wherein when the data state of the selected memory cell is the second data state, applying the second data state of the selected memory cell to the bit line causes the bit line to transition from the first level to a second level; sensing a level of the bit line using a sense amplifier to sense whether the bit line is at the first level or the second level in response to a sense amplifier enable signal, the level sensed by the sense amplifier being a sensing level; outputting the sense level at an output of the sense amplifier; passing the output of the sense amplifier through a data latch to an output coupled to an output data path, wherein a logic state transition occurs at the output of the data latch in response to the sense level indicating that the selected memory cell is in the second data state; In response to detecting the logic state transition at the output of the data latch, controlling the data latch in response to a latch signal to cause the data latch to store the second data state corresponding to the second level, and then isolating the data latch from the output of the sense amplifier, wherein the latch signal is generated based on the logic state of the sense amplifier enable signal and the logic state of the output of the data latch.

7. The method according to claim 6, further comprising: starting a timer from said start of said read cycle; and In response to the timer reaching a maximum cycle time, the data latch is coupled to the output of the sense amplifier.

8. The method of claim 6, wherein the data latch comprises: a storage element having an input and an output; and a first transmission gate coupled between the output of the sense amplifier and the input of the storage element; Wherein the step of isolating the data latch includes opening the first transmission gate.

9. The method of claim 8, wherein the storage element of the data latch further comprises: a first inverter having an input coupled to the first transmission gate and an output; a second inverter having an input coupled to the output of the first inverter and an output; and a second transmission gate coupled between the output of the second inverter and the input of the first inverter; and The step of setting the data latch includes closing the second transmission gate.

10. The method of claim 9, further comprising, at the start of the read cycle, closing the first transfer gate and opening the second transfer gate.

11. The method according to claim 10, further comprising: starting a timer from said start of said read cycle; and In response to the timer reaching a maximum cycle time, the first transmission gate is closed and the second transmission gate is opened.

12. The method according to claim 6, wherein: The first data state corresponds to an unprogrammed memory cell state; and The second data state corresponds to a programmed memory cell state.

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