Semiconductor structure, method for manufacturing a semiconductor structure and control system for a semiconductor structure

Abstract

Embodiments of the present disclosure relate to a semiconductor structure, a preparation method thereof and a control system corresponding to the semiconductor structure. The method comprises: providing a substrate, the substrate comprising a preset structure and an etching material layer on the preset structure; forming a photoresist layer on the etching material layer, the photoresist layer comprising a first opening; obtaining a first deviation between a bottom of the first opening and a top of the preset structure on a first plane, the first plane being parallel to a surface of the substrate; performing a patterning process on the etching material layer based on the photoresist layer to obtain a second opening; obtaining a second deviation between the bottom of the second opening and the bottom of the first opening on the first plane; and obtaining a photoetching compensation value according to the second deviation and the first deviation, the photoetching compensation value being used to correct the first deviation to eliminate misalignment of the second opening and the preset structure on the first plane. By using the photoetching compensation value to correct the first deviation, the influence of photoetching error and etching error on the misalignment can be eliminated.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and a corresponding control system. Background Technology

[0002] With the development of semiconductor technology, the requirements for high aspect ratio etching are becoming increasingly stringent. Due to differences in incoming wafers, calibration variations between different photolithography stations, and uneven plasma distribution during etching, misalignment occurs between the upper and lower layers of the semiconductor device formed on the wafer, leading to device failure. Simple batch-to-batch feedback control after etching or simple batch feedback control after photolithography and development cannot completely solve all misalignments between the upper and lower layers, and may even lead to over-adjustment, making the misalignment worse and affecting the yield of semiconductor devices. Therefore, solving the misalignment problem between the upper and lower layers of semiconductor devices has become an urgent issue. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, its fabrication method, and a corresponding control system, which can reduce the misalignment between the upper and lower layers of a semiconductor device and improve the yield of the semiconductor device.

[0004] This disclosure provides a method for fabricating a semiconductor structure, including:

[0005] A substrate is provided, the substrate including a preset structure and an etching material layer located on the preset structure;

[0006] A photoresist layer is formed on an etchable material layer, the photoresist layer including a first opening;

[0007] Obtain the first deviation between the bottom of the first opening and the top of the preset structure on a first plane, the first plane being parallel to the surface of the substrate;

[0008] The etching material layer is patterned based on the photoresist layer to obtain the second opening;

[0009] Obtain the second deviation between the bottom of the second opening and the bottom of the first opening on the first plane;

[0010] Based on the second deviation and the first deviation, a photolithographic compensation value is obtained. The photolithographic compensation value is used to correct the first deviation in order to eliminate the misalignment between the second opening and the preset structure on the first plane.

[0011] In one embodiment, the bottom of the first opening is flush with the upper surface of the etched material layer.

[0012] In one embodiment, the bottom of the second opening is flush with the upper surface of the preset structure.

[0013] In one embodiment, forming a photoresist layer on the etched material layer includes:

[0014] A photoresist material layer is formed on the etching material layer;

[0015] A photolithography process is performed to obtain a photoresist layer composed of the remaining photoresist material layer.

[0016] In one embodiment, the substrate further includes a hard mask material layer located on the etch material layer; patterning the etch material layer based on the photoresist layer includes:

[0017] The hard mask material layer is patterned based on the photoresist layer to obtain the hard mask layer;

[0018] The etching material layer is patterned based on a hard mask layer to form a second opening in the etching material layer.

[0019] In one embodiment, a dry etching process is used to pattern the etched material layer to form a second opening in the etched material layer.

[0020] In one embodiment, the lithography compensation value includes a first compensation value and a second compensation value. The lithography compensation value is obtained based on the second deviation and the first deviation, including:

[0021] A first compensation value is obtained based on the first deviation, and the first compensation value is used to eliminate the influence of the photolithography process on the misalignment.

[0022] A second compensation value is obtained based on the second deviation. The second compensation value is used to adjust the photolithography process to eliminate the influence of patterning the etched material layer on the misalignment.

[0023] In one embodiment, obtaining the second deviation between the bottom of the second opening and the bottom of the first opening on the first plane includes:

[0024] Obtain the third deviation between the bottom of the second opening and the top of the preset structure on the first plane;

[0025] The second deviation is obtained based on the third deviation and the first deviation.

[0026] In one embodiment, the first deviation, the second deviation, and the third deviation are all vectors.

[0027] In one embodiment, the constituent materials of the etched material layer include insulating materials, metallic materials, or semiconductor materials.

[0028] This disclosure also provides a semiconductor structure, including:

[0029] The second opening is made using the preparation method described in any of the above.

[0030] This disclosure also provides a control system corresponding to a semiconductor structure. The method for fabricating the semiconductor structure includes providing a substrate, the substrate including a preset structure and an etching material layer located on the preset structure; forming a photoresist layer including a first opening on the etching material layer; and performing patterning processing on the etching material layer based on the photoresist layer to obtain a second opening; the control system includes:

[0031] The measurement module is used to measure the first deviation between the bottom of the first opening and the top of the preset structure on a first plane, the first plane being parallel to the surface of the substrate; the measurement module is also used to measure the second deviation between the bottom of the second opening and the bottom of the first opening on the first plane.

[0032] The calculation module, connected to the measurement module, is used to obtain a photolithography compensation value based on the second deviation and the first deviation. The photolithography compensation value is used to correct the first deviation to eliminate the misalignment between the second opening and the preset structure on the first plane.

[0033] In one embodiment, the photolithography compensation value includes a first compensation value and a second compensation value, and the calculation module includes:

[0034] A first computing device is used to obtain a first compensation value based on a first deviation. The first compensation value is used to eliminate the influence of the photolithography process during the formation of the photoresist layer on the misalignment.

[0035] The second computing device is used to obtain a second compensation value based on the second deviation. The second compensation value is used to adjust the photolithography process to eliminate the influence of patterning the etched material layer on the misalignment.

[0036] In one embodiment, the measurement module is further configured to measure a third deviation between the bottom of the second opening and the top of the preset structure on a first plane; the calculation module is further configured to obtain a second deviation based on the third deviation and the first deviation.

[0037] This disclosure also provides a photolithography apparatus for forming a photoresist layer with a first opening. The photolithography apparatus is connected to a control system corresponding to any of the semiconductor structures described above, and is used to correct the position of the first opening in the photoresist layer according to the photolithography compensation value output by the control system.

[0038] The aforementioned semiconductor structure and its fabrication method include obtaining a first deviation between the bottom of a first opening in a photoresist layer and the top of a preset structure in a substrate on a first plane, wherein the first plane is parallel to the surface of the substrate; obtaining a second deviation between the bottom of a second opening in an etching material layer and the bottom of the first opening on the first plane; and then obtaining a photolithographic compensation value based on the second deviation and the first deviation, wherein the photolithographic compensation value is used to correct the first deviation to eliminate the misalignment between the second opening and the preset structure on the first plane. In this disclosed technical solution, the first deviation reflects the photolithographic error during the formation of the photoresist layer, and the second deviation reflects the etching error during the formation of the second opening. Therefore, the photolithographic compensation value obtained based on the first and second deviations can comprehensively characterize the influence of photolithographic and etching errors on the misalignment between the second opening and the preset structure on the first plane. By using the photolithographic compensation value to correct the first deviation, the influence of photolithographic and etching errors on the misalignment between the second opening and the preset structure on the first plane can be eliminated. Meanwhile, by separating the effects of lithography error and etching error on misalignment, this disclosure improves the speed of correcting the misalignment between the second opening and the preset structure on the first plane, while avoiding the problem of over-adjustment when directly adjusting the misalignment between the second opening and the preset structure on the first plane through the second deviation.

[0039] In the control system corresponding to the aforementioned semiconductor structure, the measurement module is used to obtain a first deviation between the bottom of the first opening in the photoresist layer and the top of the preset structure in the substrate on a first plane, the first plane being parallel to the surface of the substrate; simultaneously, the measurement module is also used to obtain a second deviation between the bottom of the second opening in the etching material layer and the bottom of the first opening on the first plane. The calculation module obtains a photolithography compensation value based on the second deviation and the first deviation. This photolithography compensation value is used to correct the first deviation, thereby eliminating the misalignment between the second opening and the preset structure on the first plane. In the technical solution of this disclosure, the first deviation reflects the photolithography error during the formation of the photoresist layer, and the second deviation reflects the etching error during the formation of the second opening. Therefore, the photolithography compensation value obtained by the calculation module based on the first and second deviations can comprehensively characterize the influence of photolithography error and etching error on the misalignment between the second opening and the preset structure on the first plane. By using the photolithography compensation value to correct the first deviation, the influence of photolithography error and etching error on the misalignment between the second opening and the preset structure on the first plane can be eliminated. Meanwhile, by separating the effects of lithography error and etching error on misalignment, this disclosure improves the speed of correcting the misalignment between the second opening and the preset structure on the first plane, while avoiding the problem of over-adjustment when directly adjusting the misalignment between the second opening and the preset structure on the first plane through the second deviation. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment;

[0042] Figure 2 This is a schematic cross-sectional view of a semiconductor structure after a photoresist layer has been formed in one embodiment;

[0043] Figure 3 This is a schematic diagram of the process of forming a photoresist layer on an etched material layer in one embodiment;

[0044] Figure 4 This is a schematic diagram of a process for graphically processing an etching material layer based on a photoresist layer in one embodiment;

[0045] Figure 5 for Figure 2 A cross-sectional schematic diagram of the semiconductor structure after the second opening is formed in one corresponding embodiment;

[0046] Figure 6 This is a schematic diagram of the process for obtaining the second deviation between the bottom of the second opening and the bottom of the first opening on a first plane in one embodiment;

[0047] Figure 7 This is a schematic diagram of the process for obtaining lithographic compensation values ​​based on a second deviation and a first deviation in one embodiment.

[0048] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after forming a photoresist layer by correcting the first deviation through photolithographic compensation value in one embodiment.

[0049] Figure 9 for Figure 8 A cross-sectional schematic diagram of the semiconductor structure after the second opening is formed in one corresponding embodiment;

[0050] Figure 10 This is a block diagram of the control system corresponding to the semiconductor structure in one embodiment.

[0051] Explanation of reference numerals in the attached figures:

[0052] 102. Substrate; 104. Preset structure; 106. Etching material layer; 108. Photoresist layer; 110. Hard mask material layer; 202. First opening; 204. Second opening; 302. Measurement module; 304. Calculation module. Detailed Implementation

[0053] To facilitate understanding of the embodiments of this disclosure, a more complete description of the embodiments of this disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of this disclosure are shown in the drawings. However, the embodiments of this disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this disclosure belong. The terminology used herein in the description of embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0055] In the description of the embodiments of this disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0056] It is understood that the terms "first," "second," etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first opening may be referred to as a second opening, and similarly, a second opening may be referred to as a first opening. Both the first opening and the second opening are openings, but they are not the same opening.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. In the description of this disclosure, "several" means at least one, such as one, two, etc., unless otherwise expressly specified.

[0058] Figure 1 This is a schematic flowchart of a semiconductor structure fabrication method in one embodiment, such as... Figure 1 As shown, in this embodiment, a method for fabricating a semiconductor structure is provided, comprising:

[0059] S102, providing a substrate, the substrate including a preset structure and an etching material layer located on the preset structure.

[0060] A substrate is provided, which can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, the substrate is made of single-crystal silicon. The substrate includes a preset structure and an etching material layer on the preset structure. The preset structure refers to the structure that needs to be aligned with the second opening subsequently formed, i.e., the part of the lower structure formed on the substrate that needs to contact and connect with the upper structure. The material of the preset structure can include conductive materials, insulating materials, or semiconductor materials, such as tungsten, copper, titanium, titanium nitride, silicon dioxide, silicon nitride, polycrystalline silicon, etc. The etching material layer refers to the material layer located on the preset structure that will subsequently expose the second opening of the preset structure.

[0061] S104, A photoresist layer is formed on the etching material layer, the photoresist layer including a first opening.

[0062] Specifically, a photoresist layer is formed on the etching material layer, and a first opening is formed in the photoresist layer. The first opening defines the position and shape of the second opening that will be formed in the etching material layer later.

[0063] S106, obtain the first deviation between the bottom of the first opening and the top of the preset structure on the first plane.

[0064] Specifically, the first deviation between the bottom of the first opening and the top of the preset structure on a first plane is obtained, with the first plane parallel to the surface of the substrate. First, the bottom of the first opening is orthographically projected onto the plane containing the top of the preset structure. Second, the first distance between the orthographic projection of the bottom of the first opening and the preset structure is measured. This first distance is the first deviation between the bottom of the first opening and the top of the preset structure on the first plane. Here, the first distance is actually the distance between the center position of the orthographic projection of the bottom of the first opening and the theoretical position of the orthographic projection of the center position of the bottom of the first opening on the first plane. Assuming that the second opening formed subsequently is located directly above the preset structure, theoretically, the first opening should also be located directly above the preset structure. That is, at this time, the center position of the orthographic projection of the bottom of the first opening and the center position of the preset structure should theoretically coincide. The first distance is the distance between the center position of the orthographic projection of the bottom of the first opening and the center position of the preset structure. The first deviation between the bottom of the first opening and the preset structure on the first plane reflects the photolithographic error when forming the photoresist layer.

[0065] S108, the etching material layer is patterned based on the photoresist layer to obtain the second opening.

[0066] Specifically, the photoresist layer is used as a mask to pattern the etching material layer, and a second opening is created within the etching material layer. It can be understood that the second opening penetrates the etching material layer.

[0067] S110, obtain the second deviation between the bottom of the second opening and the bottom of the first opening on the first plane.

[0068] Specifically, firstly, the bottom of the second opening is orthographically projected onto the plane containing the preset structure. Secondly, a second distance is measured between the center position of the orthographic projection of the bottom of the first opening and the center position of the orthographic projection of the second opening. This second distance represents the second deviation between the bottom of the second opening and the bottom of the first opening on the first plane. It can be understood that, theoretically, the shape and position of the orthographic projection of the second opening on the first plane are the same as and coincide with the shape and position of the orthographic projection of the first opening on the first plane. The second deviation between the bottom of the second opening and the bottom of the first opening on the first plane actually reflects the etching error during the patterning of the etching material layer based on the photoresist layer.

[0069] S112, based on the first deviation and the second deviation, obtain the lithographic compensation value used to correct the first deviation.

[0070] Specifically, a lithographic compensation value is obtained based on the second deviation and the first deviation. This lithographic compensation value is used to correct the first deviation to eliminate the misalignment between the second opening and the preset structure on the first plane. This misalignment is essentially the misalignment between the upper structure (the structure subsequently formed in the second opening) and the lower structure (the preset structure in the substrate) of the semiconductor structure. It can be understood that the first deviation reflects the lithographic error during the formation of the photoresist layer, and the second deviation reflects the etching error during the patterning of the etching material layer based on the photoresist layer. Therefore, the lithographic compensation value obtained based on the first and second deviations can comprehensively characterize the influence of lithographic and etching errors on the misalignment between the second opening and the preset structure on the first plane. By using the lithographic compensation value to correct the first deviation, the influence of lithographic and etching errors on the misalignment between the second opening and the preset structure on the first plane can be eliminated. Furthermore, by separating the influence of lithographic and etching errors on the misalignment, this disclosure improves the speed of correcting the misalignment between the second opening and the preset structure on the first plane while avoiding over-adjustment when directly adjusting the misalignment through the second deviation.

[0071] Figure 2 This is a schematic cross-sectional view of a semiconductor structure after the photoresist layer has been formed in one embodiment, such as... Figure 2As shown, firstly, a substrate 102 is provided, which includes a preset structure 104 and an etching material layer 106 located on the preset structure 104. Secondly, a photoresist layer 108 is formed on the etching material layer 106, and a first opening 202 is formed in the photoresist layer 108. Thirdly, a first deviation D1 between the bottom of the first opening 202 and the top of the preset structure 104 on a first plane is obtained, and the first deviation D1 reflects the photolithographic error during the formation of the photoresist layer 108.

[0072] In one embodiment, the constituent materials of the etched material layer 106 include insulating materials, metallic materials, or semiconductor materials.

[0073] Figure 3 This is a schematic diagram illustrating the process of forming a photoresist layer on an etched material layer in one embodiment, as shown below. Figure 3 As shown, in one embodiment, forming a photoresist layer on the etched material layer includes:

[0074] S202, a photoresist material layer is formed on the etching material layer.

[0075] Specifically, photoresist is coated on the etch material layer 106 to form a photoresist material layer on the etch material layer 106. For example, the photoresist material layer is located on the upper surface of the etch material layer 106.

[0076] S204, perform photolithography to obtain a photoresist layer composed of the remaining photoresist material layer.

[0077] Specifically, a photolithography process is performed using a photomask corresponding to the photoresist layer. After exposure and development, a photoresist layer consisting of the remaining photoresist material layer is obtained, wherein the part where the photoresist is removed is the first opening 202.

[0078] In one embodiment, the bottom of the first opening 202 is flush with the upper surface of the etched material layer 106, at which point the bottom of the first opening exposes the upper surface of the etched material layer 106.

[0079] Figure 4 This is a schematic diagram illustrating the process of patterning an etching material layer based on a photoresist layer in one embodiment. Figure 5 for Figure 2 A cross-sectional schematic diagram of the semiconductor structure after the second opening is formed in one corresponding embodiment, see reference. Figure 2 , Figure 4In one embodiment, the substrate 102 further includes a hard mask material layer 110 located on the etch material layer 106. Exemplarily, the constituent material of the hard mask material layer 110 includes at least one of nitrides, oxynitrides, and oxides. At this time, the first opening 202 exposes a portion of the upper surface of the hard mask material layer 110; patterning the etch material layer 106 based on the photoresist layer 108 includes:

[0080] S302, Based on the photoresist layer, the hard mask material layer is patterned to obtain the hard mask layer.

[0081] Specifically, using the photoresist pattern layer 108 as a mask, the hard mask material layer 110 is patterned, and the hard mask material layer 110 exposed by the first opening 202 is removed until the etching material layer 106 below is exposed. The remaining hard mask material layer 110 is the hard mask layer.

[0082] S304, Based on the hard mask layer, the etching material layer is patterned to form a second opening in the etching material layer.

[0083] Specifically, using a hard mask layer as a mask, the etching material layer 106 is patterned to remove the etching material layer 106 exposed by the hard mask layer, thereby forming a second opening 204 penetrating the etching material layer 106. (See [reference]) Figure 5 Then, the second deviation D2 between the bottom of the second opening 204 and the bottom of the first opening 202 on the first plane is obtained. The second deviation D2 reflects the etching error when the second opening 204 is formed using the photoresist patterning layer 108 as a mask. When the substrate 102 includes a hard mask material layer 110 located on the etching material layer 106, the hard mask material layer 110 is patterned using the photoresist layer 108. The sum of the first etching error in etching to form the hard mask layer and the second etching error in patterning the etching material layer 106 using the hard mask layer to form the second opening 204 in the etching material layer 106 is the second deviation D2.

[0084] In one embodiment, a dry etching process is used to pattern the etched material layer 106 to form a second opening 204 in the etched material layer 106.

[0085] In one embodiment, the etched material layer 106 is located on the upper surface of the preset structure 104.

[0086] In one embodiment, the bottom of the second opening 204 is flush with the upper surface of the preset structure 104.

[0087] Figure 6This is a schematic diagram illustrating the process of obtaining the second deviation between the bottom of the second opening and the bottom of the first opening on a first plane in one embodiment, as shown below. Figure 5 , Figure 6 As shown, in one embodiment, obtaining the second deviation D2 between the bottom of the second opening 204 and the bottom of the first opening 202 on the first plane includes:

[0088] S402, obtain the third deviation between the bottom of the second opening and the top of the preset structure on the first plane.

[0089] Specifically, after etching to form the second opening 204, the third deviation D3 between the bottom of the second opening 204 and the top of the preset structure 104 on the first plane is measured.

[0090] S404, based on the third deviation and the first deviation, the second deviation is obtained.

[0091] Specifically, the first deviation D1 is the deviation between the bottom of the first opening 202 and the top of the preset structure 104 on the first plane, and the third error D3 is the deviation between the bottom of the second opening 204 and the top of the preset structure 104 on the first plane. The difference between the third deviation D3 and the first deviation D1 is the second deviation D2 between the bottom of the first opening 202 and the top of the second opening 204 on the first plane.

[0092] In one embodiment, the first deviation D1, the second deviation D2, and the third deviation D3 are all vectors, meaning they are numerical values ​​with direction. Adding or subtracting the first deviation D1, the second deviation D2, and the third deviation D3 is equivalent to adding or subtracting vectors. Therefore, the direction of etching and development offset can be determined using the first deviation D1, the second deviation D2, and the third deviation D3, and then corrections can be made.

[0093] Figure 7 This is a schematic diagram of the process for obtaining lithographic compensation values ​​based on the second deviation and the first deviation in one embodiment, as shown below. Figure 7 As shown, in one embodiment, the lithographic compensation value includes a first compensation value and a second compensation value. The lithographic compensation value is obtained based on the second deviation D2 and the first deviation D1, including:

[0094] S502, based on the first deviation, a first compensation value is obtained to eliminate the influence of the photolithography process on the misalignment.

[0095] Specifically, the first deviation D1 is the deviation between the bottom of the first opening 202 and the top of the preset structure 104 on the first plane after the photoresist layer 108 is formed. Essentially, it is the photolithography error during the formation of the photoresist layer 108. Therefore, the first compensation value obtained based on the first deviation can be used to eliminate the influence of the photolithography process on misalignment. Specifically, a non-zero first compensation value is added to the photolithography alignment system to eliminate the influence of the photolithography process. For example, batch feedback control is used to eliminate the influence of the photolithography process on misalignment.

[0096] S504, based on the second deviation, a second compensation value is obtained to eliminate the effect of patterning the etched material layer on misalignment.

[0097] Specifically, the second deviation D2 is the deviation between the bottom of the second opening 204 and the bottom of the first opening 202 on the first plane after patterning the etching material layer 106 based on the photoresist layer 108. Essentially, it represents the etching error during the formation of the second opening 204. Therefore, applying the second compensation value obtained from the second deviation D2 to adjust the photolithography process during the formation of the photoresist layer 108 can eliminate the influence of etching deviation on misalignment. Specifically, a non-zero second compensation value is added to the photolithography alignment system to eliminate the influence of the photolithography process. For example, batch feedback control is used to eliminate the influence of etching error during the formation of the second opening 204 on misalignment.

[0098] Specifically, the first deviation D1 is measured after development. It can be obtained by measuring the distribution map (MAP) of the first deviation D1 on several adjacent or spaced wafers (e.g., 4 or 5 wafers) in a batch after development. Then, batch feedback control is used to compensate for the corresponding first compensation value in the corresponding photolithography process, thereby eliminating the misalignment caused by the photolithography process itself to subsequent products. After etching to form the second opening 204, the distribution map (MAP) of the third deviation D3 on several adjacent or spaced wafers (e.g., 4 or 5 wafers) in a batch after etching is measured. Based on the distribution map of the third deviation D3 and the distribution map of the first deviation D1, the distribution map (MAP) of the second deviation D2 between the bottom of the first opening 202 and the top of the second opening 204 is obtained. Then, batch feedback control is used to compensate for the second compensation value corresponding to the distribution map of the second deviation D2 in the corresponding photolithography process, thereby eliminating the misalignment caused by the etching process itself to subsequent products.

[0099] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the photoresist layer is formed following the correction of the first deviation using photolithographic compensation values ​​in one embodiment. Figure 9 for Figure 8 A cross-sectional schematic diagram of the semiconductor structure after the second opening is formed in one corresponding embodiment, as shown below. Figure 8 , Figure 9 As shown, after adding a photolithography compensation value in the photolithography process, the deviation between the bottom of the first opening 202 and the top of the preset structure 104 in the photoresist layer 108 formed on the etching material layer 106 on the first plane becomes a fourth deviation D4. The fourth deviation D4 makes it so that after the etching material layer 106 is patterned with the photoresist layer 108, there is no misalignment between the bottom of the second opening 204 and the top of the preset structure 104.

[0100] It should be understood that, although Figure 1 , Figure 3 , Figure 4 , Figure 6 and Figure 7 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 3 , Figure 4 , Figure 6 and Figure 7 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0101] like Figure 9 As shown, in one embodiment, this disclosure also provides a semiconductor structure including a second opening 204, which is fabricated using the preparation method described in any of the preceding claims.

[0102] The aforementioned semiconductor structure includes a second opening 204. The method for fabricating the second opening 204 includes: obtaining a first deviation between the bottom of the first opening in the photoresist layer and the top of a preset structure in the substrate on a first plane, the first plane being parallel to the surface of the substrate; obtaining a second deviation between the bottom of the second opening in the etching material layer and the bottom of the first opening on the first plane; and then obtaining a photolithographic compensation value based on the second deviation and the first deviation. This photolithographic compensation value is used to correct the first deviation to eliminate the misalignment between the second opening and the preset structure on the first plane. In this disclosed technical solution, the first deviation reflects the photolithographic error during the formation of the photoresist layer, and the second deviation reflects the etching error during the formation of the second opening. Therefore, the photolithographic compensation value obtained based on the first and second deviations can comprehensively characterize the influence of photolithographic and etching errors on the misalignment between the second opening and the preset structure on the first plane. By using the photolithographic compensation value to correct the first deviation, the influence of photolithographic and etching errors on the misalignment between the second opening and the preset structure on the first plane can be eliminated. Meanwhile, by separating the effects of lithography error and etching error on misalignment, this disclosure improves the speed of correcting the misalignment between the second opening and the preset structure on the first plane, while avoiding the problem of over-adjustment when directly adjusting the misalignment between the second opening and the preset structure on the first plane through the second deviation.

[0103] Figure 10 This is a block diagram of the control system corresponding to the semiconductor structure in one embodiment, such as... Figure 10 As shown, this disclosure also provides a control system corresponding to a semiconductor structure. The method for fabricating the semiconductor structure includes providing a substrate, the substrate including a preset structure and an etching material layer located on the preset structure; forming a photoresist layer including a first opening on the etching material layer; performing patterning processing on the etching material layer based on the photoresist layer to obtain a second opening; the control system includes: a measurement module 302 and a calculation module 304, the measurement module 302 is used to measure a first deviation D1 between the bottom of the first opening and the top of the preset structure on a first plane, the first plane being parallel to the surface of the substrate; the measurement module 302 is also used to measure a second deviation D2 between the bottom of the second opening and the bottom of the first opening on the first plane; the calculation module 304 is connected to the measurement module 302 and is used to obtain a photolithographic compensation value based on the second deviation D2 and the first deviation D1, the photolithographic compensation value being used to correct the first deviation D1 to eliminate the misalignment between the second opening and the preset structure on the first plane.

[0104] In the control system corresponding to the aforementioned semiconductor structure, the measurement module is used to obtain a first deviation between the bottom of the first opening in the photoresist layer and the top of the preset structure in the substrate on a first plane, the first plane being parallel to the surface of the substrate; simultaneously, the measurement module is also used to obtain a second deviation between the bottom of the second opening in the etching material layer and the bottom of the first opening on the first plane. The calculation module obtains a photolithography compensation value based on the second deviation and the first deviation. This photolithography compensation value is used to correct the first deviation, thereby eliminating the misalignment between the second opening and the preset structure on the first plane. In the technical solution of this disclosure, the first deviation reflects the photolithography error during the formation of the photoresist layer, and the second deviation reflects the etching error during the formation of the second opening. Therefore, the photolithography compensation value obtained by the calculation module based on the first and second deviations can comprehensively characterize the influence of photolithography error and etching error on the misalignment between the second opening and the preset structure on the first plane. By using the photolithography compensation value to correct the first deviation, the influence of photolithography error and etching error on the misalignment between the second opening and the preset structure on the first plane can be eliminated. Meanwhile, by separating the effects of lithography error and etching error on misalignment, this disclosure improves the speed of correcting the misalignment between the second opening and the preset structure on the first plane, while avoiding the problem of over-adjustment when directly adjusting the misalignment between the second opening and the preset structure on the first plane through the second deviation.

[0105] In one embodiment, the photolithography compensation value includes a first compensation value and a second compensation value. The calculation module 304 includes a first calculation device and a second calculation device. The first calculation device is used to obtain the first compensation value based on the first deviation D1. The first compensation value is used to eliminate the influence of the photolithography process during the formation of the photoresist layer on the misalignment. The second calculation device is used to obtain the second compensation value based on the second deviation D2. The second compensation value is used to adjust the photolithography process to eliminate the influence of patterning the etched material layer on the misalignment.

[0106] In one embodiment, the measurement module 302 is further used to measure a third deviation D3 between the bottom of the second opening and the top of the preset structure on a first plane; the calculation module 304 is further used to obtain a second deviation D2 based on the third deviation D3 and the first deviation D1.

[0107] In one embodiment, the first deviation D1, the second deviation D2, and the third deviation D3 are all vectors, meaning they are numerical values ​​with direction. Adding or subtracting the first deviation D1, the second deviation D2, and the third deviation D3 is equivalent to adding or subtracting vectors. Therefore, the direction of etching and development offset can be determined using the first deviation D1, the second deviation D2, and the third deviation D3, and then corrections can be made.

[0108] This disclosure also provides a photolithography apparatus for forming a photoresist layer with a first opening. The photolithography apparatus is connected to a control system corresponding to any of the semiconductor structures described above, and is used to correct the position of the first opening in the photoresist layer according to the photolithography compensation value output by the control system.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The above-described embodiments are merely illustrative of several implementation methods of the present disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present disclosure embodiments, and these all fall within the protection scope of the present disclosure embodiments. Therefore, the protection scope of the patent for the embodiments of the present disclosure should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a preset structure and an etching material layer located on the preset structure; A photoresist layer is formed on the etching material layer, the photoresist layer including a first opening; Obtain the first deviation between the bottom of the first opening and the top of the preset structure on a first plane, the first plane being parallel to the surface of the substrate; The etching material layer is patterned based on the photoresist layer to obtain the second opening; Obtain the second deviation of the bottom of the second opening from the bottom of the first opening on the first plane; Based on the second deviation and the first deviation, a photolithography compensation value is obtained. The photolithography compensation value is used to correct the first deviation in order to eliminate the misalignment between the second opening and the preset structure on the first plane. The photolithography compensation value includes a first compensation value and a second compensation value, and obtaining the photolithography compensation value based on the second deviation and the first deviation includes: The first compensation value is obtained based on the first deviation, and the first compensation value is used to eliminate the influence of the photolithography process on the misalignment. A second compensation value is obtained based on the second deviation. The second compensation value is used to adjust the photolithography process to eliminate the influence of the patterning process on the misalignment. The step of obtaining the second deviation between the bottom of the second opening and the bottom of the first opening on the first plane includes: Obtain the third deviation between the bottom of the second opening and the top of the preset structure on the first plane; The second deviation is obtained based on the third deviation and the first deviation.

2. The preparation method according to claim 1, characterized in that, The bottom of the first opening is flush with the upper surface of the etched material layer.

3. The preparation method according to claim 1, characterized in that, The bottom of the second opening is flush with the upper surface of the preset structure.

4. The preparation method according to claim 1, characterized in that, The process of forming a photoresist layer on the etched material layer includes: A photoresist material layer is formed on the etching material layer; The photolithography process is performed to obtain a photoresist layer composed of the remaining photoresist material layer.

5. The preparation method according to claim 4, characterized in that, The substrate also includes a hard mask material layer located on the etching material layer; The step of patterning the etched material layer based on the photoresist layer includes: The hard mask material layer is patterned based on the photoresist layer to obtain the hard mask layer; The etching material layer is patterned based on the hard mask layer to form a second opening in the etching material layer.

6. The preparation method according to claim 5, characterized in that, The etching material layer is patterned using a dry etching process to form a second opening in the etching material layer.

7. The preparation method according to claim 1, characterized in that, The first deviation, the second deviation, and the third deviation are all vectors.

8. The preparation method according to claim 1, characterized in that, The constituent materials of the etched material layer include insulating materials, metallic materials, or semiconductor materials.

9. A semiconductor structure, characterized in that, include: The second opening is made using the preparation method described in any one of claims 1-8.

10. A control system corresponding to a semiconductor structure, wherein the control system executes the fabrication method according to any one of claims 1-8, characterized in that, The control system includes: The measurement module is used to measure a first deviation between the bottom of the first opening and the top of the preset structure on a first plane, the first plane being parallel to the surface of the substrate; it is also used to measure a second deviation between the bottom of the second opening and the bottom of the first opening on the first plane. The calculation module, connected to the measurement module, is used to obtain a photolithography compensation value based on the second deviation and the first deviation. The photolithography compensation value is used to correct the first deviation to eliminate the misalignment between the second opening and the preset structure on the first plane. The photolithography compensation value includes a first compensation value and a second compensation value, and the calculation module includes: A first computing device is configured to obtain a first compensation value based on the first deviation, wherein the first compensation value is used to eliminate the influence of the photolithography process during the formation of the photoresist layer on the misalignment. The second computing device is used to obtain a second compensation value based on the second deviation, and the second compensation value is used to adjust the photolithography process to eliminate the influence of the patterning process on the misalignment. The measurement module is also used to measure a third deviation between the bottom of the second opening and the top of the preset structure on a first plane; the calculation module is also used to obtain the second deviation based on the third deviation and the first deviation.

11. A photolithography apparatus, characterized in that, The photolithography equipment is used to form a photoresist layer with a first opening. The photolithography equipment is connected to the control system of claim 10 and is used to correct the position of the first opening in the photoresist layer according to the photolithography compensation value output by the control system.

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