Method for Determining Parasitic Inductance of MOSFET Power Loop

Abstract

The technical solution of this application provides a method for determining the parasitic inductance of a MOSFET power loop, including: providing an equivalent power circuit of a bridge-arm MOSFET power loop, the equivalent power circuit including a driving MOSFET and a freewheeling MOSFET connected in bridge and a parasitic inductance of the power loop, and obtaining the equivalent output capacitance of the driving MOSFET; performing a double-pulse test on the bridge-arm MOSFET power loop to obtain the relationship between the turn-off voltage and time of the driving MOSFET; obtaining the resonance frequency according to the relationship between the turn-off voltage and time of the driving MOSFET; and obtaining the parasitic inductance value according to the equivalent output capacitance and the resonance frequency. The technical solution of this application solves the problem that it is difficult to obtain the parasitic inductance of a MOSFET power loop without damaging the device.

Description

Technical Field

[0001] The present application relates to the field of MOSFET circuits, and particularly to a method for determining the parasitic inductance of a MOSFET power loop. Background Art

[0002] Power semiconductor devices play an extremely important role in power electronics technology. As the core part of a power converter, the development level of power switching devices largely determines the development level of power electronic equipment.

[0003] Power switching devices such as MOSFETs and IGBTs based on Si material power semiconductors are the most widely used in the industry. However, due to the limitations of the Si material itself, its development is extremely restricted, and its characteristics have approached the theoretical limit, becoming a bottleneck for the further development of power electronic converters. The on-resistance of Si material semiconductors is relatively high at typical application voltage levels of 1200V and 1700V, resulting in relatively high switching losses for Si material power semiconductor devices. In addition, the bandgap width and thermal conductivity of Si devices are both small, limiting the maximum power and maximum operating temperature of the devices.

[0004] In high-voltage and high-power application scenarios, SiC material power semiconductors have obvious advantages. SiC material power semiconductors have good characteristics such as high breakdown voltage, high thermal conductivity, and high switching frequency, which have enabled the rapid development of SiC material power semiconductor devices in recent years and their wide commercial application. There are more and more designs, solutions, and products that use SiC material power semiconductor devices as the core components of power electronic converters. Compared with Si power devices, SiC power devices have more excellent characteristics: SiC power devices have a higher switching speed, can operate at a higher junction temperature, and can simultaneously achieve high frequency, high voltage, and large current. These characteristics can significantly improve the performance of semiconductor power converters, obtain higher power conversion efficiency, achieve higher power density, and reduce system costs, etc.

[0005] Based on the application experience of designing Si material power semiconductor devices in the past, in actual applications, SiC material power semiconductor devices still follow the driving design ideas and methods of traditional Si material power semiconductor devices. However, since SiC material power semiconductor devices generally have a faster switching speed and a higher voltage withstand capacity, and have a higher voltage change rate compared with Si devices, the influence of each parameter in the driving loop on the overall performance of the power electronic converter is more prominent. When applied to a bridge arm, the problem of gate-source voltage interference is also more serious.

[0006] As a typical device of power semiconductors made of SiC materials, the research on the characteristics of SiC MOSFET itself and its application design has very important practical significance. At present, the research on SiC MOSFET mainly focuses on the establishment of the device model itself and the testing of its excellent performance, while the analysis and research on the model of the SiC MOSFET power loop and the influence of parasitic parameters are extremely limited. Summary of the Invention

[0007] The technical problem to be solved by this application is to determine the parasitic inductance of the MOSFET power loop.

[0008] To solve the above technical problem, this application provides a method for determining the parasitic inductance of the MOSFET power loop, including: providing an equivalent power circuit of the bridge arm MOSFET power loop, the equivalent power circuit including a driven MOSFET and a freewheeling MOSFET connected in bridge and the parasitic inductance of the power loop, and obtaining the equivalent output capacitance of the driven MOSFET; performing a double-pulse test on the bridge arm MOSFET power loop to obtain the relationship between the turn-off voltage and time of the driven MOSFET; obtaining the resonance frequency according to the relationship between the turn-off voltage and time of the driven MOSFET; obtaining the value of the parasitic inductance of the power loop according to the equivalent output capacitance and the resonance frequency.

[0009] In some embodiments of this application, the equivalent output capacitance of the driven MOSFET is obtained according to the capacitance-voltage characteristic curve of the driven MOSFET.

[0010] In some embodiments of this application, the equivalent power loop further includes: a load inductance, loaded on the source and drain of the freewheeling MOSFET; a bus capacitor, the first end of the bus capacitor is electrically connected to the source of the driven MOSFET; wherein the first end of the parasitic inductance of the power loop is electrically connected to the second end of the bus capacitor, and the second end of the parasitic inductance of the power loop is electrically connected to the drain of the freewheeling MOSFET.

[0011] In some embodiments of this application, the parasitic inductance of the power loop includes device package inductance, PCB line inductance and bus capacitor equivalent series inductance.

[0012] In some embodiments of this application, the method for obtaining the resonance frequency includes: obtaining the oscillation period of the turn-off voltage of the driven MOSFET according to the relationship between the turn-off voltage and time of the driven MOSFET; obtaining the resonance frequency based on the oscillation period.

[0013] In some embodiments of this application, the value of the parasitic inductance of the power loop is calculated according to the following formula (2): Among them, L LOOP is the parasitic inductance value of the power loop, C OSS is the equivalent output capacitance for driving the MOSFET, and f0 is the resonant frequency.

[0014] In some embodiments of the present application, the method for obtaining the parasitic inductance value of the power loop includes: obtaining a simplified circuit of the equivalent power circuit based on the voltage overshoot and oscillation process when the driving MOSFET is turned off; converting the simplified circuit into a small-signal circuit based on the fact that both the voltage overshoot and oscillation process occur in the high-frequency band; and obtaining the parasitic inductance value of the power loop according to the small-signal circuit.

[0015] In some embodiments of the present application, the simplified circuit includes: an equivalent circuit of the driving MOSFET, including a current source in parallel and an equivalent output capacitance; an equivalent circuit of the freewheeling MOSFET, including a voltage source in series and an internal resistance; an equivalent circuit of the load inductance, in parallel with the equivalent circuit of the freewheeling MOSFET and including a constant current source; and a parasitic inductance of the power loop and a bus voltage source in series with the equivalent circuit of the driving MOSFET and the equivalent circuit of the freewheeling MOSFET.

[0016] In some embodiments of the present application, the small-signal circuit includes: the current source and an RLC parallel resonance circuit electrically connected across the current source, where the RLC parallel resonance circuit includes: the equivalent output capacitance, and the internal resistance and the parasitic inductance of the power loop in series.

[0017] In some embodiments of the present application, the method for obtaining the parasitic inductance value of the power loop according to the small-signal circuit includes: obtaining the following formula (1) based on the small-signal circuit: f0 is the resonant frequency, L LOOP is the parasitic inductance value of the power loop, C OSS is the equivalent output capacitance for driving the MOSFET; performing formula transformation on the formula (1) to obtain the calculation formula for the parasitic inductance value of the power loop.

[0018] In some embodiments of the present application, in the power loop of the bridge-arm MOSFET, the method for determining the resistance value of the driving resistance of the driving MOSFET includes: setting the resistance value of the driving resistance of the driving MOSFET to a preset value; obtaining the actual voltage overshoot peak value of the driving MOSFET through double-pulse testing; and determining whether the preset value is appropriate according to the actual voltage overshoot peak value of the driving MOSFET and the safety threshold of the voltage overshoot peak value.

[0019] In some embodiments of the present application, the preset value is set in a descending order, so that the actual margin between the actual voltage overshoot peak value and the safety threshold gradually approaches the target margin.

[0020] In some embodiments of the present application, the method for determining whether the preset value is appropriate includes: confirming that the actual voltage overshoot peak value is lower than the safety threshold and the actual margin reaches the target margin, then the preset value is appropriate.

[0021] In some embodiments of the present application, the method for determining whether the preset value is appropriate includes: confirming that the actual voltage overshoot peak value is lower than the safety threshold, but the actual margin is greater than the target margin, then the preset value is too large and the preset value needs to be decreased.

[0022] In some embodiments of the present application, both the driving MOSFET and the freewheeling MOSFET are SiC MOSFETs.

[0023] The method for determining the parasitic inductance of the MOSFET power loop in the technical solution of the present application obtains the relationship between the turn-off voltage and time based on a small-signal analysis model, and then extracts relevant parameters from the relationship between the turn-off voltage and time, which can solve the problem that it is difficult to obtain the parasitic inductance of the MOSFET power loop without damaging the device.

[0024] When determining the resistance value of the driving resistor of the MOSFET power loop, first set the resistance value of the driving resistor to a preset value, then obtain the voltage overshoot peak value of the driving MOSFET through double-pulse testing, and then determine whether the preset value is appropriate by comparing the actual voltage overshoot peak value of the driving MOSFET with the safety threshold of the voltage overshoot peak value. Further, the preset value is set in a descending order, so that the actual margin between the actual voltage overshoot peak value and the safety threshold gradually approaches the target margin, which can avoid the situation that the actual voltage overshoot peak value exceeds the safety threshold and damages the device at the beginning stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive intent in the present application. It should be understood that the drawings are not drawn to scale. Wherein:

[0026] Figure 1 is a schematic flow chart of the method for determining the parasitic inductance of the MOSFET power loop according to the embodiment of the present application;

[0027] Figure 2 It is a schematic diagram of an equivalent power circuit of the bridge arm MOSFET power loop according to an embodiment of the present application;

[0028] Figure 3 It is another schematic diagram of an equivalent power circuit of the bridge arm MOSFET power loop according to an embodiment of the present application;

[0029] Figure 4 It is a waveform diagram of the turn-off voltage and time for driving the MOSFET;

[0030] Figure 5 It is a schematic diagram of a simplified circuit during the turn-off process of the equivalent power circuit according to an embodiment of the present application;

[0031] Figure 6 It is a schematic diagram of the small-signal circuit according to an embodiment of the present application. Detailed implementation manners

[0032] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the figures represent the same structure or operation.

[0033] It should be understood that the "system" and "device" used herein are a way to distinguish different components, elements, parts, portions or assemblies at different levels. However, if other words can achieve the same purpose, the said words can be replaced by other expressions.

[0034] As shown in the present application and the claims, unless the context clearly indicates an exception, words such as "a", "an", "one" and / or "the" are not specifically singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0035] The terms used in this application are for the purpose of describing specific example embodiments only and are not restrictive. For example, unless the context clearly dictates otherwise, as used herein, the singular forms "a", "an" and "the" may also include the plural forms. When used in this specification, the terms "comprising", "including" and / or "containing" mean that the associated integers, steps, operations, elements and / or components exist, but do not preclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When describing the association of different components in this specification, it can be a direct relationship or an indirect relationship. For example, "A and B are connected" can mean that A and B are directly connected, or that A and B are indirectly connected through other components.

[0036] In view of the following description, the features disclosed in this specification and other features, as well as the operations and functions of the related elements of the structure, and the combination and manufacturing economy of the components can be significantly improved. Referring to the accompanying drawings, all of these form a part of the disclosure of this specification. However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the disclosure of this specification. Flowcharts are used in this application to illustrate the operations performed by the systems according to the embodiments of this application. It should be understood that the operations before or after do not necessarily have to be executed precisely in order. On the contrary, the steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0037] The following description provides specific application scenarios and requirements of this application, aiming to enable those skilled in the art to manufacture and use the content of this application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and without departing from the spirit and scope of this application, the general principles defined here can be applied to other embodiments and applications. Therefore, this application is not limited to the disclosed embodiments, but to the broadest scope consistent with the claims.

[0038] In the traditional converter design process, it is common to design the power circuit based on the device parameters provided by the SiC MOSFET manufacturer and then make samples; after testing the prototype, the design is improved. In most cases, designers directly make the prototype and then optimize the design after testing. This method will take more time and the final design can only be obtained after multiple iterations. At the same time, the failure of the prototype circuit board will also cause designers to spend more time troubleshooting and correcting.

[0039] When testing the prototype, the parasitic inductance of the power loop is difficult to accurately measure directly; since the power loop layouts of different prototypes are different, it is difficult to obtain accurate values of this parasitic inductance parameter through theoretical calculations. In many designs, the parasitic inductance parameter is often estimated based on experience and then corrected through testing. However, the parasitic inductance of the power loop directly affects the magnitude of the peak turn-off overvoltage of the SiCMOSFET. If the value of this parasitic inductance is large and a double-pulse test is directly carried out, the excessive voltage spike may cause direct damage to the device. Therefore, the parasitic inductance of the power loop is extremely important for the application reliability of SiC MOSFETs.

[0040] After the prototype is manufactured, it is necessary to perform a double-pulse test without knowing the parasitic parameters of the power loop, and then judge the rationality of the power loop parameter settings based on the waveform. This operation has a relatively high risk. Improper layout of the prototype circuit board or improper setting of the power loop parameters may cause the failure of the SiC MOSFET device itself, resulting in designers spending more time troubleshooting the reasons and correcting the design parameters.

[0041] Based on this, the technical solution of this application provides a method for determining the parasitic inductance of the MOSFET power loop, which uses special loop parameters and signals that do not damage the device, and obtains the parasitic inductance of the power loop through waveform analysis to guide and optimize the prototype design and testing.

[0042] Reference Figure 1 , the method for determining the parasitic inductance of the MOSFET power loop in the embodiment of this application includes:

[0043] Step S1: Provide an equivalent power circuit of the bridge arm MOSFET power loop, the equivalent power circuit includes a driving MOSFET and a freewheeling MOSFET connected in bridge and the parasitic inductance of the power loop, and obtain the equivalent output capacitance of the driving MOSFET;

[0044] Step S2: Perform a double-pulse test on the bridge arm MOSFET power loop to obtain the relationship between the turn-off voltage and time of the driving MOSFET;

[0045] Step S3: Obtain the resonance frequency according to the relationship between the turn-off voltage and time of the driving MOSFET;

[0046] Step S4: Obtain the parasitic inductance value of the power loop according to the equivalent output capacitance and the resonance frequency.

[0047] Reference Figure 2 , first establish an equivalent power circuit of the bridge arm MOSFET power loop. The equivalent power circuit may include a driving MOSFET Q L and a freewheeling MOSFET Q H, driving MOSFET Q L and freewheeling MOSFET Q H can be a SiC MOSFET or a semiconductor switch of other materials. The source and drain of the freewheeling MOSFET Q H are loaded with a load inductor L, and the source of the driving MOSFET Q L and the drain of the freewheeling MOSFET Q H are also connected in series with a device package inductor L LEAK , a bus capacitor C BUS , an equivalent series inductance L of the bus capacitor CBUS and a PCB line inductance L PCB . Among them, the device package inductor L LEAK , the equivalent series inductance L of the bus capacitor CBUS and the PCB line inductance L PCB can be equivalent to a power loop parasitic inductance L Loop , and for the equivalent power circuit at this time, please refer to Figure 3 . The first end of the bus capacitor C BUS is electrically connected to the source of the driving MOSFET, and the second end of the bus capacitor C BUS is electrically connected to the first end of the power loop parasitic inductance L Loop , and the second end of the power loop parasitic inductance L Loop is electrically connected to the drain of the freewheeling MOSFET Q H .

[0048] To obtain the equivalent output capacitance Coss of the driving MOSFET Q L , it can be obtained through the capacitance-voltage characteristic curve (C-V curve) of the driving MOSFET Q L . The C-V curve of the driving MOSFET Q L can be obtained from the specification sheet.

[0049] Then, perform a double-pulse test on the bridge arm MOSFET power loop to obtain the relationship between the turn-off voltage V L of the driving MOSFET Q DS and time t, and this relationship can be represented by a waveform diagram. In the embodiments of the present application, the waveform diagram of the turn-off voltage V L of the driving MOSFET Q DS and time t is as shown in Figure 4 .

[0050] According to the waveform diagram of the turn-off voltage V L of the driving MOSFET Q DS and time t, obtain the turn-off voltage VDS The resonant frequency f0. The method for determining the resonant frequency may include: according to the driving MOSFET Q L 's turn-off voltage V DS versus time t relationship, obtain the turn-off voltage V L of the driving MOSFET Q DS 's oscillation period T0; based on the oscillation period T0, obtain the resonant frequency f0: f0 = 1 / T0.

[0051] Combined with the equivalent output capacitance Coss and the resonant frequency f0 obtained above, obtain the parasitic inductance value of the power loop. The method for obtaining the parasitic inductance value of the power loop may include:

[0052] Step 41: Based on the voltage overshoot and oscillation process when the driving MOSFET turns off, obtain the simplified circuit of the equivalent power circuit;

[0053] Step 42: Based on the fact that both the voltage overshoot and the oscillation process occur in the high-frequency band, convert the simplified circuit into a small-signal circuit;

[0054] Step 43: Obtain the parasitic inductance value of the power loop according to the small-signal circuit.

[0055] During the voltage overshoot and oscillation process when the driving MOSFET Q L turns off, the states of all devices in the circuit are fixed. Therefore, the equivalent power circuit described above can be further simplified appropriately. When the driving MOSFET Q L turns off, its channel can be equivalently regarded as a current source I L that decreases from the load current I DS to 0; the body diode of the freewheeling MOSFET Q H conducts freewheeling, and it can be regarded as a voltage source V F in series with an internal resistance R F ; when the turn-off voltage V DS is high enough, the equivalent output capacitance C L of the driving MOSFET Q OSS is a constant value; when not considering the equivalent parallel capacitance of the load inductance L, the inductance of the load inductance L is very large, and it can be approximately considered that its current is basically unchanged during the whole process, and it is regarded as a constant current source I L , and the simplified circuit during the turn-off process is as shown in Figure 5 .

[0056] Refer to Figure 5, the simplified circuit includes: the equivalent circuit of the driving MOSFET, the equivalent circuit of the freewheeling MOSFET, the equivalent circuit of the load inductor, and the parasitic inductance L of the power loop connected in series with the equivalent circuit of the driving MOSFET and the equivalent circuit of the freewheeling MOSFET LOOP and the bus voltage source V BUS . The equivalent circuit of the driving MOSFET includes a current source I connected in parallel DS and the equivalent output capacitance C OSS . The equivalent circuit of the freewheeling MOSFET includes a voltage source V connected in series F and the internal resistance RF. The equivalent circuit of the load inductor L is connected in parallel with the equivalent circuit of the freewheeling MOSFET and includes a constant current source I L .

[0057] Since the turn-off voltage V DS overshoot and oscillation both occur in the high-frequency band, the constant current source I in the above simplified circuit can be treated as an open circuit, the bus voltage source V L and the voltage source V BUS are treated as short circuits, and a small-signal circuit during the turn-off process is further obtained, as shown in F . Looking in from the current source I Figure 6 , that is, the drain-source terminal of Q DS , it belongs to an RLC parallel resonance circuit. The small-signal circuit includes: the current source I L and the RLC parallel resonance circuit electrically connected across the current source I DS , where the RLC parallel resonance circuit includes: the equivalent output capacitance C DS , and the internal resistance R connected in series OSS and the parasitic inductance L of the power loop F . LOOP .

[0058] Based on the small-signal circuit, the following formula (1) is obtained:

[0059]

[0060] Formula (1) is obtained from the resonance frequency formula, where f0 in the formula is the resonance frequency, L LOOP is the value of the parasitic inductance of the power loop, and C OSS is the equivalent output capacitance of the driving MOSFET;

[0061] By transforming the formula (1), the calculation formula (2) of the parasitic inductance value of the power loop is obtained:

[0062]

[0063] Among them, LLOOP is the parasitic inductance value of the power loop, C OSS is the equivalent output capacitance of the driving MOSFET, and f0 is the resonance frequency.

[0064] During the turn-off process of the driving MOSFET, the turn-off current I DS of the driving MOSFET rapidly drops from the load current I L to zero. The rapidly changing current will generate a voltage drop across the parasitic inductance L Loop of the power loop, resulting in obvious overshoot and oscillation on the turn-off voltage V DS of the driving MOSFET. When the turn-off voltage V DS has overshoot and is higher than the breakdown voltage value of the driving MOSFET, it may cause overvoltage failure of the driving MOSFET. Therefore, it is necessary to explore the mechanism of voltage overshoot and effectively suppress it to ensure that the driving MOSFET operates in the safe operating area.

[0065] The peak value of voltage overshoot V DS-P is affected by the parasitic inductance L Loop of the power loop and the current decay rate dI DS (off) / dt, and follows the relationship of V DS-p = L Loop * dI DS (off) / dt. Therefore, the larger the parasitic inductance L Loop of the power loop or the current decay rate d DS (off) / dt, the higher the peak value of voltage overshoot V DS-P . When the driving MOSFET is turned off under the same external driving resistance R G(EXT) , the peak value of voltage overshoot V DS-P continually increases with the increase of the parasitic inductance L Loop of the power loop, and the drain-source voltage V DS oscillates more violently. When the driving MOSFET is turned off under the same parasitic inductance L Loop of the power loop, as the driving resistance R DS-P decreases, the turn-off speed of the driving MOSFET increases, the current decay rate dI G(EXT) (off) / dt increases, the peak value of voltage overshoot V DS increases, and the turn-off voltage V DS-P oscillates more violently. When the parasitic inductance L DS of the power loop remains unchanged, the faster the turn-off speed, that is, the larger the current decay rate dI Loop (off) / dt, the higher the peak value of voltage overshoot V DS , and the turn-off voltage V DS-P is higher, and the turn-off voltage V DSThe more violent the oscillation is. If the power circuit is determined, the drive resistance R G(EXT) The resistance value can reduce the shutdown speed and achieve the purpose of limiting the shutdown voltage spike.

[0066] Therefore, the embodiment of the present application also provides a method for determining the resistance value of the driving resistor of the driving MOSFET, so as to prevent excessive voltage spikes from being generated in the process of determining the parasitic inductance of the MOSFET power loop, thereby preventing the device from being damaged.

[0067] The method for determining the resistance value of a driving resistor in an embodiment of the present application may include: setting the resistance value of the driving resistor of the driving MOSFET to a preset value; obtaining an actual voltage overshoot peak value of the driving MOSFET through a double pulse test; and judging whether the preset value is appropriate based on the actual voltage overshoot peak value of the driving MOSFET and a safety threshold value of the voltage overshoot peak value.

[0068] When actually determining the driving resistor value, the preset value can be set in a manner from large to small, and try not to use a small resistor as the driving resistor at the beginning, so as to avoid the situation in which the actual voltage overshoot peak value exceeds the safety value and damages the device at the beginning. Therefore, the preset value of the embodiment of the present application is set in a manner from large to small, so that the actual margin between the actual voltage overshoot peak value and the safety threshold gradually approaches the target margin. The method for judging whether the preset value is appropriate includes: if it is confirmed that the actual voltage overshoot peak value is lower than the safety threshold, and the actual margin reaches the target margin, then the preset value is appropriate; if it is confirmed that the actual voltage overshoot peak value is lower than the safety threshold, but the actual margin is greater than the target margin, then the preset value is too large and the preset value needs to be reduced. The target margin refers to the difference between the expected voltage overshoot peak value of the driving MOSFET and the safety threshold, which is determined according to the actual situation.

[0069] Specifically, a large resistance driving resistor is set at the beginning. At this time, the actual voltage overshoot peak value of the driving MOSFET will be much lower than the safety threshold, that is, the actual margin between the actual voltage overshoot peak value and the safety threshold is large, that is, the actual margin is much larger than the target margin. Setting a large resistance at the beginning can limit the current drop rate dI DS (off) / dt, to prevent voltage overshoot peak value V DS-P Then gradually reduce the driving resistance value to make the actual margin gradually approach the target margin, and ensure that the voltage overshoot peak value V DS-P When the current is within the safe operating area, relax the current drop rate dI DS (off) / dt limitation.

[0070] In summary, after reading the content of this application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

Claims

1. A method for determining the parasitic inductance of a MOSFET power loop, characterized in that Including: Providing an equivalent power circuit of a bridge-arm MOSFET power loop, the equivalent power circuit including a driven MOSFET and a freewheeling MOSFET connected in bridge and a parasitic inductance of the power loop, and obtaining an equivalent output capacitance of the driven MOSFET; Performing a double-pulse test on the bridge-arm MOSFET power loop to obtain the relationship between the turn-off voltage and time of the driven MOSFET; Obtaining a resonance frequency according to the relationship between the turn-off voltage and time of the driven MOSFET; Obtaining a parasitic inductance value of the power loop according to the equivalent output capacitance and the resonance frequency, wherein the method for obtaining the parasitic inductance value of the power loop includes: obtaining a simplified circuit of the equivalent power circuit based on the voltage overshoot and oscillation process when the driven MOSFET turns off; Based on that both the voltage overshoot and the oscillation process occur in the high-frequency band, converting the simplified circuit into a small-signal circuit; obtaining the parasitic inductance value of the power loop according to the small-signal circuit.

2. The method for determining the parasitic inductance of the MOSFET power loop according to claim 1, wherein Obtaining the equivalent output capacitance of the driven MOSFET according to the capacitance-voltage characteristic curve of the driven MOSFET.

3. The method for determining the parasitic inductance of the MOSFET power loop according to claim 1, wherein The equivalent power loop further includes: A load inductor, loaded on the source and drain of the freewheeling MOSFET; A bus capacitor, the first end of the bus capacitor being electrically connected to the source of the driven MOSFET; Wherein the first end of the parasitic inductance of the power loop is electrically connected to the second end of the bus capacitor, and the second end of the parasitic inductance of the power loop is electrically connected to the drain of the freewheeling MOSFET.

4. The method for determining the parasitic inductance of the MOSFET power loop according to claim 3, wherein The parasitic inductance of the power loop includes a device package inductance, a PCB line inductance and an equivalent series inductance of the bus capacitor.

5. The method for determining the parasitic inductance of the MOSFET power loop according to claim 1, wherein The method for obtaining the resonance frequency includes: Obtaining the oscillation period of the turn-off voltage of the driven MOSFET according to the relationship between the turn-off voltage and time of the driven MOSFET; Obtaining the resonance frequency based on the oscillation period.

6. The method for determining the parasitic inductance of the MOSFET power loop according to claim 1, wherein Calculating the parasitic inductance value of the power loop according to the following formula (2): Among them, L LOOP is the parasitic inductance value of the power loop, C OSS is the equivalent output capacitance for driving the MOSFET, and f0 is the resonance frequency.

7. The method for determining the parasitic inductance of the MOSFET power loop according to claim 1, wherein The simplified circuit includes: An equivalent circuit of the driven MOSFET, including a current source connected in parallel and an equivalent output capacitance; An equivalent circuit of the freewheeling MOSFET, including a voltage source connected in series and an internal resistance; An equivalent circuit of the load inductor, connected in parallel with the equivalent circuit of the freewheeling MOSFET and including a constant current source; and A parasitic inductance of the power loop and a bus voltage source connected in series with the equivalent circuit of the driven MOSFET and the equivalent circuit of the freewheeling MOSFET.

8. The method for determining the parasitic inductance of the MOSFET power loop according to claim 7, wherein The small-signal circuit includes: The current source and an RLC parallel resonance circuit electrically connected across the current source, wherein the RLC parallel resonance circuit includes: The equivalent output capacitance, and the internal resistance and the parasitic inductance of the power loop connected in series.

9. The method for determining the parasitic inductance of the MOSFET power loop according to claim 8, wherein The method for obtaining the parasitic inductance value of the power loop according to the small-signal circuit includes: Obtaining the following formula (1) based on the small-signal circuit: f0 is the resonant frequency, L LOOP is the parasitic inductance value of the power loop, C OSS is the equivalent output capacitance of the driving MOSFET; Performing formula transformation on the formula (1) to obtain a calculation formula for the parasitic inductance value of the power loop.

10. The method for determining the parasitic inductance of the MOSFET power loop according to claim 1, wherein In the bridge-arm MOSFET power loop, the method for determining the resistance value of the driving resistance of the driven MOSFET includes: Set the driving resistance value of the driving MOSFET to a preset value; Obtain the actual voltage overshoot peak value of the driving MOSFET through double-pulse testing; Judge whether the preset value is appropriate according to the actual voltage overshoot peak value of the driving MOSFET and the safety threshold of the voltage overshoot peak value.

11. The method for determining the parasitic inductance of the MOSFET power loop according to claim 10, wherein The preset value is set in a decreasing order, so that the actual margin between the actual voltage overshoot peak value and the safety threshold gradually approaches the target margin.

12. The method for determining the parasitic inductance of the MOSFET power loop according to claim 11, wherein The method for judging whether the preset value is appropriate includes: confirming that the actual voltage overshoot peak value is lower than the safety threshold and the actual margin reaches the target margin, then the preset value is appropriate.

13. The method for determining the parasitic inductance of the MOSFET power loop according to claim 11, wherein, The method for judging whether the preset value is appropriate includes: confirming that the actual voltage overshoot peak value is lower than the safety threshold, but when the actual margin is greater than the target margin, the preset value is too large and the preset value needs to be reduced.

14. The method for determining the parasitic inductance of the MOSFET power loop according to claim 1, wherein Both the driving MOSFET and the freewheeling MOSFET are SiC MOSFETs.

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