Memory device containing dual etch stop layer for selector element and method of manufacturing the same

Abstract

A refractory metal-containing etch stop layer, a ruthenium etch stop layer, and a conductive material layer can be formed in sequence over the electrode layer and the selector material layer. A series of anisotropic etch processes can be employed to etch the conductive material layer with selectivity to the ruthenium etch stop layer, etch the ruthenium etch stop layer with selectivity to the refractory metal-containing etch stop layer, and etch the refractory metal-containing etch stop layer into the electrode layer with minimal over-etch. The selector material layer can then be anisotropically etched without exposure to a plasma of etchant gas to etch the refractory metal-containing etch stop layer and the conductive material layer, which can include a fluorine-containing plasma that would damage the selector material.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non-Provisional Application No. 16 / 910,799, filed June 24, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of memory devices, and in particular to a method of patterning a selector element of a magnetoresistive random access memory (MRAM) memory device using a dual etch stop layer, and a device formed using the method. BACKGROUND

[0004] Spin transfer torque (“STT”) refers to an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve is modified by a spin-polarized current. Generally, a current is non-polarized, with electrons having random spin orientations. A spin-polarized current is a current in which electrons have a non-zero net spin due to a preferential spin orientation distribution. A spin-polarized current can be generated by passing a current through a magnetically polarized layer. When a spin-polarized current flows through a free layer of a magnetic tunnel junction or spin valve, electrons in the spin-polarized current can transfer at least some of their angular momentum to the free layer, thereby creating a torque on the magnetization of the free layer. When a sufficient amount of spin-polarized current passes through the free layer, the spin transfer torque can be employed to flip the spin orientation (e.g., change the magnetization) in the free layer. A difference in resistance of the magnetic tunnel junction between different magnetization states of the free layer can be employed to store data within a magnetoresistive random access memory (MRAM) cell, depending on whether the magnetization of the free layer is parallel or anti-parallel to the magnetization of a polarizing layer (also referred to as a reference layer). SUMMARY

[0005] According to aspects of the present disclosure, a method of forming a memory device includes forming a layer stack over a substrate, the layer stack including a lower electrode layer, a selector material layer, an upper electrode layer, a refractory metal-containing etch stop layer, a ruthenium etch stop layer, a conductive material layer, and at least one memory material layer; patterning the at least one memory material layer into memory elements; patterning the conductive material layer into conductive pillars using the ruthenium etch stop layer as an etch stop point by performing a first anisotropic etch process having a first etch chemistry that etches the conductive material layer selectively with respect to ruthenium; patterning the ruthenium etch stop layer into ruthenium plates using the refractory metal-containing etch stop layer as an etch stop point by performing a second anisotropic etch process having a second etch chemistry that etches ruthenium selectively with respect to a material of the refractory metal-containing etch stop layer; patterning the refractory metal-containing etch stop layer into refractory metal-containing etch stop plates by performing a third anisotropic etch process having a third etch chemistry that etches a material of the refractory metal-containing etch stop layer selectively with respect to a material of the upper electrode layer without etching through the upper electrode layer; and anisotropically etching the upper electrode layer, the selector material layer, and the lower electrode layer by performing an additional anisotropic etch process.

[0006] According to another aspect of the present disclosure, a memory device includes a first conductive line; a memory pillar structure including a lower electrode plate, a selector material plate, an upper electrode plate, a refractory metal-containing etch stop plate, a ruthenium etch stop plate, a conductive pillar, and a memory element, and overlying the first conductive line; and a second conductive line overlying the memory pillar structure. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1A is a top-down view of an exemplary structure for forming a cross-point memory device after forming a dielectric etch stop layer, a first dielectric isolation layer, and a first line trench extending vertically through the first dielectric isolation layer according to embodiments of the present disclosure.

[0008] Figure 1B is a vertical cross-sectional view of the exemplary structure taken along a vertical plane B-B' of Figure 1A

[0009] Figure 1C is a vertical cross-sectional view of the exemplary structure taken along a vertical plane C-C' of Figure 1A

[0010] Figure 2A ​​is a top-down view of an exemplary structure after forming a first conductive line according to embodiments of the disclosure.

[0011] Figure 2B is a vertical cross-sectional view of the exemplary structure taken along vertical plane B-B' of Figure 2A

[0012] Figure 2C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C' of Figure 2A

[0013] Figure 3A is a top-down view of an exemplary structure after forming a layer stack including a lower electrode layer, an optional lower metal compound liner, a selector material layer, an optional upper metal compound liner, an upper electrode layer, a refractory metal-containing etch stop layer, a ruthenium etch stop layer, a conductive material layer, at least one memory material layer, and a metal cap layer according to embodiments of the disclosure.

[0014] Figure 3B is a vertical cross-sectional view of the exemplary structure taken along vertical plane B-B' of Figure 3A

[0015] Figure 3C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C' of Figure 3A

[0016] Figure 4A is a top-down view of an exemplary structure after patterning a metal cap layer and at least one memory material layer according to embodiments of the disclosure.

[0017] Figure 4B is a vertical cross-sectional view of the exemplary structure taken along vertical plane B-B' of Figure 4A

[0018] Figure 4C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C' of Figure 4A

[0019] Figure 5A is a top-down view of an exemplary structure after patterning a conductive material layer according to embodiments of the disclosure.

[0020] Figure 5B is a vertical cross-sectional view of the exemplary structure taken along vertical plane B-B' of Figure 5A

[0021] Figure 5C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C' of Figure 5A ​​​​​​​​

[0022] Figure 6A is a top view of an exemplary structure after patterning a ruthenium etch stop layer according to embodiments of the present disclosure.

[0023] Figure 6B is a vertical cross-sectional view of the exemplary structure taken along vertical plane B-B' of Figure 6A

[0024] Figure 6C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C' of Figure 6A

[0025] Figure 7A is a top view of an exemplary structure after patterning a refractory metal-containing etch stop layer according to embodiments of the present disclosure.

[0026] Figure 7B is a vertical cross-sectional view of the exemplary structure taken along vertical plane B-B' of Figure 7A

[0027] Figure 7C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C' of Figure 7A

[0028] Figure 8A is a top view of an exemplary structure after patterning a stack of an upper electrode layer, an optional upper metal compound liner, a selector material layer, an optional lower metal compound liner, and a lower electrode layer according to embodiments of the present disclosure.

[0029] Figure 8B is a vertical cross-sectional view of the exemplary structure taken along vertical plane B-B' of Figure 8A

[0030] Figure 8C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C' of Figure 8A

[0031] Figure 9A is a top view of an exemplary structure after forming a dielectric isolation structure according to embodiments of the present disclosure.

[0032] Figure 9B is a vertical cross-sectional view of the exemplary structure taken along vertical plane B-B' of Figure 9A

[0033] Figure 9C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C' of Figure 9A

[0034] Figure 10A ​​​​​​​​is a top-down view of an exemplary structure after formation of second conductive lines and second dielectric isolation rails according to embodiments of the present disclosure.

[0035] Figure 10B is a vertical cross-sectional view of the exemplary structure taken along a vertical plane B-B' of Figure 10A

[0036] Figure 10C is a vertical cross-sectional view of the exemplary structure taken along a vertical plane C-C' of Figure 10A DETAILED DESCRIPTION

[0037] Selector elements (also referred to as steering elements), such as ovonic threshold switch (OTS) selector elements, are used to select individual memory cells in an array of memory cells. In such cases, each memory cell includes a series connection of a memory element and a selector element. The inventors have recognized that ovonic threshold switch materials can be degraded by exposure to fluorine-containing plasma, such as an anisotropic etch process, such as a reactive ion etch process. For example, exposure to fluorine-containing plasma increases the leakage current of the ovonic threshold switch material. However, fluorine-containing plasma is effective to etch various metal materials that overlie the ovonic threshold switch material of the memory cell. Methods and structures of embodiments of the present disclosure utilize dual etch stop layers that overlie the ovonic threshold switch selector to reduce or avoid exposure to fluorine-containing plasma that can damage the ovonic threshold switch selector. In particular, dual etch stop layers that include a stack of a ruthenium etch stop layer and a refractory metal-containing etch stop layer can be used to pattern the ovonic threshold switch selector in an MRAM device without significant exposure to fluorine-containing plasma.

[0038] The drawings are not drawn to scale. Where multiple instances of an element are shown in the drawings, multiple instances of the element can be repeated unless explicitly described or otherwise clearly indicated otherwise. Numerical designations such as “first,” “second,” and “third” are merely used to identify like elements and different numerical designations can be employed throughout the specification and claims of the present disclosure. The term “at least one” element means all possibilities including the possibility of a single element and the possibility of multiple elements.

[0039] ​​The same reference numbers can be used in different drawings to represent the same or similar elements. Elements having the same numbering but having different letter suffixes are assumed to have the same composition and the same function unless otherwise indicated. “Contact” between elements means direct contact between the elements that provides a shared edge or surface of the elements unless otherwise indicated. Two or more elements are “separated” from each other or “separated” from each other if they are not in direct contact with each other or with each other. As used herein, a first element positioned “on” a second element can be positioned on an outer side of a surface of the second element or on an inner side of the second element. As used herein, a first element is “directly” positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there is an electrically conductive path between the first element and the second element that is composed of at least one electrically conductive material. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0040] As used herein, a “layer” refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of uniform or non-uniform thickness that is less than the thickness of a continuous structure. For example, a layer can be positioned between or at any pair of horizontal planes between a top surface and a bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, thereabove, and / or therebelow.

[0041] As used herein, first and second surfaces are “vertically coincident” with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first and second surfaces. A substantially vertical plane is a plane that extends linearly along a direction that deviates from a vertical direction by less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction and can or can not include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.

[0042] As used herein, a “memory level” or a “memory array level” refers to a level that corresponds to a general region between a first horizontal plane that includes a topmost surface of an array of memory elements (i.e., a plane that is parallel to a top surface of a substrate) and a second horizontal plane that includes a bottommost surface of the array of memory elements. As used herein, a “through-penetration stack” element refers to an element that extends vertically through a memory level.

[0043] As used herein, a "semiconductor material" refers to a material having an electrical conductivity in the range from 1.0 x 10 -5 S / m to 1.0 x 10 5 S / m. As used herein, a "semiconductor material" refers to a material having an electrical conductivity in the range from 1.0 x 10 -5 S / m to 1.0 S / m in the absence of electrical dopants therein, and capable of producing a doped material having an electrical conductivity in the range from 1.0 S / m to 1.0 x 10 7 S / m upon suitable doping with electrical dopants. As used herein, an "electrical dopant" refers to a p-type dopant that adds holes to a valence band within a band structure or an n-type dopant that adds electrons to a conduction band within a band structure. As used herein, an "electrically conductive material" refers to a material having an electrical conductivity greater than 1.0 x 10 5 S / m. As used herein, an "insulator material" or a "dielectric material" refers to a material having an electrical conductivity less than 1.0 x 10 -5 S / m. As used herein, a "heavily doped semiconductor material" refers to a semiconductor material that is doped with electrical dopants at a sufficiently high atomic concentration to become an electrically conductive material when formed as a crystalline material or when converted to a crystalline material (e.g., starting from an initial amorphous state) by an anneal process (i.e., to provide an electrical conductivity greater than 1.0 x 10 5 S / m). A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material that includes electrical dopants (i.e., p-type dopants and / or n-type dopants) at a concentration that provides an electrical conductivity in the range from 1.0 x 10 -5 S / m to 1.0 x 10 7 S / m. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconductive or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconductive or conductive, depending on the atomic concentration of electrical dopants therein. As used herein, a "metallic material" refers to an electrically conductive material that includes at least one metallic element therein. All electrical conductivity measurements are made at standard conditions.

[0044] Referring to Figures 1A-1C , an exemplary structure for forming an array of OTS-containing selector memory elements is shown. While the memory elements include MRAM elements in a cross-point array configuration, other memory elements and / or other array configurations can be used.

[0045] The array includes a substrate 8. The substrate 8 includes a layer of insulating material in an upper portion, and can optionally include additional layers (not shown) below, which can include, for example, a layer of semiconductor material and an interconnect level dielectric layer in which metal interconnect structures are embedded. In one embodiment, semiconductor devices such as field effect transistors can be provided on the layer of semiconductor material, and the metal interconnect structures can provide conductive paths between the semiconductor devices. An exemplary structure includes a memory array region shown herein and a peripheral region (not shown) that includes interconnect structures and / or peripheral devices. Memory cells are subsequently formed in the memory array region.

[0046] An optional dielectric etch stop layer 18 can be formed over the substrate 8. The dielectric etch stop layer 18 includes a dielectric material that can function as an etch stop material portion during subsequent anisotropic etch processes. For example, the dielectric etch stop layer 18 can include silicon nitride or a dielectric metal oxide such as aluminum oxide. The thickness of the dielectric etch stop layer 18 can be in a range from 4 nm to 40 nm, although lesser and greater thicknesses can also be employed.

[0047] A first dielectric isolation layer 110 can be deposited over the optional dielectric etch stop layer 18. The first dielectric isolation layer 110 includes a dielectric material such as silicon oxide. The first dielectric isolation layer 110 can be formed by chemical vapor deposition. The thickness of the first dielectric isolation layer 110 can be in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

[0048] A photoresist layer (not shown) can be applied over the first dielectric isolation layer 110, and can be lithographically patterned to form a line and space pattern. Elongated openings can be formed in the photoresist layer that extend laterally along a first horizontal direction hd1 and are laterally spaced apart from one another along a second horizontal direction hd2. The width of each opening along the second horizontal direction hd2 can be in a range from 10 nm to 50 nm, such as 15 nm to 25 nm, although lesser and greater widths can also be employed. The pitch of the line and space pattern can be in a range from 20 nm to 100 nm, such as 30 nm to 50 nm, although lesser and greater thicknesses can also be employed.

[0049] The pattern in the photoresist layer can be transferred through the first dielectric isolation layer 110 by an anisotropic etch process. The photoresist layer can be used as an etch mask during the anisotropic etch process. First line trenches 109 can be formed through the first dielectric isolation layer 110. The photoresist layer can be subsequently removed, for example, by ashing.

[0050] Reference Figures 2A-2CA metal liner layer including a metal barrier material can be deposited in the first line trench 109 and over the first dielectric isolation layer 110. The metal liner layer can include a conductive metal barrier material such as a conductive metal nitride material (e.g., TiN, TaN, and / or WN) and / or a conductive metal carbide material (e.g., TiC, TaC, and / or WC). The metal liner layer can be deposited by chemical vapor deposition or physical vapor deposition. A metal fill material layer can be deposited over the metal liner layer. The metal fill material layer includes a metal material having a high resistivity. For example, the metal fill material layer can include copper, tungsten, titanium, tantalum, molybdenum, ruthenium, cobalt, or combinations thereof.

[0051] Excess portions of the metal fill material layer and the metal liner layer can be removed from above a horizontal plane including a top surface 128 of the first dielectric isolation layer 110. The horizontal plane including the surface 128 defines a boundary between the dielectric isolation layer 110 and subsequently deposited layers (e.g., Figure 3B and Figure 3C layer 132L) shown in FIG. 1 and described below. Each remaining portion of the metal fill material layer includes a first metal fill material portion 124. Each remaining portion of the metal liner layer includes a first metal liner 122. Each successive combination of the first metal liner 122 and the first metal fill material portion 124 constitutes a first conductive line 12 (e.g., a word line or a bit line). The first conductive lines 12 extend laterally along a first horizontal direction hd1 and are spaced apart laterally along a second horizontal direction hd2. Alternatively, the first conductive lines 12 can be formed over the substrate 8 first, and then the first dielectric isolation layer 110 is formed between the first conductive lines 12.

[0052] Referring to Figures 3A-3C A layer stack can be formed over the first conductive lines 12 and the first dielectric isolation layer 110. The layer stack can include, from bottom to top, a selector layer stack 13L, an etch stop layer stack 14L, at least one memory material layer 15L, and an optional metal cap layer 158L.

[0053] The selector layer stack 13L can include, from bottom to top, a lower electrode layer 132L, an optional lower metal compound liner 133L, a selector material layer 134L, an optional upper metal compound liner 135L, and an upper electrode layer 136L. Each of the lower electrode layer 132L and the upper electrode layer 136L includes at least one electrically conductive material. The at least one electrically conductive material can include a non-metallic electrically conductive material. Exemplary non-metallic electrically conductive materials that can be used for the lower electrode layer 132L and the upper electrode layer 136L include amorphous carbon, amorphous boron-doped carbon, amorphous nitrogen-doped carbon, metal-carbon alloys or other carbon alloys, and layer stacks thereof. Each of the lower electrode layer 132L and the upper electrode layer 136L can be free of transition metal elements. Each of the lower electrode layer 132L and the upper electrode layer 136L can be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Each of the lower electrode layer 132L and the upper electrode layer 136L can have a respective thickness in a range from 1 nm to 10 nm, such as from 2 nm to 5 nm, although lesser and greater thicknesses can also be employed.

[0054] Each of the optional lower metal compound liner 133L and the optional upper metal compound liner 135L, if present, can include an electrically conductive metal compound material that can be used as a diffusion barrier material. Exemplary electrically conductive metal compound materials that can be used for the optional lower metal compound liner 133L and the optional upper metal compound liner 135L include electrically conductive metal nitride materials (such as WN, TaN, and / or TiN) and electrically conductive metal carbide materials (such as WC, TaC, and / or TiC). Each of the lower metal compound liner 133L and the upper metal compound liner 135L can be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Each of the lower metal compound liner 133L and the upper metal compound liner 135L can have a respective thickness in a range from 0.5 nm to 4 nm, such as from 1 nm to 2 nm, although lesser and greater thicknesses can also be employed.

[0055] The selector material layer 134L includes a material that can be used as a voltage-dependent switch. In general, the selector material layer 134L can include a threshold switching material that exhibits non-linear electrical behavior, such as a bidirectional threshold switching material.

[0056] As used herein, a bidirectional threshold switching (OTS) material is a material that does not crystallize in a low resistance state at voltages above a threshold voltage, and returns to a high resistance state when not subjected to a voltage above the threshold voltage across the layer of OTS material. As used herein, a “bidirectional threshold switching material” refers to a material that exhibits a non-linear resistivity curve under an applied external bias voltage, such that the resistivity of the material decreases with the magnitude of the applied external bias voltage. In other words, a bidirectional threshold switching material is non-ohmic, and becomes more conductive at higher external bias voltages than at lower external bias voltages.

[0057] A bidirectional threshold switching material (OTS material) can be amorphous (e.g., non-crystalline) in a high resistance state, and can remain amorphous (e.g., remain non-crystalline) in a low resistance state during application of a voltage above its threshold voltage across the OTS material. The OTS material can return to the high resistance state when the high voltage above its threshold voltage is removed. The bidirectional threshold switching material can remain amorphous (e.g., non-crystalline) throughout the resistance state change. In one embodiment, the bidirectional threshold switching material can include a layer of chalcogenide material that exhibits hysteresis in both the written state and the read state. The chalcogenide material can be a GeTe compound or a Ge-Se compound doped with a dopant selected from As, N, and C, such as a Ge-Se-As compound semiconductor material. The bidirectional threshold switching material layer can include a selector material layer 134L that contains any bidirectional threshold switching material. In one embodiment, the selector material layer 134L can include and / or can consist essentially of a GeSeAs alloy, a GeSe alloy, a SeAs alloy, a GeTe alloy, or a SiTe alloy.

[0058] In one embodiment, the material of the selector material layer 134L can be selected such that the resistivity of the selector material layer 134L decreases by at least two orders of magnitude (i.e., more than 100 times) when an external bias voltage above a critical bias voltage magnitude (also referred to as a threshold voltage) is applied. In one embodiment, the composition and thickness of the selector material layer 134L can be selected such that the critical bias voltage magnitude can be in the range of 1 V to 4 V, although the critical bias voltage magnitude can also take on smaller and larger voltages. The thickness of the selector material layer 134L can be in the range of, for example, 5 nm to 40 nm, such as 10 nm to 20 nm, although smaller and larger thicknesses can also be employed.

[0059] The etch stop layer stack 14L can include, from bottom to top, a refractory metal-containing etch stop layer 142L, a ruthenium etch stop layer 144L, and a conductive material layer 146L. The refractory metal-containing etch stop layer 142L includes a refractory metal-containing material that includes at least one refractory metal. As used herein, a refractory metal refers to the five transition metal elements consisting of tantalum, tungsten, rhenium, niobium, and molybdenum. The refractory metal-containing etch stop layer 142L can include at least one refractory metal in elemental form, in an intermetallic alloy form, or in a conductive metal compound form with at least one non-metallic element, such as TaN, WN, TaC, or WC. In one embodiment, the refractory metal-containing etch stop layer 142L can consist essentially of tantalum, tungsten, rhenium, niobium, molybdenum, their intermetallic alloys, or their conductive metal nitride materials. In one embodiment, the refractory metal-containing etch stop layer 142L can consist essentially of tantalum nitride. The refractory metal-containing etch stop layer 142L can be deposited by physical vapor deposition or chemical vapor deposition. The refractory metal-containing etch stop layer 142L can have a thickness in a range of 2 nm to 5 nm, such as 2 nm to 3 nm. The thickness of the refractory metal-containing etch stop layer 142L is selected so that the refractory metal-containing etch stop layer 142L is thick enough to act as an etch stop structure for the etching process of the ruthenium etch stop layer 144L and thin enough to be etched by a timed anisotropic etching process without etching through the entire underlying upper electrode layer 136L.

[0060] The ruthenium etch stop layer 144L can consist essentially of ruthenium. Ruthenium can be etched in an anisotropic etching process that employs a chlorine-based plasma, such as a chlorine and oxygen containing plasma, and is resistant to fluorine-based plasmas that can etch refractory metals and other metal materials. Thus, ruthenium can be used as an etch stop material for the anisotropic etching process that etches the material of the conductive material layer 146L. The ruthenium etch stop layer 144L can be deposited, for example, by atomic layer deposition or physical vapor deposition. The ruthenium etch stop layer 144L can have a thickness in a range of 2 nm to 5 nm, such as 2 nm to 3 nm. The thickness of the ruthenium etch stop layer 144L is selected so that the ruthenium etch stop layer 144L is thick enough to act as an etch stop structure for the etching process of the conductive material layer 146L and thin enough to be etched by an anisotropic etching process to enter the refractory metal-containing etch stop layer 142L with minimal collateral etching.

[0061] The conductive material layer 146L includes and / or consists essentially of a material selected from the group consisting of elemental metal materials other than ruthenium, intermetallic alloys other than ruthenium-containing alloys, conductive metal nitride materials, conductive metal carbide materials, and conductive carbon-based materials. Exemplary elemental metals that can be used for the conductive material layer 146L include refractory elemental metals such as tantalum, tungsten, rhenium, niobium, and molybdenum, and non-refractory transition metals such as titanium. Exemplary conductive metal nitride materials include TiN, TaN, and WN. Exemplary conductive metal carbide materials include TiC, TaC, and WC. Conductive carbon-based materials include amorphous carbon or diamond-like carbon doped with suitable dopant atoms such as nitrogen to increase electrical conductivity. In one embodiment, the conductive material layer 146L can include a tantalum-containing compound material. For example, the conductive material layer 146L can consist essentially of tantalum nitride. The conductive material layer 146L can be formed by physical vapor deposition or chemical vapor deposition. The thickness of the conductive material layer 146L can be in a range from 20 nm to 50 nm, such as from 30 nm to 40 nm, although lesser and greater thicknesses can also be employed.

[0062] The at least one memory material layer 15L includes at least one memory material that can be patterned into memory elements. In one embodiment, the at least one memory material layer 15L can include a vertical stack of magnetic junction material layers, i.e., a material layer stack for forming a magnetic tunnel junction (MTJ) or a spin valve for an MRAM memory cell. For example, the at least one memory material layer 15L can include a material layer stack that includes, from bottom to top or from top to bottom, a reference layer 152L (also referred to as a magnetic fixed layer), a tunnel barrier layer 154L, and a free layer 156L, which together form an MTJ 150 of an STT MRAM memory cell. The thickness of the MTJ can be in a range from 10 nm to 40 nm, such as from 20 nm to 30 nm.

[0063] The reference layer 152L can have a fixed magnetization direction, which can be either a horizontal direction or a vertical direction. The reference layer 152L can be formed as a single ferromagnetic material layer or multiple ferromagnetic material layers that are magnetically coupled to each other to provide the same magnetization direction throughout. The reference layer 152L can include a Co / Ni multilayer structure or a Co / Pt multilayer structure. In one embodiment, the reference layer 152L can also include a thin non-magnetic layer consisting of a tantalum or tungsten with a thickness in a range from 0.2 nm to 0.5 nm and a thin CoFeB layer with a thickness in a range from 0.5 nm to 3 nm. The thickness of the reference layer 152L can be in a range from 2 nm to 5 nm.

[0064] Optionally, the reference layer 152L can be provided in a synthetic anti-ferromagnetic (SAF) structure that includes a hard magnetization layer (not explicitly shown), an anti-ferromagnetic coupling layer (e.g., a Ru layer, not explicitly shown), and the reference layer 152L. Where the reference layer 152L is provided as part of a SAF structure, the magnetization of the hard magnetization layer and the magnetization of the magnetic fixed layer can be anti-ferromagnetically coupled through the anti-ferromagnetic coupling layer.

[0065] The tunnel barrier layer 154L can include a tunnel barrier dielectric material such as magnesium oxide or aluminum oxide. The tunnel barrier layer 154L can have a thickness in the range of 0.6 nm to 2 nm, such as 0.8 nm to 1.2 nm. The tunnel barrier layer 154L is in contact with the reference layer 152L and provides spin sensitive tunneling of electrical current between the reference layer 152L and the free layer 156L. In other words, the amount of electrical current that passes through the tunnel barrier layer 154L depends on the relative alignment of the magnetization between the reference layer 152L and the free layer 156L, i.e., whether the magnetization directions are parallel to each other or anti-parallel to each other.

[0066] The free layer 156L can be formed as a single layer of ferromagnetic material or multiple layers of ferromagnetic material that are magnetically coupled to each other to provide the same magnetization direction throughout. The free layer 156L has a thickness that is less than 2 nm and preferably less than 1.5 nm, such as 0.8 nm to 1.5 nm. For example, the free layer 156L can include a CoFeB layer and / or a CoFe layer. The free layer 156L can be programmed by flowing electrical current in the vertical direction up or down. Additional layers (not shown) can be included in the MTJ 150.

[0067] The metal cap layer 158L includes a non-magnetic metal material including at least one non-magnetic transition metal or a non-magnetic transition metal alloy. For example, the metal cap layer 158L can include or can consist essentially of Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, alloys thereof, and electrically conductive metal nitrides or electrically conductive metal carbides thereof. The metal cap layer 158L can be deposited by physical vapor deposition or chemical vapor deposition. The metal cap layer 158L can have a thickness in the range of 1 nm to 20 nm, such as 2 nm to 10 nm, although lesser and greater thicknesses can also be employed.

[0068] In alternative embodiments, the at least one memory material layer 15L is not limited to MRAM memory cell layers and can include any memory material, i.e., a material that can be programmed to have at least two different memory states. In one embodiment, the at least one memory material layer 15L includes a resistive memory material. As used herein, a "resistive memory material" or "reversible resistance switching material" is a material that can have its resistivity changed by applying a voltage across the material. As used herein, a "resistive memory material layer" refers to a layer that includes a resistive memory material. As used herein, a "resistive memory element" refers to an element in a configuration that includes a portion of a resistive memory material that enables the resistive memory material to be programmed to have at least two states with different resistance values.

[0069] In one embodiment, the at least one memory material layer 15L includes a phase change memory material to form a phase change random access memory ("PCRAM" or "PRAM") device. As used herein, a "phase change memory material" refers to a material that has at least two different phases that provide different resistivities. The at least two different phases can be provided, for example, by controlling the rate of cooling from a heated state to provide an amorphous state with a higher resistivity and a polycrystalline state with a lower resistivity. In this case, the higher resistivity state of the phase change memory material can be achieved by a faster quenching of the phase change memory material after heating to the amorphous state, and the lower resistivity state of the phase change memory material can be achieved by a slower cooling of the phase change memory material after heating to the amorphous state.

[0070] Exemplary phase change memory materials include, but are not limited to, a germanium telluride antimony compound such as Ge2Sb2Te5(GST), a germanium antimony compound, an indium germanium telluride compound, an aluminum selenium telluride compound, an indium selenium telluride compound, and an aluminum indium selenium telluride compound. These compounds (e.g., compound semiconductor materials) can be doped (e.g., nitrogen-doped GST) or undoped. Thus, the resistive memory material layer can include and / or can consist essentially of a material selected from a germanium telluride antimony compound, a germanium antimony compound, an indium germanium telluride compound, an aluminum selenium telluride compound, an indium selenium telluride compound, or an aluminum indium selenium telluride compound. In this case, the thickness of the at least one memory material layer 15L can be in a range from 1 nm to 60 nm, such as from 3 nm to 40 nm and / or from 10 nm to 25 nm, although lesser and greater thicknesses can also be used.

[0071] In another implementation, the at least one memory material layer 15L includes a barrier-modulated unit memory material. For example, an oxygen-vacancy-containing metal oxide that exhibits different conductive properties depending on the level of oxygen vacancies can be deposited for the at least one memory material layer 15L. The oxygen-vacancy-containing metal oxide can be formed with oxygen defects (e.g., vacancies), or can be annealed to form oxygen defects. One of the electrodes of such a memory device can include a high work function material with a work function greater than 4.5 eV, and can be used to provide a high potential barrier for electrons at the interface with the reversible resistance-switching material. Thus, at moderate voltages (less than one volt), very low current will flow through the reversible resistance-switching material. The presence of oxygen vacancies (V O ππ ) can lower the energy barrier at the interface between the electrode and the reversible resistance-switching material. In this case, the interface between the electrode and the reversible resistance-switching material can provide the characteristics of a low-resistance contact (ohmic contact). The oxygen vacancies in the metal oxide of the reversible resistance-switching material act as n-type dopants, converting the initially insulating metal oxide to an electrically insulating material with a lower resistivity (but still insulating).

[0072] When a large forward bias voltage is applied across the reversible resistance-switching material (such as a negative voltage of about -1.5 volts applied to the high work function electrode relative to the opposite electrode), the oxygen vacancies drift toward the interface between the high energy barrier material (such as platinum or n-doped polysilicon) and the reversible resistance-switching material, and thus the potential barrier at the interface between the electrode and the reversible resistance-switching material is reduced, and a relatively high current can flow through the structure. The device is then in its low resistance (conducting) state, with the reversible resistance-switching material acting as a semiconducting or conducting material.

[0073] The conductive path can be broken by applying a large reverse bias voltage across the reversible resistance-switching material (such as a positive voltage of about 1.5 volts applied to the electrode relative to the lower electrode). Under the appropriate reverse bias conditions, the oxygen vacancies move away from the vicinity of the interface between the high work function material and the reversible resistance-switching material. The resistivity of the reversible resistance-switching material reverts to its high resistance state. Both the conducting state and the non-conducting state are non-volatile. Sensing the conduction of the memory storage element (e.g., by applying a voltage of about 0.5 volts) can readily determine the state of the resistive memory element.

[0074] While this particular conduction mechanism can not apply to all metal oxides, as a group they have similar behavior: transitioning from a low conductive state to a high conductive state when the appropriate voltage is applied, and both states are non-volatile. Examples of other materials that can be used for non-volatile resistive memory elements include hafnium oxide, such as HfO xwhere 1.9 < x < 2.1. Suitable materials for the lower electrode (e.g., word line) are any electrically conductive materials such as Ti(O)N, Ta(O)N, TiN, TiAlN, WN, and TaN. Suitable materials for the electrode (e.g., local bit line) include metals and doped semiconductors with high work functions (typically > 4.5 eV) that are capable of absorbing oxygen in contact with the metal oxide to create oxygen vacancies at the contact. Some examples are TaCN, TiCN, Ru, RuO2, Pt, Ti-rich TiO x , TiAlN, TaAlN, TiSiN, TaSiN, IrO2, and doped polysilicon. The thickness of the electrode is typically 1 nm or more. The thickness of the metal oxide can typically range from 2 nm to 20 nm.

[0075] In yet another embodiment, the resistive memory material for the at least one memory material layer 15L can comprise a filamentary metal oxide material such as nickel oxide or TiO2, in which electrically conductive filamentary paths can be formed or removed depending on external electrical biasing conditions. In this case, the at least one memory material layer 15L can optionally comprise a first lower conductive liner layer (such as a lower TiN liner) underneath the resistive memory material layer and a first upper conductive liner layer (such as an upper TiN liner) overlying the resistive memory material layer.

[0076] For MRAM memory devices, a mask layer 160L, such as an ion milling mask material layer 160L, can be deposited over the metal cap layer 158L. The ion milling mask material layer 160L comprises a material that can be used as a mask material for a subsequently employed ion milling process. For example, the ion milling mask material layer 160L can comprise diamond-like carbon (DLC). The thickness of the ion milling mask material layer 160L can range from 15 nm to 60 nm, such as from 20 nm to 40 nm, although lesser and greater thicknesses can also be employed.

[0077] Referring to Figures 4A-4C An optional photoresist layer (now shown) can be applied over the ion milling mask material layer 160L and can be lithographically patterned to form a two-dimensional array of discrete photoresist material portions. An anisotropic etching process can be performed to transfer the pattern of the two-dimensional array of discrete photoresist material portions through the ion milling mask material layer 160L. The patterned portions of the ion milling mask material layer 160L form a two-dimensional array of mask material portions 160, which can be arranged as a two-dimensional periodic array, such as a rectangular array. The pitch of the two-dimensional array of mask material portions 160 along the second horizontal direction hd2may be the same as the pitch of the first conductive lines 12 along the second horizontal direction hd2. The photoresist layer can be subsequently removed, for example, by ashing.

[0078] An ion milling process can be performed to remove the metal cap layer 158L and unmasked portions of the at least one memory material layer 15L. The array of mask material portions 160 can function as an ion milling mask during the ion milling process. The metal cap layer 158L can be patterned into a two-dimensional array of metal cap plates 158. The at least one memory material layer 15L can be patterned into an array of memory elements 15. In a case where the at least one memory material layer 15L includes a layer stack of a reference layer 152L, a tunnel barrier layer 154L, and a free layer 156L, each memory element 15 can include an MTJ 150 including a layer stack of a reference layer 152, a tunnel barrier layer 154, and a free layer 156. Each reference layer 152 can be a patterned portion of the reference layer 152L formed as in the processing step of Figures 3A-3C Each tunnel barrier layer 154 can be a patterned portion of the tunnel barrier layer 154L formed as in the processing step of Figures 3A-3C Each free layer 156 can be a patterned portion of the free layer 156L formed as in the processing step of Figures 3A-3C A top surface of the conductive material layer 146L can be physically exposed after the ion milling process.

[0079] Each memory element 15 can have a columnar shape. The columnar shape can have at least one tapered sidewall due to tapering resulting from ion milling. In a case where the columnar shape has at least one tapered sidewall, a taper angle of the at least one tapered sidewall can be in a range from 1 degree to 30 degrees, such as 3 degrees to 15 degrees, although smaller and larger taper angles can also be employed. A horizontal cross-sectional shape of each column structure can be circular, elliptical, rectangular, rounded rectangular, and / or a two-dimensional substantially curvilinear closed shape. The at least one conductive material layer 146L acts as an ion milling buffer layer and can be partially recessed during ion milling.

[0080] Reference is made to Figures 5A-5CA first anisotropic etch process can be performed to etch the remaining unmasked portions of the conductive material layer 146L. The chemical reactions of the first anisotropic etch process can be selected such that the first anisotropic etch process etches the material of the conductive material layer 146L with selectivity to the material of the ruthenium etch stop layer 144L, i.e., with selectivity to ruthenium. In one embodiment, the selectivity of the first anisotropic etch process to ruthenium can be in a range from 3 to 100, such as from 5 to 20. In other words, the ratio of the etch rate of the material of the conductive material layer 146L to the etch rate of ruthenium during the first anisotropic etch process can be in a range from 3 to 100, such as from 5 to 30. In one embodiment, the first anisotropic etch process can employ a plasma of a chlorine-free etch gas. For example, if the conductive material layer 146L includes a refractory metal or a refractory metal nitride (e.g., TaN), the first anisotropic etch process can employ a fluorine-based plasma generated from a chlorine-free etch gas. Exemplary chlorine-free etch gases include hydrofluorocarbon etch gases (C x H y F z ), such as CHF3. Alternatively, if the conductive material layer 146L includes carbon-doped or carbon-un-doped, an oxygen plasma is employed during the first anisotropic etch process. The first anisotropic etch process can include an over-etch step to ensure that all unmasked portions of the conductive material layer 146L are removed by the first anisotropic etch process. As a result, incidental etching of the top portion of the ruthenium etch stop layer 144L can occur during the terminal portion of the first anisotropic etch process. The duration of the first anisotropic etch process can be selected such that the ruthenium etch stop layer 144L is not etched by the first anisotropic etch process all the way through. Each patterned portion of the conductive material layer 146L includes a conductive pillar 146. The conductive pillars 146 can have a taper angle that is less than the taper angle of the sidewalls of the memory elements 15 and can be wider (e.g., have a greater width, such as a greater diameter) than the width overlying the MTJs 150, such as having a greater width than the width of the tunnel barrier layer 154. For example, the sidewalls of the conductive pillars 146 can be substantially vertical or can have a taper angle in a range from 0.1 degrees to 5 degrees.

[0081] Reference Figures 6A-6CA second anisotropic etch process can be performed to etch the unmasked portions of the ruthenium etch stop layer 144L. The chemical reactions of the second anisotropic etch process can be selected such that the second anisotropic etch process selectively etches ruthenium relative to the material of the refractory metal-containing etch stop layer 142L. In one embodiment, the selectivity of the second anisotropic etch process relative to the material of the refractory metal-containing etch stop layer 142L can be in a range from 2 to 100, such as from 4 to 20. In other words, the ratio of the etch rate of ruthenium to the etch rate of the refractory metal-containing etch stop layer 142L during the second anisotropic etch process can be in a range from 2 to 100, such as from 4 to 30. In one embodiment, the second anisotropic etch process can employ a plasma of a chlorine-containing etch gas. For example, the second anisotropic etch process can employ a chlorine-based plasma generated from an etch gas that includes chlorine. Exemplary chlorine-containing etch gases include Cl2and BCl3. Oxygen gas and / or argon gas can be employed during the second anisotropic etch process such that Cl2and O2etch gases are used to etch the ruthenium etch stop layer 144L. The second anisotropic etch process can include an over-etch step to ensure that all unmasked portions of the ruthenium etch stop layer 144L are removed by the second anisotropic etch process. As a result, incidental etching of the top portion of the refractory metal-containing etch stop layer 142L can occur during the terminal portion of the second anisotropic etch process. The duration of the second anisotropic etch process can be selected such that the refractory metal-containing etch stop layer 142L is not etched by the second anisotropic etch process at all times. Each patterned portion of the ruthenium etch stop layer 144L includes a ruthenium etch stop plate 144. The ruthenium etch stop plate 144 can have a taper angle that is less than the taper angle of the sidewalls of the memory element 15. For example, the sidewalls of the ruthenium etch stop plate 144 can be substantially vertical, or can have a taper angle in a range from 0.1 degrees to 5 degrees.

[0082] REFERENCE Figures 7A-7CA third anisotropic etch process can be performed to etch the unmasked portions of the refractory metal-containing etch stop layer 142L. The chemical reaction of the third anisotropic etch process can be selected such that the third anisotropic etch process has a selectivity to etching the material of the refractory metal-containing etch stop layer 142L over the material of the upper electrode layer 136L. In one embodiment, the selectivity of the third anisotropic etch process to the material of the upper electrode layer 136L can be in a range of 1.5 to 10, such as 2 to 5. In other words, the ratio of the etch rate of the material of the refractory metal-containing etch stop layer 142L to the etch rate of the material of the upper electrode layer 136L during the third anisotropic etch process can be in a range of 1.5 to 10, such as 2 to 5. In one embodiment, the third anisotropic etch process can employ a plasma of a chlorine-free etch gas. For example, the third anisotropic etch process can employ a fluorine-based plasma generated from a chlorine-free etch gas. Exemplary chlorine-free etch gases include hydrofluorocarbon etch gases (C x H y F z ), such as CHF3. Oxygen and / or argon gas can be employed during the third anisotropic etch process. The third anisotropic etch process can be a timed etch process with a sufficient duration to ensure that all unmasked portions of the refractory metal-containing etch stop layer 142L are removed by the third anisotropic etch process. Thus, incidental etching of the top portion of the upper electrode layer 136L can occur during the terminal portion of the third anisotropic etch process. The duration of the third anisotropic etch process can be selected such that the etching of the upper electrode layer 136L is less than 10 nm, such as 1 nm - 2 nm, and the upper electrode layer 136L is not etched all the way through by the third anisotropic etch process to avoid damaging the underlying OTS selector material layer 134L with the fluorine plasma. Thus, the dual etch stop layers (144L, 142L) prevent the upper electrode layer 136L from being etched all the way through such that the OTS selector element layer 134L is not exposed to the damaging fluorine plasma used to etch the layer 146L. This means that the upper electrode layer 136L does not have to act as an etch stop for deep fluorine plasma etching, and the upper electrode layer 136L thickness can be reduced. The reduced thickness reduces stress on the underlying layers and the likelihood of delamination of the upper electrode layer 136L during anneal steps, such as anneal steps used to improve the quality of the MTJ 150.

[0083] Each patterned portion of the refractory metal-containing etch stop layer 142L includes a refractory metal-containing etch stop plate 142. The refractory metal-containing etch stop plate 142 can have a taper angle that is less than the taper angle of the sidewalls of the memory element 15. For example, the sidewalls of the refractory metal-containing etch stop plate 142 can be substantially vertical, or can have a taper angle in the range of 0.1 degrees to 5 degrees. Each vertical stack of the refractory metal-containing etch stop plate 142, the ruthenium etch stop plate 144, and the conductive pillar 146 is referred to herein as a conductive plate stack 14.

[0084] Reference is made to Figures 8A-8C An additional anisotropic etch process can be performed to etch through the unmasked portions of the selector layer stack 13L. The selector layer stack 13L includes, from top to bottom, the upper electrode layer 136L, the optional upper metal compound liner 135L, the selector material layer 134L, the optional lower metal compound liner 133L, and the lower electrode layer 132L. The additional anisotropic etch process can include multiple anisotropic etch steps that include respective etch chemistry reactions for etching respective material layers within the selector layer stack 13L.

[0085] In the illustrative example, the upper electrode layer 136L and the optional upper metal compound liner 135L can be etched by an anisotropic etch step that employs an oxygen plasma if the liner 135L is thin enough. The selector material layer 134L can be etched by an anisotropic etch step that employs a plasma that is free of fluorine-containing etch gases. In one embodiment, the anisotropic etch step for etching the selector material layer 134L can be a plasma that is free of fluorine-containing etch gases, such as a plasma that includes a bromine-containing etch gas (such as HBr or Br2) or a plasma that includes methane or another hydrocarbon gas. The lower electrode layer 132L and the optional lower metal compound liner 133L can be etched by an anisotropic etch step that employs an oxygen plasma if the liner 133L is thin enough.

[0086] Each patterned portion of the upper electrode layer 136L includes an upper electrode plate 136. Each patterned portion of the optional upper metal compound liner 135L, if present, includes an upper metal compound plate 135. Each patterned portion of the selector material layer 134L includes a selector material plate 134, such as an OTS selector material plate 134. Each patterned portion of the lower metal compound liner 133L includes a lower metal compound plate 133. Each patterned portion of the lower electrode layer 132L includes a lower electrode plate 132. Each vertical stack of the upper electrode plate 136, the optional upper metal compound plate 135, the selector material plate 134, the optional lower metal compound plate 133, and the lower electrode plate 132 constitutes a selector element 13.

[0087] Memory pillar structures (13, 14, 15, 158) are provided over the first conductive lines 12. Each of the memory pillar structures (13, 14, 15, 158) can include a selector element 13, a stack of conductive plates 14, a memory element 15, and a metal cap plate 158. The memory pillar structures (13, 14, 15, 158) can be arranged as a periodic two-dimensional array, such as a rectangular array.

[0088] Referring Figures 9A-9C As shown, the two-dimensional array of mask material portions 160 can be removed, e.g., by ashing. At least one dielectric material can be deposited over and between the memory pillar structures (13, 14, 15, 158). Excess portions of the at least one dielectric material can be removed from above a horizontal plane that includes top surfaces of the memory pillar structures (13, 14, 15, 158) by a planarization process, such as a chemical mechanical planarization (CMP) process. The remaining portions of the at least one dielectric material include dielectric isolation structures (172, 174). The dielectric isolation structures (172, 174) can include an optional dielectric liner 172 and a dielectric fill material portion 174. The optional dielectric liner 172 includes a dielectric diffusion barrier material, such as silicon nitride. The thickness of the conductive liner 172 can be in a range of 3 nm to 10 nm, although lesser and greater thicknesses can also be employed. The dielectric fill material portion 174 includes a planarizable dielectric material, such as undoped silicate glass or doped silicate glass.

[0089] Referring Figures 10A-10C A second dielectric isolation layer 210 can be deposited over the two-dimensional array of memory pillar structures (13, 14, 15, 158). The second dielectric isolation layer 210 includes a dielectric material, such as silicon oxide. The second dielectric isolation layer 210 can be formed by chemical vapor deposition. The thickness of the second dielectric isolation layer 210 can be in a range of 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

[0090] A photoresist layer (not shown) can be applied over the second dielectric isolation layer 210 and can be lithographically patterned to form a line and space pattern. Elongated openings can be formed in the photoresist layer that extend laterally along the second horizontal direction hd2 and are laterally spaced apart from each other along the first horizontal direction hd1. Each opening along the first horizontal direction hd1 can have a width in a range from 10 nm to 50 nm, such as from 15 nm to 25 nm, although smaller and larger widths can also be employed. The pitch of the line and space pattern along the first horizontal direction hd1 can be the same as the pitch of the two-dimensional array of memory pillar structures (13, 14, 15, 158) along the first horizontal direction hd1. The pitch of the line and space pattern can be in a range from 20 nm to 100 nm, such as from 30 nm to 50 nm, although smaller and larger thicknesses can also be employed.

[0091] The pattern in the photoresist layer can be transferred through the second dielectric isolation layer 210 by an anisotropic etching process. The photoresist layer can be used as an etch mask during the anisotropic etching process. Second line trenches can be formed through the second dielectric isolation layer 210. The photoresist layer can be subsequently removed, e.g., by ashing.

[0092] A metal liner layer including a metal barrier material can be deposited in the second line trenches and over the second dielectric isolation layer 210. The metal liner layer can include a conductive metal barrier material, such as a conductive metal nitride material (e.g., TiN, TaN, and / or WN) and / or a conductive metal carbide material (e.g., TiC, TaC, and / or WC). The metal liner layer can be deposited by chemical vapor deposition or physical vapor deposition. A metal fill material layer can be deposited over the metal liner layer. The metal fill material layer includes a metal material having a high electrical resistivity. For example, the metal fill material layer can include copper, tungsten, titanium, tantalum, molybdenum, ruthenium, cobalt, or combinations thereof.

[0093] Excess portions of the metal fill material layer and the metal liner layer can be removed from above a horizontal plane including a top surface of the second dielectric isolation layer 210. Each remaining portion of the metal fill material layer includes a second metal fill material portion 224. Each remaining portion of the metal liner layer includes a second metal liner 222. Each continuous combination of a second metal liner 222 and a second metal fill material portion 224 constitutes a second conductive line 22 (e.g., another one of a bit line or a word line). The second conductive lines 22 extend laterally along the second horizontal direction hd2 and are laterally spaced apart along the first horizontal direction hd1. Alternatively, the second conductive lines 22 can be formed first, followed by the second dielectric isolation layer 210 second conductive lines 22.

[0094] While in previous embodiments the memory element 15 overlies the selector element 13, embodiments are expressly contemplated herein in which the selector element 13 overlies the memory element 15. In such cases, the conductive plate stack 14 can overlie the memory element 15 and the selector element 13.

[0095] Referring to all of the drawings and in accordance with various embodiments of the present disclosure, a memory device is provided that includes a first conductive line 12; a memory pillar structure (13, 14, 15, 158) including a lower electrode plate 132 overlying the first conductive line 12, a selector material plate 134, an upper electrode plate 136, a refractory metal-containing etch stop plate 142, a ruthenium etch stop plate 144, a conductive pillar 146, and a memory element 15; and a second conductive line 22 overlying the memory pillar structure (13, 14, 15, 158).

[0096] In one embodiment, the refractory metal-containing etch stop plate 142 consists essentially of tantalum, tungsten, rhenium, niobium, molybdenum, intermetallic alloys thereof, or conductive metal nitrides thereof. In one embodiment, the conductive pillar 146 includes and / or consists essentially of a material selected from the group consisting of elemental metals, intermetallic alloys, conductive metal nitride materials, conductive metal carbide materials, and conductive carbon-based materials. In one embodiment, the conductive pillar 146 consists essentially of tantalum nitride, undoped carbon, or carbon doped with boron or nitrogen; the ruthenium etch stop plate 144 consists essentially of ruthenium; the refractory metal-containing etch stop plate 142 consists essentially of tantalum nitride, and the upper electrode plate 136 includes undoped amorphous carbon or amorphous carbon doped with boron or nitrogen. In one embodiment, the conductive pillar has a thickness in a range of 20 nm to 50 nm, the ruthenium etch stop plate has a thickness in a range of 2 nm to 5 nm, the refractory metal-containing etch stop plate has a thickness in a range of 2 nm to 5 nm, and the upper electrode plate thickness ranges from 1 nm to 10 nm.

[0097] In one embodiment, the memory element 15 includes a vertical magnetic tunnel junction 150 of a spin transfer torque (STT) magnetoresistive random access memory (MRAM) cell. The vertical magnetic tunnel junction 150 has a cone angle in a range of 1 degree to 30 degrees with respect to a vertical direction.

[0098] In one embodiment, the selector material plate 133 includes a bidirectional threshold switch selector element. In one embodiment, the vertical magnetic tunnel junction 150 is narrower than the bidirectional threshold switch selector element 134.

[0099] While certain preferred embodiments have been mentioned above, it is to be understood that the present disclosure is not limited thereto. Those skilled in the art will recognize that various modifications can be made to the disclosed embodiments, and that such modifications are intended to fall within the scope of the present disclosure. Embodiments shown in the present disclosure employing a particular structure and / or configuration, it is meant to be understood that the present disclosure can be practiced in any other compatible structure and / or configuration, as would be recognized by one of ordinary skill in the art, so long as the changes do not depart from the spirit and scope of the present disclosure. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A method of forming a memory device, the method comprising: forming a layer stack over a substrate, the layer stack comprising a lower electrode layer, a selector material layer, an upper electrode layer, a refractory metal-containing etch stop layer, a ruthenium etch stop layer, a conductive material layer, and at least one memory material layer; patterning the at least one memory material layer into memory elements; patterning the conductive material layer into conductive pillars using the ruthenium etch stop layer as an etch stop point by performing a first anisotropic etch process having a first etch chemistry that selectively etches the conductive material layer relative to ruthenium; patterning the ruthenium etch stop layer into ruthenium plates using the refractory metal-containing etch stop layer as an etch stop point by performing a second anisotropic etch process having a second etch chemistry that selectively etches ruthenium relative to a material of the refractory metal-containing etch stop layer; patterning the refractory metal-containing etch stop layer into refractory metal- containing etch stop plates by performing a third anisotropic etch process having a third etch chemistry that selectively etches a material of the refractory metal- containing etch stop layer relative to a material of the upper electrode layer without etching through the upper electrode layer; and patterning the upper electrode layer, the selector material layer, and the lower electrode layer by performing an additional anisotropic etch process; and wherein a bidirectional threshold switch selector element is formed by anisotropically etching the selector material layer; and wherein the refractory metal-containing etch stop layer consists of tantalum, tungsten, rhenium, niobium, molybdenum, an intermetallic alloy thereof, or a conductive metal nitride thereof; and wherein the third anisotropic etch process is a timed-based etch process that employs a fluorine-based plasma that is timed to etch through the refractory metal- containing etch stop layer without always etching through the upper electrode layer such that bidirectional threshold switch material is not exposed to the fluorine-based plasma.

2. The method of claim 1, wherein the first anisotropic etch process employs another fluorine-based or oxygen-based plasma, and the second anisotropic etch process employs a chlorine-based plasma.

3. The method of claim 2, wherein the conductive material layer comprises a material selected from an elemental metal, an intermetallic alloy, a conductive metal nitride material, a conductive metal carbide material, or a conductive carbon-based material.

4. The method of claim 3, wherein: the conductive material layer consists of tantalum nitride, undoped carbon, or doped carbon; the ruthenium etch stop layer consists of ruthenium; the refractory metal-containing etch stop layer consists of tantalum nitride; and the upper electrode layer comprises undoped amorphous carbon or amorphous carbon doped with boron or nitrogen.

5. The method of claim 4, wherein: a thickness of the conductive material layer ranges from 20 nm to 50 nm; a thickness of the ruthenium etch stop layer ranges from 2 nm to 5 nm; ​ the refractory metal-containing etch stop layer has a thickness in a range from 2 nm to 5 nm; and the upper electrode layer has a thickness in a range from 1 nm to 10 nm.

6. The method of claim 1, wherein the at least one memory material layer comprises a vertical magnetic tunnel junction of a spin transfer torque (STT) magnetoresistive random access memory (MRAM) cell.

7. The method of claim 6, the method further comprising: forming an ion milling mask over the at least one memory material layer; and patterning the at least one memory material layer into an array of memory elements by ion milling using the ion milling mask.

8. The method of claim 6, wherein the vertical magnetic tunnel junction is narrower than the ovonic threshold switch selector element.

9. A memory device, the memory device comprising: a first conductive line; a memory pillar structure comprising a lower electrode plate, a selector material plate, an upper electrode plate, a refractory metal-containing etch stop plate, a ruthenium etch stop plate, a conductive pillar, and a memory element, and overlying the first conductive line; and a second conductive line overlying the memory pillar structure; and wherein: the conductive pillar consists of tantalum nitride, undoped carbon, or carbon-doped; the ruthenium etch stop plate consists of ruthenium; the refractory metal-containing etch stop plate consists of tantalum nitride; and the upper electrode plate comprises undoped amorphous carbon or amorphous carbon doped with boron or nitrogen.

10. The memory device of claim 9, wherein: the conductive pillar has a thickness in a range from 20 nm to 50 nm; the ruthenium etch stop plate has a thickness in a range from 2 nm to 5 nm; the refractory metal-containing etch stop plate has a thickness in a range from 2 nm to 5 nm; and the upper electrode plate has a thickness in a range from 1 nm to 10 nm.

11. The memory device of claim 9, wherein the memory element comprises a vertical magnetic tunnel junction of a spin transfer torque (STT) magnetoresistive random access memory (MRAM) cell.

12. The memory device of claim 11, wherein: the vertical magnetic tunnel junction has a taper angle relative to a vertical direction; and the taper angle is in a range from 1 degree to 30 degrees.

13. The memory device of claim 11, wherein the selector material plate comprises an ovonic threshold switch selector element, and wherein the vertical magnetic tunnel junction is narrower than the ovonic threshold switch selector element.

14. An electrical system comprising: a memory device comprising at least one memory device of claim 9.

14. A memory device, the memory device comprising: a first conductive line; a memory pillar structure comprising a lower electrode plate, a selector material plate, an upper electrode plate, a refractory metal-containing etch stop plate, a ruthenium etch stop plate, a conductive pillar, and a memory element, and overlying the first conductive line; and a second conductive line overlying the memory pillar structure; and wherein: the conductive pillar consists of tantalum nitride, undoped carbon, or carbon-doped; the ruthenium etch stop plate consists of ruthenium; the refractory metal-containing etch stop plate consists of tantalum nitride; and the upper electrode plate comprises undoped amorphous carbon or amorphous carbon doped with boron or nitrogen.

15. The memory device of claim 14, wherein: the conductive pillar has a thickness in a range from 20 nm to 50 nm; the ruthenium etch stop plate has a thickness in a range from 2 nm to 5 nm; the refractory metal-containing etch stop plate has a thickness in a range from 2 nm to 5 nm; and the upper electrode plate has a thickness in a range from 1 nm to 10 nm.

16. The memory device of claim 14, wherein the memory element comprises a vertical magnetic tunnel junction of a spin transfer torque (STT) magnetoresistive random access memory (MRAM) cell.

17. The memory device of claim 16, wherein: the vertical magnetic tunnel junction has a taper angle relative to a vertical direction; and the taper angle is in a range from 1 degree to 30 degrees.

18. The memory device of claim 16, wherein the selector material plate comprises an ovonic threshold switch selector element, and wherein the vertical magnetic tunnel junction is narrower than the ovonic threshold switch selector element. a memory device comprising at least one memory device of claim 14.

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