Dynamic trim selection based on operating voltage level of semiconductor devices and related methods and systems

Abstract

Dynamic fine selection based on operating voltage levels of a semiconductor device and associated methods and systems are disclosed. Certain semiconductor devices are expected to operate at two or more operating voltage levels. In some embodiments, the semiconductor device can be characterized to determine optimal timing and / or voltage conditions across multiple operating voltage levels. Thus, multiple sets of timing and / or voltage conditions can be identified depending on the operating voltage levels that can be stored in a non-volatile memory (NVM) array of the semiconductor device. During operation, the semiconductor device can determine the operating voltage level currently supplied to the semiconductor device and select one of the timing and / or voltage conditions stored in the NVM array so that the semiconductor device can operate at the optimal timing and / or voltage conditions that have been predetermined for the semiconductor device operating at the operating voltage level.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to dynamic fine-tuning selection based on the operating voltage of the semiconductor device, and related methods and systems. Background Technology

[0002] Semiconductor devices are widely used to process information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Some semiconductor devices are used to store information—for example, memory devices. Memory devices can be volatile or non-volatile and can come in various types, such as magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), and synchronous dynamic RAM (SDRAM). Information is stored in various types of RAM by charging memory cells to different states. Improvements to RAM memory devices typically include increasing memory cell density, increasing read / write speeds or otherwise reducing operating latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs. Summary of the Invention

[0003] According to one aspect of this application, a semiconductor device is provided. The semiconductor device includes: a non-volatile memory (NVM) array configured to store a plurality of trimming codes, each of the plurality of trimming codes corresponding to one of a plurality of voltage level ranges of an operating voltage of the semiconductor device; and a peripheral circuitry system coupled to the NVM array, the peripheral circuitry system being configured to: determine that the operating voltage is within the plurality of voltage level ranges; select a trimming code from the plurality of trimming codes, the trimming code corresponding to the voltage level range; and transmit the trimming code to a trimming adjustment circuitry of the semiconductor device coupled to the peripheral circuitry system.

[0004] According to another aspect of this application, a method of operating a semiconductor device is provided. The method includes: determining that an operating voltage of the semiconductor device is within a voltage level range, wherein the voltage level range is one of a plurality of voltage level ranges of the operating voltage; selecting a fine-tuning code from a plurality of fine-tuning codes stored in a non-volatile memory (NVM) array of the semiconductor device, wherein each of the plurality of fine-tuning codes corresponds to one of the plurality of voltage level ranges, and the selected fine-tuning code corresponds to the voltage level range; and transmitting the fine-tuning code to a fine-tuning circuit of the semiconductor device.

[0005] According to another aspect of this application, a method is provided. The method includes: supplying a first voltage to an operating voltage of a semiconductor device; determining a first set of timing and / or voltage conditions for one or more tunable circuits of the semiconductor device to operate under the first voltage; generating a first fine-tuning code corresponding to the first set of timing and / or voltage conditions; storing the first fine-tuning code in a non-volatile memory (NVM) array of the semiconductor device; supplying a second voltage to the operating voltage; determining a second set of timing and / or voltage conditions for the one or more tunable circuits to operate under the second voltage; generating a second fine-tuning code corresponding to the second set of timing and / or voltage conditions; and storing the second fine-tuning code in the NVM array. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This is a block diagram of a memory device, illustrating various components for dynamically fine-tuning selection based on operating voltage levels according to embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart illustrating dynamic fine-tuning selection based on operating voltage level according to an embodiment of the present disclosure.

[0009] Figure 3 This is a block diagram schematically illustrating a memory system according to an embodiment of the present disclosure.

[0010] Figure 4 and 5 This is a flowchart of a method for dynamically fine-tuning selection based on operating voltage level according to an embodiment of the present disclosure. Detailed Implementation

[0011] For some high-performance memory systems, power consumption increases with system speed. This increased power consumption typically leads to higher operating temperatures for the memory devices (e.g., DRAM) within the system. To meet the thermal boundaries of the memory devices, it is desirable to reduce or maintain power consumption while providing increased speed. For this purpose, the memory device may include complementary metal-oxide-semiconductor (CMOS) components and / or circuitry capable of meeting higher performance at reduced operating voltages. However, the memory device may also operate at operating voltages specified by industry standards (e.g., those published by the Federation of Electron Device Engineering (JEDEC)), which may be higher than the reduced operating voltage. Therefore, it is expected that the memory device will operate over a wide range of voltage levels (voltage values) for its operating voltages (VDD, VDD1, VDD2, VDD2L).

[0012] For example, for some applications (e.g., where memory devices are deployed as individual components), the memory devices may be supplied with an operating voltage (VDD) of approximately 1.1V (e.g., 1.1V + 6%, 1.1V - 3%). For other applications (e.g., where multiple memory devices operate together as a memory module with power management components), the memory devices may be supplied with a VDD of approximately 1.0V ± 3% (e.g., through power management components). Thus, the total voltage level window for the VDD of the memory devices can be in the range of 0.97V to 1.116V. In some cases, certain customers may want to operate the memory devices (e.g., as individual components) at operating voltages that are preferred for their applications (e.g., one or more of VDD, VDD1, VDD2, VDD2L), which may differ from this specification. Furthermore, if such memory devices are deployed in applications that operate at larger operating voltages (e.g., 1.0V, 1.1V), the total window of VDD voltage levels may be even larger for memory devices manufactured using advanced processing technology nodes that can be designed to operate at even lower operating voltages (e.g., 0.8V or even less).

[0013] Because memory devices contain various circuitry and functional blocks sensitive to VDD voltage (e.g., VDD level, VDD value), it is difficult to maintain optimal operation of the memory device over such a wide range of operating voltage (VDD) levels. For example, regions highly sensitive to VDD levels include operations associated with the memory array of the memory device, such as circuitry controlling timing requirements associated with row paths (e.g., when executing activation or precharge commands), column paths (e.g., when performing column selection operations), and data paths (e.g., when maintaining data setup and / or holding timing). Furthermore, memory devices may contain other circuitry and functional blocks that require extensive “training” processes, such as command bus training, read DQ calibration, and / or training, to identify an optimal set of timing and / or voltage conditions.

[0014] When testing memory devices (e.g., probe testing), a set of timing and / or voltage conditions can be carefully tuned (e.g., fine-tuned, fine-tuned) for the performance-critical VDD-sensitive circuitry described above to ensure that the memory device performs optimally at a specific VDD level (e.g., a specific voltage level specified by the JEDEC specification) or within a relatively narrow range of VDD levels that includes that specific VDD level. This finely tuned set of timing and / or voltage conditions may be referred to as the fine-tuning conditions. However, fine-tuning conditions determined at a specific VDD level (or within a narrow range of VDD levels) are unlikely to guarantee optimal performance of the memory device at different VDD levels. Furthermore, maintaining multiple test procedures (test programs, test flows), each designed to optimize memory device performance at a specific VDD level, would be costly. Additionally, managing the inventory of memory devices after fine-tuning them to different VDD levels in different ways will increase costs.

[0015] To address the aforementioned problems and challenges, embodiments of this disclosure provide a scheme for dynamic fine-tuning selection based on the operating voltage level of a memory device. When probing a memory device (e.g., during a test procedure or probe test), the memory device can be characterized across multiple voltage level ranges within which it can operate (e.g., a total window of voltage levels for VDD, multiple customer-preferred voltage levels). In some embodiments, such multiple voltage level ranges may take into account the entire voltage level range (window) of the operating voltage (e.g., across the entire VDD level). In other words, multiple sets of fine-tuning conditions can be determined based on multiple voltage level ranges (sub-ranges) corresponding to the total entire range. In some embodiments, the multiple voltage level ranges do not overlap with each other. Each fine-tuning condition can be represented as a fine-tuning code having a certain number of bits (e.g., 2 bits, 3 bits, 4 bits, 5 bits). Thus, multiple fine-tuning codes can be generated during probe testing, where each of the multiple fine-tuning codes corresponds to one of the multiple voltage level ranges of the operating voltage. The fine-tuning code can be stored (programmed) in a non-volatile memory (NVM) array of a memory device—for example, in a fuse (or antifuse) array.

[0016] During operation of the memory device (e.g., initialization process, power-on procedure), the memory device retrieves (e.g., reads) fine-tuning code from the NVM array and stores it in one or more internal latches (e.g., registers, dedicated memory arrays). Furthermore, the memory device can determine that the VDD level supplied to the memory device falls within one of a plurality of voltage level ranges. For this purpose, in some embodiments, the memory device includes voltage detection circuitry configured to detect the voltage level (VDD level) of the operating voltage. In other embodiments, the memory device includes a mode register configured to store an indication of the voltage level of the operating voltage. Based on determining that the voltage level supplied to the memory device is its operating voltage, the memory device can select one of the fine-tuning codes stored in the internal latches. The memory device can then transmit the selected fine-tuning code to the fine-tuning adjustment circuitry of the memory device, which is configured to adjust a set of timing and / or voltage conditions of one or more fine-tunable circuits (e.g., performance-critical VDD-sensitive circuitry) of the memory device according to the selected fine-tuning code.

[0017] In this way, the various fine-tunable circuits of the memory device can operate under an appropriate set of timing and / or voltage conditions pre-configured (pre-defined, pre-identified) based on the VDD level supplied to the memory device during probe testing. Therefore, the memory device can be tested using a single test procedure (configured to characterize the performance of the memory device across the entire voltage level range, under which the memory device is expected to operate). Furthermore, considering that the fine-tuning codes stored in the NVM array of the memory device can be retrieved and selected based on the actual voltage level of the operating voltage supplied to the memory device, inventory management of the memory devices can be simplified.

[0018] Figure 1 This is a block diagram of memory device 105, illustrating various components for dynamic fine-tuning selection based on operating voltage levels according to embodiments of the present disclosure. Memory device 105 includes a master array and / or fine-tunable circuitry 110, which collectively represent performance-sensitive circuitry and / or functional blocks of memory device 105—e.g., circuitry controlling the timing of row / column paths of the master array, circuitry associated with a command bus for training memory device 105, etc. The master array and / or fine-tunable circuitry 110 is coupled to pads 115 of memory device 105. Pads 115 may be configured to supply operating voltages to memory device 105 including the master array and / or fine-tunable circuitry 110. In some embodiments, pads 115 are configured to be coupled to an external voltage source. In other embodiments, pads 115 are configured to be coupled to an internal voltage source of memory device 105 (e.g., a charge pump, voltage regulator).

[0019] Memory device 105 includes a non-volatile memory (NVM) array 120 configured to store a plurality of trimming codes. Each of the plurality of trimming codes corresponds to one of a plurality of voltage level ranges of the operating voltage of memory device 105. In some embodiments, NVM array 120 includes a fuse array having a plurality of fuses and / or antifuses, a flash memory cell array, a phase-change memory cell array, or a combination thereof.

[0020] The NVM array 120 is coupled to logic circuitry 125, which is configured to retrieve a plurality of fine-tuning codes from the NVM array 120. Furthermore, the logic circuitry 125 is configured to transfer the plurality of fine-tuning codes to one or more internal latches 130 (also identified as 130a-n) of the memory device 105—for example, during initialization or power-on processes. In some embodiments, the logic circuitry 125 includes fuse logic configured to access (e.g., program / write, read) an array of fuses (or antifuses) of the NVM array 120. Additionally, the logic circuitry 125 may include broadcast logic configured to send (e.g., transmit, broadcast, scatter) information retrieved from the NVM array 120 to various functional blocks of the memory device 105 (e.g., internal latches 130), such that the information stored in the NVM array 120 is available at any time after the initialization process is completed (e.g., locally available).

[0021] In some embodiments, the memory device 105 includes a voltage detection circuit 135 coupled to pads 115. The voltage detection circuit 135 is configured to detect a voltage level (e.g., pad voltage) present at the pads 115 as an operating voltage supplied to the memory device 105. Thus, the memory device 105 can determine that the operating voltage level falls within a range of voltage levels. In some embodiments, the voltage detection circuit 135 is configured to detect the pad voltage upon power-up (e.g., an initialization process, a power-on procedure). Alternatively or additionally, the voltage detection circuit 135 may be configured to periodically (e.g., during refresh operations or other suitable periodic operations performed by the memory device 105) detect the pad voltage and / or detect the pad voltage in response to certain operations (e.g., calibrating input / output impedance (ZQ), switching out of a power-saving operating mode)—e.g., a predefined set of operations and / or events of the memory device 105. In some embodiments, the voltage detection circuit 135 may be configured to continuously detect the pad voltage. In addition, the voltage detection circuit 135 can be configured to detect pad voltage at a sampling rate (e.g., a detection sampling rate), which can be determined based on the product type and / or application purpose of the memory device 105 (e.g., high-performance applications, mobile applications).

[0022] Furthermore, voltage detection circuit 135 may generate an output signal 140 indicating the current voltage level (e.g., supply voltage, VDD level) of the operating voltage. In some embodiments, output signal 140 indicates a multiplexer 145 coupled to internal latch 130 regarding which trim code to select among a plurality of trim codes stored in internal latch 130. In some embodiments, when the voltage level is very close to a threshold between two operating voltage level ranges—for example, when the operating voltage level is approximately 1.0V (e.g., at the boundary of the range) in the example described below—voltage detection circuit 135 may be configured to provide a reliable selection between two trim codes (e.g., avoiding or preventing indeterminate oscillations (or switching) between the two trim codes).

[0023] For example, when the operating voltage (e.g., pad voltage) roughly corresponds to 1.0V (e.g., within ±0.5% or less, within ±1% or less, within ±2% or less), the voltage detection circuit 135 may initially determine that the pad voltage is in a higher range (e.g., VDD level greater than or equal to 1.0V and less than 1.03V). Subsequently, the voltage detection circuit 135 maintains this initial determination and does not switch the detection result to a lower range (e.g., VDD level greater than or equal to 0.97V and less than 1.0V) until the pad voltage decreases to 0.98V or less (instead of only 2 to 3 mV below 1.0V). In other words, the voltage detection circuit 135 may be configured to remain within the current voltage range based on the detected pad voltage until a change in the pad voltage causes the operating voltage to fall well into a different voltage range—e.g., exceeding a range boundary, exceeding a predetermined threshold amount (e.g., 5 mV or more, 10 mV or more, 15 mV or more, 20 mV or more). In this way, when the detected voltage level change exceeds the boundary value of the voltage level range but does not reach a predetermined hysteresis threshold, the voltage detection circuit 135 provides a stable indication of the voltage level range. In other words, the hysteresis characteristic requires that the change in pad voltage be greater than the predetermined hysteresis threshold to overcome the strain of the voltage detection circuit 135 switching its determination, so that the voltage detection circuit 135 can provide a stable indication of the voltage level range.

[0024] The output signal 140 of the voltage detection circuit 135 is transmitted to the multiplexer 145, allowing the multiplexer 145 to select one of the fine-tuning codes stored in the internal latches 130. Each latch of the internal latches 130 stores a fine-tuning code retrieved from the NVM array 120 as described herein. For example, the first latch 130a may store a first fine-tuning code "001" representing a first set of timing / voltage conditions (first fine-tuning condition) corresponding to a first voltage level range (e.g., VDD level greater than or equal to 0.97V and less than 1.0V). Similarly, the second latch 130b may store a second fine-tuning code "010" representing a second set of timing / voltage conditions (second fine-tuning condition) corresponding to a second voltage level range (e.g., VDD level greater than or equal to 1.0V and less than 1.03V). If the output signal 140 from the voltage detection circuit 135 indicates that the current voltage supplied to the memory device 105 corresponds to 1.01V (or instructs the multiplexer 145 to select the second trimming code based on determining that the current voltage supplied to the memory device 105 corresponds to 1.01V), then the multiplexer 145 generates (outputs) an output signal 150 containing the second trimming code "010", so that the trimming circuit 155 can receive the second trimming code "010".

[0025] The fine-tuning circuit 155 is configured to adjust (e.g., slightly adjust, finely tune) a set of timing and / or voltage conditions of one or more finely tuned circuits (e.g., array and / or finely tuned circuit 110) of the memory device 105 in response to receiving a fine-tuning code from the multiplexer 145. For example, if the fine-tuning circuit 155 receives a second fine-tuning code "010" from the multiplexer 145, the fine-tuning circuit 155 can adjust one or more finely tuned circuits to operate under a second set of timing / voltage conditions based on receiving the received second fine-tuning code "010"—for example, one that corresponds to the second fine-tuning code "010". In this way, the memory device 105 can dynamically select an appropriate fine-tuning condition that has been pre-configured (e.g., during probe testing of the memory device 105) based on determining the actual operating voltage level supplied to the memory device 105 during operation. In this regard, the voltage detection circuit 135, the internal latch 130, and the multiplexer 145 can be collectively referred to as the dynamic fine-tuning selector 175 (or peripheral circuitry) of the memory device 105.

[0026] In some embodiments, memory device 105 includes a mode register 165, which a host device (e.g., a memory controller) operatively coupled to memory device 105 can access (read, write) the mode register. Thus, the host device can program mode register 165 to indicate the voltage (e.g., 1.01V) supplied to memory device 105 as an operating voltage (e.g., via a power management component, via an external voltage source). Memory device 105 can determine that the operating voltage is within a voltage level range (e.g., VDD level greater than or equal to 1.0V and less than 1.03V) based on mode register 165 indicating the voltage level. Therefore, voltage detection circuitry 135 can be omitted in such embodiments. In some embodiments, mode register 165 provides an output 170 indicating the current level at pad 115 to multiplexer 145. As described herein, in response to receive output 170, multiplexer 145 may select (output) one of the fine-tuning codes stored in internal latch 130 (e.g., a second fine-tuning code "010") for use by fine-tuning circuitry 155. In response to receiving the fine-tuning code, fine-tuning circuitry 155 adjusts one or more of the fine-tunable circuitry of memory device 105 to operate under appropriate timing / voltage conditions (e.g., a second set of timing / voltage conditions) consistent with the received fine-tuning code.

[0027] Although the foregoing example embodiments depict a three (3)-bit trimming code for illustrative purposes, this disclosure is not limited thereto. For example, in other embodiments, the trimming code may contain a different number of bits—e.g., 1 (1) bit, two (2) bits, four (4) bits, five (5) bits, or even more. In some embodiments, a one-bit trimming code may correspond to an on / off setting of the voltage detection circuit 135 (or mode register 165) controlling the trimming status.

[0028] In some embodiments, memory device 105 may include more than one pad (e.g., pad 115) configured to supply operating voltages to memory device 105. For example, memory device 105 may include additional pads (e.g., second pads) configured to supply different functional blocks of memory device 105 with operating voltages different from those distributed by pad 115 (e.g., first pad). In such embodiments, a scheme for dynamically selecting tuning conditions can be applied to the additional pads by providing additional dynamic tuning selectors (e.g., dynamic tuning selector 175) so that memory device 105 can operate under optimal tuning conditions based on the actual voltage level present at the additional pads. In some embodiments, two or more pads (e.g., first pad and second pad) may be connected together. In such cases, the pads may be coupled to a common dynamic tuning selector (e.g., dynamic tuning selector 175).

[0029] In some embodiments, pad 115 provides operating voltages for the main array (e.g., VARY) of memory device 105 and the functional blocks coupled thereto (e.g., row decoders, column decoders, sense amplifiers). In some cases, VARY can be generated from VDD. Therefore, if the VDD level range of memory device 105 is wide, the VARY level will also have a wide range, which makes it difficult to maintain optimal array operation across the entire VARY level range—for example, considering the various array operations that require precise timing control as described above. In such embodiments, a scheme of dynamically selecting trim conditions can be applied to VARY so that memory device 105 can operate under optimal trim conditions based on the actual voltage level of VARY—for example, by providing a dynamic trim selector (e.g., dynamic trim selector 175) to the pad that provides the operating voltage for the main array (VARY).

[0030] Figure 2 This is a flowchart 201 illustrating dynamic fine-tuning selection based on operating voltage level according to an embodiment of this disclosure. The diagram may be as shown in reference... Figure 1 Examples of aspects of a test procedure (test flow) configured for dynamically fine-tuning selection of a semiconductor device (e.g., memory device 105) are described, or aspects of said test procedure (test flow) are included. According to aspects of this disclosure, a tester (e.g., a probe station, test equipment) can implement the test procedure of flowchart 201.

[0031] At block 210, the tester characterizes the memory device to determine (identify) multiple sets of tuning conditions across a supply voltage range (e.g., different VDD levels). For example, the tester may apply a first voltage (e.g., 0.99V) to the memory device against its operating voltage to determine a first set of timing and / or voltage conditions at which one or more tuned circuits of the memory device operate at the first voltage. The tester may generate a first tuning code (e.g., "001") representing the first set of timing and / or voltage conditions (first tuning condition) and store the first tuning code in the NVM array of the memory device—for example, by fusing the first tuning code into the fuse array of the memory device.

[0032] Subsequently, the tester can apply a second voltage (e.g., 1.01V) to the memory device relative to its operating voltage to determine a second set of timing and / or voltage conditions under which one or more fine-tunable circuits of the memory device operate at the second voltage. The tester can generate a second fine-tuning code (e.g., "010") representing the second set of timing and / or voltage conditions (second fine-tuning conditions) and store the second fine-tuning code in the NVM array of the memory device—for example, by fusing the second fine-tuning code into an array of fuses. In some embodiments, the entire supply voltage range can be segmented (divided) into multiple ranges (sub-ranges) such that a first range (e.g., 0.97V to 1.0V) of the multiple ranges contains a first voltage (e.g., 0.99V), and a second range (e.g., 1.0V to 1.03V) of the multiple ranges contains a second voltage (e.g., 1.01V). In this way, the tester can determine multiple fine-tuning conditions to optimize the performance of the memory device across the entire supply voltage range. The test process corresponding to box 210 can be referred to as probe testing—for example, a probe station can use probes placed on the memory device to test the memory device.

[0033] At box 215, the memory device is packaged and tested again to confirm multiple tuning conditions determined based on different voltage levels of the operating voltage. In some cases, the tuning conditions can be further fine-tuned to ensure optimal performance of the packaged memory device. After confirming the tuning conditions of the packaged memory device, the tester introduces the packaged memory device into the component inventory stage (box 220), where it is ready for shipment.

[0034] At box 225, a memory device can be delivered to a first application, wherein the memory device is deployed as a separate component. The memory device may be supplied with a VDD of approximately 1.1V (e.g., as specified by the JEDEC specification). As described herein, the memory device may determine that the operating voltage level corresponds to 1.1V (e.g., via voltage detection circuitry 135 or mode register 165) and select an appropriate fine-tuning code corresponding to VDD of 1.1V, such that one or more fine-tunable circuits of the memory device can operate under determined (pre-configured) optimal timing and / or voltage conditions during probe testing.

[0035] Similarly, at block 230, a memory device can be deployed in a second application, wherein multiple memory devices operate collectively as a memory module with power management components. The memory device may be supplied with a VDD of approximately 1.0V (e.g., via the power management components). As described herein, the memory device may determine that the operating voltage level corresponds to 1.0V (e.g., via voltage detection circuitry 135 or mode register 165) and select an appropriate fine-tuning code corresponding to VDD of 1.0V, such that one or more adjustable circuits of the memory device operate under determined optimal timing and / or voltage conditions during probe testing.

[0036] In this way, despite multiple operating voltage levels supplied to the memory device, the dynamic tuning selection scheme helps maintain a single test flow. Furthermore, the dynamic tuning selection scheme achieves unified inventory management, at least in part, due to the multiple tuning codes stored in the NVM array of the memory device. Although Figure 2 The foregoing examples and embodiments depict two different applications (e.g., individual component-level applications, memory module-level applications) for illustrative purposes only, but this disclosure is not limited thereto. For example, in some cases, a memory device may be shipped to different customers to operate the memory device at different operating voltages (e.g., one or more of VDD, VDD1, VDD2, VDD2L at different voltage levels) that are preferred for their own applications. In such cases, the memory device (e.g., via voltage detection circuit 135 or mode register 165) can determine the actual operating voltage level at which the memory device operates (e.g., multiple voltage levels preferred by different customers for their applications) so that appropriate fine-tuning conditions can be selected based on the actual operating voltage.

[0037] Figure 3 This is a schematic block diagram illustrating a memory system 300 according to an embodiment of the present disclosure. The memory system 300 includes a host device 310 operatively coupled to a memory module 320 (e.g., a two-wire through-hole memory module (DIMM)). The memory module 320 may include a controller circuitry 330 operatively connected to a plurality of memory devices 350 via a bus 340. The memory devices 350 may be referenced... Figure 1Examples of aspects of the described memory device 105 or aspects thereof are included. According to an aspect of this disclosure, memory device 350 includes an NVM array configured to store a plurality of trim codes, each of which corresponds to one of a plurality of voltage level ranges of the operating voltage of memory device 350. Furthermore, memory device 350 includes a peripheral circuitry (not shown, e.g., a dynamic trim selector 175) configured to determine if the voltage level of the operating voltage (e.g., VDD level) falls within a plurality of voltage level ranges, select a trim code from the plurality of trim codes corresponding to the voltage level range, and transmit the trim code to a trim adjustment circuitry (not shown, e.g., trim adjustment circuitry 155) of the memory device coupled to the peripheral circuitry. The trim adjustment circuitry can then adjust a set of timing and / or voltage conditions of one or more trimmable circuits (e.g., performance-critical VDD-sensitive circuitry) of the memory device according to the selected trim code. In this way, the memory device 350 can dynamically select the optimal fine-tuning state based on the current level of the operating voltage supplied to the memory device 350.

[0038] Figure 4 This is a flowchart 400 illustrating a method of operating a semiconductor device (e.g., memory device 105, memory device 350) according to embodiments of the present disclosure. Flowchart 400 may be memory device 105 (or a dynamic fine-tuning selector 175 combined with other components of memory device 105) as shown in reference... Figures 1 to 3 An instance of the method performed as described, or an aspect containing the method.

[0039] The method includes determining that the operating voltage of the semiconductor device is within a voltage level range, wherein the voltage level range is one of a plurality of voltage level ranges for the operating voltage (block 410). According to one aspect of this disclosure, the determining feature of block 410 may be determined by reference to... Figure 1 The described dynamic tuning selector (e.g., dynamic tuning selector 175, which in some cases is combined with mode register 165) is used to perform this.

[0040] The method further includes selecting a fine-tuning code from a plurality of fine-tuning codes stored in an array of non-volatile memory (NVM) of a semiconductor device, wherein each of the plurality of fine-tuning codes corresponds to one of a plurality of voltage level ranges, and the selected fine-tuning code corresponds to said voltage level range (block 415). According to one aspect of this disclosure, the selection feature of block 415 may be determined by reference to... Figure 1 The described dynamic fine-tuning selector 175 (in some cases combined with multiplexer 145) is used to perform this.

[0041] The method further includes fine-tuning circuitry (block 420) that transmits fine-tuning code to a memory device. According to one aspect of this disclosure, the transmission characteristics of block 420 may be as described in reference... Figure 1 The described dynamic fine-tuning selector 175 (in some cases combined with multiplexer 145) is used to perform this.

[0042] In some embodiments, the plurality of voltage level ranges correspond to the entire voltage level range of the operating voltage. In some embodiments, the method may further include storing a plurality of fine-tuning codes retrieved from the NVM array in one or more internal latches of the semiconductor device, wherein selecting a fine-tuning code corresponds to selecting a fine-tuning code stored in one or more internal latches. In some embodiments, determining that the operating voltage of the semiconductor device is within a voltage level range includes detecting the voltage level at pads of the semiconductor device configured to supply the operating voltage to the semiconductor device.

[0043] In some embodiments, determining that the operating voltage of the semiconductor device is within a voltage level range includes receiving an indication of the voltage level from a mode register of the semiconductor device, the mode register being configured to store the indication of the voltage level. In some embodiments, the method may further include adjusting a set of timing and / or voltage conditions of one or more tunable circuits of the semiconductor device, at least in part based on receiving a fine-tuning code, at a fine-tuning adjustment circuit.

[0044] Figure 5 This is a flowchart 500 illustrating a method for testing a semiconductor device (e.g., memory device 105, memory device 350) according to embodiments of the present disclosure. Flowchart 500 may be a reference. Figure 2 Examples of aspects of the described test process or aspects including said test process. According to aspects of this disclosure, a tester (e.g., a probe station, test equipment) may be implemented as described in reference. Figure 2 The features described in boxes 510 to 545.

[0045] The method includes supplying a first voltage to the operating voltage of a semiconductor device (box 510). The method further includes determining a first set of timing and / or voltage conditions for one or more tunable circuits of the semiconductor device to operate under the first voltage (box 515). The method further includes generating a first fine-tuning code corresponding to the first set of timing and / or voltage conditions (box 520). The method further includes storing the first fine-tuning code in a non-volatile memory (NVM) array of the semiconductor device (box 525). The method further includes supplying a second voltage to the operating voltage (box 530). The method further includes determining a second set of timing and / or voltage conditions for one or more tunable circuits to operate under the second voltage (box 535). The method further includes generating a second fine-tuning code corresponding to the second set of timing and / or voltage conditions (box 540). The method further includes storing the second fine-tuning code in an NVM array (box 545).

[0046] In some embodiments, the method may further include: supplying a third voltage to the operating voltage; determining a third set of timing and / or voltage conditions for one or more tunable circuits to operate at the third voltage; generating a third fine-tuning code corresponding to the third set of timing and / or voltage conditions; and storing the third fine-tuning code in an NVM array. In some embodiments, the plurality of voltage level ranges of the operating voltage correspond to the entire voltage level range of the operating voltage; a first voltage is included in a first voltage level range of the plurality of voltage level ranges; and a second voltage is included in a second voltage level range of the plurality of voltage level ranges. In some embodiments, the respective voltage level ranges of the plurality of voltage level ranges do not overlap with each other.

[0047] It should be noted that the methods described above depict possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the described methods can be combined.

[0048] Those skilled in the art will understand that the above description Figures 1 to 5 The components, blocks, and steps shown can be modified in a variety of ways. For example, the order of the logic can be rearranged, sub-steps can be executed in parallel, the logic shown can be omitted, other logic can be included, and so on. In some implementations, one or more of the components described above can perform one or more of the processes described below.

[0049] The information and signals disclosed herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, wherein the buses may have various bit widths.

[0050] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located at various locations, including distribution such that different parts of the functionality are implemented at different physical locations.

[0051] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0052] The algorithms and methods presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. The architectures of many of these systems are presented as described herein. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0053] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0054] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

[0055] References to “implementation” or “example” in this specification (e.g., “some implementations / examples,” “various implementations / examples,” “one implementation / example,” “implementation / example,” etc.) mean that a particular feature, structure, or characteristic described in connection with an implementation / example is included in at least one implementation / example of this disclosure. The appearance of these phrases in various places in the specification does not necessarily refer to the same implementation / example, nor are they separate or alternative implementations / examples that are mutually exclusive with other implementations / examples. Furthermore, various features that may be exhibited by some implementations / examples but not by others are described. Similarly, various requirements are described, which may be requirements for some implementations / examples but not for others.

[0056] As used in this article, the word “or” refers to any possible permutation of a set of items. For example, the phrase “A, B or C” refers to at least one of A, B, C, or any combination thereof, such as any of the following: A; B; C; A and B; A and C; B and C; A, B and C; or, for example, A and A; B, B and C; multiples of any of the items A, A, B, C and C, etc.

Claims

1. A semiconductor device comprising: A non-volatile memory (NVM) array configured to store a plurality of trimming codes, wherein each of the plurality of trimming codes corresponds to one of a plurality of voltage level ranges of the operating voltage of the semiconductor device; as well as A peripheral circuitry system coupled to the NVM array, the peripheral circuitry system being configured to: The operating voltage is determined to be within the voltage level range of the plurality of ranges; Select a fine-tuning code from the plurality of fine-tuning codes, wherein the fine-tuning code corresponds to the voltage level range; and The fine-tuning code is transmitted to the fine-tuning circuit of the semiconductor device coupled to the peripheral circuit system.

2. The semiconductor device of claim 1, wherein the plurality of voltage level ranges do not overlap with each other.

3. The semiconductor device of claim 1, wherein the peripheral circuit system is further configured to: The plurality of fine-tuning codes retrieved from the NVM array are stored in one or more internal latches of the semiconductor device, wherein selecting the fine-tuning code corresponds to selecting the fine-tuning code stored in the one or more internal latches.

4. The semiconductor device of claim 1, wherein the peripheral circuit system includes a voltage detection circuit configured to detect a voltage level of the operating voltage, and wherein determining the operating voltage within the voltage level range is at least partially based on the voltage detection circuit detecting the voltage level.

5. The semiconductor device of claim 4, wherein the voltage detection circuit is configured to provide a stability indication of the voltage level range if the extent to which a detected change in voltage level exceeds a boundary value of the voltage level range does not reach a predetermined hysteresis threshold.

6. The semiconductor device of claim 4, wherein the voltage detection circuit is coupled to a pad of the semiconductor device, the pad being configured to supply the operating voltage to the semiconductor device.

7. The semiconductor device of claim 6, wherein the voltage detection circuit is configured to detect the operating voltage at the pad in response to a predefined operation performed on the semiconductor device.

8. The semiconductor device of claim 1, further comprising: A mode register is configured to indicate the voltage level of the operating voltage, wherein the determination of the operating voltage within the voltage level range is based at least in part on the mode register indicating the voltage level.

9. The semiconductor device of claim 8, wherein the host device programs the mode register to indicate the voltage level, and the host device is operatively coupled to the semiconductor device.

10. The semiconductor device of claim 1, wherein the fine-tuning circuitry is configured to adjust a set of timing and / or voltage conditions of one or more fine-tunable circuits of the semiconductor device, at least in part, based on receiving the fine-tuning code from the peripheral circuitry system.

11. The semiconductor device of claim 10, wherein the set of timing and / or voltage conditions has been pre-configured to cause the one or more tunable circuits to operate within the voltage level range of the operating voltage.

12. The semiconductor device of claim 1, further comprising: A logic circuit coupled to the NVM array, the logic circuit being configured to retrieve the plurality of fine-tuning codes from the NVM array and transmit the plurality of fine-tuning codes to one or more internal latches of the semiconductor device.

13. A method of operating a semiconductor device, comprising: Determine that the operating voltage of the semiconductor device is within a voltage level range, wherein the voltage level range is one of a plurality of voltage level ranges of the operating voltage; A fine-tuning code is selected from a plurality of fine-tuning codes stored in a non-volatile memory (NVM) array of the semiconductor device, wherein each of the plurality of fine-tuning codes corresponds to one of the plurality of voltage level ranges, and the selected fine-tuning code corresponds to the voltage level range. as well as The fine-tuning code is transmitted to the fine-tuning circuitry of the semiconductor device.

14. The method of claim 13, further comprising: The plurality of fine-tuning codes retrieved from the NVM array are stored in one or more internal latches of the semiconductor device, wherein selecting the fine-tuning code corresponds to selecting the fine-tuning code stored in the one or more internal latches.

15. The method of claim 13, wherein determining the operating voltage of the semiconductor device within the voltage level range comprises: The voltage level at the pads of the semiconductor device is detected, the pads being configured to supply the operating voltage to the semiconductor device.

16. The method of claim 13, wherein determining the operating voltage of the semiconductor device within the voltage level range comprises: The voltage level indication is received from the mode register of the semiconductor device, the mode register being configured to store the voltage level indication.

17. The method of claim 13, further comprising: At the fine-tuning circuitry, a set of timing and / or voltage conditions of one or more fine-tunable circuits of the semiconductor device are adjusted, at least in part, based on receiving the fine-tuning code.

18. A method of operating a semiconductor device, comprising: A first voltage is supplied for the operating voltage of the semiconductor device, wherein the first voltage is included within a first voltage level range of a plurality of voltage level ranges of the operating voltage; Determine a first set of timing and / or voltage conditions for one or more tunable circuits of the semiconductor device to operate at the first voltage; Generate a first fine-tuning code corresponding to the first set of timing and / or voltage conditions; The first fine-tuning code is stored in the non-volatile memory (NVM) array of the semiconductor device; A second voltage is supplied to the operating voltage, wherein the second voltage is contained within a second voltage level range of the plurality of voltage level ranges, and the plurality of voltage level ranges correspond to the entire voltage level range of the operating voltage and do not overlap with each other; Determine a second set of timing and / or voltage conditions for the operation of the one or more finely adjustable circuits at the second voltage; Generate a second fine-tuning code corresponding to the second set of timing and / or voltage conditions; as well as The second fine-tuning code is stored in the NVM array.

19. The method of claim 18, further comprising: A third voltage is supplied to the operating voltage; Determine a third set of timing and / or voltage conditions for the operation of the one or more finely adjustable circuits under the third voltage; Generate a third fine-tuning code corresponding to the third set of timing and / or voltage conditions; as well as The third fine-tuning code is stored in the NVM array.

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