Integrated circuit device and oscillator

Abstract

The present application provides an integrated circuit device and an oscillator capable of preventing a decrease in precision of a clock frequency by a shielding effect of a ground connection pad or the like and achieving an efficient layout configuration that effectively uses a connection pad area. The integrated circuit device includes an oscillation circuit that generates an oscillation signal using an oscillator, an output buffer circuit that outputs a clock signal based on the oscillation signal, a direct current voltage generation circuit that generates a direct current voltage used for generating the oscillation signal or the clock signal, a power supply connection pad that is supplied with a power supply voltage, a ground connection pad that is supplied with a ground voltage, and a clock connection pad that outputs the clock signal. Furthermore, the ground connection pad and the direct current voltage generation circuit are arranged in an overlapping manner in plan view.

Description

TECHNICAL FIELD

[0001] The present application relates to an integrated circuit device and an oscillator or the like. BACKGROUND

[0002] In the past, an integrated circuit device having an oscillator circuit that oscillates a vibrator such as a quartz vibrator has been known. A layout configuration of an integrated circuit device having a temperature compensation type oscillator circuit is disclosed in Patent Literature 1. For example, an integrated circuit device is disclosed in Patent Literature 1 in which, in an integrated circuit device of an oscillator having a temperature compensation circuit, by providing a discontinuous portion between a region of a clock signal output circuit and a region of a temperature compensation circuit in a power supply line provided along an outer periphery, propagation of power supply noise is suppressed.

[0003] Patent Literature 1: Japanese Patent Application Publication No. 2018-98428

[0004] However, even if propagation of noise is suppressed by separating a power supply line as in Patent Literature 1, it is possible that radiation noise is superimposed on a direct current voltage generated by a circuit provided around an output buffer circuit that outputs a clock signal, resulting in deterioration of noise performance of an oscillator. SUMMARY

[0005] One embodiment of the present application relates to an integrated circuit device including: an oscillator circuit that generates an oscillation signal using a vibrator; an output buffer circuit that outputs a clock signal based on the oscillation signal; a direct current voltage generation circuit that generates a direct current voltage used for generating the oscillation signal or the clock signal; a power supply land to which a power supply voltage is supplied; a ground land to which a ground voltage is supplied; and a clock land that outputs the clock signal, in which the ground land and the direct current voltage generation circuit are configured in an overlapping manner in plan view.

[0006] Further, one embodiment of the present application relates to an oscillator including the above-described integrated circuit device and the vibrator. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a configuration example of the integrated circuit device of the present embodiment.

[0008] Figure 2 is a detailed configuration example of the integrated circuit device of the present embodiment.

[0009] Figure 3 is a detailed configuration example of a PLL circuit.

[0010] Figure 4 is a cross-sectional view showing a configuration relationship of a ground land and a direct current voltage generation circuit.

[0011] Figure 5 is a cross-sectional view showing another configuration example of the ground connection pad.

[0012] Figure 6 is a configuration example of the reference voltage generation circuit.

[0013] Figure 7 is another configuration example of the reference voltage generation circuit.

[0014] Figure 8 is a configuration example of the regulator.

[0015] Figure 9 is another configuration example of the regulator.

[0016] Figure 10 is a configuration example of the temperature sensor circuit.

[0017] Figure 11 is a configuration example of the temperature compensation circuit.

[0018] Figure 12 is a layout configuration example of the integrated circuit device of the present embodiment.

[0019] Figure 13 is another example of the layout configuration of the integrated circuit device of the present embodiment.

[0020] Figure 14 is an explanatory diagram regarding phase noise.

[0021] Figure 15 is a configuration example of the oscillator.

[0022] Explanation of Reference Signs

[0023] 4: oscillator; 5: passivation film; 6: land metal; 7, 8, 9: conductive layer; 10: vibrator; 15: package; 16: base; 17: lid; 18, 19: external terminal; 20: integrated circuit device; 30: oscillation circuit; 40: PLL circuit; 41: phase comparator; 42: charge pump circuit; 43: loop filter; 44: voltage controlled oscillation circuit; 45: frequency division circuit; 46: output frequency division circuit; 50: output buffer circuit; 60: power supply circuit; 61: direct current voltage generation circuit; 62: reference voltage generation circuit; 64, 65, 66, 67, 68: regulator; 70: logic circuit; 72: delta-sigma modulation circuit; 78: nonvolatile memory; 80: temperature compensation circuit; 82: 0th order correction circuit; 84: 1st order correction circuit; 86: higher order correction circuit; 88: current voltage conversion circuit; 90: temperature sensor circuit; 92: test circuit; 94: interface circuit; BMP: bump; BP1, BP2, BP3, BPT: bipolar transistor; CA: capacitor; CK, CKQ, CKV: clock signal; CP: parasitic capacitance; DI1, DI2, DI3: diode; DR, DR1, DR2, DR3, DR4: direction; FCK: feedback clock signal; IST: current source; NWL: well; OE: output enable signal; OPA: operational amplifier; OSC: oscillation signal; PCK: clock land; PGND: ground land; POE: output enable land; PSUB: substrate; PVDD: power supply land; PWL: well; PX1, PX2: land; RA1 ~ RA3, RD1 ~ RD3, RE1, RE2: resistance; SD1, SD2, SD3, SD4: side; TA1, TA2, TD1 ~ TD3, TE1 ~ TE5: transistor; TCK, TGND, TOE, TVDD: external terminal; VB: bias voltage; VCP: temperature compensation voltage; VDD: power supply voltage; VREF: reference voltage; VREG, VREG1, VREG2, VREG3, VREG4: regulated power supply voltage; VT: temperature detection voltage. DETAILED DESCRIPTION

[0024] Hereinafter, the present embodiment will be described. Note that the present embodiment described hereinafter does not unduly limit the recited content of the claims. Also, the structures described in the present embodiment are not necessarily all the essential components.

[0025] 1. Integrated circuit device

[0026] Figure 1A configuration example of the integrated circuit device 20 of the present embodiment will be shown. The integrated circuit device 20 of the present embodiment includes the oscillation circuit 30, the output buffer circuit 50, a power supply land PVDD, a ground land PGND, and a clock land PCK. In addition, the integrated circuit device 20 can include a power supply circuit 60, lands PX1, PX2 for use in connection of the vibrator. For example, the integrated circuit device 20 includes a reference voltage generation circuit 62, a regulator 64 as the direct current voltage generation circuit 61 to be described later. In the present embodiment, the reference voltage generation circuit 62, the regulator 64 as the direct current voltage generation circuit 61 are provided to the power supply circuit 60. Further, the oscillator 4 of the present embodiment includes the vibrator 10 and the integrated circuit device 20. The vibrator 10 is electrically connected to the integrated circuit device 20. For example, the vibrator 10 is electrically connected to the integrated circuit device 20 using internal wiring, bonding wires, or metal bumps of a package in which the vibrator 10 and the integrated circuit device 20 are housed, or the like. Figure 4 Figure 5 Figure 1 In the present embodiment, the reference voltage generation circuit 62, the regulator 64 as the direct current voltage generation circuit 61 are provided to the power supply circuit 60. Further, the oscillator 4 of the present embodiment includes the vibrator 10 and the integrated circuit device 20. The vibrator 10 is electrically connected to the integrated circuit device 20. For example, the vibrator 10 is electrically connected to the integrated circuit device 20 using internal wiring, bonding wires, or metal bumps of a package in which the vibrator 10 and the integrated circuit device 20 are housed, or the like.

[0027] The vibrator 10 is an element that generates mechanical vibration by an electric signal. The vibrator 10 can be implemented by, for example, a vibration piece such as a quartz vibration piece. For example, the vibrator 10 can be implemented by a quartz vibration piece that performs thickness shear vibration by AT cut or SC cut, a tuning fork type quartz vibration piece, or a double tuning fork type quartz vibration piece, or the like. For example, the vibrator 10 can be a vibrator built in a temperature compensated type quartz oscillator (TCXO) that does not have a thermostat, or a vibrator built in a thermostat type quartz oscillator (OCXO) that has a thermostat. Alternatively, the vibrator 10 can be a vibrator built in an oscillator of an SPXO (Simple Packaged Crystal Oscillator). In addition, the vibrator 10 of the present embodiment can be implemented by various vibration pieces other than the thickness shear vibration type, the tuning fork type, or the double tuning fork type, a piezoelectric vibration piece formed of a material other than quartz, or the like. For example, as the vibrator 10, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator formed using a silicon substrate as a silicon vibrator, or the like can be used.

[0028] The integrated circuit device 20 is, for example, an IC (Integrated Circuit) manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. In the present embodiment, the integrated circuit device 20 includes the oscillation circuit 30, the output buffer circuit 50, and the power supply circuit 60. Figure 1

[0029] ​​​The oscillation circuit 30 is a circuit that oscillates the vibrator 10. The oscillation circuit 30 is electrically connected to the connection pads PX1 and PX2, for example, and generates an oscillation signal OSC by oscillating the vibrator 10. The connection pad PX1 is a first connection pad, and the connection pad PX2 is a second connection pad. The oscillation circuit 30 can be implemented by an active element such as a capacitor or a resistor provided between the connection pad PX1 and the connection pad PX2, for example. The drive circuit can be implemented by an inverter circuit of CMOS or a bipolar transistor, for example. The drive circuit is a core circuit of the oscillation circuit 30, and the drive circuit voltage-drives or current-drives the vibrator 10, thereby oscillating the vibrator 10. As the oscillation circuit 30, various types of oscillation circuits such as an inverter type, a Pierce type, a Colpitts type, or a Hartley type can be used, for example. Further, a variable capacitance circuit is provided in the oscillation circuit 30, and the oscillation frequency can be adjusted by adjustment of the capacitance of the variable capacitance circuit. The variable capacitance circuit can be implemented by a variable capacitance element such as a varicap diode, for example. The variable capacitance circuit can be implemented by a variable capacitance element that controls the capacitance in accordance with a temperature compensation voltage, for example. Alternatively, the variable capacitance circuit can be implemented by a capacitor array and a switch array connected to the capacitor array. The variable capacitance circuit can be configured by a capacitor array having a plurality of capacitors whose capacitance values are binary-weighted and a switch array having a plurality of switches that turn on and off connection between each of the capacitors of the capacitor array and a ground node, for example. Note that the connection in the present embodiment is an electrical connection. The electrical connection is a connection that enables transmission of an electrical signal, and is a connection that enables transmission of information based on the electrical signal. The electrical connection can be a connection via a passive element or the like.

[0030] The output buffer circuit 50 outputs a clock signal CKQ based on the oscillation signal OSC.

[0031] For example, the output buffer circuit 50 buffers the oscillation signal OSC and outputs it as a clock signal CKQ to the clock connection pad PCK. Also, this clock signal CKQ is output to the outside via the external terminal TCK of the oscillator 4. For example, the output buffer circuit 50 outputs the clock signal CKQ in the form of a signal of a single-ended CMOS. In addition, the output buffer circuit 50 can also output the clock signal CKQ in a signal form other than CMOS. For example, the output buffer circuit 50 can also output a differential clock signal to the outside in a signal form of LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed Current Steering Logic), or a differential CMOS (Complementary MOS).

[0032] The power supply circuit 60 is supplied with the power supply voltage VDD from the power supply connection pad PVDD and the ground voltage from the ground connection pad PGND, and supplies various power supply voltages for the internal circuit of the integrated circuit device 20 to the internal circuit. For example, as described later, the power supply circuit 60 supplies a regulated power supply voltage based on the power supply voltage VDD to the oscillation circuit 30 and the like. Also, the power supply circuit 60 includes a reference voltage generation circuit 62 as a direct current voltage generation circuit 61, a regulator 64. Figure 4 , Figure 5 The reference voltage generation circuit 62 generates and outputs a reference voltage. The reference voltage generation circuit 62, for example, generates a reference voltage that is a constant voltage even if the power supply voltage VDD and the temperature change. For example, the reference voltage generation circuit 62 generates a reference voltage that is used to generate at least one of a bias current, a bias voltage, or a regulated power supply voltage. For example, the integrated circuit device 20 has an analog circuit, and the reference voltage generation circuit 62 generates a reference voltage that is used to generate a bias current or a bias voltage of the analog circuit. The regulator 64 is supplied with the power supply voltage VDD and generates various regulated power supply voltages. For example, the regulator 64 generates a regulated power supply voltage that is a constant voltage after step-down of the power supply voltage VDD in accordance with the reference voltage generated by the reference voltage generation circuit 62, and supplies the generated regulated power supply voltage to each circuit block of the integrated circuit device 20. The reference voltage generation circuit 62 can be implemented by, for example, a band gap reference circuit, a circuit using a difference in work function of a gate, or a circuit using a difference in threshold voltage due to a change in channel impurity concentration, and the like.

[0033] Further, the integrated circuit device 20 includes a power supply land PVDD, a ground land PGND, a clock land PCK, lands PX1, PX2 for connection of the vibrator. These lands are, for example, terminals of the integrated circuit device 20 as a semiconductor chip. In the land area, for example, a metal layer is exposed from a passivation film as an insulating layer, and the lands of the integrated circuit device 20 are constituted by the exposed metal layer. The power supply land PVDD is a land to which a power supply voltage VDD is input. For example, the power supply voltage VDD from an external power supply device is supplied to the power supply land PVDD. The ground land PGND is a terminal to which GND as a ground voltage is supplied. GND can also be referred to as VSS, and the ground voltage is, for example, a ground potential. In the present embodiment, the ground is appropriately written as GND. The clock land PCK is a land to output a clock signal CKQ. For example, the clock signal CKQ based on an oscillation signal OSC in the oscillation circuit 30 is output from the clock land PCK to the outside. The power supply land PVDD, the ground land PGND, and the clock land PCK are electrically connected to external terminals TVDD, TGND, TCK for external connection of the oscillator 4, respectively. The electrical connection is made, for example, using internal wiring, bonding wires, or metal bumps of a package, or the like. Also, the external terminals TVDD, TGND, TCK of the oscillator 4 are electrically connected to external devices. In addition, the lands PX1, PX2 are lands for connection of the vibrator 10. For example, the land PX1 is electrically connected to one end of the vibrator 10, and the land PX2 is electrically connected to the other end of the vibrator 10. The lands PX1, PX2 of the integrated circuit device 20 and the vibrator 10 are electrically connected, for example, using internal wiring, bonding wires, or metal bumps of a package that accommodates the vibrator 10 and the integrated circuit device 20, or the like.

[0034] Figure 2 A detailed configuration example of the integrated circuit device 20 of the present embodiment is shown. In Figure 2 the integrated circuit device 20, in addition to the circuit blocks shown in Figure 1 , a PLL circuit 40, a logic circuit 70, a nonvolatile memory 78, a temperature compensation circuit 80, a temperature sensor circuit 90, a test circuit 92, and an interface circuit 94 are included. In addition, the integrated circuit device 20 includes an output enable land POE in addition to the lands shown in Figure 1

[0035] ​The PLL circuit 40 performs a PLL operation for generating a clock signal CKQ that is phase-synchronized with the oscillation signal OSC. For example, the PLL circuit 40 receives the oscillation signal OSC as an oscillation clock signal from the oscillation circuit 30, and outputs a clock signal CK that is phase-synchronized with the oscillation signal OSC. Specifically, the PLL circuit 40 outputs a clock signal CK that is phase-synchronized with the oscillation signal OSC and has a frequency that is multiplied by the frequency of the oscillation signal OSC. Further, the output buffer circuit 50 is inputted with the clock signal CK from the PLL circuit 40, and outputs the clock signal CKQ. That is, the output buffer circuit 50 buffers the clock signal CK that is based on the oscillation signal OSC, and outputs it as the clock signal CKQ. Details of the PLL circuit 40 will be described later.

[0036] The logic circuit 70 is a control circuit that performs various control processes. For example, the logic circuit 70 performs control of the entire integrated circuit device 20, or performs control of the operation sequence of the integrated circuit device 20. For example, the logic circuit 70 performs control of each circuit block of the integrated circuit device 20, such as the oscillation circuit 30, the output buffer circuit 50, the power supply circuit 60, or the temperature compensation circuit 80. Further, the logic circuit 70 performs write control or readout control of the nonvolatile memory 78. The logic circuit 70 can be realized by, for example, a circuit of an ASIC (Application Specific Integrated Circuit) that is automatically configured by a wiring based on a gate array or the like.

[0037] The nonvolatile memory 78 stores various information used in the integrated circuit device 20. The nonvolatile memory 78 can be realized by an EEPROM such as a FAMOS (Floating gate Avalanche injection MOS) memory or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) memory, but is not limited thereto, and can be an OTP (One Time Programmable) memory or a fuse type ROM or the like.

[0038] The temperature compensation circuit 80 performs temperature compensation of the oscillation signal OSC of the oscillation circuit 30. The temperature compensation of the oscillation signal OSC is temperature compensation of the oscillation frequency of the oscillation circuit 30. Specifically, the temperature compensation circuit 80 performs temperature compensation in accordance with temperature detection information from the temperature sensor circuit 90. For example, the temperature compensation circuit 80 generates a temperature compensation voltage VCP in accordance with a temperature detection voltage VT from the temperature sensor circuit 90, and outputs the generated temperature compensation voltage VCP to the oscillation circuit 30, thereby performing temperature compensation of the oscillation signal OSC of the oscillation circuit 30. For example, the temperature compensation circuit 80 performs temperature compensation by outputting a temperature compensation voltage VCP that becomes a capacitance control voltage of a variable capacitance circuit possessed by the oscillation circuit 30 to the variable capacitance circuit. In this case, the variable capacitance circuit of the oscillation circuit 30 is realized by a variable capacitance element such as a varactor diode. Temperature compensation is processing that suppresses and compensates for variation in the oscillation frequency caused by temperature variation. For example, the temperature compensation circuit 80 performs temperature compensation in an analog manner based on polynomial approximation. For example, in a case where a temperature compensation voltage that compensates for the frequency-temperature characteristic of the resonator 10 is approximated by a polynomial, the temperature compensation circuit 80 performs temperature compensation in an analog manner in accordance with coefficient information of the polynomial. Temperature compensation in an analog manner is, for example, temperature compensation realized by addition processing of current signals, voltage signals, and the like as analog signals. Specifically, coefficient information of a polynomial for temperature compensation is stored in the nonvolatile memory 78, the logic circuit 70 reads out the coefficient information from the nonvolatile memory 78, and sets it in a register of, for example, the temperature compensation circuit 80. Also, the temperature compensation circuit 80 performs temperature compensation in an analog manner in accordance with the coefficient information set in the register. In addition, the temperature compensation circuit 80 can also perform temperature compensation in a digital manner. In this case, the temperature compensation circuit 80 is realized by, for example, a logic circuit. Specifically, the temperature compensation circuit 80 performs digital temperature compensation processing in accordance with temperature detection data that is temperature detection information of the temperature sensor circuit 90. For example, the temperature compensation circuit 80 calculates frequency adjustment data in accordance with the temperature detection data. Also, in accordance with the calculated frequency adjustment data, the capacitance value of the variable capacitance circuit of the oscillation circuit 30 is adjusted, thereby realizing temperature compensation processing of the oscillation frequency of the oscillation circuit 30. In this case, the variable capacitance circuit of the oscillation circuit 30 is realized by a capacitor array and a switch array that have a plurality of capacitors weighted in a binary manner. Furthermore, the nonvolatile memory 78 stores a lookup table that indicates correspondence of temperature detection data and frequency adjustment data, and the temperature compensation circuit 80 performs temperature compensation processing of calculating frequency adjustment data in accordance with temperature data using the lookup table read out from the nonvolatile memory 78 by the logic circuit 70.

[0039] The temperature sensor circuit 90 is a sensor circuit that detects temperature. Specifically, the temperature sensor circuit 90 outputs a temperature-dependent voltage that varies in accordance with the temperature of the environment as a temperature detection voltage VT. For example, the temperature sensor circuit 90 generates the temperature detection voltage VT using a circuit element having temperature dependence. Specifically, the temperature sensor circuit 90 outputs the temperature detection voltage VT whose voltage value varies in dependence on temperature by using the temperature dependence of the forward voltage of a PN junction. As the forward voltage of a PN junction, for example, the base-emitter voltage of a bipolar transistor or the like can be used. Further, in the case where digital temperature compensation processing is performed, the temperature sensor circuit 90 measures the temperature of the environment or the like, and outputs the result as temperature detection data. The temperature detection data is data that monotonically increases or monotonically decreases with respect to temperature, for example. As the temperature sensor circuit 90 in this case, a temperature sensor circuit that utilizes the fact that the oscillation frequency of a ring oscillator has temperature dependence can be used. Specifically, the temperature sensor circuit 90 includes a ring oscillator and a counter circuit. The counter circuit counts the output pulse signal that is the oscillation signal of the ring oscillator during a count period defined by a clock signal based on the oscillation signal OSC from the oscillation circuit 30, and outputs the count value as temperature detection data.

[0040] The output enable pad POE is a pad for controlling the output enable of the clock signal CKQ. Specifically, the output enable of the clock signal CKQ is controlled in accordance with an output enable signal OE input via the output enable pad POE. The output enable pad POE is electrically connected to the external terminal TOE for external connection of the oscillator 4. The logic circuit 70, for example, accepts the output enable signal OE from the output enable pad POE, and performs output enable control of the clock signal CKQ in the output buffer circuit 50. For example, when the output enable signal OE becomes active, the clock signal CKQ is output from the output buffer circuit 50. On the other hand, when the output enable signal OE becomes inactive, the clock signal CKQ is set to a fixed voltage level such as a low level. Note that, by signal active, a high level in the case of positive logic, for example, or a low level in the case of negative logic is meant. Further, by signal inactive, a low level in the case of positive logic, for example, or a high level in the case of negative logic is meant.

[0041] The test circuit 92 is a circuit for testing of the integrated circuit device 20. The test circuit 92 is used for testing of a circuit block such as an analog circuit of the integrated circuit device 20. In addition, the interface circuit 94 is, for example, a circuit for communication of a serial interface. In a test mode or the like, the clock pad PCK becomes an input terminal of a serial clock signal, and the output enable pad POE becomes an input / output terminal of serial data. Then, the interface circuit 94 performs communication of a serial interface that takes in serial data or outputs serial data in synchronization with the serial clock signal.

[0042] The interface circuit 94 can be implemented by, for example, a serial interface circuit such as an SPI (Serial Peripheral Interface) or an I2C (Inter-Integrated Circuit). By using such an interface circuit 94, it is possible to write information for temperature compensation into the nonvolatile memory 78, for example.

[0043] Figure 3 A detailed configuration example of the PLL circuit 40 is shown. In Figure 3 The PLL circuit 40 is a fractional-N type PLL circuit that can perform fractional frequency multiplication of the frequency of the oscillation signal OSC.

[0044] The PLL circuit 40 includes a phase comparator 41, a charge pump circuit 42, a loop filter 43, a voltage control oscillation circuit 44, a frequency division circuit 45, and an output frequency division circuit 46. The logic circuit 70 includes a delta-sigma modulation circuit 72.

[0045] The phase comparator 41 of the PLL circuit 40 compares the phases of the oscillation signal OSC that is a reference clock signal and the feedback clock signal FCK from the frequency dividing circuit 45, and outputs a phase comparison result signal. The phase comparison result signal is a signal corresponding to the phase difference between the oscillation signal OSC and the feedback clock signal FCK. Specifically, the phase comparator 41 outputs an up signal or a down signal as the phase comparison result signal. The charge pump circuit 42 converts the phase comparison result signal that is the up signal or the down signal from the phase comparator 41 into an output current. That is, the up signal and the down signal that are voltage pulses in a rectangular shape are converted into the output current that is a current pulse in a rectangular shape. For example, the charge pump circuit 42 outputs a positive current pulse in a case where the up signal is input, and outputs a negative current pulse in a case where the down signal is input. The loop filter 43 performs smoothing of the output signal of the charge pump circuit 42, generates a control voltage that controls the oscillation frequency of the voltage-controlled oscillation circuit 44, and outputs to the voltage-controlled oscillation circuit 44. Specifically, the loop filter 43 current-voltage converts the output current of the charge pump circuit 42, and performs a filter process. The control voltage that is the output voltage of the loop filter 43 rises in a case where the up signal is output, and falls in a case where the down signal is output, for example. The loop filter 43 can be implemented by an RC filter of 3rd or 4th order, for example. That is, the loop filter 43 can be implemented by a passive RC filter using a resistor and a capacitor. Furthermore, the loop filter 43 can also be a passive filter using an inductor as a passive element. Also, by inputting the control voltage from the loop filter 43 to the voltage-controlled oscillation circuit 44, the capacitance of a variable capacitance element implemented by a varactor diode or the like is changed, and the oscillation frequency of the voltage-controlled oscillation circuit 44 that is a VCO is controlled. Then, the clock signal CKV of the frequency set by the control voltage is output to the frequency dividing circuit 45. Furthermore, the voltage-controlled oscillation circuit 44 generates the clock signal CKV by a resonance circuit using an inductor, for example.

[0046] Further, in the present embodiment, a fractional divider is constituted by the frequency dividing circuit 45 and the delta-sigma modulation circuit 72. The fractional divider divides the clock signal CKV by the reciprocal of the multiplication rate of the PLL circuit 40 as a division ratio, and outputs the clock signal divided as a feedback clock signal FCK to the phase comparator 41. The delta-sigma modulation circuit 72 delta-sigma modulates the value of the fractional part of the division ratio, and generates a modulation value as an integer. For example, the delta-sigma modulation circuit 72 performs delta-sigma modulation processing three or four times. Further, the addition value of the value of the integer part of the division ratio and the modulation value is set as a set value of the division ratio in the frequency dividing circuit 45. Thus, the PLL circuit 40 of the fractional-N type is realized. Further, in the PLL circuit 40, the output frequency dividing circuit 46 is provided, which outputs a signal divided by the clock signal CKV from the voltage control oscillation circuit 44 as a clock signal CK to the output buffer circuit 50. Further, the output buffer circuit 50 outputs a signal buffered by the clock signal CK as a clock signal CKQ. Alternatively, a modification in which the output frequency dividing circuit 46 is not provided can be implemented.

[0047] Further, in the present embodiment, the adjustment of the clock frequency of the clock signal CKQ is performed by the adjustment of the multiplication rate of the PLL circuit 40. Figure 3 Further, in the present embodiment, the adjustment of the clock frequency of the clock signal CKQ is performed by the adjustment of the multiplication rate of the PLL circuit 40. Figure 1 Further, in the present embodiment, the adjustment of the clock frequency of the clock signal CKQ is performed by the adjustment of the multiplication rate of the PLL circuit 40. Figure 2 Further, in the present embodiment, the adjustment of the clock frequency of the clock signal CKQ is performed by the adjustment of the multiplication rate of the PLL circuit 40. Further, in the present embodiment, the adjustment of the clock frequency of the clock signal CKQ is performed by the adjustment of the multiplication rate of the PLL circuit 40.

[0048] As described above, the integrated circuit device 20 of the present embodiment includes the oscillation circuit 30 that generates an oscillation signal OSC using the vibrator 10, the output buffer circuit 50 that outputs a clock signal CKQ based on the oscillation signal OSC, a power supply land PVDD, a ground land PGND, and a clock land PCK. Further, a reference voltage generation circuit 62 that generates a direct current voltage, a direct current voltage generation circuit 61 such as a regulator 64, and the like are included, which are used for generating the oscillation signal OSC or the clock signal CKQ. The regulator 64 is, for example, a regulator 65, 66, 67, 68, and the like as shown. Figure 3

[0049] Further, it is ascertained that in such an integrated circuit device 20, due to electromagnetic coupling, electrostatic coupling between the output buffer circuit 50, the clock land PCK, and the direct current voltage generation circuit 61 such as the reference voltage generation circuit 62, the regulator 64, and the like, high frequency noise is transmitted to the direct current voltage generation circuit 61, and a problem of a decrease in accuracy of a clock frequency occurs. Specifically, in the integrated circuit device 20, the oscillation signal OSC is generated, or the clock signal CKQ is generated, based on a direct current voltage such as a reference voltage or a regulated power supply voltage that is output from the direct current voltage generation circuit 61. Therefore, if high frequency noise is superimposed on this direct current voltage, the accuracy of an oscillation frequency in the oscillation circuit 30 decreases, and a problem of a decrease in accuracy of a clock frequency, or a decrease in accuracy of a clock frequency at the time of generation of a clock signal in the PLL circuit 40 and the like, occurs.

[0050] On the other hand, in recent years, the proportion of a land area in the entire area of the integrated circuit device 20 has become high. Further, in the integrated circuit device 20 used in the oscillator 4, since no active circuit is disposed below the land, the disposition position of the land becomes a dead zone in the integrated circuit device 20. Therefore, when the proportion of the land area in the entire area of the integrated circuit device 20 becomes high, the dead zone caused by the land increases, and the miniaturization of the integrated circuit device 20 is hindered. On the other hand, if the area of the land is reduced in order to reduce the dead zone caused by such a land, flip-chip mounting, mounting based on a bonding wire, and the like described later become difficult. Therefore, in order to achieve stable mounting, a method of reducing the dead zone by further miniaturizing the land cannot be adopted.

[0051] ​Further, when the distance between the reference voltage generation circuit 62, the regulator 64, and the like, and the ground connection pad PGND of the direct current voltage generation circuit 61 is long, the direct current voltage output from the direct current voltage generation circuit 61 can fluctuate in potential due to the impedance of the limited ground wiring in the case of sharing the ground wiring with other circuits. For example, the reference voltage output from the reference voltage generation circuit 62, the regulator 64, and the like, of the direct current voltage generation circuit 61 can fluctuate in potential. When the direct current voltage such as the reference voltage, the regulated power supply voltage fluctuates in potential like this, the accuracy of the frequency of the clock signal generated in accordance with the direct current voltage decreases.

[0052] Therefore, in the present embodiment, as shown in FIG. 10, the ground connection pad PGND and the direct current voltage generation circuit 61 are arranged in an overlapping manner in plan view. Specifically, the ground connection pad PGND and the direct current voltage generation circuit 61 are arranged in an overlapping manner in plan view in the direction DR. For example, the direct current voltage generation circuit 61 is arranged below the ground connection pad PGND, that is, on the direction DR side. The direction DR is, for example, a direction perpendicular to the semiconductor substrate, that is, the substrate PSUB, of the integrated circuit device 20. Further, it is not necessary that the entire circuit portions of the ground connection pad PGND and the direct current voltage generation circuit 61 overlap in plan view, and for example, it is also possible to arrange the ground connection pad PGND and the direct current voltage generation circuit 61 in a layout in which a portion of the direct current voltage generation circuit 61 does not overlap the ground connection pad PGND. Figure 4 Figure 4

[0053] Figure 4 is a cross-sectional view showing the arrangement relationship of the ground connection pad PGND and the direct current voltage generation circuit 61. The integrated circuit device 20 is a wiring structure of five layers of metal layers ALA to ALE of aluminum or the like, and the connection pad metal 6 is formed of the uppermost metal layer ALE. Specifically, the connection pad metal 6 is exposed from the passivation film 5 at the opening portion of the connection pad region, and flip-chip mounting and wire-bonding-based mounting described later can be performed. In addition, a P-type well PWL and an N-type well NWL are formed in the P-type substrate PSUB, and the N-type transistors constituting the direct current voltage generation circuit 61 are formed in the P-type well PWL, and the P-type transistors are formed in the N-type well NWL. Further, the ground connection pad PGND is formed of the N-type well NWL. Figure 4 is a cross-sectional view showing the arrangement relationship of the ground connection pad PGND and the direct current voltage generation circuit 61. The integrated circuit device 20 is a wiring structure of five layers of metal layers ALA to ALE of aluminum or the like, and the connection pad metal 6 is formed of the uppermost metal layer ALE. Specifically, the connection pad metal 6 is exposed from the passivation film 5 at the opening portion of the connection pad region, and flip-chip mounting and wire-bonding-based mounting described later can be performed. In addition, a P-type well PWL and an N-type well NWL are formed in the P-type substrate PSUB, and the N-type transistors constituting the direct current voltage generation circuit 61 are formed in the P-type well PWL, and the P-type transistors are formed in the N-type well NWL. Further, the ground connection pad PGND is formed of the N-type well NWL.

[0054] Figure 5 is a cross-sectional view showing another configuration example of the ground connection pad PGND. In the present embodiment, the ground connection pad PGND is formed of the N-type well NWL, and the P-type well PWL is formed in the P-type substrate PSUB. The N-type well NWL is formed in the P-type substrate PSUB, and the P-type well PWL is formed in the N-type well NWL. The N-type well NWL is formed in the P-type well PWL, and the P-type well PWL is formed in the N-type well NWL. Further, the ground connection pad PGND is formed of the N-type well NWL. Figure 5 ​​In the present embodiment, the conductive layers 7, 8, 9 are formed on the land metal 6, for example, by plating or the like. The conductive layer 7 is formed of a material that has good adhesion to the land metal 6 formed of aluminum or an aluminum alloy, for example, nickel or a nickel alloy. The conductive layer 7 has a thickness of, for example, 2 μm to 10 μm. By thus increasing the thickness of the conductive layer 7, even if a large load is applied when the bump or the wire is joined to the ground land PGND, the load is difficult to transmit to the lower side of the ground land PGND. Therefore, it is possible to prevent the occurrence of a situation in which the DC voltage generation circuit 61 provided on the lower side of the ground land PGND is adversely affected by the load at the time of joining the bump or the wire. The conductive layer 8 is interposed between the conductive layer 7 and the conductive layer 9, improves the close adhesion of the conductive layers 7, 9, and functions as a barrier layer that prevents the diffusion of the conductive layer 7 to the conductive layer 9. The conductive layer 8 is formed of a material that has good close adhesion to both the conductive layer 7 and the conductive layer 9, for example, palladium or a palladium alloy. In addition, the conductive layer 8 can be omitted as needed, for example, in the case where the conductive layer 7 and the conductive layer 9 have good close adhesion, and the like. The conductive layer 9 functions as a connection layer to the bump or the wire. The conductive layer 9 is formed of a material that has a low contact resistance to the bump or the wire, for example, gold or an alloy of gold. By using the conductive layer 9, it is possible to join the bump or the wire with a low contact resistance, and to achieve ease of mounting, improvement in reliability, and the like. Figure 5 The ground land PGND having such a configuration can protect the DC voltage generation circuit 61 below the land from a load at the time of mounting the bump or the wire to the ground land PGND, and can join the bump or the wire with a low contact resistance, achieving ease of mounting, improvement in reliability, and the like.

[0055] As described above, in the present embodiment, in the integrated circuit device 20 having the oscillation circuit 30, the output buffer circuit 50, the DC voltage generation circuit 61, the power supply land PVDD, the ground land PGND, and the clock land PCK, the ground land PGND and the DC voltage generation circuit 61 are arranged in a manner that overlaps in plan view.

[0056] Thus, the ground land PGND functions as a shielding member, and it is possible to suppress the transmission of high-frequency noise to the DC voltage generation circuit 61. For example, by reducing the electromagnetic coupling and the electrostatic coupling between the output buffer circuit 50, the clock land PCK, and the DC voltage generation circuit 61 based on the shielding effect of the ground land PGND, it is possible to prevent the superposition of high-frequency noise on the DC voltage output from the DC voltage generation circuit 61. Therefore, it is possible to prevent problems such as a decrease in the precision of the oscillation frequency and a decrease in the precision of the clock frequency, or a decrease in the precision of the clock frequency at the time of generation of the clock signal, due to high-frequency noise. As a result, it is possible to achieve an integrated circuit device 20 that can generate a clock signal CKQ with high precision.

[0057] Further, by arranging the ground connection pad PGND and the direct current voltage generation circuit 61 so as to overlap when viewed from above, the area of the ground connection pad PGND can be effectively used to arrange the direct current voltage generation circuit 61. Therefore, the area of the ground connection pad PGND can be prevented from becoming a dead zone. In this way, by arranging the direct current voltage generation circuit 61 in the area of the ground connection pad PGND that would otherwise become a dead zone, even if the proportion of the area of the connection pad in the overall area of the integrated circuit device 20 becomes high, the layout area of the integrated circuit device 20 can be reduced, and the size of the integrated circuit device 20 can be reduced.

[0058] Further, by arranging the ground connection pad PGND and the direct current voltage generation circuit 61 so as to overlap when viewed from above, the area of the ground connection pad PGND can be effectively used to arrange the direct current voltage generation circuit 61. Therefore, the area of the ground connection pad PGND can be prevented from becoming a dead zone. In this way, by arranging the direct current voltage generation circuit 61 in the area of the ground connection pad PGND that would otherwise become a dead zone, even if the proportion of the area of the connection pad in the overall area of the integrated circuit device 20 becomes high, the layout area of the integrated circuit device 20 can be reduced, and the size of the integrated circuit device 20 can be reduced.

[0059] Here, the direct current voltage generation circuit 61 arranged below the ground connection pad PGND is a circuit that generates a direct current voltage used to generate an oscillation signal OSC or a clock signal CKQ. For example, the direct current voltage generation circuit 61 is a circuit that generates a direct current voltage such as a reference voltage, a frequency control voltage, and the like, which is input to the oscillation circuit 30. Alternatively, the direct current voltage generation circuit 61 is a circuit that generates a direct current voltage such as a reference voltage, a frequency control voltage, and the like, which is input to a frequency control voltage generation circuit such as the temperature compensation circuit 80 that controls the oscillation frequency of the oscillation circuit 30. Alternatively, the direct current voltage generation circuit 61 is a circuit that generates a direct current voltage used in the PLL circuit 40 that operates in accordance with the oscillation signal OSC from the oscillation circuit 30.

[0060] Specifically, the direct current voltage generating circuit 61 is, for example, a reference voltage generating circuit 62 that generates a reference voltage used for generating at least one of a bias current, a bias voltage, or a regulated power supply voltage. That is, the ground land PGND and the reference voltage generating circuit 62 as the direct current voltage generating circuit 61 are arranged in a manner that overlaps when viewed from above. In this way, by the shielding effect based on the ground land PGND, electromagnetic coupling, electrostatic coupling between the output buffer circuit 50, the clock land PCK, and the reference voltage generating circuit 62 is reduced, and superposition of high frequency noise on the reference voltage output from the reference voltage generating circuit 62 can be prevented. Therefore, reduction in accuracy of the clock frequency due to high frequency noise can be prevented. In addition, the reference voltage generating circuit 62 can be arranged using the area of the ground land PGND effectively, and thus the layout area of the integrated circuit device 20 can be reduced, and miniaturization of the integrated circuit device 20 can be achieved. In addition, the ground voltage from the ground land PGND can be supplied to the reference voltage generating circuit 62 using the path of the short through second ground wiring that is separate from the first ground wiring that connects other circuits at a distance farther from the ground land PGND to the ground land PGND. Therefore, potential variation due to the impedance of the first ground wiring that connects other circuits to the ground land PGND can be suppressed from being transmitted to the reference voltage of the reference voltage generating circuit 62, and reduction in accuracy of the clock frequency due to the potential variation can be prevented.

[0061] Alternatively, the direct current voltage generating circuit 61 can also be a regulator 64 that generates a regulated power supply voltage from the power supply voltage VDD. That is, the ground land PGND and the regulator 64 as the direct current voltage generating circuit 61 are arranged in a manner that overlaps when viewed from above. In this way, by the shielding effect based on the ground land PGND, superposition of high frequency noise on the regulated power supply voltage output from the regulator 64 can be prevented, and reduction in accuracy of the clock frequency due to high frequency noise can be prevented. In addition, since the regulator 64 can be arranged using the area of the ground land PGND effectively, miniaturization of the integrated circuit device 20 can be achieved. In addition, potential variation due to the impedance of the ground wiring that connects other circuits to the ground land PGND can be suppressed from being transmitted to the regulated power supply voltage of the regulator 64, and reduction in accuracy of the clock frequency due to the potential variation can be prevented.

[0062] In addition, as Figure 3As shown, the integrated circuit device 20 includes a PLL circuit 40 that generates a clock signal CK from an oscillation signal OSC, and the PLL circuit 40 includes a phase comparator 41, a charge pump circuit 42, and a loop filter 43. In this case, the direct current voltage generation circuit 61 configured in a manner that overlaps the ground land PGND in plan view can also be the charge pump circuit 42, the loop filter 43, or a regulator 66 that supplies the regulated power supply voltage VREG2 to the charge pump circuit 42. That is, the ground land PGND is configured in a manner that overlaps the charge pump circuit 42, the loop filter 43, or the regulator 66 that is the direct current voltage generation circuit 61 in plan view. In this way, by the shielding effect based on the ground land PGND, it is possible to prevent high frequency noise from being superimposed on the output voltage of the charge pump circuit 42, the loop filter 43, or the regulator 66, and it is possible to prevent a decrease in the precision of the clock frequency due to high frequency noise. Further, since it is possible to effectively utilize the area of the ground land PGND to configure the charge pump circuit 42, the loop filter 43, or the regulator 66, it is possible to achieve a reduction in the size of the integrated circuit device 20. Further, it is possible to suppress a potential variation caused by the impedance of a ground wiring that connects other circuits and the ground land PGND from being transmitted to the output voltage of the charge pump circuit 42, the loop filter 43, or the regulator 66, and it is possible to prevent a decrease in the precision of the clock frequency due to the potential variation.

[0063] Figure 6 A configuration example of the reference voltage generation circuit 62 is shown. Figure 6 The reference voltage generation circuit 62 includes an N-type transistor TD1, resistors RD1, RD2, RD3, bipolar transistors BP1, BP2 provided between the VDD node and the GND node. Further, the reference voltage generation circuit 62 includes P-type transistors TD2, TD3 to which a bias voltage VB is input to the gates thereof, and a bipolar transistor BP3 provided between the drain node of the transistor TD2 and the GND node. The reference voltage generation circuit 62 is a band gap reference circuit that generates and outputs a reference voltage VREF based on a band gap voltage. For example, the base-emitter voltage of the PNP-type bipolar transistors BP1, BP2 is set to VBE1, VBE2, and ΔVBE = VBE1 - VBE2 is set. The reference voltage VREF output by the reference voltage generation circuit 62 is, for example, VREF = K x ΔVBE + VBE2. K is set in accordance with the resistance values of the resistors RD1, RD2. For example, VBE2 has a negative temperature characteristic, and ΔVBE has a positive temperature characteristic, and thus by adjusting the resistance values of the resistors RD1, RD2, it is possible to generate a reference voltage VREF that is a constant voltage having no temperature dependence. Then, the generated reference voltage VREF is a constant voltage that is referenced to the ground voltage.

[0064] Figure 7Fig. 2 shows another configuration example of the reference voltage generation circuit 62. Figure 7 The reference voltage generation circuit 62 of Fig. 2 is also a band gap reference circuit, and includes N-type transistors TE1, TE2, P-type transistors TE3, TE4, TE5, resistors RE1, RE2, and diodes DI1, DI2, DI3 having PN junctions. The N-type transistors TE1, TE2 constitute a current mirror circuit, and the P-type transistors TE3, TE4, TE5 also constitute a current mirror circuit, so that the currents flowing through these transistors are substantially equal. In addition, the voltages at the sources of the N-type transistors TE1, TE2 are also substantially equal. Furthermore, the number of parallel connections of the PN junction in the diode DI2 is made M times the number of parallel connections of the PN junction in the diode DI1. Thus, in the case where the saturation current of the diode DI1 is Is, the saturation current of the diode DI2 becomes M x Is. Here, when the current flowing through the transistors TE3, TE4, TE5 is I, the voltages across the diodes DI1, DI2, DI3 are Vd1, Vd2, Vd3, respectively, and the resistance values of the resistors RE1, RE2 are R1, R2, respectively, the reference voltage VREF generated by the reference voltage generation circuit 62 is given by the following equation (1).

[0065] VREF = I • R2 + Vd3

[0066] = (R2 / R1) • (kT / q) • In(M) + Vd3 (1)

[0067] Here, k is the Boltzmann constant, T is the absolute temperature, and q is the charge of an electron. If the above equation (1) is differentiated with respect to the absolute temperature T, it becomes the following equation (2).

[0068] dVREF / dT = (R2 / R1) • (k / q) • In(M) + Vd3 / dT (2)

[0069] In the above equation (2), the term Vd3 / dT has a negative temperature characteristic, and by adjusting the value of (R2 / R1) • (k / q) • In(M) to a positive value in correspondence therewith, it is possible to make the value of the above equation (2) zero, and to generate a reference voltage VREF that eliminates temperature dependence. In addition, the reference voltage generation circuit 62 is not limited to the configuration of Figure 6 、 Figure 7 Fig. 2, and various circuits such as a circuit that generates a reference voltage VREF using a work function difference voltage of a transistor can be used.

[0070] Figure 8A configuration example of the regulator 64 is shown. The regulator 64 includes a transistor TA1 of N type for driving, resistors RA1, RA2, and an operational amplifier OPA, which are arranged in series between the VDD node and the GND node. Further, the regulator 64 can include a resistor RA3 and a capacitor CA arranged on the output terminal side of the operational amplifier OPA. The non-inverting input terminal of the operational amplifier OPA is input with the reference voltage VREF, and the inverting input terminal is input with a voltage VDA obtained by voltage-dividing the regulated supply voltage VREG by the resistors RA1, RA2. Further, the output of the operational amplifier OPA is input to the gate of the transistor TA1 via the resistor RA3, and the regulated supply voltage VREG is output from the drain node of the transistor TA1. Figure 9 A different configuration example of the regulator 64 is shown. In this example, the transistor for driving is a transistor TA2 of P type, the reference voltage VREF is input to the inverting input terminal of the operational amplifier OPA, and the voltage VDA is input to the non-inverting input terminal. Figure 9 Figure 8 Further, in this example, the connection structure of the capacitor CA for phase compensation is also different from that of the example shown in FIG. 6. Figure 9 Figure 8 Further, the regulators 65, 66, 67, 68 explained in Figure 3 may be implemented by, for example, the regulator 64 of the configuration shown in Figure 8 , Figure 9

[0071] As described above, the reference voltage generation circuit 62 or the regulator 64 generates the reference voltage VREF, the regulated supply voltage VREG with the ground voltage as a reference. Therefore, when high-frequency noise from the output buffer circuit 50 or the like is superimposed on the ground voltage, the potential of the reference voltage VREF, the regulated supply voltage VREG also fluctuates. Therefore, it is important to take measures to suppress superimposition of high-frequency noise from the output buffer circuit 50 or the like on the ground voltage.

[0072] Figure 10 A configuration example of the temperature sensor circuit 90 is shown. The temperature sensor circuit 90 includes a current source IST and a bipolar transistor BPT arranged in series between the power supply node and the GND node. The collector node and the base node of the bipolar transistor BPT are connected, becoming a diode connection. Thus, a temperature detection voltage VT having a temperature dependency is output from the output node NCQ of the temperature sensor circuit 90. For example, the temperature detection voltage VT of a negative temperature characteristic is output due to the temperature dependency of the base-emitter voltage. Note that the configuration of the temperature sensor circuit 90 is not limited to this example. Figure 10 ​​​The structure of the temperature sensor circuit 90 can be modified in various ways. For example, a resistor can be provided between the output node NCQ of the temperature sensor circuit 90 and the collector node of the bipolar transistor BPT, and a variable resistor can be provided between the emitter node of the bipolar transistor BPT and the GND node. By providing such a structure, the temperature sensor circuit 90 can be used to implement 0th-order correction for temperature compensation.

[0073] Figure 11 A structure example of the temperature compensation circuit 80 is shown. The temperature compensation circuit 80 includes a 0th-order correction circuit 82, a 1st-order correction circuit 84, a higher-order correction circuit 86, and a current-voltage conversion circuit 88. In addition, in the case of performing 3rd-order correction, 4th-order correction, 5th-order correction, or the like, a plurality of correction circuits such as a 3rd-order correction circuit, a 4th-order correction circuit, a 5th-order correction circuit, or the like are provided as the higher-order correction circuit 86. The higher-order correction circuit 86 is also referred to as a function generation circuit, and generates a function current corresponding to a polynomial approximating the characteristic of the temperature compensation voltage VCP. The polynomial is, for example, a function with temperature as a variable.

[0074] The temperature compensation circuit 80 performs temperature compensation in an analog manner based on polynomial approximation. Specifically, the temperature compensation circuit 80 generates and outputs the temperature compensation voltage VCP by approximation of a polynomial that is a function with temperature as a variable. For example, Figure 2 The nonvolatile memory 78 stores 0th-order coefficients, 1st-order coefficients, and higher-order coefficients of a polynomial approximating the characteristic of the temperature compensation voltage VCP as 0th-order correction data, 1st-order correction data, and higher-order correction data. Then, the 0th-order correction circuit 82, the 1st-order correction circuit 84, and the higher-order correction circuit 86 output 0th-order correction current signals, 1st-order correction current signals, and higher-order correction current signals in accordance with these 0th-order correction data, 1st-order correction data, and higher-order correction data. The 0th-order correction current signals, the 1st-order correction current signals, and the higher-order correction current signals can be referred to as 0th-order component signals, 1st-order component signals, and higher-order component signals of a function current. Then, the 1st-order correction current signals and the higher-order correction current signals are generated in accordance with the temperature detection voltage VT that changes linearly with respect to temperature and output to the 1st-order correction circuit 84 and the higher-order correction circuit 86. The current-voltage conversion circuit 88 performs addition processing of the 0th-order correction current signals, the 1st-order correction current signals, and the higher-order correction current signals and performs current-voltage conversion, and outputs the temperature compensation voltage VCP. Thus, temperature compensation in an analog manner based on polynomial approximation is implemented.

[0075] Further, in the case of 0th-order correction for temperature compensation using the temperature sensor circuit 90 as described above, the structure of the 0th-order correction circuit 82 can be omitted.

[0076] 2. Layout Configuration

[0077] Figure 12An example layout configuration of the integrated circuit device 20 according to this embodiment is shown. The outer shape of the integrated circuit device 20 includes edge SD1 and edge SD2 opposite to edge SD1. Edge SD1 is the first edge, edge SD2 is the second edge, and edge SD2 is the opposite edge of edge SD1. In addition, the outer shape of the integrated circuit device 20 includes edge SD3 and edge SD4 intersecting edge SD1 and edge SD2. Edge SD3 is the third edge, edge SD4 is the fourth edge, and edge SD4 is the opposite edge of edge SD3. The outer shape of the integrated circuit device 20 is, for example, the shape of a rectangular semiconductor chip. For example, edges SD1, SD2, SD3, and SD4 are edges of the substrate of the semiconductor chip. The semiconductor chip is also called a silicon chip. Here, the direction from edge SD1 to edge SD2 is defined as DR1, and the direction from edge SD3 to edge SD4 is defined as DR2. In addition, the direction opposite to direction DR1 is defined as direction DR3, and the direction opposite to direction DR2 is defined as direction DR4. Directions DR1, DR2, DR3, and DR4 are the first, second, third, and fourth directions, respectively.

[0078] like Figure 12 As shown, the integrated circuit device 20 includes a ground connection pad PGND, a power connection pad PVDD, a clock connection pad PCK, an output enable connection pad POE, and connection pads PX1 and PX2 for oscillator connection. For example, the power connection pad PVDD is located at the first corner where sides SD1 and SD3 intersect. The output enable connection pad POE is located at the second corner where sides SD2 and SD3 intersect. The clock connection pad PCK is located on the side of side SD1, and the ground connection pad PGND is located on the side of side SD2. For example, the clock connection pad PCK is located in the first region between the center line of sides SD1 and SD2 and side SD1, and the ground connection pad PGND is located in the second region between the center line of sides SD1 and SD2 and side SD2. Furthermore, the connection pads PX1 and PX2 for oscillator connection are located along side SD3 between the power connection pad PVDD and the output enable connection pad POE. For example, the oscillation circuit 30 and the connection pads PX1 and PX2 are located in the region along side SD3.

[0079] Furthermore, in Figure 12 In this configuration, the reference voltage generation circuit 62, serving as the DC voltage generation circuit 61, is arranged to overlap with the ground connection pad PGND when viewed from above. That is, as... Figure 4 , Figure 5As described above, the reference voltage generation circuit 62 is arranged below the ground land PGND. Thus, by the shielding effect of the ground land PGND, the transmission of high-frequency noise to the reference voltage generation circuit 62 can be suppressed, and the generation of potential variation in the reference voltage generated by the reference voltage generation circuit 62 can be prevented, thereby preventing a decrease in the accuracy of the clock frequency. In addition, since the reference voltage generation circuit 62 can be arranged using the arrangement region of the ground land PGND effectively, the size of the integrated circuit device 20 can be reduced.

[0080] Further, as Figure 12 indicated in the present embodiment, in the integrated circuit device 20, the clock land PCK and the output buffer circuit 50 are arranged in an overlapping manner in plan view. That is, as Figure 4 , Figure 5 in the arrangement relationship of the ground land PGND and the direct-current voltage generation circuit 61, the output buffer circuit 50 is arranged below the clock land PCK. In addition, it is not necessary that all of the circuit portions of the output buffer circuit 50 overlap the clock land PCK in plan view, and for example, a layout configuration in which a part of the output buffer circuit 50 does not overlap the clock land PCK can be adopted.

[0081] Thus, by arranging the clock land PCK and the output buffer circuit 50 in an overlapping manner in plan view, the clock signal CKQ from the output buffer circuit 50 can be output to the clock land PCK using a short-path clock wiring path from the output buffer circuit 50 toward the clock land PCK arranged directly above. Thus, the impedance of the clock wiring can be suppressed to a minimum, and the potential variation caused by the impedance can be suppressed. Since the output buffer circuit 50 needs to drive a large load outside, the output buffer circuit 50 has a high driving capability. Thus, if the impedance of the clock wiring is high, the potential variation thereof becomes large, and the signal quality of the clock signal CKQ deteriorates. In this regard, if the clock land PCK and the output buffer circuit 50 are arranged in an overlapping manner in plan view, the clock wiring path connecting the output buffer circuit 50 and the clock land PCK can be set to a short-path, and the impedance of the clock wiring can be suppressed to a minimum, thereby suppressing the deterioration of the signal quality of the clock signal CKQ. Further, since the output buffer circuit 50 has a high driving capability to be able to drive the external load, the generated high-frequency noise is large, and the output buffer circuit 50 and the clock land PCK outputting the clock signal CKQ become a high-frequency noise source. In this regard, if the clock land PCK and the output buffer circuit 50 are arranged in an overlapping manner in plan view, such a high-frequency noise source can be arranged concentratedly at one position. Thus, measures such as a layout configuration for alleviating the adverse effects of noise from the high-frequency noise source can be implemented easily.

[0082] In addition, such as Figure 12 As shown, the integrated circuit device 20 includes side SD1 and side SD2 opposite to side SD1. An output buffer circuit 50 and a clock connection disk PCK are disposed on side SD1, and a reference voltage generation circuit 62 (serving as a DC voltage generation circuit 61) and a ground connection disk PGND are disposed on side SD2. Side SD1 is the first side, and side SD2 is the second side. For example, the output buffer circuit 50 and the clock connection disk PCK are disposed closer to side SD1 than side SD2. Additionally, the reference voltage generation circuit 62 (serving as a DC voltage generation circuit 61) and the ground connection disk PGND are disposed closer to side SD2 than side SD1. For example, the output buffer circuit 50 and the clock connection disk PCK are disposed in a first region between side SD1 and the center line of sides SD1 and SD2, and the reference voltage generation circuit 62 and the ground connection disk PGND are disposed in a second region between side SD2 and the center line of sides SD1 and SD2. Thus, the output buffer circuit 50 and clock connection disk PCK, which are sources of high-frequency noise, are configured on the SD1 side, while the reference voltage generation circuit 62 and ground connection disk PGND, which need to avoid high-frequency noise, are configured on the SD2 side. This increases the distance between the output buffer circuit 50 and clock connection disk PCK, which are sources of high-frequency noise, and the reference voltage generation circuit 62 and ground connection disk PGND. Therefore, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 50 and clock connection disk PCK to the reference voltage generation circuit 62 and ground connection disk PGND, and to prevent the degradation of clock frequency accuracy caused by high-frequency noise.

[0083] Furthermore, the integrated circuit device 20 includes a PLL circuit 40, which performs PLL operation to generate a clock signal CKQ synchronized with the oscillation signal OSC. For example, the PLL circuit 40 outputs a clock signal CK synchronized with the oscillation signal OSC, and the output buffer circuit 50 buffers this clock signal CK and outputs it as the clock signal CKQ. Thus, the integrated circuit device 20 outputs a clock signal CKQ synchronized with the oscillation signal OSC. Moreover, the DC voltage generation circuit 61 is a reference voltage generation circuit 62 that generates the reference voltage used in the operation of the PLL circuit 40. Figure 3For example, the regulators 66, 67 generate the regulated power supply voltages VREG2, VREG3 in accordance with the reference voltage VREF generated by the reference voltage generation circuit 62, and the PLL circuit 40 operates in accordance with the regulated power supply voltages VREG2, VREG3. Alternatively, the charge pump circuit 42, the voltage control oscillation circuit 44, and the like of the PLL circuit 40 operate in accordance with the bias current, the bias voltage based on the reference voltage VREF generated by the reference voltage generation circuit 62. By providing such a PLL circuit 40, the integrated circuit device 20 is able to output the clock signal CKQ that is in phase with the oscillation signal OSC and has a frequency set to a desired frequency. Moreover, the reference voltage generation circuit 62 that generates the reference voltage required for the operation of such a PLL circuit 40 is arranged so as to overlap the ground connection pad PGND in plan view. Thus, it is possible to prevent a decrease in the accuracy of the clock frequency due to high-frequency noise, and to achieve a reduction in the size of the integrated circuit device 20 and the like by effectively utilizing the area of the ground connection pad PGND in the arrangement of the reference voltage generation circuit 62.

[0084] Further, as explained in Figure 3 , the PLL circuit 40 includes the phase comparator 41, the charge pump circuit 42, and the loop filter 43. Moreover, as shown in Figure 12 , the charge pump circuit 42 is arranged on the side SD2 side as the second side. For example, in Figure 12 , the charge pump circuit 42 is arranged between the side SD2 and the ground connection pad PGND. For example, in a case where the direction from the side SD1 toward the side SD2 is set as DR1, the charge pump circuit 42 is arranged on the direction DR1 side of the ground connection pad PGND. Specifically, the charge pump circuit 42 is arranged along the side SD2 together with the phase comparator 41. That is, the charge pump circuit 42 is arranged so as to have its long side direction along the side SD2. In this way, it is possible to arrange the charge pump circuit 42 together with the reference voltage generation circuit 62 and the ground connection pad PGND on the side SD2 side. Thus, it is possible to arrange the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND on a position that is distant from the output buffer circuit 50 and the clock connection pad PCK arranged on the side SD1 side. Therefore, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 50 and the clock connection pad PCK to the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND, and to prevent a deterioration in the accuracy of the clock frequency due to high-frequency noise. That is, as Figure 3As shown, there is a capacitive coupling based on the parasitic capacitance CP between the output of the output buffer circuit 50 and the output of the charge pump circuit 42, and due to this capacitive coupling, high-frequency noise from the output buffer circuit 50 can be superimposed on the output signal of the charge pump circuit 42. Also, if high-frequency noise is superimposed on the output signal of the charge pump circuit 42, the potential of the control voltage input to the voltage-controlled oscillation circuit 44 fluctuates, the accuracy of the clock frequency of the clock signal CK output from the PLL circuit 40 decreases, and the accuracy of the clock frequency of the clock signal CKQ output from the integrated circuit device 20 also decreases. In this regard, by arranging the charge pump circuit 42 on the side SD2, it is possible to make the distance from the output buffer circuit 50 and the clock connection pad PCK arranged on the side SD1 longer, it is possible to suppress the transmission of noise from these high-frequency noise sources, and thus it is possible to prevent a decrease in the accuracy of the clock frequency.

[0085] Further, as shown in FIG. 2, the loop filter 43 is arranged on the side SD2. For example, in the case where the direction from the side SD3 toward the side SD4 is set as DR2, the loop filter 43 is arranged on the side of the direction DR2 of the ground connection pad PGND and the charge pump circuit 42. In this way, it is possible to arrange the loop filter 43 together with the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND on the side SD2. Therefore, it is possible to arrange the loop filter 43, the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND on the side SD2 in a position away from the output buffer circuit 50 and the clock connection pad PCK arranged on the side SD1. Thus, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 50 and the clock connection pad PCK to the loop filter 43, the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND, and it is possible to prevent a decrease in the accuracy of the clock frequency due to high-frequency noise. Figure 12 Figure 12 Further, as shown in FIG. 2, the loop filter 43 is arranged on the side SD2. For example, in the case where the direction from the side SD3 toward the side SD4 is set as DR2, the loop filter 43 is arranged on the side of the direction DR2 of the ground connection pad PGND and the charge pump circuit 42. In this way, it is possible to arrange the loop filter 43 together with the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND on the side SD2. Therefore, it is possible to arrange the loop filter 43, the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND on the side SD2 in a position away from the output buffer circuit 50 and the clock connection pad PCK arranged on the side SD1. Thus, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 50 and the clock connection pad PCK to the loop filter 43, the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND, and it is possible to prevent a decrease in the accuracy of the clock frequency due to high-frequency noise.

[0086] Further, as shown in FIG. 2, the loop filter 43 is arranged on the side SD2. For example, in the case where the direction from the side SD3 toward the side SD4 is set as DR2, the loop filter 43 is arranged on the side of the direction DR2 of the ground connection pad PGND and the charge pump circuit 42. In this way, it is possible to arrange the loop filter 43 together with the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND on the side SD2. Therefore, it is possible to arrange the loop filter 43, the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND on the side SD2 in a position away from the output buffer circuit 50 and the clock connection pad PCK arranged on the side SD1. Thus, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 50 and the clock connection pad PCK to the loop filter 43, the charge pump circuit 42, the reference voltage generation circuit 62, and the ground connection pad PGND, and it is possible to prevent a decrease in the accuracy of the clock frequency due to high-frequency noise. Figure 3 ​As explained in the foregoing, the integrated circuit device 20 includes the regulator 66 that supplies the regulated power voltage VREG2 generated in accordance with the reference voltage VREF to the charge pump circuit 42. Also, the regulator 66 is disposed on the side SD2. For example, when high-frequency noise is superimposed on the output signal of the charge pump circuit 42, the potential of the control voltage input to the voltage control oscillation circuit 44 fluctuates, and the accuracy of the clock frequency of the clock signal CK output from the PLL circuit 40 decreases. Therefore, in the present embodiment, the regulator 66 for the charge pump circuit 42 is provided, and the charge pump circuit 42 is caused to operate by the regulated power voltage VREG2 generated by the regulator 66. However, when high-frequency noise from the output buffer circuit 50 or the like is superimposed on the regulated power voltage VREG2, the output signal of the charge pump circuit 42 also has high-frequency noise superimposed thereon, and thus the accuracy of the clock frequency of the clock signal CK output from the PLL circuit 40 decreases, and the accuracy of the clock frequency of the clock signal CKQ output from the integrated circuit device 20 also decreases. In this regard, in the Figure 12 present embodiment, not only the charge pump circuit 42, but also the regulator 66 that supplies the regulated power voltage VREG2 to the charge pump circuit 42 is concentratedly disposed on the side SD2. In this way, the distance between the regulator 66 and the source of high-frequency noise such as the output buffer circuit 50 can be lengthened. Thus, superimposition of high-frequency noise on the regulated power voltage VREG2 can be suppressed, and a decrease in the accuracy of the clock frequency can be prevented. Furthermore, since the regulated power voltage VREG2 from the regulator 66 can be supplied to the charge pump circuit 42 through a short power supply line, fluctuation of the regulated power voltage VREG2 due to the impedance of the power supply line can also be suppressed.

[0087] In addition, in the present embodiment, the regulator 66 is disposed on the side SD2. Thus, the distance between the regulator 66 and the output buffer circuit 50 or the like can be lengthened. Thus, superimposition of high-frequency noise on the regulated power voltage VREG2 can be suppressed, and a decrease in the accuracy of the clock frequency can be prevented. Figure 12In this circuit, a regulator 65 that supplies the regulated power supply voltage VREG1 to the oscillation circuit 30 is positioned on the side SD3. For example, the regulator 65 is positioned along the side SD3 between the side SD1 and the oscillation circuit 30, and is located near the oscillation circuit 30. Therefore, the regulated power supply voltage VREG1 from the regulator 65 can be supplied to the oscillation circuit 30 via a short-circuited power supply line, thus suppressing fluctuations in the regulated power supply voltage VREG1 due to the impedance of the power supply line. Furthermore, a regulator 67 that supplies the regulated power supply voltage VREG3 to the voltage-controlled oscillation circuit 44 is positioned on the side SD1. For example, the regulator 67 is positioned between the side SD1 and the voltage-controlled oscillation circuit 44. Additionally, a regulator 68 that supplies the regulated power supply voltage VREG4 to the logic circuit 70 is also positioned on the side SD1. For example, the regulator 68 is positioned between the logic circuit 70 and the temperature compensation circuit 80, and is located near the logic circuit 70. Therefore, since the regulated power supply voltages VREG3 and VREG4 from the regulators 67 and 68 can be supplied to the voltage control oscillation circuit 44, logic circuit 70, etc. through the short-circuited power supply line, the fluctuation of the regulated power supply voltages VREG3 and VREG4 due to the impedance of the power supply line can be suppressed.

[0088] Furthermore, the integrated circuit device 20 includes logic circuitry 70 that controls the PLL circuitry 40. Figure 3 For example, logic circuit 70 controls the division ratio of the frequency divider circuit 45 of PLL circuit 40 through Δ-Σ modulation. Alternatively, logic circuit 70 can also control the enabling or disabling of PLL circuit 40, or control the setting of various operating modes of PLL circuit 40. Furthermore, in Figure 12 In this circuit, the logic circuit 70 that controls the PLL circuit 40 is located on the SD1 side. For example, the logic circuit 70 operates according to a logic clock signal, generating high-frequency noise through the logic operation. Moreover, when this high-frequency noise is superimposed on the reference voltage generated by the reference voltage generation circuit 62 and the output signal of the charge pump circuit 42, a problem of reduced clock frequency accuracy occurs. Regarding this point, in Figure 12 In this configuration, the logic circuit 70, along with the output buffer circuit 50, is also centrally located on the SD1 side. This allows the reference voltage generation circuit 62, charge pump circuit 42, and other components located on the SD2 side to be spaced further apart from the logic circuit 70, output buffer circuit 50, and other components that become sources of high-frequency noise, thus preventing a decrease in clock frequency accuracy due to high-frequency noise.

[0089] In addition, such as Figure 3As shown, the PLL circuit 40 includes a voltage control oscillation circuit 44. For example, the PLL circuit 40 includes the voltage control oscillation circuit 44 that performs oscillation operation at an oscillation frequency corresponding to the control voltage from the loop filter 43 and outputs a clock signal CKV. Also, as shown, the voltage control oscillation circuit 44 is disposed between the clock land PCK and the ground land PGND. For example, the voltage control oscillation circuit 44 is disposed on the direction DR1 side of the clock land PCK, and the ground land PGND is disposed on the direction DR1 side of the voltage control oscillation circuit 44. In this way, the region between the clock land PCK and the ground land PGND can be effectively utilized to configure the voltage control oscillation circuit 44, and efficient layout configuration can be achieved. Further, the clock signal CKV generated by the voltage control oscillation circuit 44 can be input to the output buffer circuit 50 as a clock signal CK through a short-pass clock signal wiring via the output frequency division circuit 46, for example. Also, the output buffer circuit 50 can output a signal that has been buffered with respect to the clock signal CK as a clock signal CKQ. For example, by shortening the clock signal wiring, high-frequency noise generated from the clock signal wiring can also be reduced. In addition, the voltage control oscillation circuit 44 has a resonance circuit that uses an inductor, and most of the configuration region of the voltage control oscillation circuit 44 becomes a configuration region of the inductor. The inductor is realized by, for example, wiring a metal line in a spiral shape or the like. Figure 12

[0090] Further, the integrated circuit device 20 includes a temperature compensation circuit 80 that performs temperature compensation of the oscillation frequency of the oscillation signal OSC. Also, as shown, the temperature compensation circuit 80 is disposed on the direction DR1 side of the oscillation circuit 30. For example, the temperature compensation circuit 80 is disposed on the direction DR1 side of the oscillation circuit 30. In this way, the region on the direction DR1 side of the oscillation circuit 30 can be effectively utilized to configure the temperature compensation circuit 80, and efficient layout configuration can be achieved. Further, the oscillation signal OSC generated by the oscillation circuit 30 can be input to the temperature compensation circuit 80 as a clock signal CK through a short-pass clock signal wiring via the output frequency division circuit 46, for example. Also, the temperature compensation circuit 80 can output a signal that has been temperature-compensated with respect to the clock signal CK as a clock signal CKQ. For example, by shortening the clock signal wiring, high-frequency noise generated from the clock signal wiring can also be reduced. In addition, the temperature compensation circuit 80 has a configuration region that uses an inductor, and most of the configuration region of the temperature compensation circuit 80 becomes a configuration region of the inductor. The inductor is realized by, for example, wiring a metal line in a spiral shape or the like.

[0090] Further, the integrated circuit device 20 includes a temperature compensation circuit 80 that performs temperature compensation of the oscillation frequency of the oscillation signal OSC. Also, as shown, the temperature compensation circuit 80 is disposed on the direction DR1 side of the oscillation circuit 30. For example, the temperature compensation circuit 80 is disposed on the direction DR1 side of the oscillation circuit 30. In this way, the region on the direction DR1 side of the oscillation circuit 30 can be effectively utilized to configure the temperature compensation circuit 80, and efficient layout configuration can be achieved. Further, the oscillation signal OSC generated by the oscillation circuit 30 can be input to the temperature compensation circuit 80 as a clock signal CK through a short-pass clock signal wiring via the output frequency division circuit 46, for example. Also, the temperature compensation circuit 80 can output a signal that has been temperature-compensated with respect to the clock signal CK as a clock signal CKQ. For example, by shortening the clock signal wiring, high-frequency noise generated from the clock signal wiring can also be reduced. In addition, the temperature compensation circuit 80 has a configuration region that uses an inductor, and most of the configuration region of the temperature compensation circuit 80 becomes a configuration region of the inductor. The inductor is realized by, for example, wiring a metal line in a spiral shape or the like.

[0091] Further, the integrated circuit device 20 includes a temperature compensation circuit 80 that performs temperature compensation of the oscillation frequency of the oscillation signal OSC. Also, as shown, the temperature compensation circuit 80 is disposed on the direction DR1 side of the oscillation circuit 30. For example, the temperature compensation circuit 80 is disposed on the direction DR1 side of the oscillation circuit 30. In this way, the region on the direction DR1 side of the oscillation circuit 30 can be effectively utilized to configure the temperature compensation circuit 80, and efficient layout configuration can be achieved. Further, the oscillation signal OSC generated by the oscillation circuit 30 can be input to the temperature compensation circuit 80 as a clock signal CK through a short-pass clock signal wiring via the output frequency division circuit 46, for example. Also, the temperature compensation circuit 80 can output a signal that has been temperature-compensated with respect to the clock signal CK as a clock signal CKQ. For example, by shortening the clock signal wiring, high-frequency noise generated from the clock signal wiring can also be reduced. In addition, the temperature compensation circuit 80 has a configuration region that uses an inductor, and most of the configuration region of the temperature compensation circuit 80 becomes a configuration region of the inductor. The inductor is realized by, for example, wiring a metal line in a spiral shape or the like. Figure 12As shown, the temperature compensation circuit 80 is provided between the oscillation circuit 30 and the clock connection pad PCK and the ground connection pad PGND. For example, the temperature compensation circuit 80 is provided on the direction DR2 side of the oscillation circuit 30, and the clock connection pad PCK and the ground connection pad PGND are provided on the direction DR2 side of the temperature compensation circuit 80. Further, the temperature compensation circuit 80 is provided between the oscillation circuit 30 and the voltage control oscillation circuit 44, and the temperature compensation circuit 80 is provided on the direction DR2 side of the oscillation circuit 30, and the voltage control oscillation circuit 44 is provided on the direction DR2 side of the temperature compensation circuit 80. In this way, by providing the temperature compensation circuit 80 between the oscillation circuit 30 and the clock connection pad PCK and the ground connection pad PGND, the temperature compensation circuit 80 can be efficiently configured using the area between the oscillation circuit 30 and the clock connection pad PCK and the ground connection pad PGND, and efficient layout configuration can be achieved. Further, the temperature compensation circuit 80 can be configured in the vicinity of the oscillation circuit 30, and the temperature compensation voltage VCP from the temperature compensation circuit 80 can be input to the oscillation circuit 30 through a short signal path, and temperature compensation of the oscillation frequency can be achieved.

[0092] Further, the integrated circuit device 20 includes a temperature sensor circuit 90 that detects a temperature, a temperature compensation circuit 80 that performs temperature compensation of an oscillation frequency of an oscillation signal OSC based on an output of the temperature sensor circuit 90, and an output enable connection pad POE for controlling output enable of a clock signal CKQ. Also, as shown in FIG. 1, the temperature sensor circuit 90 and the output enable connection pad POE are configured in an overlapping manner in plan view. Figure 12 Figure 4 , Figure 5 ​The temperature sensor circuit 90 is also arranged below the output enable pad POE as shown in the illustration. In this way, the temperature sensor circuit 90 can be effectively arranged using the area of the output enable pad POE, and the area of the output enable pad POE can be prevented from becoming a dead area. In this way, by arranging the temperature sensor circuit 90 in the area of the output enable pad POE that would otherwise become a dead area, even if the proportion of the area of the pads in the overall area of the integrated circuit device 20 becomes high, the layout area of the integrated circuit device 20 can be reduced, and the integrated circuit device 20 can be made smaller. In addition, if the temperature sensor circuit 90 is arranged in an overlapping manner with the output enable pad POE when viewed from above, the output enable pad POE functions as a shielding member, and the transmission of high-frequency noise to the temperature sensor circuit 90 can be suppressed. For example, by the shielding effect of the output enable pad POE, the electromagnetic coupling, electrostatic coupling between the output buffer circuit 50 and the temperature sensor circuit 90 can be reduced, and the superimposition of high-frequency noise on the output signal of the temperature sensor circuit 90 can be prevented. Thus, the output signal of the temperature sensor circuit 90 can be prevented from fluctuating due to high-frequency noise, and the occurrence of a situation in which the temperature compensation processing cannot be performed properly, and the accuracy of the clock frequency is reduced can be prevented. In addition, in Figure 12 In the above embodiment, the temperature sensor circuit 90 and the output enable pad POE are arranged in an overlapping manner, but a variation can be implemented in which the temperature sensor circuit 90 and the ground pad PGND are arranged in an overlapping manner when viewed from above. In this way, as in the case in which the temperature sensor circuit 90 and the output enable pad POE are arranged in an overlapping manner, the improvement of the layout efficiency can be achieved, and the fluctuation of the output signal of the temperature sensor circuit 90 can be suppressed using the shielding effect, and the like.

[0093] In addition, the test circuit 92 and the interface circuit 94 of Figure 2 may also be arranged so as to overlap the output enable pad POE when viewed from above. For example, the test circuit 92 is a circuit for testing the internal circuit such as the analog circuit of the integrated circuit device 20 using the output enable pad POE, and thus is preferably arranged below the output enable pad POE. The interface circuit 94 also uses the output enable pad POE as an input and output terminal for serial data, and thus is preferably arranged below the output enable pad POE.

[0094] In addition, the layout arrangement of the integrated circuit device 20 of the present embodiment is not limited to Figure 12 the arrangement shown above, and various variations can be implemented. For example, another layout arrangement example of the integrated circuit device 20 is shown in Figure 13 In Figure 12 , the phase comparator 41, the charge pump circuit 42, and the loop filter 43 are arranged on the side of the edge SD2, but in Figure 13In the circuit, phase comparator 41, charge pump circuit 42, and loop filter 43 are configured on side SD1. Additionally, in... Figure 12 In the middle, logic circuit 70 is configured on the SD1 side, but... Figure 13 In the middle, logic circuit 70 is configured on the SD2 side. Figure 12 In this configuration, circuit blocks that will become sources of high-frequency noise are concentrated on side SD1, while circuit blocks that are to be protected from the adverse effects of high-frequency noise are placed on side SD2. From the viewpoint of preventing clock frequency accuracy degradation caused by high-frequency noise, this is the preferred approach. Figure 12 Layout configuration.

[0095] For example, Figure 14 This is an explanatory diagram about phase noise. The horizontal axis represents the offset frequency, and the vertical axis represents the phase noise. Figure 14 A1 shows the noise characteristics of the clock signal CKQ when the PLL circuit 40 operates freely without phase synchronization. On the other hand, A2 and A3 show the noise characteristics of the clock signal CKQ when the PLL circuit 40 is phase-synchronized with the oscillation signal OSC. Since the phase noise of the oscillation signal OSC is relatively low, synchronizing the PLL circuit 40 with the oscillation signal OSC can reduce noise. Figure 14 The noise entering from the left side of the line shown in A4. Furthermore, Figure 14 A2 is adopted Figure 13 In terms of noise characteristics under the given layout configuration, A3 adopts... Figure 12 Noise characteristics under certain layout configurations. For example... Figure 12 As shown, the output buffer circuit 50, logic circuit 70, etc., which will become the source of high-frequency noise, are concentrated on the SD1 side, while the reference voltage generation circuit 62, charge pump circuit 42, etc., which are intended to be located away from the high-frequency noise source, are concentrated on the SD2 side. Thus, as Figure 14 As shown in A3, it can reduce the phase noise of the clock signal CKQ.

[0096] 3. Oscillator

[0097] Figure 15 An example of the construction of the oscillator 4 according to this embodiment is shown. The oscillator 4 includes an oscillator 10, an integrated circuit device 20, and a package 15 for housing the oscillator 10 and the integrated circuit device 20. The package 15 is formed of, for example, ceramic, and has a housing space inside, in which the oscillator 10 and the integrated circuit device 20 are housed. The housing space is hermetically sealed, preferably in a near-vacuum state, i.e., a depressurized state. Through the package 15, the oscillator 10 and the integrated circuit device 20 can be appropriately protected from the effects of impact, dust, heat, moisture, etc.

[0098] Package 15 includes a base 16 and a cover 17. Specifically, package 15 comprises a base 16 supporting the oscillator 10 and the integrated circuit device 20, and a cover 17 engaged with the upper surface of the base 16 to form a receiving space between the cover and the base 16. The oscillator 10 is supported by a stepped portion provided inside the base 16 via terminal electrodes. The integrated circuit device 20 is disposed on the inner bottom surface of the base 16. Specifically, the integrated circuit device 20 is disposed with its active surface facing the inner bottom surface of the base 16. The active surface is the surface of the integrated circuit device 20 where circuit elements are formed. Furthermore, bumps BMP are formed on the connection pads that serve as terminals of the integrated circuit device 20. The integrated circuit device 20 is supported on the inner bottom surface of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, through which the oscillator 10 and the integrated circuit device 20 are electrically connected. Furthermore, the integrated circuit device 20 is electrically connected to external terminals 18 and 19, which serve as external connection terminals for the oscillator 4, via the bump plate (BMP) and internal wiring of the package 15. External terminals 18 and 19 are formed on the outer bottom surface of the package 15. External terminals 18 and 19 are connected to external devices via external wiring. External wiring may be, for example, wiring formed on a circuit board on which external devices are mounted. This allows clock signals to be output to external devices.

[0099] In addition, Figure 15 In this embodiment, the integrated circuit device 20 is flip-chip mounted with its active surface facing downwards, but this embodiment is not limited to this mounting. For example, the integrated circuit device 20 may also be mounted with its active surface facing upwards. That is, the integrated circuit device 20 may be mounted with its active surface facing the oscillator 10. Alternatively, the oscillator 4 may also be a wafer-level package (WLP) oscillator. In this case, the oscillator 4 includes: a base having a semiconductor substrate and a through electrode penetrating between a first surface and a second surface of the semiconductor substrate; an oscillator 10 fixed to the first surface of the semiconductor substrate via a conductive bonding member such as a metal bump; and an external terminal disposed on the second surface side of the semiconductor substrate via an insulating layer such as a redistribution wiring layer. Furthermore, an integrated circuit, which becomes the integrated circuit device 20, is formed on the first or second surface of the semiconductor substrate. In this case, the multiple bases and multiple covers are joined by bonding a first semiconductor wafer having multiple bases configured with an oscillator 10 and an integrated circuit to a second semiconductor wafer having multiple covers, and then the oscillator 4 is monolithically produced using a dicing machine or the like. In this way, a wafer-level packaged oscillator 4 can be realized, and the oscillator 4 can be manufactured with high throughput and low cost.

[0100] As explained above, the integrated circuit device of the present embodiment includes an oscillation circuit that generates an oscillation signal using a resonator, an output buffer circuit that outputs a clock signal based on the oscillation signal, a direct current voltage generation circuit that generates a direct current voltage used for generating the oscillation signal or the clock signal, a power supply land to which a power supply voltage is supplied, a ground land to which a ground voltage is supplied, and a clock land that outputs the clock signal. Also, the ground land and the direct current voltage generation circuit are arranged in an overlapping manner in plan view.

[0101] According to the present embodiment, the power supply voltage and the ground voltage are supplied to the integrated circuit device through the power supply land and the ground land, the oscillation signal is generated by the oscillation circuit using the resonator, and the clock signal based on the oscillation signal is output from the clock land through the output buffer circuit. Also, the direct current voltage generation circuit that generates the direct current voltage used for generating the oscillation signal or the clock signal is arranged in an overlapping manner with the ground land in plan view. In this way, the ground land functions as a shielding member, and it is possible to suppress the transmission of high frequency noise to the direct current voltage generation circuit, and it is possible to prevent problems such as a decrease in the precision of the clock frequency due to high frequency noise. In addition, it is possible to effectively use the area of the ground land that would otherwise be a dead space to arrange the direct current voltage generation circuit, and thus it is possible to achieve an efficient layout arrangement, and it is possible to achieve a reduction in the size of the integrated circuit device. In this way, according to the present embodiment, it is possible to provide an integrated circuit device and the like that can achieve both the prevention of a decrease in the precision of the clock frequency through the shielding effect of the ground land and the like and the efficient layout arrangement that effectively uses the land area.

[0102] Further, in the present embodiment, the clock land and the output buffer circuit can be arranged in an overlapping manner in plan view.

[0103] In this way, it is possible to output the clock signal from the output buffer circuit to the clock land arranged directly above the output buffer circuit using the path of the short clock wiring that extends from the output buffer circuit toward the clock land. Due to this, it is possible to minimize the impedance of the clock wiring, and it is possible to suppress the potential variation caused by the impedance. Further, since the output buffer circuit that is a source of high frequency noise and the clock land can be arranged in one location, it is possible to easily achieve measures such as a layout arrangement for mitigating the adverse effects of noise from the source of high frequency noise.

[0104] Further, in the present embodiment, the direct current voltage generation circuit can be a reference voltage generation circuit that generates a reference voltage used for generating at least one of a bias current, a bias voltage, or a regulated power supply voltage.

[0105] Thus, by the shielding effect based on the ground connection pad, the electromagnetic coupling and the electrostatic coupling between the output buffer circuit, the clock connection pad, and the reference voltage generation circuit are reduced, and superposition of high-frequency noise on the reference voltage output from the reference voltage generation circuit is prevented.

[0106] Further, in the present embodiment, the direct-current voltage generation circuit is a regulator that generates a regulated power supply voltage from a power supply voltage.

[0107] Thus, by the shielding effect based on the ground connection pad, superposition of high-frequency noise on the regulated power supply voltage output from the regulator is prevented, and reduction in the precision of the clock frequency due to high-frequency noise is prevented.

[0108] Further, in the present embodiment, the integrated circuit device can include a PLL circuit that performs a PLL operation for generating a clock signal that is in phase with an oscillation signal, and the direct-current voltage generation circuit can be a regulator that supplies a regulated power supply voltage to the charge pump circuit, the loop filter, or the charge pump circuit.

[0109] Thus, by the shielding effect based on the ground connection pad, superposition of high-frequency noise on the output voltage of the charge pump circuit, the loop filter, or the regulator is prevented, and reduction in the precision of the clock frequency due to high-frequency noise is prevented.

[0110] Further, in the present embodiment, the integrated circuit device can include a first side and a second side opposite the first side, and the output buffer circuit and the clock connection pad can be disposed on the first side, and the direct-current voltage generation circuit and the ground connection pad can be disposed on the second side.

[0111] Thus, the distance between the output buffer circuit and the clock connection pad, which are sources of high-frequency noise, and the direct-current voltage generation circuit and the ground connection pad can be increased, and transmission of high-frequency noise from the output buffer circuit and the clock connection pad to the direct-current voltage generation circuit and the ground connection pad can be suppressed.

[0112] Further, in the present embodiment, the integrated circuit device can include a PLL circuit that performs a PLL operation for generating a clock signal that is in phase with an oscillation signal, and the direct-current voltage generation circuit can be a reference voltage generation circuit that generates a reference voltage used in the operation of the PLL circuit.

[0113] By providing such a PLL circuit, a clock signal that is in phase with the oscillation signal and has a desired frequency can be output. Furthermore, the reference voltage generation circuit that generates a reference voltage required for the operation of such a PLL circuit is disposed so as to overlap the ground connection pad in plan view, and reduction in the precision of the clock frequency due to high-frequency noise and the like can be prevented.

[0114] Further, in the present embodiment, the PLL circuit can include a phase comparator, a charge pump circuit, and a loop filter, and the charge pump circuit can be provided on the second side.

[0115] In this way, the charge pump circuit, the reference voltage generation circuit, and the ground connection pad can be collectively arranged at a position away from the output buffer circuit and the clock connection pad arranged on the first side, and transmission of high-frequency noise from the output buffer circuit and the clock connection pad to the charge pump circuit and the like can be suppressed.

[0116] Further, in the present embodiment, the loop filter can be provided on the second side.

[0117] In this way, the loop filter, the reference voltage generation circuit, and the ground connection pad and the like can be collectively arranged at a position away from the output buffer circuit and the clock connection pad arranged on the first side, and transmission of high-frequency noise from the output buffer circuit and the clock connection pad to the loop filter and the like can be suppressed.

[0118] Further, in the present embodiment, the integrated circuit device can include a regulator that supplies a regulated power supply voltage generated in accordance with the reference voltage to the charge pump circuit, and the regulator can be provided on the second side.

[0119] In this way, the distance between the regulator and the high-frequency noise source such as the output buffer circuit can be increased, and superposition of high-frequency noise on the regulated power supply voltage can be suppressed, and a decrease in the precision of the clock frequency can be prevented.

[0120] Further, in the present embodiment, the integrated circuit device can include a logic circuit that controls the PLL circuit, and the logic circuit can be provided on the first side.

[0121] In this way, the logic circuit is also collectively arranged on the first side together with the output buffer circuit and the like. Thus, the distance between the reference voltage generation circuit and the like arranged on the first side and the logic circuit and the output buffer circuit and the like that are high-frequency noise sources can be increased, and a decrease in the precision of the clock frequency due to high-frequency noise can be prevented.

[0122] Further, in the present embodiment, the PLL circuit can include a voltage control oscillation circuit, and the voltage control oscillation circuit can be provided between the clock connection pad and the ground connection pad.

[0123] In this way, the voltage control oscillation circuit can be arranged using the area between the clock connection pad and the ground connection pad effectively, and efficient layout arrangement can be achieved.

[0124] Further, in the present embodiment, the integrated circuit device can have a shape including a third side that intersects the first side and the second side, and the oscillation circuit can be provided on the third side.

[0125] Thus, the distance between the output buffer circuit or the like arranged on the first side and the oscillation circuit can be made longer, and the situation in which high-frequency noise of the output buffer circuit is superimposed on the oscillation signal and the oscillation characteristics deteriorate can be prevented. Further, the distance between the reference voltage generation circuit or the like arranged on the second side and the oscillation circuit can be made longer, and the situation in which oscillation noise from the oscillation circuit is superimposed on the reference voltage of the reference voltage generation circuit or the like and the precision of the clock frequency decreases or the like can be prevented.

[0126] Further, in the present embodiment, the integrated circuit device can include a temperature compensation circuit that performs temperature compensation of the oscillation frequency of the oscillation signal, and the temperature compensation circuit can be arranged between the oscillation circuit and the clock connection pad and the ground connection pad.

[0127] Thus, the temperature compensation circuit can be arranged using the area between the oscillation circuit and the clock connection pad and the ground connection pad effectively, and efficient layout arrangement can be achieved.

[0128] Further, in the present embodiment, the integrated circuit device can include a temperature sensor circuit that detects a temperature, a temperature compensation circuit that performs temperature compensation of the oscillation frequency of the oscillation signal based on an output of the temperature sensor circuit, and an output enable connection pad for controlling output enable of the clock signal. Further, the temperature sensor circuit can be arranged in an overlapping manner with the output enable connection pad or the ground connection pad in plan view.

[0129] Thus, the electromagnetic coupling and the electrostatic coupling between the output buffer circuit or the like and the temperature sensor circuit are reduced by the shielding effect of the output enable connection pad or the ground connection pad, and superimposition of high-frequency noise on the output signal of the temperature sensor circuit can be prevented.

[0130] Further, the present embodiment relates to an oscillator that includes the integrated circuit device described above and a resonator.

[0131] Further, the present embodiment has been described in detail as described above, but a person skilled in the art can easily understand that various modifications that do not substantially depart from the present application can be made. Therefore, such modified examples are all included in the scope of the present application. For example, in the specification or the drawings, a term described at least once together with a different term of broader meaning or synonymous meaning can be replaced with the different term in any place in the specification or the drawings. In addition, all combinations of the present embodiment and the modified examples are also included in the scope of the present application. Further, the structure, the operation, and the like of the integrated circuit device and the oscillator are not limited to those described in the present embodiment, and various modifications can be made.

Claims

1. An integrated circuit device, characterized in that, The integrated circuit device includes: An oscillating circuit that uses an oscillator to generate an oscillating signal; An output buffer circuit that outputs a clock signal based on the oscillation signal; A DC voltage generating circuit generates a DC voltage, which is used to generate the oscillation signal or the clock signal; The power connector is supplied with power voltage. The grounding connection plate is supplied with grounding voltage; as well as A clock connection disk that outputs the clock signal. When viewed from above, the grounding connection plate and the DC voltage generation circuit are arranged in an overlapping manner.

2. The integrated circuit device according to claim 1, characterized in that, In the top view, the clock connection disk and the output buffer circuit are configured in an overlapping manner.

3. The integrated circuit device according to claim 1 or 2, characterized in that, The DC voltage generation circuit is a reference voltage generation circuit that generates a reference voltage, which is used to generate at least one of bias current, bias voltage, or regulating power supply voltage.

4. The integrated circuit device according to claim 1 or 2, characterized in that, The DC voltage generation circuit is a regulator that generates and adjusts the power supply voltage based on the power supply voltage.

5. The integrated circuit device according to claim 1 or 2, characterized in that, The integrated circuit device includes a PLL circuit that performs PLL operations to generate a clock signal that is phase-synchronized with the oscillation signal. The PLL circuit includes a phase comparator, a charge pump circuit, and a loop filter. The DC voltage generation circuit is a regulator that supplies a regulated power supply voltage to the charge pump circuit, the loop filter, or the charge pump circuit.

6. The integrated circuit device according to claim 1, characterized in that, The shape of the integrated circuit device includes a first side and a second side opposite to the first side. The output buffer circuit and the clock connection disk are arranged on the first side. The DC voltage generation circuit and the grounding connection plate are arranged on the second side.

7. The integrated circuit device according to claim 6, characterized in that, The integrated circuit device includes a PLL circuit that performs PLL operations to generate a clock signal that is phase-synchronized with the oscillation signal. The DC voltage generation circuit is a reference voltage generation circuit that generates the reference voltage used in the operation of the PLL circuit.

8. The integrated circuit device according to claim 7, characterized in that, The PLL circuit includes a phase comparator, a charge pump circuit, and a loop filter. The charge pump circuit is located on the second side.

9. The integrated circuit device according to claim 8, characterized in that, The loop filter is located on the second side.

10. The integrated circuit device according to claim 8 or 9, characterized in that, The integrated circuit device includes a regulator that supplies a regulated power supply voltage, generated based on the reference voltage, to the charge pump circuit. The regulator is located on the second side.

11. The integrated circuit device according to any one of claims 7 to 9, characterized in that, The integrated circuit device includes logic circuitry for controlling the PLL circuit. The logic circuit is located on the first side.

12. The integrated circuit device according to any one of claims 7 to 9, characterized in that, The PLL circuit includes a voltage-controlled oscillation circuit. The voltage-controlled oscillation circuit is located between the clock connection disk and the ground connection disk.

13. The integrated circuit device according to any one of claims 6 to 9, characterized in that, The outline of the integrated circuit device includes a third side that intersects the first side and the second side. The oscillation circuit is located on the third side.

14. The integrated circuit device according to claim 1 or 2, characterized in that, The integrated circuit device includes a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the oscillation signal. The temperature compensation circuit is disposed between the oscillation circuit and the clock connection disk and the ground connection disk.

15. The integrated circuit device according to claim 1 or 2, characterized in that, The integrated circuit device includes: Temperature sensor circuit, which detects temperature; A temperature compensation circuit, which performs temperature compensation on the oscillation frequency of the oscillation signal based on the output of the temperature sensor circuit; and The output enable connection panel is used to control the output enable of the clock signal. In the top view, the temperature sensor circuit is configured to overlap with the output enable connection panel or the ground connection panel.

16. An oscillator, characterized in that, The oscillator contains: The integrated circuit device according to any one of claims 1 to 15; and The oscillator.

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