Method and apparatus for accelerating convergence and controlling behavior of digital control loops

Abstract

A system for converging a control loop to a reference value. A device under control of the control loop generates an output signal. A comparator compares the output signal to a reference value. In response to the output signal being less than the reference value, an up signal is output, and in response to the output signal being greater than the reference value, a down signal is output. A counter is configured to maintain a counter value that is incremented in response to the up signal and decremented in response to the down signal. The counter outputs a gain control value. An up / down signal tracker is configured to track a pattern of an up signal and a down signal and compare the tracked pattern to one or more predetermined patterns, such that in response to the up signal and the down signal matching one of the one or more predetermined patterns, the counter size is reduced.

Description

Technical Field

[0001] The present invention relates to control loop convergence and, more particularly, to a system and method for increasing the rate for control loop convergence using a dynamic step size or a variable counter size. Background Art

[0002] As part of communication between remote locations, it is necessary to process the received signal after it has passed through a channel to convert the received signal into data or other useful form. As will be appreciated, whether the signal is optical or electrical, passing through the channel can degrade the signal and cause it to lose power. However, other components in the communication system require the signal at a specified and known power level for downstream processing. This presents several challenges when receiving and processing the received signal.

[0003] One such challenge is that the power level of the received signal may be highly variable. For example, if the channel is poor or long in length, or if the signal is transmitted at a low power level, the received signal amplitude will be small. Alternatively, the channel may be short, high quality, or the signal may be transmitted at a high power level, in which case the amplitude of the received signal will be high. Of course, any range of received signal amplitudes between high and low may also be received, and this may vary over time based on any number of different factors, including but not limited to changes in channels, changes in supply voltage, changes in installation (connection to different channels), or many other factors. Regardless of the power of the received signal, it is desirable to present a signal of a preferred power level (amplitude) to the downstream processing elements. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art and provide additional benefits, a method for controlling the convergence of an automatic gain control system is disclosed. The exemplary method uses a variable gain amplifier (VGA) to adjust the amplitude of an input signal to generate a VGA output signal. In this embodiment, the amplitude adjustment occurs based on a control vector provided to the VGA. The method also includes processing the VGA output signal with a detector to determine the amplitude value of the VGA output signal and comparing the amplitude value with a target value.

[0005] In response to the comparison, the method determines whether the amplitude value is less than the target value. If so, the method evaluates the amplitude value relative to the target value to determine the difference between the amplitude value and the target value. Thereafter, the method reduces the control vector by a first amount, a second amount, or directly to an amount of a minimum control vector based on evaluating the amplitude value relative to the target value. Alternatively, in response to determining that the amplitude value is greater than the target value in the comparison, the amplitude value is evaluated relative to the target value to determine the difference between the amplitude value and the target value. Thereafter, based on evaluating the amplitude value relative to the target value, the control vector is increased by a first amount, a second amount, or directly to an amount of a maximum control vector.

[0006] In one embodiment, the first amount is a step size of a single step and the second amount is a step size greater than a single step. In one configuration, the amplitude value is a peak value of the VGA output signal. The method may also include converting the control vector into an analog control signal such that the analog control signal is a control signal for controlling the gain of the VGA.

[0007] A system for controlling the gain of a variable gain amplifier is also disclosed, the system comprising a detector module configured to determine an amplitude value output by the variable gain amplifier. Also part of this embodiment is a comparator module configured to compare the amplitude value with a target value and, in response to the comparison, generate an up_dn signal. The digital control module is configured to receive the up_dn signal and process the up_dn signal to generate a control vector. One or more digital-to-analog converters are configured to convert the control vector into an analog control signal such that the analog control signal controls the gain of the variable gain amplifier.

[0008] In one embodiment, the comparator module consists of three comparators. The detector module can be configured as a peak detector, which is configured to detect the peak value of the variable gain amplifier output. In one configuration, the digital control module includes control logic, a user interface, a memory or register, and one or more comparators. It is conceivable that the digital control module can be configured to evaluate the up_dn signal relative to a threshold value, and increase or decrease the control vector by a step maximum value or adjust the control vector up or down by a small step size in response to the evaluation. In another variation, the digital control module evaluates the past value of the up_dn signal to adjust the step size value, so that the step size signal controls the rate of change of the control vector, and increases or decreases the control vector by the step size value based on the up_dn signal.

[0009] A method for controlling the gain of a variable gain amplifier based on a control vector value is also disclosed, the method comprising: monitoring a variable gain amplifier output signal to generate a monitoring signal, and comparing the monitoring signal with a target value to generate an up_dn value, the up_dn value indicating whether the monitoring signal is greater than or less than the target value. Then, the up_dn value is evaluated for changes in the up_dn value over a predetermined number of up_time values. In response to changes in the up_dn value over a predetermined number of up_time values, the step size value is reduced. In response to zero changes in the up_dn value over a predetermined number of up_dn values ​​or changes less than a certain number, the step size value is increased. Then, if the monitoring signal is greater than the target value, the control vector value is increased by the step size value, or if the monitoring signal is greater than the target value, the control vector value is increased by the step size value? Thereafter, the gain of the variable gain amplifier is adjusted based on the control vector value. In this embodiment, reducing the control vector value increases the gain, and increasing the control vector value decreases the gain. However, in other embodiments, other relationships can be established between the control vector value and the gain, so the claims and disclosure are not limited to a specific set relationship.

[0010] In one embodiment, the method further includes converting the control vector value into an analog control signal and providing the analog control signal to the variable gain amplifier. The step of monitoring the variable gain amplifier output signal may include determining a peak value of the variable gain amplifier output signal. In one configuration, the up_dn signal is a logic "0" value indicating that the variable gain amplifier output signal is less than a target value or a logic "1" value indicating that the variable gain amplifier output signal is greater than the target value. The step size value has a maximum value that determines a maximum rate of change of the control vector value. In an example embodiment, the predetermined number of up_dn values ​​is ten, decreasing the step size value decreases the step size value by half, and increasing the step size value doubles the step size value.

[0011] A method for controlling the convergence of an automatic gain control unit is also disclosed, comprising receiving an input signal and adjusting the peak-to-peak amplitude of the input signal with a variable gain amplifier (VGA) based on a control vector. In the method, the VGA generates a VGA output signal. The VGA output signal is then processed with a peak detector to determine a peak value of the VGA output signal, and the peak value is compared with a target value. In response to the comparison, it is determined whether the peak value is greater than or less than the target value, and in response to the comparison, it is determined whether the peak value is less than the target value, and then the following operations are performed. The peak value is compared with the target value to determine whether the peak value is less than a threshold value than the target value, and in response to the peak value not being greater than the target value by a threshold value, it is determined whether the control vector is at a minimum value. In response to the control vector being at the minimum value, the control vector is not changed. Alternatively, in response to the control vector not being at the minimum value, the control vector is reduced by a first amount.

[0012] The thresholds are controlled by analog circuitry rather than being under digital control. In one embodiment, the thresholds are programmable, but in other embodiments, the values ​​are fixed. The thresholds should be programmed to assert up_max and dn_max when the output signal amplitude is significantly wrong. "up_max" should be asserted when the control vector should be significantly increased. "dn_max" should be asserted when the control vector should be significantly decreased.

[0013] The method further includes: in response to the comparison, determining whether the peak value is greater than the target value by a threshold value, determining whether the control vector is within a step maximum value of a minimum control vector value. In response to the control vector being within the step maximum value of the minimum control vector value, reducing the control vector to the minimum control vector value. Otherwise, in response to the control vector being greater than the step maximum value away from the minimum control vector value, reducing the control vector by the step maximum value.

[0014] In the method, in response to the comparison, determining whether the peak value is greater than a target value, comparing the peak value to the target value to determine whether the peak value is less than the target value by a second threshold value. And, in response to the peak value not being greater than the target value by the second threshold value, determining whether the control vector is at a maximum value. In response to the control vector being at a minimum value, not changing the control vector, and in response to the control vector not being less than the maximum value, increasing the control vector by a first amount.

[0015] The method further includes: in response to the comparison, determining whether the peak value is greater than the target value by a second threshold, determining whether the control vector is within a step maximum of the maximum control vector value, and then, in response to the control vector being within the step maximum of the maximum control vector value, increasing the control vector to the maximum control vector value, or in response to the control vector being greater than the step maximum from the maximum control vector value, increasing the control vector by the step maximum.

[0016] In one embodiment, the second amount is greater than two step sizes. In one configuration, the control vector controls a gain of the VGA. The step maximum is the maximum amount that the control vector can change at one time.

[0017] To overcome the shortcomings of the prior art, a system for controlling the gain of a variable amplifier is disclosed. In one embodiment, the system includes an error detector configured to compare the amplifier output with a reference value and, in response thereto, output an error signal. Additionally, part of the system is a counter having a counter size, configured to maintain a counter value reflecting the output of the error detector over time, and, in response to the counter value reaching the counter size, output a gain control signal. An error detector signal monitor is configured to track the error detector signal over time, and, in response to the error detector signal satisfying a predetermined pattern, provide a counter size control signal to the counter to reduce the counter size, which reduces the time required for the amplifier output to reach the reference value.

[0018] In one embodiment, the reference value includes an expected or desired amplifier output amplitude (peak, average or other designation). The system may also include a loop state machine and a digital-to-analog converter, such that the loop state machine is configured to convert the gain control signal to a digital gain control value, wherein the digital gain control value is provided to the digital-to-analog converter, and the digital-to-analog converter converts the digital gain control value to an analog gain control signal, and the analog gain control signal is provided to the variable amplifier. In one configuration, wherein the error detector signal monitor is configured to increase a counter size in response to the error detector signal not satisfying a predetermined pattern. The step of increasing the counter size may include resetting the counter size to a maximum counter size.

[0019] A method for controlling the gain of a variable gain amplifier is also disclosed. In one embodiment, the method includes comparing a variable gain amplifier output signal with a reference value to determine whether the variable gain amplifier output signal is greater than or less than the reference value. Then, in response to the variable gain amplifier output signal being greater than the reference value, an up signal is generated. In response to the variable gain amplifier output signal being less than the reference value, a down signal is generated, and a counter is updated in response to the up signal and the down signal. The operating method tracks the number of up signals and down signals associated with a predetermined pattern. In response to the counter reaching a maximum counter value or a minimum counter value, a counter output signal is output to adjust the gain of the variable gain amplifier. In response to the number of up signals and down signals associated with a predetermined pattern satisfying the predetermined pattern, the size of the counter is changed.

[0020] In one embodiment, the reference value comprises an expected or desired amplifier output amplitude (peak, average or other designation). The method may also include updating a counter in response to the up signal and the down signal. The tracking step may include maintaining a running total or previous pattern of the up signal and / or the down signal compared to a predetermined or predefined pattern of the up signal and the down signal. The counter size is a counter value that must be reached before the counter generates an output and resets.

[0021] The pattern may be a predetermined number of consecutive up signals or a predetermined number of consecutive down signals. In another embodiment, the pattern is a predetermined number of up signals or a predetermined number of consecutive down signals with respect to a predetermined number of up signals and down signals. The method may further include: in response to the counter value reaching a counter size value or a predetermined counter minimum value, resetting the counter to a counter midpoint value.

[0022] A system for controlling the convergence of a control loop to a reference value is also disclosed, the system comprising a device configured to generate an output signal under control of the control loop, and a comparator configured to: compare the output signal with a reference value, output an up signal in response to the output signal being less than the reference value, and output a down signal in response to the output signal being greater than the reference value. In addition, part of the system is a counter having a counter size defining a counter maximum value and a counter minimum value. The counter is configured to maintain a counter value that is incremented in response to an up signal and decremented in response to a down signal, such that the counter outputs a gain control value. An up / down signal tracker is provided and configured to track a pattern of up and down signals and compare the pattern to one or more predetermined patterns, and to change the counter size in response to the up and down signals matching one of the one or more predetermined patterns.

[0023] In one embodiment, the up / down signal tracker includes a memory and one or more comparators. It is contemplated that changing the counter size may include sending a control signal to the counter to reduce the size of the counter. The device under the control of the control loop may be a variable gain amplifier. The system may also include a loop state machine configured to increase or decrease a digital value representing the gain control signal in response to a gain control value from the counter. The system may also include: increasing the counter size in response to the up signal and the down signal not matching one of the one or more predetermined patterns.

[0024] By studying the following drawings and detailed description, other systems, methods, features and advantages of the present invention will be or will become clear to those skilled in the art. All such additional systems, methods, features and advantages are intended to be included within this description, within the scope of the present invention, and protected by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The components in the drawings are not necessarily drawn to scale, emphasis instead being placed upon illustrating the principles of the present invention. In the drawings, like reference numerals designate corresponding parts throughout the different views.

[0026] Figure 1 An exemplary fiber optic communication link is shown.

[0027] Figure 2A A block diagram of an exemplary variable gain amplifier control system is shown.

[0028] Figure 2B A block diagram of an exemplary digital control unit is shown.

[0029] Figure 3 A prior art method for control vector regulation is shown.

[0030] Figure 4 is a more detailed version of the prior art process for adjusting the control vector.

[0031] Figure 5 Shows Figure 4 Example plots of control vector values ​​versus time for the method.

[0032] Figure 6 An operational flow chart of the VGA control method is shown.

[0033] Figure 7 Shows Figure 6 A plot of the control vector value versus time for the method.

[0034] Fig. 8A It is shown Figure 8B and Figure 8C An index graph of the relationships.

[0035] Figure 8B A first part of an operational flow chart of an alternative method of control vector regulation is shown.

[0036] Figure 8C Shows Figure 8B The second part of the operational flow chart of the alternative method of control vector regulation is shown.

[0037] Fig. 9 Shown based on Figure 8B and Figure 8C Example graph of control vector adjustment of the method.

[0038] Fig.10 A block diagram of an exemplary system with adjustable counter size is shown.

[0039] Fig.11 A graph showing the dynamic step sizes described in the parent application.

[0040] Fig.12 Shown based on Fig.10 Signal graph of the system shown.

[0041] Fig.13 A signal graph of a prior art loop control is shown.

[0042] Fig.14 A signal graph of a loop control based on the innovation disclosed herein is shown.

[0043] Fig.15 Exemplary signal graphs for a loop control system combining dynamic step size and variable counter size are shown.

[0044] Fig.16A and Fig. 16BAn exemplary method of operation of an example embodiment of a loop control system with a variable counter size is shown. DETAILED DESCRIPTION

[0045] One example environment of use is in an optical communication system utilizing a fiber optic link and a laser or some other form of optical signal generator (light source).Although shown in an optical communication system, it is also envisioned that the system could be electrical and used as a conductive channel. Figure 1 An exemplary fiber optic communication link is shown. To enable communication between remote networking devices 104A, 104B, a fiber optic transmitter and receiver are provided. A laser driver 112, which is part of a transmitter 108, drives a laser 116 with a modulated current that produces a modulated light output from the laser. The light output is coupled into an optical fiber 120 for signal transmission. On the receiving side of the fiber optic link is a receiver 128. The light energy is converted into an electrical signal by a photodiode 132 and further processed by an amplifier 136 to set the signal amplitude to a level suitable for downstream processing elements. It is contemplated that the innovations disclosed herein may be used in other environments, or that the use environment may be different from that shown.

[0046] Figure 2A A block diagram of an exemplary variable gain amplifier control system is shown. This is only one possible configuration, and it is contemplated that other embodiments are possible without departing from the scope of the invention. In this embodiment, the control system 204 provides an analog control signal to a VGA (variable gain amplifier) ​​208 to control the gain of the VGA. An input signal is provided to the VGA 208 from an input terminal 212. The input signal may be provided from any device or system, such as, but not limited to, a photodetector. The input signal is amplified (or de-amplified) and presented as an output signal at an output terminal 216. The amount of amplification (or de-amplification) (also referred to as gain) is determined by the control signal.

[0047] The VGA control system 204 is configured with a peak detector 220, as shown, which receives an output signal from the output terminal 216. Although shown and described as a peak detector in this article, any aspect of the signal can be detected, such as but not limited to the amplitude, average value, and peak value. The detected peak value can be any type of monitor or detector. The peak detector 220 analyzes the output signal and generates a value representing the peak op amplitude (signal amplitude) of the output signal. In other embodiments, devices other than the peak detector can be used. The peak detector 220 is generally known in the art, so it is not described in detail herein. In this embodiment, the peak detector 220 can also convert the signal into a digital format, so one or more analog-to-digital converters can be included. In some embodiments, the peak detector does not include a comparator 224 or is part of a comparator 224.

[0048] The output of the peak detector 220 is fed to a comparator 224. Although shown as one comparator 224, the comparator can be one or more comparators. The comparator 224 compares the signal amplitude from the detector 220 with a target value 228. The target value 228 is a value representing the desired signal amplitude that is most suitable for downstream processing of the output signal. The target value can be programmed and changed by the user using a user interface, or it can be fixed. The target value can be stored in a memory. In this example embodiment, the comparator 228 provides a logic level output of a "0" or "1" logic value. In the discussion herein, the output of the comparator 228 provides a comparator output signal indicating the comparison result. For the purpose of discussion, the signal is referred to as an up_dn signal, so that a logic "0" value indicates that the output signal is less than the target value, and a logic level "1" value indicates that the output signal is greater than the target value. When the output signal is less than the target amplitude, the function of the VGA control system 204 is to increase the gain of the VGA 208, which in turn increases the amplitude of the output to the target value. The gain of the VGA is increased by reducing the control vector (digital control value). Conversely, when the output signal is greater than the target amplitude, the function of the VGA control system 204 is to reduce the gain of the VGA 208, which in turn reduces the amplitude of the output to the target value. Over time, the output signal amplitude will approach and be at the target value. The output of the comparator 224 is defined as the up_dn signal, which indicates whether the gain should be increased or decreased.

[0049] The comparator output is fed into a digital control unit 232. The digital control unit 232 includes one or more logic elements, registers, memories, or other elements configured to process the up_dn signal from the comparator 224 to generate a control vector. The control vector is a digital value representing the gain, such that increasing the control vector decreases the gain, and increasing the control vector decreases the gain. In other embodiments or configurations, a different relationship between the gain and the control vector may be established. During each clock cycle or sampling period, the gain may be increased by a small amount, a single step, or a large amount (e.g., many steps). It is expected that during a period or repeated time period, the output signal is sampled by the detector, resulting in a new up_dn signal being generated over time.

[0050] The control vector from the digital control unit 232 is provided to one or more digital-to-analog converters 236. The DAC 236 converts the control vector from a digital format to an analog format suitable for injection into the analog VGA 208 to control the gain. The digital control vector and DAC are configured with a high resolution, which is determined by the number of steps between the minimum and maximum control vector values. For example, there may be 1000 or more steps between the minimum and maximum control vector values. The greater the resolution (i.e., the number of digital steps between the maximum and minimum control vector values), the greater the ability to control the gain and output signal amplitude of the VGA. For accuracy, it is generally preferred to have a high degree of output signal amplitude control, so a large number of steps are required in the digital control vector and DAC 236. However, if a large number of steps are available, it will take a greater number of cycles to change from a high gain state to a lower gain state.

[0051] Figure 2B Shows Figure 2A . This is only one possible configuration of components, and other components or arrangements may be used without departing from the present innovation. The digital control unit 232 includes control logic configured to process received signals as described herein and interact with one or more other components of the digital control unit. In various embodiments, the digital control unit 232 will not include Figure 2B . In addition, part of the digital control unit 232 is a data storage register and / or memory 254. The data storage register and / or memory 254 can store up_dn signals, max_step, step_size values, or any other data or machine readable code, such as software. The processor can also be part of the digital control unit 232, which is configured to execute the machine readable code stored in the memory 254 in a non-transitory state to perform the functions described herein. The functions are performed either or in part by the control logic 250.

[0052] A user interface 258 is provided in the digital control unit 232 to provide a user with access to set or change one or more values ​​stored in the registers / memory 254, or to update software / machine readable code, or to perform any other function to achieve operation or adaptation of the system. It is contemplated that the functions described herein may be performed by hardware using control logic and registers, software executed in the processor 266, or a combination of both. As discussed herein, one or more comparators 262 are also provided to compare various values. In some embodiments, the comparators 262 may be implemented by, for example, Figure 2A The comparator 224 shown instead, or may be a software function.

[0053] One challenge presented by systems that adjust gain involves the rate at which gain changes over time. While it is possible to increase or decrease gain by large amounts during a clock cycle, doing so is generally undesirable because large, sudden changes in gain corrupt the signal, disrupting downstream signal processing and decoding, which in turn introduces errors, causing the bit error rate to spike.

[0054] At the same time, changing the gain too slowly also presents several disadvantages. One such disadvantage exists during training. During training, the system adapts to unknown channels, and therefore the gain may need to be increased significantly. If the rate of change of gain is slow, for example due to having a large number of steps in the digital control vector between the minimum and maximum values, the VGA may take too much time to present an output signal with an amplitude that matches the target value. If this happens, the system will not complete training during the set training time period, and downstream system training will also be delayed or fail. The following discussion focuses on the operation of comparator 224 and digital control unit 232 to implement various routines for control vector generation and adaptation that overcome the shortcomings of the prior art.

[0055] In other words, the digital controller 232 drives multiple output signals to an array of small digital-to-analog (DAC) circuits 236. In other embodiments, a single output may be provided to a single DAC. In this example embodiment, the DACs 236 are 6-bit DAC circuits that work together to define the gain of the (VGA) 208. The digital control unit 232 determines how multiple DACs 236 work together in the system based on the value of the wider 11-bit loop control vector. In this embodiment, the automatic gain control (AGC) loop has 2018 (0-2017) unique values ​​for the loop control vector. In other embodiments, the control vector may have a different number of unique values. This number is a function of the number of DACs 236 and the number of unique values ​​for each DAC. The control loop is intentionally updated at a relatively slow speed to reduce the chance of interfering with the movement of the data path. As a result, in prior art systems, ramping the control vector to its convergence point consumes a lot of time.

[0056] exist Figure 6 In the embodiment of , there are three input signals ("up_max", "dn_max", and "up_dn") that instruct the digital control loop how to adjust the control vector. These signals are generated by a comparator that compares the actual signal strength (such as the peak value) to a predefined target. A peak detector (most likely) is used to measure the signal strength of the output waveform. The purpose of the closed loop system is to ensure that the output signal strength is predictable no matter how strong or weak the input signal is (within limits of course).

[0057] In discussion Figure 6 Previously, the discussion Figure 3 and Figure 4 . Figure 3 A prior art method for control vector regulation is shown. Figure 3 The method begins at step 304 by collecting samples, but then discards some samples that are transitional or outside the average range at step 308. At step 312, the system calculates the average of valid samples. Next, at decision step 316, the method of operation evaluates whether the time constant or time period has expired. If not, the operation returns to collect more samples and continue to calculate the average. Once the time period expires, the sample is compared to the target value at step 320, and the control signal adjusts the control vector, which in turn adjusts the gain of the VGA. It is also conceivable that the host controller can disable the automatic loop and instead manually set the gain. In this embodiment, the digital control unit does not automatically change the gain. It is assumed that any automatic adjustment originates from the host controller. Although this method of operation is effective, it lacks the benefits of real-time tracking and gain adjustment.

[0058] Figure 4 is a more detailed version of the prior art process for adjusting the control vector. Starting from step 404, the digital controller determines whether the up_dn signal is a logical 0 or 1, that is, whether the output signal is less than or greater than the target value. If the up_dn signal is a 0 value, the control vector should be reduced and the operation proceeds to decision step 408. In decision step 408, the digital controller determines whether the control vector is at a minimum value. If the control vector is at a minimum value, the operation proceeds to the end and no change is made to the control vector. Alternatively, if the control vector is not at a minimum value in step 408, the control vector is reduced by one unit or increment. The terms control vector and control code can be used interchangeably.

[0059] Alternatively, if at step 404, the up_dn signal is a logic 1 value indicating that the control vector should be increased, the operation proceeds to decision step 420. At decision step 420, the control logic determines whether the control vector is at a maximum control vector value. If so, the operation ends without making any changes to the control vector because the control vector is already at its maximum value. Alternatively, if at step 420 the control vector is not at its maximum value, the operation proceeds to step 424. At step 424, the digital controller increases the control vector by one step size. In this example embodiment, the analog system is designed so that the maximum control vector code corresponds to the lowest gain, and the minimum control vector code corresponds to the highest gain. In other embodiments, other relationships may be established without departing from the scope of the claims. When the up_dn signal is at a logic level 0, it indicates that the signal strength is less than the target, so the system should increase the gain (by reducing the control vector code).

[0060] In this example method of operation, the control vector is automatically adjusted based on the up_dn feedback signal from the analog portion of the loop. The control vector changes only one unit or increment at a time using a single step size, which reduces the chance of disturbing the data path. If the data path has been disturbed by a sudden change in the input signal, a slow control loop may take a long time to adjust to the new equilibrium, causing the training phase to time out before achieving ideal gain convergence. Using a single step size prolongs this disturbance.

[0061] Figure 5 Shows Figure 4 504 . The vertical axis represents the control vector value and the horizontal axis represents time. As can be seen in the graph 504 , the control signal increases over time, starting from a first time 508 until a second time 512 to reach the desired gain level. Using a single step as shown, 1009 loop iterations are required in this example to regain balance. The settling time is long because the control vector needs to go through many steps to reach the new equilibrium point. This number of steps and this amount of time are too long to be completed during the training period.

[0062] Although Figure 4 The prior art approach discussed in is suitable for use in prior art environments, but it suffers from several drawbacks in VGA control systems that have high resolution gain control and / or require that the output signal be acquired to a target value more slowly than slowly.

[0063] Figure 6An operational flow chart of a VGA control method is shown. This is only one possible method of operation, and deviations from this exact method are not expected to depart from the innovation disclosed herein. Typically, this method of operation utilizes a control loop with three comparators. A comparator compares an output signal with a target value to determine whether the output signal is greater than or less than the target value, and the resulting comparison results in an up_dn signal. A second comparator compares the output signal with the target value to determine whether the output signal is greater than the target value by a first threshold. The second comparator outputs a Dn_max signal in response to the comparison. The Dn_max signal is a logic value output of 0 or 1. A logic value of 0 indicates that the output signal is not greater than the target by a first threshold. A third comparator compares the output signal with the target value to determine whether the output signal is less than the target value by a second threshold. The third comparator outputs an Up_max signal in response to the comparison. The Up_max signal is a logic value output of 0 or 1. A logic value of 0 indicates that the output signal is not less than the target by a second threshold. The first threshold and the second threshold may be the same or different values, but are assumed to be greater than 1. The second comparator outputs a Dn_max signal in response to the comparison. Therefore, during operation, three control signals are generated, namely, the up_dn signal, the Dn_max signal, and the Up_max signal.

[0064] Using these values, in some cases, it is possible to adjust the control vector by more than one step at a time. In particular, if the comparison between the output signal amplitude and the target value reveals that the output signal amplitude differs from the target value by an amount greater than a first threshold or a second threshold, this is an indication that the output signal is away from the target value to an amount greater than the threshold. When this occurs, it indicates that the control vector should move more than one increment, and therefore, the control value is increased or decreased by a number of increments defined as the max_step value. The max_step value is a user-settable value stored in a memory or register. The max_step value is a value that defines how many units or increments the control value will increase or decrease when the output signal is greater than or less than the target value from a threshold amount. Figure 6 A more detailed description of the method of operation is provided.

[0065] The method of operation begins at step 604, where a comparison is made between the output signal (peak value of the VGA output) and the target value. Decision step 608 occurs, so that the comparator output signal (up_dn signal) from the comparator is detected and analyzed by the digital control unit. If the up_dn signal is a logic 0 value (meaning that the peak value is less than the target value), the operation proceeds to decision step 612. This can generally be defined as reducing the path of the control vector. In decision step 612, the comparator determines whether the output signal is greater than the target value by a threshold. If the output signal is not greater than the target value by a threshold in decision step 612, the Dn_max signal is set to a logic level 0, and the operation proceeds to decision step 616.

[0066] At decision step 616, it is determined whether the control vector is already at its minimum value and therefore cannot be further reduced. If the control vector is at its minimum value, the process proceeds to step 622 and ends, but monitoring and comparison of the output signal to the target value continues over time to provide real-time and dynamic gain control.

[0067] Alternatively, if at step 616 the control vector is greater than the minimum value, then operation proceeds to step 620. At step 620, the control system adjusts (decreases) the control vector by one and adjusts the VGA gain down by one unit or increment.

[0068] Alternatively, if at step 612 the comparator determines that the output signal is greater than the target value by a threshold, the Dn_max signal is set to a logic level 1 and operation proceeds to decision step 624. At decision step 624, if the control vector is within a max_step number of increments of the minimum control vector value, operation proceeds to step 632 and the control vector is reduced to the minimum value and thereafter operation ends at step 622, but monitoring continues.

[0069] Alternatively, if at decision step 624, the digital control unit determines that the control vector value is greater than the step_max value from the minimum value, the control vector is reduced by the step_max value. This occurs at step 628. Therefore, since the step_max value is much greater than 1, such as 10 or 20 steps as an example, or any value greater than 1, the control vector is reduced by more than one unit or increment. This allows the output signal to reach the target value faster than the prior art system, which only provides an increment of one unit during the cycle of the control loop. The step maximum value is selected so that moving the gain by the maximum step amount will not disrupt the system operation. In one embodiment, this is 1% to 7% of the total number of steps from the minimum to the maximum control vector value. In another embodiment, it is less than 15% of the total. Thereafter, the process proceeds to end step 622, and another loop cycle of monitoring and processing occurs.

[0070] Alternatively, if at step 608, the comparison of the output signal with the target value determines that the output signal amplitude (such as a peak value or peak-to-peak value) is greater than the target value, then the operation proceeds to decision step 636. This operation path adds a control vector. At decision step 636, a determination is made regarding the difference between the output signal and the target signal relative to the Up_max signal. As described above, the Up_max signal is a determination of whether the difference between the output signal and the target signal is so large that the change in the control vector should be greater than one unit or step size. If the difference (difference) between the output signal and the target signal is less than the Up_max value (threshold), then the logical output of the comparator performing the comparison is a logical 0, and the operation proceeds to decision step 640.

[0071] In decision step 640, it is determined whether the control vector is at its maximum value or whether the control vector is less than the maximum value. If the control vector is at its maximum value, the operation proceeds to end step 622 and no change is made to the control vector. This is because no additional increase can be made to a control vector that is already at its maximum value.

[0072] Alternatively, if the control vector is less than the maximum control vector value at step 640, the operation proceeds to step 644 and the control vector is increased by one unit or step size. After the increase, the operation proceeds to step 622 and the loop process repeats. Therefore, because the control output signal value (amplitude peak to peak) is not greater than the target value by more than the Up_max value, the gain is close to correct, so the control vector should only be increased by one unit or step size.

[0073] Returning to step 636, if the comparison between the difference (differential) between the output signal and the target signal is greater than the Up_max value (threshold), then the logic output of the comparator performing the comparison is a logic 1 and the operation proceeds to decision step 648. At decision step 648, a determination is made regarding the value of the step_max value and the control current vector value. If at decision step 648, the control vector is greater than the step_max value from the maximum value, then the operation proceeds to step 652, at which point the control vector is increased by the max_step value because it has been determined that the output signal amplitude is away from the target value and therefore a substantial increase in the control vector is required to increase the convergence rate. After step 652, the operation proceeds to step 622 and the loop repeats.

[0074] Alternatively, if the operation determines at step 648 that the control vector is within the step_max value of the maximum control vector value, then the operation proceeds to step 656 and the control vector is incremented to the maximum value and this completes the loop iteration at step 622 .

[0075] The control vector is automatically adjusted based on "up_max", "dn_max" and "up_dn" feedback from the analog portion of the control loop. Two additional signals provide a way to tell the digital block when the control vector is "off" equilibrium. When "up_max" is asserted, the loop moves a number of steps defined by the control register "step_max". When "dn_max" is asserted, the control vector decreases by the "step_max" number of steps. Otherwise, the loop moves a single step up or down based on the "up_dn" input signal. This requires the analog block to determine when the control vector has deviated significantly from the target. In one embodiment, this enhanced control option is enabled by setting the "step_mode" register to "01".

[0076] Figure 7 Shows Figure 6 708. The control vector value is represented on the vertical axis 730, and time is represented on the horizontal axis 734. At the loop start time 708, the loop begins to detect and analyze the output signal relative to the target value. During the time period corresponding to the signal curve graph 712, the system determines that the output signal differs from the target value by a large amount, greater than the Up_max or Dn_max value, so it quickly ramps up the control vector by adding step_max to the control vector for each loop iteration. At time 714, the detection system determines that the difference between the output signal and the target value is not so different that it warrants an increase in max_step in the control vector, so during the time period of the signal curve graph portion 716, the loop performs a single unit or incremental increase in the control vector, which results in a small step size in the gain. At time 720, the output signal has reached the target value, and the loop has reached equilibrium.

[0077] use Figure 6 In this example, only 65 loop iterations are required to regain equilibrium. This is in contrast to using the Figure 4 and Figure 5 This is a 93.6% improvement in the single step size.

[0078] Fig. 8A It is shown Figure 8B and Figure 8C The index of the relationship between . Figure 8B and Figure 8C An operational flow chart of an alternative method of control vector adjustment is shown. This is only one possible method of operation, and it is contemplated that other methods of operation may be implemented without departing from the scope of the present invention. In this embodiment, the control vector is automatically adjusted based on an "up_dn" feedback signal from the analog portion of the loop. The digital block monitors the history of "up_dn" over time to determine whether the control vector has significantly deviated from the target based on the historical values ​​of the up_dn signal. In this embodiment, a shift register or other memory type stores the value of "up_dn" each time the control loop is updated. The oldest value is discarded from the end of the stack and the newest value is inserted at the beginning. This may be referred to as a first-in, first-out process. As in other embodiments, the up_dn value (signal) is a logical value of 0 or 1.

[0079] like Figure 8BAs shown, the operation method starts so that a comparison occurs between the output signal (peak value of the VGA output) and the target value. The comparison generates an up_dn signal. The process can be repeated several times so that the up_dn value is stored in a memory / register. If the value of "up_dn" is not the same N times in a row (where N is a value set by the user in a digital range), the control loop has recently crossed its convergence point and the step size is reduced by half. This occurs because the change in the up_dn value over time indicates that the output signal has recently been at or crossed the target value. This reduction of half of the control vector occurs each time the control loop is updated until the step size becomes "step_min" (default value 1). The time delay from the digital control unit output back to the "up_dn" input is relatively small, so 8 loop iterations are sufficient to detect multiple crossings. In other embodiments, a different number of iterations can be used. When the output signal converges with the target signal, the step size should always be the minimum size. When the up_dn signal does not change over a predetermined number (N) of samples, it indicates that the step size can be increased or decreased. For each loop iteration, reducing the step size by half causes the step size, and therefore the control vector, to change more slowly over time. For example, if the step size is 128, then reducing it by half causes the step size to be 64, and during the next iteration it is 32, and during the next iteration, the step size drops to 16. Thus, in only three cycles, the step size has dropped from 128 to 16. This results in a faster rate of change of the control vector, but not so fast that it interrupts operation. These numbers are exemplary only, and the claims are not limited to these numerical values. The step size is the amount by which the control vector changes, which in turn controls the gain, which in turn controls the output signal amplitude.

[0080] The same principle applies to increasing the step size, when N number of up_dn signals are the same (i.e. logic 1 value), the step size is doubled. If the N most recent up_dn signal values ​​are the same, the step size is doubled. If the up_dn signal does not change, the step size increases each time the control loop is updated until the maximum step size is reached or until the value of "up_dn" changes. The maximum step size prevents the step size from becoming too large, which may cause the gain to vary too much in one step size. If the control vector reaches the upper limit while "up_dn" is "1", the step size is immediately reduced to the minimum step size "step_min". If the control vector reaches the lower limit while "up_dn" is "0", the step size is immediately reduced to "step_min". A dynamic step size can be selected by setting the "step_mode" register to "10" (default value).

[0081] Return to Figure 8B, which generates a new up_dn value at the digital control unit, particularly in a data storage register. The method of operation begins at step 604, where a comparison is made between the output signal (peak value of the VGA output) and the target value. The comparison determines the up_dn value stored in the memory / register. At step 808, the digital control unit shifts the latest up_dn value into the register, which causes the other values ​​to shift to the left so that the new value is inserted to the right. Next, at decision step 812, the digital control unit determines whether the last N consecutive values ​​of up_dn stored in the register are the same, or whether the N values ​​are different. If the last N values ​​of the up_dn value are not the same, the operation proceeds to decision step 816. At decision step 816, a determination is made regarding the step size and whether the step size is at a minimum value or greater than the minimum value. If the step size is greater than the minimum step size value at decision step 816, the operation proceeds to step 820. At step 820, the step size is reduced by half. In other embodiments, the step size may be reduced (or increased) at a rate or amount other than half. After step 820, the operation proceeds to decision step 832, which will be described below in Figure 8C discussed in more detail above.

[0082] Now returning to step 816, if the step size is at the minimum value, it follows that it cannot be reduced any further, so the operation proceeds to decision step 832 discussed below. Returning to step 812, if the up_dn history is such that the history (register) shows N identical consecutive up_dn values, the operation proceeds to decision step 824. At decision step 824, a determination is made by comparing the step size to the step size maximum. If the step size is at the maximum value, the operation proceeds to step 832, and since the step size is already at the maximum value, no change is made to the step size. Alternatively, if the step size is less than the maximum value, the operation proceeds to step 828, and the step size is doubled, either as described above, or increased by a value, ratio, or factor. After step 828, the operation proceeds to step 832.

[0083] In decision step 832 ( Figure 8C ), the digital control unit determines whether the comparison between the output signal and the target value results in the up_dn signal being a logic level 0 or a logic level 1. If up_dn is 0, meaning that the output signal is less than the target value, then the operation proceeds to step decision step 836 (for the final reduction of the control vector). In decision step 836, it is determined whether the control vector is within the step_size value of the minimum control vector value, or whether the control vector is greater than the step_size minimum value.

[0084] If the control vector is within the step_size value of the minimum control vector value, the operation proceeds to step 840. At step 840, the digital controller unit reduces the control vector to the minimum value, and the step_size value is also reduced to its minimum value. Thereafter, the value adjustment ends at step 858, and the loop iterates by returning to step 804.

[0085] Alternatively, if the control vector value is greater than the step_size value above the minimum value at step 836, the operation proceeds to step 842. At step 842, the digital control unit decreases the control vector by the step_size value (code). After step 842, the operation ends at step 858, and a new loop iteration occurs by returning to step 804.

[0086] Returning to step 832, if the up_dn value is 1, meaning that the output signal is greater than the target value, the operation proceeds to decision step 846. At decision step 846, it is determined whether the control vector is less than step_size below the maximum value, or whether the control vector is within step_size of the maximum value. If at decision step 846, the control vector is within step_size of the maximum value, the operation proceeds to step 850, and the digital control unit increases the control vector to the maximum value and also decreases the step_size value to the minimum value. Thereafter, the operation ends at step 858, and the loop iterates by returning to step 804.

[0087] Alternatively, if the control vector is less than the step_size value at the maximum value, the operation proceeds to step 854, and the digital control unit increases the control vector by the step_size number of units, also referred to as a value, increment, or code. The step size is calculated above in steps 812-828. Thereafter, the operation ends at step 858, and the loop repeats by returning to step 804.

[0088] In other words, in this example embodiment, the control vector is automatically adjusted based on the up_dn feedback signal from the analog portion of the loop. The digital control unit monitors the history of the up_dn signal over time to determine whether the control vector has deviated significantly from the target, which is determined in this embodiment by the up_dn signal not changing over N consecutive loop iterations determined by N consecutive up_dn values ​​in the shift register. Each time the control loop is updated, the shift register stores the value of the up_dn signal. During each iteration, the oldest stored value of the up_dn signal is discarded from the end of the stack and the newest value is inserted at the beginning. N can be any value, but high values ​​cause the control value to change more slowly.

[0089] If the value of the up_dn signal is not the same N times in a row, the control loop has recently crossed its convergence point and the step size is reduced by half. This happens every time the control loop is updated until the step size becomes step_min (default value 1). The time delay from the digital output back to the up_dn signal input is relatively small, so eight loop iterations are sufficient to detect multiple crossings of the convergence point. In other embodiments, a different number of iterations can be defined (used). When converging, the step size should always be the minimum size, but before that, when the desired gain level is found, the control vector and even the gain can be varied in a range above and below the target value.

[0090] If the N most recent values ​​of "up_dn" are the same, then the step size is increased by 1. When the control loop is updated, the step size is doubled (or increased by some other increment or factor in other embodiments) until a maximum step size is reached or until the value of the up_dn signal changes. In this embodiment, the step size is equal to 2. S , where S is the step size register that is incremented or decremented. When S increases by 1, the step size is doubled. When S decreases by 1, the step size is halved. In other embodiments, other mathematical algorithms can be implemented. If the control vector reaches the upper limit and up_dn is still a logic level 1, the step size is immediately reduced to the minimum step size step_min value. If the control vector reaches the lower limit and "up_dn" is a logic level 0, the step size is immediately reduced to the step_min value. In one implementation, a dynamic step size can be selected by setting the step_mode register to "10" (default value).

[0091] The N loop iteration delay before increasing the step size gives a valuable hysteresis, thereby avoiding instabilities. In the embodiment described herein, the step size is kept small until 8 loop iterations have passed with the up_dn signal equal to 1. During this time, the control vector is increased in small steps. Once the up_dn signal goes to logic level 0, the step size is immediately reduced, for example by half of some other value. This asymmetric behavior reduces the chance that the control vector will alternately exceed the minimum step size (default value 1) when converging. During simulations, it was revealed that using an N loop iteration delay before increasing the step size 8 loop iterations with the up_dn signal equal to 1 would result in a significant increase in the control vector. Fig. 8A , Figure 8B Using the dynamic step size mode described in , only 35 loop iterations are needed to regain equilibrium in this example. This is a 96.5% improvement over using a single step size.

[0092] Fig. 9 Shown based on Figure 8B and Figure 8C1. Example diagram of control vector adjustment of the method of FIG. The vertical axis represents the control vector and the horizontal axis represents time. The control vector signal adjustment process starts at time 904. During the initial stage, the signal increases slowly over N iterations. At signal point 908, N cycles have occurred and the step_size doubles. Fig. 9 , the step size is shown above the graph and is shown from left to right with values ​​of 1, 2, 1, 2, 1, 2, 4, 8, 16, 32, 64, 32, 16, 8, 4, 2, 1. These numbers double from 1 to 2 to 4 to 8, etc. until a maximum step size of 64 steps is reached. This progression begins near marker 908. Once the maximum step size is reached (marker 912), the control vector will increase at this constant rate based on the maximum step size until a convergence point is crossed. The portion of the graph 912 identifies the time period when the step size is at its maximum value (64). In other embodiments, other maximum step sizes may be utilized.

[0093] Then, at signal point 916, the output signal amplitude has exceeded the target value, causing the control vector to begin to decrease. Then, during signal point 920, a state close to equilibrium has occurred and is reached at time 924.

[0094] While the dynamic step size described above works well, it can lead to unwanted loop convergence behavior. For example, if a larger step size is chosen (e.g., 32X), it can cause the loop to stick to a larger step size mode, which will negatively impact dither and, therefore, BER. This behavior limits how fast the loop can operate. A rough equation for the worst-case convergence time with dynamic step size is shown below.

[0095] Convergence time = clock period × number of digital loop states × average dynamic step size (2)

[0096] This equation is a first-order approximation.

[0097] Dynamic Average

[0098] Another way to reduce the loop convergence time is to dynamically change the averaging applied to the UP / DN signals. The averaging used during operation is primarily to avoid mode dependency and to have good temperature cycling behavior. Based on laboratory measurements, the loop average (counter value) can be set to 128 and still operate satisfactorily at startup when mode dependency is not too problematic. This indicates that one can comfortably achieve an approximate increase in convergence speed of 32x (4096 / 128). Another aspect is that the system is not only able to achieve faster convergence times, but is also able to maintain good loop behavior. For representative convergence behavior of a loop utilizing "dynamic averaging", refer to Figure 4With appropriate dynamic averaging, the convergence time will be approximately:

[0099] Convergence time = clock period × number of digital loop states × average / dynamic step size × dynamic average speedup (3)

[0100] Fig.10 A block diagram of an exemplary system with an adjustable counter size is shown. This is just one possible embodiment, so other configurations that implement similar control functions are possible. In this embodiment, input 1004 transmits an input signal to a device under control, such as amplifier 1008. Although shown and described as an amplifier for the purpose of this discussion and to aid understanding, it is disclosed that any device or element under the control of a feedback loop may be used and will benefit from the loop control system and method as described herein.

[0101] In this embodiment, amplifier 1008 is configured to maintain its output signal amplitude at a reference value so that loop feedback provides a control signal to increase or decrease the gain of the amplifier. As discussed herein, at startup or at reset, the output value of the amplifier may move away from the reference value that the amplified signal should be at. As discussed below, it is desirable to converge the amplified signal to the reference value quickly.

[0102] The output of the amplifier, i.e., the amplified signal, is provided as an output on the output path 1012 to the error detector 1016. The error detector 1016 also receives a reference signal from the input 1020. The error detector 1016 compares the amplified signal with a reference value. Based on the comparison, the error detector 1016 outputs an up signal or a down signal to the digital average counter 1024 and the up / down detector (tracker). The error detector may include a comparator or any other device capable of comparing a signal with a reference value. The reference value may be provided to the error detector 1016 at the time of manufacture, at startup, or may be dynamically adjusted during operation or based on input via a user interface (not shown). A memory or register may store the reference value.

[0103] The digital average 1024 can be configured as a counter with a counter size that can be adjusted during operation. The counter size ranges from zero to a maximum counter size. The counter size is the value that the counter must reach before it generates an output (usually a logic 1 value or a logic 0 value) and then resets. In one embodiment, when reset, the counter is reset to a midpoint value between zero and the maximum counter size. Based on the control input from the up / down detector (tracker) 1028, the counter size can be adjusted. For example, the counter size can range from zero to 4096, or from zero to 265, or any range. For large counter sizes, more inputs are required to advance the counter value to the maximum counter value or to reduce the counter value to the zero counter value. For smaller counter sizes, fewer inputs are required to advance the counter value to the maximum counter value or to reduce the counter value to zero. The digital average counter 1024 increments upward with each upward signal output from the error detector 1016, and decrements downward with each downward signal output from the error detector 1016. When the maximum counter value is reached, the digital average counter 1024 outputs a logic 1 value, and when the zero counter value is reached, the digital average counter outputs a logic 0 value. After reaching the maximum counter value or zero, the counter value is reset to a midpoint value between zero and the maximum counter value, and the process repeats.

[0104] The up / down detector 1028 monitors and tracks the up / down output from the error detector 1020. The up / down detector 1028 may include memory, registers, control logic, software, or any other element or combination thereof configured to perform as described herein. Upon receiving a predetermined pattern of up / down signals, the up / down detector adjusts the counter size of the digital average counter 1024. In various embodiments, the predetermined pattern may be a continuous number of up signals or a continuous number of down signals, such as, but not limited to, eight consecutive identical signals. In one embodiment, the predetermined pattern may be a certain number of up signals or down signals in a larger signal group, such as, but not limited to, six up signals in the last eight signals from the error detector.

[0105] When the predetermined pattern is met, it indicates that the amplified signal is away from the reference value. The amplified signal can be much greater than the reference value or much lower than the reference value. Therefore, it is possible to reduce the time when the amplified signal value is at or near the reference value by reducing the counter size. Reducing the counter size reduces the number of upward outputs from the error detector 1020 required for the digital average counter 1024 to reach the maximum count value, as described below, and the maximum count value is required to increase the gain of the amplifier 1008. Similarly, reducing the counter size reduces the number of downward outputs from the error detector 1020 required for the digital average counter 1024 to reach the zero count value, which is required to reduce the gain of the amplifier 1008, also discussed below. In one embodiment, the counter size starts at 4096 and, over time, in response to the error detector outputting a predetermined pattern of values ​​(signals), and is reduced in size to 2048, to 1024, to 512, to 256. At any time, if the error detector output does not match the predetermined pattern, the counter can be reset to its maximum size, such as 4096.

[0106] The control signal from the up / down detector 1028 to the digital average counter 1024 controls the counter value of the digital average counter. If the predetermined pattern occurs several times in succession, the counter size may be reduced several times in succession, such as from 4096 to 2048, to 1024, etc., all the way to 256. These numbers are provided for the purpose of understanding only, and therefore, other embodiments may have different counter size values. However, in one embodiment, if the up / down detector 1028 receives an input pattern that does not meet the predetermined criteria, this is an indication that the amplified signal is at or near the reference value, and therefore, the up / down detector resets the counter size of the digital average counter 1024 to its maximum value, such as 4096 in this example embodiment.

[0107] The output of the digital average counter 1024 is provided to a loop state machine, which increases or decreases a digital control value representing the current gain state. The loop state machine may include one or more of a memory, control logic, software, a processor, a comparator, a register, or any combination of these elements, which is configured to monitor and track a series of up / down signals from the error detector 1016 and compare the series of up / down signals to a predetermined pattern. After increasing or decreasing the digital control value representing the current gain state, the digital value is provided to a digital-to-analog converter 1036, which converts the digital control value to an analog signal, which is then provided to the amplifier as a gain control signal to adjust the gain. The gain can be adjusted up or down.

[0108] Fig.11A graph of the dynamic step size described in the parent application is shown. The horizontal axis 1108 represents time, while the vertical axis 1108 represents the loop state. The loop state represents the gain control signal. During the first signal portion 1118, the step size is fixed to a normal step size. After this small step size occurs for a period of time, the step size is changed to a large step size 1126 for the second signal portion 1122. Note that the time taken to adjust the gain, represented by the time period 1130, is the same for both the first signal portion 1118 and the second signal portion 1122. Therefore, even if the step size increases, the time between step size changes is fixed.

[0109] This process repeats until point 1134. However, at point 1134, the gain value has exceeded the desired steady state level 1114. Then, a signal portion 1138 and additional time associated therewith are required to approach the steady state. Thereafter, the loop control maintains the gain value at the steady state during signal portion 1140. Fig.10 The illustrated system and resulting method of operation overcomes the constant time between step size changes and overshoot.

[0110] Fig.12 Shown based on Fig.10 12 is a signal graph of the system shown. This graph is exemplary only and is provided for the purpose of discussion and aiding understanding. The horizontal axis 1208 represents time, while the vertical axis 1204 represents the loop state. Fig.11 As can be seen in comparison, the time 1216 between changes in gain value (step size) during signal graph portion 1212 is less than the time between step changes in signal graph portion 1230. This reduces the time it takes for the actual gain level to reach the desired gain level at or near the steady state value 1114 and reduces or eliminates overshoot associated with the dynamic step size of the prior art methods and the parent application.

[0111] Fig.10 The system shown in has been implemented and tested. Fig.13 , Fig.14 and Fig.15 The improvement demonstrated by actual signal graphs is shown. Fig.13 A signal graph of a prior art loop control is shown. The horizontal axis 1304 represents time, while the vertical axis 1308 represents the loop state in volts. As shown, the signal graph 1312 slowly ramps up to a steady state level 1316. In this prior art system, approximately 90 microseconds are required. During this period, the gain level of the amplifier or any other device under control is not at an appropriate level, thereby inhibiting the desired system operation and possibly preventing subsequent system operations from starting, such as a training process.

[0112] Fig.14 14 shows a signal graph of loop control based on the innovation disclosed herein. The horizontal axis 1404 represents time, while the vertical axis 1408 represents the loop state in volts. As shown, the signal graph 1412 quickly ramps up to a steady state level 1416. In this system, convergence occurs faster than Fig.13 This speeds up system operation and allows subsequent system operations, such as training procedures, to begin.

[0113] It is also contemplated that the methods and apparatus of the parent application and the variable counter size methods disclosed herein may be combined to allow for greater improvements. The loops may be operated individually or configured as a single loop to allow for dynamic step sizes as well as having variable counter sizes. Thus, the counter step size can be reduced to speed up convergence to a stable state, but the step size can be increased (the step size increases or decreases the gain), which also speeds up convergence to a stable state.

[0114] Fig.15 An exemplary signal graph of a loop control system combining dynamic step size and variable counter size is shown. The horizontal axis 1504 represents time, while the vertical axis 1508 represents the loop state in volts. As shown, the signal graph 1512 quickly ramps up to a steady state level 1516. In this system, the convergence ratio Fig.13 The prior art graph is approximately 100 times faster than the previous one. This speeds up system operation and allows subsequent system operations to begin, such as training procedures.

[0115] Fig.16A and Fig. 16BAn exemplary method of operation of an exemplary embodiment of a loop control system with a variable counter size is shown. This is only one possible method of operation, and therefore, other methods of implementing a variable counter size are contemplated and possible. In step 1604, the method of operation sets an initial digital average counter size for the digital average counter. The digital average counter size is the size of a counter or other element that determines the number of up inputs or down inputs that must be received in excess of the number of opposite up or down inputs before the digital average counter will output a 1 or 0 output. For example, the counter size may be 4096, and if the starting value of the counter is the midpoint of 2048, then 2048 up signals will be required, in excess of the amount of any down signals received, to output a logic 1 output from the digital average counter. Similarly, if the counter size is 2048 and the starting value of the counter is the midpoint of 1024, then 1024 down signals will be required, in excess of the amount of any up signals received, to output a logic zero output from the digital average counter. As described below, during operation, the counter size may be varied to adjust the rate at which the device under control converges to its desired level or value.

[0116] At step 1608, a threshold required to change the size of the digital averager counter is set for the continuous up / down signal pattern tracker. For example, the up / down signal pattern can be set to various patterns of up / down signals. And when the defined pattern of up / down signals is received, the counter size can be changed.

[0117] In step 1612, the amplifier (device under control) receives an input signal that will be amplified to, at, or near a reference value. Although discussed with respect to amplification levels, the device under control can be any device controlled by a loop, which will benefit from improved loop convergence time. In step 1616, the amplifier amplifies the received signal to produce an amplified signal. Then, in step 1620, the amplified signal is compared to a reference value using an error detector or any type of comparator. The reference value is the value that the received signal should have after amplification. The reference value can be stored in a memory or register, and it can be set at the time of manufacture, set by the user at a later time, or dynamically adjusted during operation. A user interface (not shown) can provide means for setting or changing the reference value.

[0118] At step 1624, based on the comparison at step 1620, the error detector generates and outputs an up signal or a down signal. The up signal indicates that the amplified signal is less than the reference value, and the down signal indicates that the amplified signal is greater than the reference value. At step 1628, the up signal or the down signal output from the error detector is provided to the digital average counter. At step 1632, when the up signal is received, the digital average counter increments its count, while receiving the down signal causes the digital average counter to decrement its count by 1. Then, at step 1636, a comparison is made between the current count of the digital average counter value and the digital average counter size.

[0119] Go to Fig. 16B , at the decision step, if the digital averager counter value is equal to the counter size or equal to zero, the operation proceeds to step 1644. At step 1644, because the counter has reached its maximum or minimum size, it will generate an output, which results in the output of incrementing or decrementing the loop state. The loop state can be a digital value representing the gain value of the amplifier. A logic 1 output from the counter causes the loop state to increment, while a logic 0 value from the counter causes the loop state to decrement. Increasing the loop state increases the gain of the amplifier, while decrementing the loop state results in a decrease in the amplifier gain. In other embodiments, other annotations can be established.

[0120] From step 1644, operation proceeds to step 1648 and the gain is adjusted based on the change in loop state. Fig.10 , the gain is adjusted because the loop state is provided as a digital value to the DAC, which then provides an analog control signal to the amplifier. At step 1648, the digital average counter is reset to its midpoint, which in this embodiment is between zero and the maximum counter size. This step may alternatively occur later in the method of operation. After step 1648, the operation proceeds to decision step 1652.

[0121] Alternatively, if it is determined at decision step 1640 that the digital average counter size is not equal to the counter maximum or minimum value, the operation proceeds to decision step 1652. At decision step 1652, it is determined whether the current up / down signal from the error counter is the same as the last up / down signal. In this embodiment, the pattern is a certain number of consecutive up signals or down signals. In other embodiments, the pattern of previous up / down signals that must be met may not be continuous, such as a certain number of up / down signals in a group of recently received signals. If the pattern of the up / down detector is not met, the operation proceeds to step 1672. At step 1672, it is determined whether the current digital average counter size is less than the maximum counter size. If so, the operation proceeds to step 1676, and the system sets the digital average counter size to the maximum size. Thereafter, the operation proceeds to step 1680, and since the most recent up / down signal is different from the last up / down signal, the up / down detector is reset. After step 1680, the operation proceeds to step 1668 and the operation returns to step 1612. If at step 1672, the digital average counter size is not less than the maximum value, then the operation proceeds to step 1680. At step 1680, the up / down detector is reset and the operation proceeds to step 1668.

[0122] Alternatively, if at step 1652, the current up / down signal is the same as the previous up / down signal, the operation proceeds to step 1656, and the pattern within the up / down detector is updated to reflect another up signal or down signal that is the same as the previous signal from the error detector. Then at decision step 1660, it is determined whether the number (or pattern) of consecutive up signals or consecutive down signals meets a threshold (or pattern). For example, the threshold may be eight consecutive up signals or eight consecutive down signals. In other embodiments, the predetermined number or pattern may vary.

[0123] If at step 1660, the number of consecutive up signals or consecutive down signals does not meet the threshold, the operation proceeds to step 1668 and the system operation returns to step 1612. Alternatively, if at step 1660, the number of consecutive up signals or consecutive down signals meets the threshold, the operation proceeds to step 1664 and the system reduces the size of the digital averaging counter if the counter is not already at its minimum value. In this method of operation, the counter size can be reduced by half, or some other multiple or amount. In one embodiment, the counter size starts at 4096, but over time will be reduced to 256 in a set manner. After step 1668, the operation returns to step 1668 and then returns to step 1612.

[0124] By studying the following drawings and detailed description, other systems, methods, features and advantages of the present invention will be or will become clear to those skilled in the art. All such additional systems, methods, features and advantages are intended to be included within this description, within the scope of the present invention, and protected by the appended claims.

[0125] Although various embodiments of the present invention have been described, it will be apparent to those skilled in the art that many more embodiments and implementations within the scope of the present invention are possible. In addition, the various features, elements and embodiments described herein may be claimed or combined in any combination or arrangement.

Claims

1. A system for controlling the gain of a variable amplifier, comprising: an error detector configured to compare the amplifier output with a reference value and output an error signal in response thereto; a counter having a counter size, configured to maintain a counter value reflecting the error detector output over time, and in response to the counter value reaching the counter size, output a gain control signal; as well as an error detector signal monitor configured to track an error detector signal over time and, in response to the error detector signal satisfying a predetermined pattern, provide a counter size control signal to the counter to reduce the counter size, which reduces the time required for the amplifier output to reach the reference value.

2. The system according to claim 1, wherein: The reference value includes an ideal amplifier output amplitude.

3. The system according to claim 1 further includes a loop state machine and a digital-to-analog converter, so that the loop state machine is configured to convert the gain control signal into a digital gain control value, the digital gain control value is provided to the digital-to-analog converter, the digital-to-analog converter converts the digital gain control value into an analog gain control signal, and the analog gain control signal is provided to the variable amplifier.

4. The system according to claim 1, wherein: In response to the error detector signal not satisfying the predetermined pattern, the error detector signal monitor is configured to increase the counter size.

5. The system according to claim 4, wherein: Increasing the counter size includes resetting the counter size to a maximum counter size.

6. A method for controlling the gain of a variable gain amplifier, comprising: comparing the variable gain amplifier output signal with a reference value to determine whether the variable gain amplifier output signal is greater than or less than the reference value; generating an up signal in response to the variable gain amplifier output signal being greater than the reference value; generating a down signal in response to the variable gain amplifier output signal being less than the reference value; updating a counter in response to an up signal and in response to a down signal; Track the number of up and down signals relative to a predetermined pattern; outputting a counter output signal to adjust the gain of the variable gain amplifier in response to the counter reaching a maximum counter value or a minimum counter value; In response to a number of up signals and down signals associated with the predetermined pattern satisfying the predetermined pattern, a size of the counter is changed.

7. The method according to claim 6, wherein: The reference value includes an ideal amplifier output amplitude.

8. The method according to claim 6, wherein: Updating the counter in response to the up signal and the down signal includes incrementing the counter value in response to the up signal and decrementing the counter value in response to the down signal.

9. The method according to claim 6, wherein: Tracking includes monitoring a series of previous signals from the error detector and comparing the series of previous signals to the predetermined pattern such that if the series of previous signals from the error detector matches the predetermined pattern, the counter size is reduced.

10. The method according to claim 6, wherein: The counter size is the maximum counter value that must be reached before the counter outputs a counter output.

11. The method according to claim 6, wherein: The pattern is a predetermined number of consecutive up signals or a predetermined number of consecutive down signals.

12. The method according to claim 6, wherein: The pattern is a predetermined number of up signals or a predetermined number of consecutive down signals with respect to a predetermined number of up signals and down signals.

13. The method according to claim 6, further comprising: In response to the counter value reaching the counter size value or a predetermined counter minimum value, the counter is reset to a counter midpoint value.

14. A system for controlling the convergence of a control loop to a reference value, comprising: a device, under control of said control loop, configured to generate an output signal; Comparator, configured as: comparing the output signal with a reference value; In response to the output signal being smaller than the reference value, outputting an upward signal; as well as In response to the output signal being greater than the reference value, outputting a down signal; a counter having a counter size defining a counter maximum value and a counter minimum value, the counter being configured to maintain a counter value that is incremented in response to an up signal and decremented in response to a down signal such that the counter outputs a gain control value; Up / Down signal tracker, configured to: tracking patterns of up signals and down signals and comparing the patterns to one or more predetermined patterns; In response to the up signal and the down signal matching one of the one or more predetermined patterns, the counter size is changed.

15. The system of claim 14, wherein: The up / down signal tracker includes a memory and one or more comparators.

16. The system of claim 14, wherein: Changing the counter size includes sending a control signal to the counter to decrease the size of the counter.

17. The system of claim 14, wherein: The device under control of the control loop is a variable gain amplifier.

18. The system of claim 14, wherein: A loop state machine is included that is configured to increase or decrease a digital gain control value in response to the gain control value from the counter.

19. The system of claim 14, further comprising: In response to the up signal and the down signal not matching one of the one or more predetermined patterns, the counter size is increased.

20. The system of claim 14, further comprising a system for performing dynamic step size adjustment.

Images