Silicon-based liquid crystal panel and preparation method thereof

Abstract

The application provides a silicon-based liquid crystal panel and a preparation method thereof. The preparation method comprises wafer-level packaging, manufacturing a plurality of through holes penetrating through a silicon substrate in each die area on a wafer substrate, manufacturing a plurality of conductive interfaces on the back surface of the wafer substrate, the conductive interfaces corresponding to the through holes one by one, and each conductive interface being electrically connected to an active circuit in the die area where the conductive interface is located through the corresponding through hole; liquid crystal packaging, coating frame glue around a pixel circuit area of the active circuit on the front surface of the wafer substrate in each die area on the wafer substrate, injecting liquid crystal into a liquid crystal space defined by the frame glue, and adhering a glass substrate with a transparent conductive layer to the wafer substrate through the frame glue; and cutting the wafer substrate and the glass substrate to obtain a plurality of silicon-based liquid crystal panels. The technical scheme makes the wafer-level chip scale packaging of the silicon-based liquid crystal panel feasible, reduces the cost, and makes the total area of the obtained silicon-based liquid crystal panel small and the thickness thin.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a liquid crystal on silicon (LCoS) panel and its preparation method. Background Technology

[0002] Wafer-level packaging (WLP) technology is an effective method for mass production of chips. Compared to simple integrated circuit chips, LCoS panels include not only integrated circuits but also liquid crystal packaging structures. Building a complete LCoS wafer-level packaging production line requires not only integrated circuit packaging but also liquid crystal packaging. Currently, such a complete production line does not exist; it can only be achieved through equipment customization or modification, resulting in very high upfront costs and hindering rapid industrialization. Furthermore, production lines for manufacturing silicon-based liquid crystal panels require equipment from the semiconductor industry, which is extremely expensive. If the equipment cannot operate at full capacity, the production cost is even higher.

[0003] On the other hand, to maintain the lowest possible wafer cost, more dies need to be packed into a standard wafer, resulting in a reduction in die design size. However, the smaller die size introduces new problems for subsequent module packaging. In traditional LCOS panels, the dies are connected to the external circuit board via leads extending from conductive pads located on the front edge of the wafer substrate. Because the area available for lead placement is reduced, while the number of leads remains the same, conventional wire bonding or thin-film printed circuit wiring becomes increasingly difficult and time-consuming. More importantly, this prevents improvements in signal processing speed.

[0004] Therefore, it is necessary to develop a new mass production solution for silicon-based liquid crystal panels and a corresponding silicon-based liquid crystal panel structure. Summary of the Invention

[0005] This invention provides a method for fabricating a silicon-based liquid crystal panel, comprising the following steps: providing a wafer substrate, the wafer substrate including a silicon substrate having opposing first and second surfaces, the wafer substrate being divided into multiple die regions by intersecting dividing lines, each die region including an active circuit disposed on the first surface, the active circuit including at least a pixel circuit region and a peripheral circuit region; wafer-level packaging, on the wafer substrate, in each die region, fabricating multiple vias penetrating the first and second surfaces, and fabricating multiple conductive interfaces on the second surface, the conductive interfaces corresponding one-to-one with the vias, each conductive interface being electrically connected to the active circuit of the die region in which it is located through its corresponding via; liquid crystal packaging, in the wafer substrate... On a wafer substrate, in each of the die regions, a frame adhesive is formed on one side of the first surface, such that the frame adhesive at least surrounds the pixel circuit area of ​​the active circuit, and the frame adhesive defines the liquid crystal space of the die region in which it is located; liquid crystal is injected into each of the liquid crystal spaces of the wafer substrate; a glass substrate with a transparent conductive layer on its surface is provided, such that the surface of the glass substrate with the transparent conductive layer is bonded to the wafer substrate through the frame adhesive; the wafer substrate is cut along the dividing line, and the glass substrate is cut accordingly to obtain a plurality of silicon-based liquid crystal panels; the silicon-based liquid crystal panels can be electrically connected to an external circuit board to obtain a silicon-based liquid crystal module, wherein the active circuit is electrically connected to the external circuit board in sequence through the plurality of vias and the plurality of conductive interfaces.

[0006] The fabrication method of this silicon-based liquid crystal panel, by employing through-silicon via (TSV) technology on the wafer substrate, brings process advantages, making it possible to "separate the front-end circuit packaging and the back-end liquid crystal packaging processes into two independent parts." Specifically, by using TSV technology to create vias (metallized holes) penetrating the silicon substrate, the active circuits on the wafer substrate are electrically connected to the conductive interfaces on the back side (i.e., the second surface) of the wafer substrate through the vias, thus completing the circuit packaging. The subsequent liquid crystal packaging process is mainly carried out on the front side (i.e., the first surface side) of the wafer substrate, which neither damages the circuit packaging structure nor requires additional circuit packaging processes on the front side of the wafer substrate during the liquid crystal packaging process. After the liquid crystal packaging is completed, it can be diced to obtain individual silicon-based liquid crystal panels, and there is no need for further die-level packaging of the silicon-based liquid crystal panels. Downstream OEMs only need to directly install them on an external circuit board to obtain silicon-based liquid crystal modules for use. In other words, the circuit packaging and liquid crystal packaging processes can be performed independently and completely by different factories / workshops / equipment, both at the wafer level. This avoids the need for repeated switching between different factories / workshops / equipment for different stages of the same process (counter-example: steps A and C are performed in the wafer packaging factory / workshop / equipment, while steps B and D are performed in the liquid crystal filling factory / workshop / equipment; if production were carried out in the order of ABCD steps, the wafer would need to be transported back and forth between the two factories / workshops / equipment, leading to a decrease in yield). Simultaneously, this allows for rapid mass production in the early stages of the industry by leveraging mature wafer-level packaging and liquid crystal packaging plants, solving the problems of excessive initial investment costs and long investment cycles. In summary, this makes cost control, production planning, and output improvement much easier.

[0007] Furthermore, employing through-silicon via (TSV) technology on the wafer substrate to form vias penetrating the silicon substrate allows the silicon-based liquid crystal panel to directly connect to an external circuit board via a conductive interface on the back. This results in the most compact silicon-based liquid crystal module packaging structure, reducing overall size while improving signal processing speed, leading to lower signal distortion and lower total power consumption. This technology eliminates the need for FPC lines to connect the silicon-based liquid crystal panel to the external circuit board, enabling mass production at a more cost-effective material level. Moreover, the current flow in this structure is perpendicular to the panel direction, allowing for thinner designs. The structure essentially consists of only three layers: a glass substrate layer, a liquid crystal layer, and a wafer substrate layer, eliminating the need for redundant metal plates and heat sinks on the back. This makes it suitable for applications such as head-mounted displays and micro-projectors.

[0008] This invention also provides a method for fabricating a silicon-based liquid crystal panel, comprising the following steps: providing a wafer substrate, the wafer substrate including a silicon substrate having opposing first and second surfaces, the wafer substrate being divided into multiple die regions by intersecting dividing lines; wafer-level packaging, on the wafer substrate, in each of the die regions, fabricating multiple vias penetrating the first and second surfaces, then fabricating active circuits disposed on the first surface in each of the die regions, the active circuits including at least a pixel circuit region and a peripheral circuit region, then fabricating multiple conductive interfaces on the second surface, the conductive interfaces corresponding one-to-one with the vias, the active circuits being electrically connected to the multiple conductive interfaces through the multiple vias; liquid crystal packaging, on the wafer substrate... On the board, in each of the die regions, a frame adhesive is formed on one side of the first surface, such that the frame adhesive at least surrounds the pixel circuit area of ​​the active circuit, and the frame adhesive defines the liquid crystal space of the die region in which it is located; liquid crystal is injected into each of the liquid crystal spaces of the wafer substrate; a glass substrate with a transparent conductive layer on its surface is provided, such that the surface of the glass substrate with the transparent conductive layer is bonded to the wafer substrate by the frame adhesive; the wafer substrate is cut along the dividing line, and the glass substrate is cut accordingly to obtain a plurality of silicon-based liquid crystal panels; the silicon-based liquid crystal panels can be electrically connected to an external circuit board to obtain a silicon-based liquid crystal module, wherein the active circuit is electrically connected to the external circuit board in sequence through the plurality of vias and the plurality of conductive interfaces.

[0009] This fabrication method shares the same inventive concept as the methods listed in the first paragraph of the invention description. Both methods separate wafer-level circuit packaging and wafer-level liquid crystal packaging into two completely independent process steps. The only difference lies in whether the integrated circuit manufacturing occurs before or after via fabrication. Both integrated circuit manufacturing and circuit packaging can be performed in a wafer fab. Since the inventive concepts for separating the process steps are the same in both methods, and the structural features of the silicon-based liquid crystal panel that enable this process separation are the same, the beneficial effects achieved by both methods are also the same, and will not be elaborated further here.

[0010] In one embodiment of the preparation method, the thickness of the silicon substrate ranges from 60 μm to 750 μm, and the thickness of the glass substrate ranges from 60 μm to 750 μm.

[0011] In one embodiment of the preparation method, the thickness of the silicon substrate ranges from 60 μm to 200 μm.

[0012] In one embodiment of the fabrication method, during the wafer-level packaging step, for each die region, the projections of multiple vias manufactured on the wafer substrate are arranged to avoid and surround the pixel circuit region. Since the size of a single pixel circuit in the pixel circuit region directly affects the pixel size of the silicon-based liquid crystal panel, the pixel circuit region needs to be designed very densely. This technical solution places the vias connecting to the input / output terminals of the active circuits outside the pixel circuit region. This avoids occupying a compact pixel area, which is beneficial for increasing pixel density. Furthermore, it avoids the through-hole process from damaging the stability of the pixel circuit, thus improving process feasibility.

[0013] In one embodiment of the fabrication method, during the wafer-level packaging step, for each die region, the projections of the fabricated vias onto the wafer substrate are arranged to avoid and surround the peripheral circuit area. This technical solution avoids the influence of vias on the peripheral circuit and reduces the process difficulty of through-silicon via (TSV) technology, thus offering better process feasibility.

[0014] In one embodiment of the fabrication method, the active circuit includes multiple metal layers, each metal layer including multiple input / output terminals located at different positions. Each via is vertically connected to a different input / output terminal of the metal layer, thereby achieving electrical connection with the pixel circuit area and / or the peripheral circuit area.

[0015] In one embodiment of the fabrication method, each die region further includes a plurality of conductive pads spaced apart on the first surface. These conductive pads are electrically connected to the active circuitry and can be used to test the active circuitry before / during the liquid crystal packaging step. This technical solution facilitates testing the wafer before / during liquid crystal packaging without damaging the conductive interfaces (e.g., without needing to solder the conductive interfaces to the testing device). Furthermore, the testing can be performed from the front side of the wafer (the side of the first surface), making the operation more convenient.

[0016] In one embodiment of the fabrication method, within each die region, for at least a portion of the vias, there exists a corresponding and electrically connected conductive pad, and the projections of each conductive pad and its corresponding via on the wafer substrate are staggered. This technical solution makes the physical connection between the conductive pad and the active circuit relatively independent of the physical connection between the via and the active circuit, resulting in greater flexibility in circuit layout.

[0017] In one embodiment of the fabrication method, within each die region, for at least a portion of a via, there exists a corresponding and electrically connected conductive pad, and the projections of each conductive pad and its corresponding via on the wafer substrate overlap. This technical solution reduces the number of input / output terminals that need to be placed on the metal layer, which is beneficial for reducing the overall die size.

[0018] In a preferred embodiment, within each die region, each via has a corresponding conductive pad, and the corresponding via is electrically connected to the conductive pad. This technical solution allows for testing the functionality of all active circuits connected by the vias using the conductive pads, greatly improving the testing convenience during the manufacturing process.

[0019] In one embodiment of the fabrication method, the sealant does not cover the conductive pad during the liquid crystal encapsulation step. This technique allows the performance of the active circuit to be tested through the conductive pad after the sealant is formed.

[0020] In one embodiment of the fabrication method, during the liquid crystal encapsulation step, a frame adhesive covers the conductive pads. This technique ensures that the final silicon-based liquid crystal panel has no exposed conductive pads on the front side, and eliminates the need for additional layers to cover the conductive pads, thus reducing the number of process steps.

[0021] In one embodiment of the fabrication method, the conductive interface is electrically connected to an external circuit board by welding, and the welding temperature of the conductive interface material is selected to avoid damage to the liquid crystal.

[0022] In one embodiment of the fabrication method, the conductive interface includes at least one of a ball grid array packaging structure, a pin grid array structure, and a grid array packaging structure.

[0023] In one embodiment of the fabrication method, the conductive interface is electrically connected to the external circuit board via mechanical pressing or mechanical coupling. This technical solution significantly reduces the bonding temperature between the silicon-based liquid crystal panel and the external circuit board compared to methods such as welding, thus avoiding the impact of excessively high temperatures from welding on the liquid crystal molecules.

[0024] In one embodiment of the fabrication method, at least a portion of the conductive interfaces are projected onto the wafer substrate closer to the center of the die than the projection of the corresponding vias onto the wafer substrate. By connecting the vias and conductive interfaces using circuitry on the second surface of the wafer substrate, some conductive interfaces can be distributed at the corresponding pixel circuit regions of the die, avoiding excessive crowding of conductive interfaces at the edges. This also allows for larger conductive interfaces and higher transmission efficiency.

[0025] In another aspect, the present invention provides a silicon-based liquid crystal panel, comprising: a wafer substrate, the wafer substrate including a silicon substrate having opposing first and second surfaces, an active circuit located on the first surface, a plurality of conductive interfaces located on the second surface, and a plurality of vias penetrating the first and second surfaces, wherein the conductive interfaces correspond one-to-one with the vias, and each conductive interface is electrically connected to the active circuit through its corresponding via, the active circuit including at least a pixel circuit region and a peripheral circuit region; a glass substrate having a transparent conductive layer on its surface, disposed opposite to the wafer substrate; a sealant located between the wafer substrate and the glass substrate, the sealant at least surrounding the pixel circuit region of the active circuit and defining a liquid crystal space; and liquid crystal located within the liquid crystal space; the silicon-based liquid crystal panel can be electrically connected to an external circuit board through the conductive interfaces.

[0026] The design of this silicon-based liquid crystal panel, through the use of through-silicon via (TSV) technology on the wafer substrate, makes it possible to separate the front-end circuit packaging and the back-end liquid crystal packaging processes into two independent parts. Specifically, by using TSV technology to create vias penetrating the silicon substrate, active circuits on the wafer substrate are electrically connected to conductive interfaces on the back of the wafer substrate, thus completing the circuit packaging. The subsequent liquid crystal packaging process is mainly performed on the front side of the wafer substrate, without damaging the circuit packaging structure or requiring additional circuit packaging steps on the front side of the wafer substrate during the liquid crystal packaging process. After liquid crystal packaging, the wafer can be diced to obtain individual silicon-based liquid crystal panels, without further die-level packaging; they can be directly mounted onto an external circuit board. This design allows both circuit packaging and liquid crystal packaging to be implemented at the wafer level, making cost control, production planning, and yield improvement much easier. The current flow of this silicon-based liquid crystal panel is perpendicular to the panel direction, which allows for a thinner thickness. It has only a three-layer structure consisting of a glass substrate layer, a liquid crystal layer, and a wafer substrate layer. It does not require redundant metal plates and heat sinks on the back, and can be applied in fields such as head-mounted displays and micro projectors.

[0027] In one embodiment, the projections of multiple vias on the wafer substrate avoid and surround the pixel circuit area. This technical solution positions the vias at the input / output terminals of the active circuit outside the pixel circuit area. On the one hand, this avoids occupying a compact pixel area, which is beneficial for increasing pixel density. On the other hand, it avoids the through-hole process from damaging the stability of the pixel circuit, which is beneficial for improving process feasibility.

[0028] In one embodiment, the projections of multiple vias on the wafer substrate avoid and surround the peripheral circuit area.

[0029] In one embodiment, some vias are located in the peripheral circuit area. This technical solution allows for more flexible peripheral circuit layout design and also helps to improve the transmission rate of the circuit corresponding to these vias.

[0030] In one embodiment, the active circuit includes multiple metal layers, each metal layer including multiple input / output terminals located at different positions, and each via is vertically connected to a different input / output terminal of the metal layer, thereby realizing electrical connection with the pixel circuit area and / or the peripheral circuit area.

[0031] In one embodiment, the wafer substrate further includes a plurality of conductive pads spaced apart on the first surface. The conductive pads are electrically connected to active circuits, and for at least a portion of the vias, there is a corresponding conductive pad that is electrically connected. This technical solution facilitates testing the wafer before / during liquid crystal packaging without damaging the conductive interfaces (e.g., without needing to solder the conductive interfaces to the testing device), and the testing can be performed from the front side of the wafer (one side of the first surface), making the operation more convenient.

[0032] In one implementation, the conductive interface is electrically connected to the external circuit board by welding, and the welding material of the conductive interface is selected to ensure that the welding temperature is lower than the temperature that the liquid crystal can tolerate.

[0033] In one embodiment, the conductive interface includes at least one of a ball grid array package structure, a pin grid array structure, and a grid array package structure.

[0034] In one embodiment, the conductive interface is electrically connected to the external circuit board via mechanical pressing or mechanical coupling. This technical solution significantly reduces the bonding temperature between the silicon-based liquid crystal panel and the external circuit board compared to methods such as soldering, avoiding the impact of excessively high temperatures from soldering on the liquid crystal molecules. In a further embodiment, the liquid crystal display panel and the external circuit board are further secured by snap-fit ​​connections, improving the reliability of the mechanical pressing or mechanical coupling connection.

[0035] In one embodiment, at least a portion of the conductive interfaces are projected onto the wafer substrate closer to the center of the silicon-based liquid crystal panel than the projection of the corresponding vias onto the wafer substrate. By connecting the vias and conductive interfaces using circuitry on the second surface of the wafer substrate, some conductive interfaces can be distributed at the locations of the pixel circuit areas of the corresponding dies, avoiding excessive crowding of conductive interfaces at the edges. This also allows for larger conductive interfaces and higher transmission efficiency.

[0036] In one embodiment, the thickness of the silicon substrate of the silicon-based liquid crystal panel ranges from 60 μm to 750 μm, and the thickness of the glass substrate ranges from 60 μm to 750 μm.

[0037] In one embodiment, the thickness of the silicon substrate ranges from 60 μm to 200 μm. Attached Figure Description

[0038] Figure 1 This is a schematic flowchart illustrating a method for fabricating a silicon-based liquid crystal panel according to an embodiment of the present invention.

[0039] Figure 2 for Figure 1 A top view of the wafer substrate provided in step S1.

[0040] Figure 3 for Figure 2 A schematic diagram showing the section cut along line III-III.

[0041] Figure 4 for Figure 1 A schematic cross-sectional view of the wafer substrate provided in step S2.

[0042] Figure 5 for Figure 1 In step S3 Figure 4 A schematic diagram of an alignment layer formed on a wafer substrate.

[0043] Figure 6 for Figure 1 A top view of step S3, which involves forming multiple frames of adhesive on a wafer substrate.

[0044] Figure 7 for Figure 6 A schematic diagram showing the section cut along line VI-VI.

[0045] Figure 8 for Figure 1 A schematic diagram of injecting liquid crystal into each liquid crystal space in step S3.

[0046] Figure 9 for Figure 1 A schematic diagram of bonding the glass substrate and the wafer substrate using frame adhesive in step S3.

[0047] Figure 10 for Figure 1 A schematic diagram of step S4, in which the glass substrate and the wafer substrate are cut to obtain multiple silicon-based liquid crystal panels.

[0048] Figure 11 for Figure 1 A schematic diagram of step S4, which involves placing the back side of the wafer substrate onto a carrier plate.

[0049] Figure 12 This is a schematic diagram of step S5, which involves electrically connecting the silicon-based liquid crystal panel to an external circuit board to obtain a silicon-based liquid crystal module.

[0050] Figure 13 This is a cross-sectional schematic diagram of a silicon-based liquid crystal panel according to an embodiment of the present invention.

[0051] Figure 14 for Figure 13 A top-view perspective diagram of a silicon-based liquid crystal panel.

[0052] Figure 15 for Figure 13 A bottom-view diagram of a silicon-based liquid crystal panel.

[0053] Explanation of main component symbols

[0054] Wafer substrate 10

[0055] Divider line L

[0056] die region 10a

[0057] Silicon substrate 11

[0058] First surface 112

[0059] Second surface 114

[0060] Via 116

[0061] Active circuit 12

[0062] Input / output terminal 13

[0063] Conductive interface 14

[0064] Patterned conductive layer 15

[0065] Insulation layer 16

[0066] Conductive pad 17

[0067] Insulating film layer 18

[0068] Frame adhesive 20

[0069] LCD space 22

[0070] LCD 30

[0071] Glass substrate 40

[0072] Glass substrate 42

[0073] Transparent conductive layer 44

[0074] Alignment layer 50

[0075] Conductive adhesive 60

[0076] Carrier plate 70

[0077] Groove 72

[0078] Silicon-based LCD panel 110

[0079] External circuit board 120

[0080] Silicon-based liquid crystal module 100

[0081] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0082] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0084] In this invention, a die refers to the part of a silicon-based liquid crystal panel that does not include the liquid crystal packaging structure (liquid crystal, glass substrate, frame adhesive, etc.), mainly including a wafer (silicon substrate + active circuit) and a circuit packaging structure (via + conductive interface, etc.); a silicon-based liquid crystal panel refers to a die + liquid crystal packaging structure, which can be sold as an independent product; a silicon-based liquid crystal module refers to a silicon-based liquid crystal panel + external circuit board, which can be obtained by downstream OEMs combining the silicon-based liquid crystal panel onto the PCB board of their products, or it can be packaged and sold after the silicon-based liquid crystal panel is produced. The functional integrity of the silicon-based liquid crystal panel is not limited by the external circuit board.

[0085] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0086] Figure 1 This is a schematic flowchart illustrating a method for fabricating a silicon-based liquid crystal panel according to an embodiment of the present invention. Figure 1 As shown, the method for manufacturing this silicon-based liquid crystal panel includes the following steps.

[0087] Step S1: Provide a wafer substrate.

[0088] Step S2: Wafer-level packaging, fabricating vias and conductive interfaces in each die area of ​​the wafer substrate.

[0089] Step S3: Liquid crystal packaging, forming a frame adhesive in each die area of ​​the wafer substrate, injecting liquid crystal, and pressing the glass substrate to the wafer substrate through the frame adhesive.

[0090] Step S4: Cut the glass substrate and the wafer substrate to obtain multiple silicon-based liquid crystal panels.

[0091] When the silicon-based liquid crystal panel obtained by the method of the present invention is applied to a product, it further includes step S5: silicon-based liquid crystal panel mounting, which electrically connects the silicon-based liquid crystal panel to an external circuit substrate to obtain a silicon-based liquid crystal module. Step S5 is not necessarily considered a necessary step in the method of preparing the silicon-based liquid crystal panel.

[0092] The following combination Figures 2 to 12 Explain the fabrication method of this silicon-based liquid crystal panel.

[0093] Step S1: Provide a wafer substrate.

[0094] like Figure 2 As shown, the wafer substrate 10 includes a silicon substrate 11. The wafer substrate 10 is divided into multiple die regions 10a by multiple intersecting dividing lines L (represented by dashed lines in the figure; the dividing lines can be actual scribe lines or virtual lines). Each die region includes active circuitry 12, and the active circuitry 12 includes at least a pixel circuit region and a peripheral circuit region.

[0095] like Figure 3 As shown, the silicon substrate 11 has a first surface 112 (also referred to as the front side of the silicon substrate) and a second surface 114 (also referred to as the back side of the silicon substrate). Active circuitry 12 is disposed on the first surface 112. In this embodiment, the thickness of the silicon substrate 11 ranges from 60 μm to 200 μm. A silicon substrate of this thickness results in a thinner overall silicon-based liquid crystal panel, which is advantageous for applications such as head-mounted displays or micro-projections. In other embodiments of the invention, the thickness of the silicon substrate 11 can range from 60 μm to 750 μm. Preferably, the thickness of the silicon substrate 11 is between 100 μm and 200 μm, balancing product size, mechanical reliability, and optical flatness, and also facilitating subsequent through-silicon via (TSV) processes.

[0096] The active circuit 12 is composed of a metal layer, in Figure 3 In the illustrated embodiment, only two metal layers are shown. It can be understood that in other embodiments of the present invention, the active circuit may have more metal layers. Multiple metal layers may be stacked along a direction perpendicular to the silicon substrate 11, with a dielectric layer (such as silicon glass) disposed between different metal layers, and a dielectric layer (not shown in the figure) also disposed between the metal layers and the silicon substrate 11. The metal layers include input / output terminals 13. The active circuit 12 is connected to a more external circuit structure through the input / output terminals 13. Since the active circuit 12 is electrically connected to the input / output terminals 13 (represented by dotted lines in the figure) and belongs to the same metal layer, the input / output terminals 13 can also be regarded as part of the active circuit 12, and are simultaneously etched during integrated circuit manufacturing. Figure 2 In this embodiment, only two input / output terminals 13 are shown in each die region 10a. In other embodiments, the number of input / output terminals 13 in each die region 10a is not limited.

[0097] In one embodiment of the present invention, the diameter of the wafer substrate 10 is, for example, 8 inches (200 mm). The silicon substrate 11 is made of, for example, bulk silicon, silicon germanide, silicon carbide, etc.

[0098] The active circuit 12 specifically includes an active display driving matrix composed of multiple metal oxide semiconductor (MOS) transistors (not shown) and multiple reflective electrodes (not shown).

[0099] In this embodiment, the provided wafer substrate can be obtained through integrated circuit manufacturing before or during step S1. This step can be performed in a wafer fab.

[0100] Step S2: Wafer-level packaging, fabricating vias and conductive interfaces in each die area of ​​the wafer substrate.

[0101] On the wafer substrate obtained in step S1, a plurality of vias (metallized vias) penetrating the first surface and the second surface are formed in each die region 10a, and a plurality of conductive interfaces are formed on the second surface.

[0102] like Figure 4 As shown, the silicon substrate 11 has vias 116 penetrating the first surface 112 and the second surface 114. Each via 116 corresponds to an input / output terminal 13. Similarly, a die region 10a may include multiple vias 116, not limited to the number shown in the figure. The second surface 114 of the silicon substrate 11 is provided with multiple conductive interfaces 14 at intervals. Each conductive interface 14 corresponds to a via 116, and each conductive interface 14 is electrically connected to the active circuit 12 of the die region 10a in which it is located through its corresponding via 116.

[0103] In one specific embodiment, a via 116 is formed by forming a via on a silicon substrate 11 at the corresponding input / output terminal 13, and forming a patterned insulating film layer 18 and a conductive layer 15 on the via and the second surface 114 of the silicon substrate 11. The insulating film layer 18 covers the inner wall of the via, and the conductive layer 15 covers the inner wall of the via formed by the insulating film layer 18, thereby isolating the conductive layer 15 from contact with the silicon substrate 11. The conductive layer 15 is deposited on the surface of the input / output terminal 13 at one end of the via, thus achieving electrical connection. Specifically, a via is first made on the silicon substrate 11, then the insulating film layer 18 is deposited, then the portion of the insulating film layer 18 at the bottom of the via is etched away, exposing the input / output terminal 13, and then the conductive layer 15 is deposited. Figure 4In the wafer substrate 10, an insulating layer 16 is also included, which exposes a partially patterned conductive layer 15 on a second surface 114, and a conductive interface 14 is formed on the exposed patterned conductive layer 15.

[0104] The insulating layer 16 is made of, for example, polyimide (PI) or epoxy resin, and the insulating material may fill the via 116. The patterned conductive layer 15 is made of, for example, copper, or other metals or metal alloys. The conductive interface 14 is made of, for example, one or more of the following materials: tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony, and may include an activator.

[0105] Step S3: Liquid crystal packaging, forming a frame adhesive in each die region 10a of the wafer substrate 10, injecting liquid crystal, and pressing the glass substrate to the wafer substrate through the frame adhesive.

[0106] In one embodiment, step S3 further includes cleaning the wafer substrate 10 (e.g., cleaning with deionized water followed by plasma cleaning) and forming an alignment layer 50 on the wafer substrate 10 (e.g., ...). Figure 5 (As shown). The alignment layer 50 is used to give the liquid crystal molecules an initial orientation, so that the liquid crystal molecules at different positions are aligned in a consistent manner. The alignment layer 50 can be formed on the wafer substrate 10 by processes such as evaporation, coating, chemical vapor deposition (CVD), or atomic layer deposition (ALD) to form an alignment film; then, several alignment trenches are formed on the surface of the alignment film by a rubbing process, thus obtaining the alignment layer 50 with alignment capability. The material of the alignment layer 50 is, for example, polyimide or silicon dioxide.

[0107] Since alignment films are also required on the two glass substrates of a TFT (Thin Film Transistor) liquid crystal panel to position the liquid crystal molecules, in one embodiment, the step of cleaning the wafer substrate 10 can be performed on a conventional liquid crystal display panel production line.

[0108] like Figure 6 and Figure 7As shown, on the wafer substrate 10, a sealant 20 is formed on one side of the first surface 112 in each die region 10a. Each sealant 20 is generally a closed annular structure. The sealant 20 defines the liquid crystal space 22 of the die region 10a in which it is located, for accommodating the liquid crystal 30. The sealant 20 is arranged such that it at least surrounds the pixel circuit area of ​​the active circuit 12, so that the light emitted by the pixels of the silicon-based liquid crystal panel can be emitted within the area enclosed by the sealant. In this invention, the width of the sealant is 50 μm to 1000 μm.

[0109] In one embodiment, the frame adhesive can be applied by screen printing or injection molding.

[0110] like Figure 8 As shown, liquid crystal 30 is injected into each liquid crystal space 22 of the wafer substrate 10. The injected liquid crystal 30 covers the active circuit 12, particularly the pixel circuit area of ​​the active circuit 12. In one embodiment, the liquid crystal 30 is injected using a one-drop filling (ODF) process. This ODF process can significantly reduce the time required to inject the liquid crystal 30 and improve the utilization rate of the liquid crystal 30. In other embodiments, liquid crystal 30 can also be injected into the liquid crystal space 22 using a potting method.

[0111] like Figure 9 As shown, a glass substrate with a transparent conductive layer on its surface is provided, and the surface of the glass substrate with the transparent conductive layer is bonded to the wafer substrate by a frame adhesive.

[0112] In one embodiment, the provided glass substrate 40 is the same size as the wafer substrate 10. Step S3 further includes cleaning the glass substrate 40 (e.g., cleaning with deionized water followed by plasma cleaning) and forming an alignment layer 50 on the glass substrate 40. In this embodiment, the thickness of the glass substrate 40 ranges from 60 μm to 750 μm, and a thinner glass substrate can be obtained by a grinding process.

[0113] In one embodiment, the step of cleaning the glass substrate 40 can be performed on a conventional liquid crystal display panel production line.

[0114] The alignment layer 50 is made of materials such as polyimide or silicon dioxide. Figure 9 As shown, the glass substrate 40 includes a glass substrate 42 and a transparent conductive layer 44 located on one surface of the glass substrate 42. An alignment layer 50 is formed on the surface of the transparent conductive layer 44 away from the glass substrate 42. The transparent conductive layer 44 is made of, for example, indium tin oxide (ITO), fluorine-doped tin oxide (SnO2:F, FTO), aluminum-doped zinc oxide (ZnO:Al, ZAO), or an oxide of indium / antimony / zinc / cadmium.

[0115] Specifically, under vacuum conditions, the glass substrate 40 and the wafer substrate 10 are aligned using a laminating machine, and then the frame adhesive 20 is cured by ultraviolet light or heat. In one embodiment, both light curing and heat curing can be used to compensate for the areas of the frame adhesive 20 not irradiated by ultraviolet light, thus avoiding insufficient curing in the frame adhesive 20 area. In addition to bonding the wafer substrate 10 and the glass substrate 40 together, the frame adhesive 20 also serves to resist the intrusion of external environmental factors such as moisture.

[0116] In one embodiment, each frame adhesive 20 has a plurality of spacers (not shown) to facilitate maintaining the spacing between the wafer substrate 10 and the glass substrate 40. The spacers are made of materials such as plastic, silicon dioxide, glass, resin or other mixtures with similar properties, but are not limited thereto.

[0117] In one embodiment, since the size of the liquid crystal space 22 is very small, and to avoid the spacers affecting the movement of the liquid crystal molecules 30, and also to prevent the spacers from reducing the pixel fill rate, no spacers are provided in the liquid crystal space 22.

[0118] like Figure 9 As shown, after the glass substrate 40 is bonded to the wafer substrate 10, the liquid crystal 30 is located between the two alignment layers 50, thereby determining the orientation of the liquid crystal molecules.

[0119] Step S4: Cut the glass substrate and the wafer substrate to obtain multiple silicon-based liquid crystal panels.

[0120] like Figure 10 As shown, in step S4, the glass substrate 40 and the wafer substrate 10 are cut along the dividing line L to obtain a plurality of silicon-based liquid crystal panels 110.

[0121] Specifically, step S4 includes cutting. First, using a general silicon wafer sawing device, a fracture groove is cut on the silicon substrate 11 along the dividing line L. Then, using a general glass cutting device, corresponding separation lines are drawn on the surface of the glass substrate 42. Finally, the fracture groove and the separation lines on the surface of the glass substrate 42 are cut along the back side of the silicon substrate 11 (i.e., one side of the second surface 114) to separate multiple silicon-based liquid crystal panels 110.

[0122] In step S4, such as Figure 11 As shown, the back side of the wafer substrate 10 can be placed on a carrier plate 70, and the carrier plate 70 has a groove 72 for receiving the conductive interface 14 at the position corresponding to the conductive interface 14. In this way, the conductive interface 14 can be protected on the one hand, and the wafer can be diced on the other hand.

[0123] In one embodiment, the separation line and the dividing line L correspond. That is, the edge of the cut on the glass substrate 40 is aligned with the edge of the cut on the wafer substrate 10. Compared to cutting the wafer substrate 10 and the glass substrate 40 according to different dividing lines L, this method can reduce manufacturing costs, reduce manufacturing time, and is less prone to damage during manufacturing.

[0124] In this invention, the total thickness of the obtained silicon-based liquid crystal panel ranges from 130μm to 1500μm, mainly comprising the thickness of the glass substrate layer, the liquid crystal layer, and the wafer substrate layer. In terms of size, the dimensions after cutting, i.e., the dimensions of the silicon-based liquid crystal panel 110, are the same as the die size; that is, the packaging process of this invention is CSP (chip scale package). The reduction in the overall size of the silicon-based liquid crystal panel 110 makes it more suitable for applications in head-mounted displays and micro-projection fields.

[0125] Step S5: Install the silicon-based liquid crystal panel, electrically connect the silicon-based liquid crystal panel to an external circuit board, and obtain multiple silicon-based liquid crystal modules.

[0126] Figure 12 The diagram illustrates a silicon-based liquid crystal panel 110 electrically connected to an external circuit board 120. The external circuit board 120 can be a flexible circuit board or a printed circuit board. The silicon-based liquid crystal panel 110 is electrically connected to the external circuit board 120 via conductive interfaces 14, allowing active circuitry 12 to be electrically connected to the external circuit board 120 through multiple input / output terminals 13, multiple vias 116, and multiple conductive interfaces 14 for signal input and output. Specifically, the silicon-based liquid crystal module 100 defines multiple pixels (not shown), and an active display driving matrix provides a set of MOS transistors for each pixel. Each set of MOS transistors in the active display driving matrix can control the electric field of the liquid crystal molecules corresponding to each pixel by controlling the voltage applied to the reflective electrodes, thereby adjusting the rotation angle of the liquid crystal molecules corresponding to each pixel, and thus controlling the polarization state of the light emitted from the region corresponding to each pixel. This, in conjunction with a polarization beam splitter, enables image modulation.

[0127] In this method for preparing a silicon-based liquid crystal panel, after forming a frame adhesive 20 and injecting liquid crystal 30 on a whole wafer substrate 10, it is then bonded to a glass substrate 40, and then a slitting step is performed to obtain multiple silicon-based liquid crystal panels 110. Compared with the method of first dividing the whole wafer substrate 10 and glass substrate 40 into individual pieces, and then performing processes such as coating, pressing, curing, and injecting liquid crystal 30, the production efficiency is improved, and the thickness of the liquid crystal 30 layer in the finished silicon-based liquid crystal panel 110 can be guaranteed to be consistent.

[0128] The above embodiments provide a method for fabricating a silicon-based liquid crystal panel. Under the same inventive concept, there is another modified embodiment of the method for fabricating a silicon-based liquid crystal panel. The difference between this technical solution and the above embodiments lies only in whether the integrated circuit is manufactured before or after the via fabrication. Specifically, the fabrication method of this modified embodiment includes:

[0129] Step S1': A wafer substrate is provided, the wafer substrate including a silicon substrate having opposing first and second surfaces, the wafer substrate being divided into multiple die regions by intersecting slitting lines; the difference from step S1 is that the wafer substrate in this modified embodiment does not have the following... Figure 2 and Figure 3 The active circuit 12 and input / output terminal 13 shown indicate that the wafer substrate does not contain integrated circuits.

[0130] Step S2': Wafer-level packaging. On the wafer substrate, in each die region, multiple vias penetrating the first and second surfaces are fabricated. Then, in each die region, active circuitry disposed on the first surface is fabricated. The active circuitry includes at least a pixel circuit area and a peripheral circuit area. Then, multiple conductive interfaces are fabricated on the second surface, with each conductive interface corresponding to a via. The active circuitry is electrically connected to the multiple conductive interfaces through the multiple vias. Step S2' is essentially the same as step S2 and can be used interchangeably, except that active circuitry and input / output terminals are not present when fabricating the vias. After completing step S2', a structural schematic diagram can be referenced. Figure 4 The structure above the first surface 112 after the structure is removed.

[0131] After completing step S2', the structural diagram can be referred to. Figure 4 As shown, the subsequent process can be referred to. Figure 1 The process of S3-S4 in the illustrated embodiment.

[0132] Step S3': Liquid crystal packaging. On the wafer substrate, in each die region, a frame adhesive is formed on one side of the first surface, such that the frame adhesive at least surrounds the pixel circuit area of ​​the active circuit, and the frame adhesive defines the liquid crystal space of the die region in which it is located; liquid crystal is injected into each liquid crystal space of the wafer substrate; a glass substrate with a transparent conductive layer on its surface is provided, and the surface of the glass substrate with the transparent conductive layer is bonded to the wafer substrate by the frame adhesive. Step S3' can be referred to the detailed description of step S3 and its extended embodiments.

[0133] Step S4': Cut the wafer substrate along the dicing line, and correspondingly cut the glass substrate to obtain multiple silicon-based liquid crystal panels. Step S4' can be referred to the detailed description of step S4 and its extended embodiments.

[0134] Similarly, when the silicon-based liquid crystal panel obtained by the method of this embodiment is applied to a product, it further includes step S5': silicon-based liquid crystal panel mounting, which electrically connects the silicon-based liquid crystal panel to an external circuit board to obtain multiple silicon-based liquid crystal modules. In each silicon-based liquid crystal module, the active circuitry is electrically connected to the external circuit board sequentially through multiple vias and multiple conductive interfaces. Step S5' can be found in the detailed description of step S5 and its extended embodiments. Step S5' is also not necessarily considered a mandatory step in the method of preparing the silicon-based liquid crystal panel.

[0135] An embodiment of the present invention also provides a silicon-based liquid crystal panel and a silicon-based liquid crystal module obtained by the above-described methods for preparing silicon-based liquid crystal panels. The silicon-based liquid crystal module includes a silicon-based liquid crystal panel and an external circuit board that are electrically connected. The silicon-based liquid crystal panel is electrically connected to the external circuit board through a conductive interface.

[0136] like Figure 13 As shown, the silicon-based liquid crystal panel 110 includes a wafer substrate 10 and a glass substrate 40 disposed opposite to each other. The wafer substrate 10 includes a silicon substrate 11 having a first surface 112 and a second surface 114 opposite to each other. The wafer substrate 10 also includes an active circuit 12 located on the first surface 112, a plurality of conductive interfaces 14 located on the second surface 114, and a plurality of vias 116 penetrating the first surface 112 and the second surface 114. The conductive interfaces 14 and vias 116 correspond one-to-one, and each conductive interface 14 is electrically connected to the active circuit 12 through its corresponding via 116. The active circuit includes a pixel circuit region and a peripheral circuit region. Specifically, the pixel circuit region includes a plurality of pixel circuits, each corresponding to a liquid crystal pixel of the silicon-based liquid crystal panel. By controlling the electric field of the liquid crystal molecules in the liquid crystal pixels, the deflection of the liquid crystal molecules is controlled. The peripheral circuit region is connected to the pixel circuit region by a circuit and is used to process input image signals, power signals, and other control signals, thereby outputting control signals for the pixel circuits to the pixel circuit region.

[0137] A transparent conductive layer 44 is provided on one surface of the glass substrate 40, and the transparent conductive layer 44 is disposed facing the wafer substrate 10. The wafer substrate 10 and the glass substrate 40 are connected by a frame adhesive 20 disposed between them. The frame adhesive 20 at least surrounds the pixel circuit area of ​​the active circuit 12 and defines a liquid crystal space. That is, the frame adhesive 20, the wafer substrate 10 and the glass substrate 40 together form a closed space for filling liquid crystal 30. The thickness of the glass substrate 40 ranges from 60 μm to 750 μm.

[0138] In one embodiment, the thickness of the silicon substrate 11 ranges from 60 μm to 200 μm. A silicon-based liquid crystal panel with this thickness is relatively thin, which is advantageous for applications such as head-mounted displays or micro-projections. In embodiments of the present invention, the thickness of the silicon substrate 11 ranges from 60 μm to 750 μm. Preferably, the thickness of the silicon substrate 11 is between 100 μm and 200 μm, balancing product size, mechanical reliability, and optical flatness, and also facilitating the placement of vias 116.

[0139] In one embodiment, the silicon-based liquid crystal panel 110 further includes an alignment layer 50 for initial orientation of the liquid crystal molecules in the liquid crystal 30. Generally, alignment layers 50 need to be provided on both sides of the liquid crystal 30. That is, the transparent conductive layer 44 of the glass substrate 40 has an alignment layer 50 near the surface of the liquid crystal 30, and the wafer substrate 10 also has an alignment layer 50 near the surface of the liquid crystal 30.

[0140] In one embodiment, the frame adhesive 20 has a plurality of spacers to provide sufficient mechanical support.

[0141] This silicon-based liquid crystal panel has a wafer substrate 10 with vias 116 penetrating a silicon substrate 11. The vias 116, input / output terminals 13, and active circuitry 12 are connected via conductive interfaces 14 located on the back of the wafer substrate 10. This allows the silicon-based liquid crystal panel to be manufactured using a passive liquid crystal display panel production line, performing the liquid crystal packaging process from the front of the wafer substrate 10, reducing equipment investment costs. Furthermore, by employing through-silicon via (TSV) technology on the wafer substrate 10 to form vias 116 penetrating the silicon substrate 11, the silicon-based liquid crystal panel 110 can be directly connected to an external circuit board via the conductive interfaces 14, eliminating the need for FPC lines, thus improving signal processing speed and saving costs.

[0142] like Figure 13 As shown, the projection of via 116 on the wafer substrate 10 avoids and surrounds the pixel circuit region of the active circuit 12 (which can be considered to at least avoid the area below the liquid crystal 30). In the case of multiple vias, each via avoids the pixel circuit region. In terms of process technology, in the embodiment of the above fabrication method, in the wafer-level packaging step (i.e., S2 / S2'), for each die region 10a, the projections of the manufactured multiple vias 116 on the wafer substrate 10 are arranged to avoid and surround the pixel circuit region.

[0143] like Figure 14 As shown, vias 116 avoid the area where the active circuit 12 is located to facilitate process feasibility. Furthermore, vias 116 surround the pixel array area, and are provided on all four sides of the pixel array area. In one embodiment, the number of vias 116 can be as high as 60 or more, such a dense number of holes further reduces the feasibility of creating openings below the active circuit 12.

[0144] In some embodiments of the present invention, the projection of the via 116 on the wafer substrate 10 avoids and surrounds the peripheral circuit area. For example... Figure 13 As shown, the portion of the active circuit 12 located directly below the frame adhesive 20 can be considered as part of the peripheral circuit. The two vias 116 shown in the figure both avoid this portion of the peripheral circuit. In terms of the manufacturing process, in the embodiment of the above-described fabrication method, in the wafer-level packaging step (i.e., S2 / S2'), for each die region 10a, the projections of the manufactured vias 116 on the wafer substrate 10 avoid and surround the peripheral circuit area.

[0145] In a modified embodiment of the present invention, some vias can be located in the peripheral circuit area. This technical solution makes the peripheral circuit layout design more flexible and is also conducive to improving the transmission rate of the circuit corresponding to these vias.

[0146] In another embodiment, in the above-described method for preparing a silicon-based liquid crystal panel, in step S1 or S2', the active circuit 12 includes multiple metal layers, and the multiple metal layers include multiple input / output terminals 13 located at different positions. Each via 116 is vertically connected to a different input / output terminal 13 of the metal layer, thereby realizing electrical connection with the pixel circuit area and / or the peripheral circuit area.

[0147] like Figure 13 As shown, the wafer substrate 10 also includes a plurality of conductive pads 17 spaced apart on the first surface. The conductive pads 17 are electrically connected to the active circuit 12. For at least a portion of the vias 116, there is a corresponding conductive pad 17 that is electrically connected. In terms of the manufacturing process, when providing the wafer substrate 10 in step S1 or when manufacturing the integrated circuit in step S2', a plurality of conductive pads 17 spaced apart on the first surface 112 are obtained in each die region 10a. The conductive pads 17 are electrically connected to the active circuit 12, and the conductive pads 17 can be used to test the active circuit 12 before / during the liquid crystal packaging step. This technical solution is advantageous for testing the wafer before / during liquid crystal packaging without damaging the conductive interface 14 (e.g., without needing to solder the conductive interface to the testing device), and the testing can be performed from the front side of the wafer (the first surface side), making the operation more convenient.

[0148] In some embodiments of the present invention, for each via 116, there is a unique conductive pad 17 electrically connected to it. Therefore, the circuits corresponding to each conductive interface 14 can be tested for proper operation by using the conductive pad 17 as an input / output interface.

[0149] In some embodiments, a separate conductive pad 17 is also included, such as Figure 13The conductive pad 17 shown on the right is electrically connected to the active circuit 12 on one side and electrically connected to the transparent conductive layer 44 of the glass substrate 40 through conductive adhesive 60 on the other side, thereby acting as a conductor to provide voltage to the transparent conductive layer 44.

[0150] In some embodiments of the present invention, for at least a portion of the vias 116, there is a corresponding and electrically connected conductive pad 17, and the projections of each conductive pad 17 and its corresponding via 116 on the wafer substrate 10 are staggered. This technical solution makes the physical connection between the conductive pad and the active circuit relatively independent of the physical connection between the via and the active circuit, making the circuit layout more flexible.

[0151] In another embodiment, the projections of each conductive pad 17 and its corresponding via 116 on the wafer substrate 10 overlap (e.g., Figure 13 (The conductive pad and via on the left side). This technical solution reduces the number of input / output terminals 13 that need to be set on the metal layer, so that the conductive pad 17 and via 116 can be connected to the same input / output terminal 13 at the same time, which helps to reduce the overall size of the silicon-based liquid crystal panel 110.

[0152] In this invention, the conductive interface 14 includes at least one of a ball grid array (BGA), a pin grid array (PGA), and a land grid array (LGA). This type of packaging structure allows the silicon-based liquid crystal panel 110 to be connected to an external circuit board in the vertical direction.

[0153] Since the BGA mounting method involves a heating process, which may damage the liquid crystal, it is preferable to use PGA or LGA connection methods.

[0154] From the perspective of the mounting temperature of the silicon-based liquid crystal panel 110, the manufacturing method of the present invention preferably adopts a lower-temperature mounting method. In one embodiment of the present invention, the conductive interface 14 is electrically connected to the external circuit board by mechanical pressing or mechanical coupling. Furthermore, the silicon-based liquid crystal panel and the external circuit board can be further fixed by clips, improving the reliability of the mechanical pressing or mechanical coupling connection.

[0155] like Figure 15 As shown, multiple conductive interfaces 14 are arranged in an array on the second surface 114 of the silicon substrate 11. Through-silicon vias (TSVs) are used to create holes in the silicon substrate 11, allowing the active circuitry 12 to be guided from the first surface 112 of the silicon substrate 11 to the second surface 114. The conductive interfaces 14 are provided on the second surface 114 of the silicon substrate 11, thereby enabling electrical connection between the conductive interfaces 14 and the external circuit board 120.

[0156] Reference Figure 14 and Figure 15 At least some of the conductive interfaces 14 are projected onto the wafer substrate 10 closer to the center of the silicon-based liquid crystal panel 110 than the projection of the vias 116 corresponding to the conductive interfaces 14 onto the wafer substrate. By connecting the vias and conductive interfaces using circuits on the second surface of the wafer substrate, some conductive interfaces can be distributed in the pixel circuit area of ​​the corresponding die, avoiding excessive crowding of conductive interfaces at the edges. At the same time, the size of the conductive interfaces can be increased, resulting in higher transmission efficiency. Figure 15 In the embodiment shown, the conductive interfaces 14 are arranged in a uniform array on the second surface 114. It can be understood that the present invention does not limit the specific arrangement of the conductive interfaces 14 on the second surface, and it can also be a non-uniform arrangement. Examples will not be given here.

[0157] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for preparing a silicon-based liquid crystal panel, comprising the following steps: A wafer substrate is provided, the wafer substrate including a silicon substrate having opposing first and second surfaces, the wafer substrate being divided into multiple die regions by intersecting multiple dividing lines, each die region including an active circuit disposed on the first surface, the active circuit including at least a pixel circuit region and a peripheral circuit region. In wafer-level packaging, on the wafer substrate, in each die region, a plurality of vias are formed that penetrate the first surface and the second surface, and a plurality of conductive interfaces are formed on the second surface. The conductive interfaces correspond one-to-one with the vias, and each conductive interface is electrically connected to the active circuit of the die region in which it is located through its corresponding via. In a liquid crystal package, on the wafer substrate, in each of the die regions, a frame adhesive is formed on one side of the first surface, such that the frame adhesive at least surrounds the pixel circuit region of the active circuit, and the frame adhesive defines the liquid crystal space of the die region in which it is located; liquid crystal is injected into each of the liquid crystal spaces on the wafer substrate. A glass substrate with a transparent conductive layer on its surface is provided, and the surface of the glass substrate with the transparent conductive layer is bonded to the wafer substrate by the frame adhesive; The wafer substrate is cut along the dividing line, and the glass substrate is cut accordingly to obtain a plurality of silicon-based liquid crystal panels; the silicon-based liquid crystal panels can be electrically connected to an external circuit board to obtain a silicon-based liquid crystal module, wherein the active circuit is electrically connected to the external circuit board in sequence through the plurality of vias and the plurality of conductive interfaces. In the wafer-level packaging step, for each die region, the projections of the plurality of vias manufactured on the wafer substrate are arranged to avoid and surround the pixel circuit region.

2. A method for preparing a silicon-based liquid crystal panel, comprising the following steps: A wafer substrate is provided, the wafer substrate including a silicon substrate having opposing first and second surfaces, the wafer substrate being divided into multiple die regions by intersecting multiple dividing lines; In wafer-level packaging, multiple vias penetrating the first surface and the second surface are fabricated in each die region on the wafer substrate. Then, active circuits disposed on the first surface are fabricated in each die region. The active circuits include at least a pixel circuit region and a peripheral circuit region. Then, multiple conductive interfaces are fabricated on the second surface. The conductive interfaces correspond one-to-one with the vias. The active circuits are electrically connected to the multiple conductive interfaces through the multiple vias. In a liquid crystal package, on the wafer substrate, in each of the die regions, a frame adhesive is formed on one side of the first surface, such that the frame adhesive at least surrounds the pixel circuit region of the active circuit, and the frame adhesive defines the liquid crystal space of the die region in which it is located; liquid crystal is injected into each of the liquid crystal spaces on the wafer substrate. A glass substrate with a transparent conductive layer on its surface is provided, and the surface of the glass substrate with the transparent conductive layer is bonded to the wafer substrate by the frame adhesive; The wafer substrate is cut along the dividing line, and the glass substrate is cut accordingly to obtain a plurality of silicon-based liquid crystal panels; the silicon-based liquid crystal panels can be electrically connected to an external circuit board to obtain a silicon-based liquid crystal module, wherein the active circuit is electrically connected to the external circuit board in sequence through the plurality of vias and the plurality of conductive interfaces. In the wafer-level packaging step, for each die region, the projections of the plurality of vias manufactured on the wafer substrate are arranged to avoid and surround the pixel circuit region.

3. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, The thickness of the silicon substrate ranges from 60 μm to 750 μm, and the thickness of the glass substrate ranges from 60 μm to 750 μm.

4. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, In the wafer-level packaging step, for each die region, the projections of the plurality of vias manufactured on the wafer substrate are arranged to avoid and surround the peripheral circuit area.

5. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, The active circuit includes multiple metal layers, each metal layer including multiple input / output terminals located at different positions. Each via is perpendicularly connected to a different input / output terminal of the metal layer, thereby achieving electrical connection with the pixel circuit area and / or the peripheral circuit area.

6. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, Each of the die regions also includes a plurality of conductive pads spaced apart on the first surface. The conductive pads are electrically connected to the active circuit and can be used to test the active circuit before / during the liquid crystal packaging step.

7. The method for preparing a silicon-based liquid crystal panel as described in claim 6, characterized in that, In each of the die regions, for at least a portion of the via, there is a corresponding and electrically connected conductive pad, and the projections of each conductive pad and its corresponding via on the wafer substrate are offset from each other.

8. The method for preparing a silicon-based liquid crystal panel as described in claim 6, characterized in that, In the liquid crystal encapsulation step, the sealant does not cover the conductive pad.

9. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, The conductive interface includes at least one of a ball grid array packaging structure, a pin grid array structure, and a grid array packaging structure.

10. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, The conductive interface is electrically connected to the external circuit board through mechanical pressing or mechanical coupling.

11. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, At least a portion of the projection of the conductive interface on the wafer substrate is closer to the center of the silicon-based liquid crystal panel than the projection of the via corresponding to the conductive interface on the wafer substrate.

12. A silicon-based liquid crystal panel, characterized in that, include: A wafer substrate includes a silicon substrate having opposing first and second surfaces, an active circuit on the first surface, a plurality of conductive interfaces on the second surface, and a plurality of vias penetrating the first and second surfaces. Each conductive interface corresponds to one of the vias, and each conductive interface is electrically connected to the active circuit through its corresponding via. The active circuit includes at least a pixel circuit region and a peripheral circuit region. The projections of the plurality of vias on the wafer substrate avoid and surround the pixel circuit region. A glass substrate with a transparent conductive layer on its surface is disposed opposite to the wafer substrate; A frame adhesive is located between the wafer substrate and the glass substrate, and the frame adhesive at least surrounds the pixel circuit area of ​​the active circuit and defines a liquid crystal space; as well as Liquid crystal, located within the liquid crystal space; The silicon-based liquid crystal panel can be electrically connected to an external circuit board through the conductive interface.

13. The silicon-based liquid crystal panel as described in claim 12, characterized in that, The projections of the plurality of vias on the wafer substrate avoid and surround the peripheral circuit area.

14. The silicon-based liquid crystal panel as described in claim 12 or 13, characterized in that, The active circuit includes multiple metal layers, each metal layer including multiple input / output terminals located at different positions. Each via is perpendicularly connected to a different input / output terminal of the metal layer, thereby achieving electrical connection with the pixel circuit area and / or the peripheral circuit area.

15. The silicon-based liquid crystal panel as described in claim 12 or 13, characterized in that, The wafer substrate further includes a plurality of conductive pads spaced apart on the first surface. The conductive pads are electrically connected to the active circuit. For at least some vias, there is a corresponding conductive pad that is electrically connected to it.

16. The silicon-based liquid crystal panel as described in claim 12 or 13, characterized in that, The conductive interface includes at least one of a ball grid array packaging structure, a pin grid array structure, and a grid array packaging structure.

17. The silicon-based liquid crystal panel as described in claim 12 or 13, characterized in that, The conductive interface is electrically connected to the external circuit board through mechanical pressing or mechanical coupling.

18. The silicon-based liquid crystal panel as described in claim 12 or 13, characterized in that, At least a portion of the projection of the conductive interface on the wafer substrate is closer to the center of the silicon-based liquid crystal panel than the projection of the via corresponding to the conductive interface on the wafer substrate.

19. The silicon-based liquid crystal panel as described in claim 12 or 13, characterized in that, The thickness of the silicon substrate ranges from 60 μm to 750 μm, and the thickness of the glass substrate ranges from 60 μm to 750 μm.

20. The silicon-based liquid crystal panel as described in claim 19, characterized in that, The thickness of the silicon substrate ranges from 60 μm to 200 μm.

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