Methods, electronic devices, computer-readable storage media for mapping

Abstract

The present disclosure provides a mapping method, which comprises: dividing at least one cut group in a to-be-mapped computation graph; each operator of the computation graph corresponds to a polyhedron, each cut group comprises a plurality of operators in the computation graph, and the polyhedrons corresponding to all operators in each cut group are located in a same cut space; cutting each cut group; mapping the computation graph after cutting the cut groups; the cutting of each cut group comprises: performing linear transformation on the polyhedrons corresponding to at least part of the operators in the cut group according to a transformation algorithm; cutting each polyhedron in the cut group into k+1 sub-polyhedrons along k hyperplanes in the cut space of the cut group, k being an integer greater than or equal to 1; each sub-polyhedron corresponds to an operator, a plurality of sub-polyhedrons in a same relative position relative to the hyperplanes belong to a fusion group, and sub-polyhedrons in different relative positions relative to the hyperplanes belong to different fusion groups, and the operators corresponding to k+1 fusion groups of each cut group are respectively mapped to k+1 processing units in the mapping. The present disclosure also provides an electronic device and a computer readable storage medium.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computation graph mapping, and particularly relates to a mapping method, an electronic device, and a computer readable storage medium. BACKGROUND

[0002] An overall operation (such as a neural network, which is used to implement a certain function, such as speech recognition, image processing, etc.) to be performed can be represented in the form of a computation graph; the computation graph includes a plurality of operators (or nodes), each of which is a partial operation in the overall operation; and data transmission can be performed between different operators, such as a calculation result of one operator can be input to another operator as its input.

[0003] To improve efficiency, a plurality of processing units (such as processing cores) can be used to process the overall operation together. For example, according to the computation graph, each operator of the computation graph can be mapped (or assigned) to a plurality of processing units, and each processing unit processes part of the operators. SUMMARY

[0004] The present disclosure provides a mapping method, an electronic device, and a computer readable storage medium.

[0005] In a first aspect, the embodiments of the present disclosure provide a mapping method, which includes:

[0006] At least one cut group is divided in a computation graph to be mapped; the computation graph includes a plurality of operators, each of which corresponds to a polyhedron, and each cut group includes a plurality of operators in the computation graph, and each polyhedron corresponding to all operators in the same cut group is located in the same cut space;

[0007] Each cut group is cut;

[0008] The computation graph after the cut of the cut group is mapped;

[0009] The cutting of each cut group includes:

[0010] According to a transformation algorithm, a linear transformation is performed on the polyhedrons corresponding to at least part of the operators in the cut group;

[0011] Each polyhedron in the cut group is cut into k+1 sub-polyhedrons along k hyperplanes in the cut space of the cut group, k is an integer greater than or equal to 1; each sub-polyhedron corresponds to an operator, a plurality of sub-polyhedrons in the same relative position relative to each hyperplane belong to a fusion group, and sub-polyhedrons in different relative positions relative to each hyperplane belong to different fusion groups, and the operators corresponding to the k+1 fusion groups of the same cut group are respectively mapped to k+1 processing units in the mapping.

[0012] In some embodiments, the hyperplane is parallel to at least one dimension of the partition space.

[0013] In some embodiments, after the k hyperplanes in the segmentation space of the segmentation group divide each polyhedron into k+1 sub-polyhedra, the method further includes:

[0014] If the mapping condition is not met, change the transformation algorithm and return to the step of performing a linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm.

[0015] In some embodiments, the change transformation algorithm includes:

[0016] The transformation algorithm is modified in a way that reduces the amount of data transmitted between groups; the amount of data transmitted between groups is the total amount of data that needs to be transmitted between the operators of any two fusion groups of the segmentation group when the computation graph is running.

[0017] In some embodiments, the change of the transformation algorithm in a manner that reduces inter-group data transmission volume includes:

[0018] The gradient descent algorithm is used to reduce the amount of data transmitted between groups.

[0019] In some embodiments, the mapping conditions include at least one of the following:

[0020] The inter-group data transmission volume is less than a predetermined threshold; the inter-group data transmission volume is the total amount of data that needs to be transmitted between the operators of any two fusion groups of the segmentation group when the computation graph is running.

[0021] The inter-group data transmission volume converged;

[0022] The process of returning to the step of performing linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm reaches a predetermined number of times.

[0023] In some embodiments, performing a linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm includes:

[0024] Through formula P′ i =P i T A i For the polyhedron P corresponding to the i-th operator in the segmentation group i Perform a linear transformation; where P′ i Let T denote the polyhedron obtained after the transformation, and A denote the transpose. i Indicates the use of P i The transformation matrix is ​​an n*n dimensional matrix for performing the transformation, where n represents the dimension of the segmentation space of the segmentation group, and n is an integer greater than or equal to 2.

[0025] In some embodiments, performing a linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm includes:

[0026] Through formula P′ i =P i T A i +B i For the polyhedron P corresponding to the i-th operator in the segmentation group i Perform a linear transformation; where P′ i Let T denote the polyhedron obtained after the transformation, and A denote the transpose. i Indicates the use of P i The transformation matrix B is an n*n dimensional matrix used for the transformation. i Indicates the use of P i The transformation vector is an n-dimensional vector, where n represents the dimension of the partition space of the partition group, and n is an integer greater than or equal to 2.

[0027] Secondly, this disclosure provides an electronic device comprising:

[0028] At least one processor;

[0029] A memory that is communicatively connected to the at least one processor;

[0030] The memory stores one or more computer programs that can be executed by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the mapping method described above.

[0031] Thirdly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described mapping method.

[0032] In this embodiment of the disclosure, by performing a linear transformation on the polyhedron corresponding to some operators to divide it into sub-polyhedrons, it is equivalent to splitting each operator in each segmentation group, and the newly split operators are located in different fusion groups. Then, by mapping the operators from multiple (e.g., two) fusion groups from one segmentation group to multiple (e.g., two) processing units respectively, the mapping of the computation graph can be realized. The above process is simple to operate, and it can ensure that after splitting and mapping (fusion) the operators according to the process, the amount of data that needs to be transferred between different processing cores is small, thereby improving the running efficiency. Attached Figure Description

[0033] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and are used to explain the principles of the present disclosure, and are not intended to limit the present disclosure. The above and other features and advantages of the present disclosure will become more apparent from the detailed description in conjunction with the accompanying drawings, in which:

[0034] Figure 1 A schematic diagram of a process for splitting and mapping operators in a graph;

[0035] Figure 2 A flowchart of a mapping method provided by an embodiment of the present disclosure;

[0036] Figure 3 A schematic diagram of polyhedrons corresponding to some operators;

[0037] Figure 4 A schematic diagram of polyhedrons corresponding to some other operators;

[0038] Figure 5 A schematic diagram of a process for splitting polyhedrons of a split group in a mapping method provided by an embodiment of the present disclosure;

[0039] Figure 6 A schematic diagram of a process for splitting polyhedrons of a split group in another mapping method provided by an embodiment of the present disclosure;

[0040] Figure 7 A flowchart of another mapping method provided by an embodiment of the present disclosure;

[0041] Figure 8 A block diagram of an electronic device provided by an embodiment of the present disclosure;

[0042] Figure 9 A block diagram of a computer readable storage medium provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the mapping method, the electronic device and the computer readable storage medium provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

[0044] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0045] The present disclosure can be described with reference to plan views and / or cross-sectional views by idealized illustrations of the described embodiments. Thus, the example illustrations can not reflect the specific layout of the actual devices. Details of the device structures can be schematically depicted in order not to obscure the disclosure.

[0046] Embodiments of the present disclosure and respective features in embodiments can be combined, if not in conflict.

[0047] The terminology used by the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein the terms "comprises," "comprising," "consisting of," and "consists of" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0049] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of configurations formed based on manufacturing processes. Therefore, the regions exemplified in the drawings have a schematic property, and the shape of the regions shown in the drawings exemplifies a specific shape of a region of an element, but is not intended to be restrictive.

[0050] An overall operation (e.g., a neural network for implementing a certain function such as speech recognition, image processing, etc.) to be performed can be expressed in the form of a computational graph including a plurality of operators (or nodes). To improve efficiency, a plurality of processing units (e.g., processing cores) can be used to process the overall operation together.

[0051] With reference to Figure 1 In some related art, based on capacity limitations of processing units and the like, it can be necessary to "split" some of the operators in the computational graph, i.e., to divide one operator into a plurality of new operators, and then map the split computational graph. Of course, at this time, a processing unit can be mapped with new operators split from a plurality of different old operators (equivalent to fusion of new operators).

[0052] However, the operator splitting manner in the related art is unreasonable, resulting in a large amount of data to be transmitted between the split new operators, so that after the new operators are mapped to different processing units (if the multiple new operators split from one operator are mapped to one processing unit, it is actually equal to unnecessary splitting), a large amount of data transmission needs to be performed between different processing units, reducing the running efficiency.

[0053] In a first aspect, the embodiments of the present disclosure provide a mapping method.

[0054] With reference to Figure 1 The method of the embodiments of the present disclosure is used to split part of the operators (or nodes) in the to-be-mapped computation graph (the overall operation to be performed, such as a neural network, which is used to implement a certain function, such as speech recognition, image processing, etc.), and then map (or assign) the operators (including old operators and split new operators) in the computation graph to the processing units of the processing device.

[0055] For example, the processing device can be a many-core system, and the processing unit can be a processing core in the many-core system. The many-core system includes multiple processing cores, each processing core has a certain data processing capability, and data transmission can be achieved between the processing cores and between the processing cores and the outside of the many-core system through an on-chip network; by mapping part of the operators of the computation graph in each processing core, the overall operation can be processed by the many-core system (i.e., multiple processing cores), improving the running efficiency.

[0056] With reference to Figure 2 The mapping method of the embodiments of the present disclosure includes:

[0057] S101, dividing at least one cut group in the to-be-mapped computation graph.

[0058] The computation graph includes multiple operators, each operator corresponds to a polyhedron, and each cut group includes multiple operators in the computation graph, and each polyhedron corresponding to all operators in the same cut group is located in the same cut space.

[0059] The to-be-mapped computation graph is an initial computation graph obtained according to the overall operation to be performed (such as a neural network) in a certain manner, for example, each neuron in the neural network can be used as an operator (or node) in the computation graph, and the operators are connected according to the connection relationship of the neurons to generate the computation graph. The specific manner of obtaining the to-be-mapped computation graph is not limited here.

[0060] As before, the essence of each operator is a certain "operation", and according to the "polyhedron compilation technology", with reference to Figures 3 to 6 Each operation can be represented as a polyhedron in an n (n is an integer greater than or equal to 2) dimensional space (i.e., "cut space").

[0061] For example, if there are two operators, Operator A and Operator B, their corresponding codes (program codes) are as follows (where For table loop, the same below) :

[0062] Operator A:

[0063] for i:1 to 4

[0064] for j:1 to 6

[0065] a[i][j] = 1;

[0066] Operator B:

[0067] for i:1 to 6

[0068] for j:1 to 4

[0069] b[i][j] = a[j][i];

[0070] According to Figure 3 , Operator A and Operator B can be converted into polyhedrons in the same 2-dimensional space (i.e., n = 2, two dimensions are i and j respectively).

[0071] It should be understood that according to Figure 3 , since it is a 2-dimensional space, the "polyhedron" therein is also 2-dimensional, that is, the polyhedrons corresponding to Operator A and Operator B are actually "rectangles" (rectangles can also be regarded as a special polyhedron in mathematics).

[0072] It should be understood that according to the 2-dimensional space of Figure 3 , the polyhedrons corresponding to Operator A and Operator B should actually be "partially overlapped", but in order to clearly show in the figure, they are represented separately in Figure 3 .

[0073] Wherein, if the values of i and j in Operator A and Operator B are limited to integers, the polyhedrons corresponding to them can refer to the form of Figure 4 .

[0074] It should be understood that although Operator A and Operator B correspond to some discontinuous points at this time, they can still be understood as polyhedrons and are applicable to the method of the embodiments of the present disclosure.

[0075] In the embodiments of the present disclosure, one or more cut groups are first drawn in the computation graph, each cut group has a plurality of operators, and the polyhedrons of these operators are located in the same cut space.

[0076] It should be understood that "same split space" refers to the same number of dimensions (n) and the specific meaning of each dimension. For example, the 2-dimensional space generated based on the i-dimension and the j-dimension is different from the 2-dimensional space generated based on the h-dimension and the k-dimension.

[0077] In the embodiments of the present disclosure, in a split group, each operator can be connected with at least one other operator (i.e., data transmission is required between the two), that is, all operators included in each split group should be "continuously distributed" or "associated" in the calculation graph (of course, it still needs to meet the condition that all operators are located in the same split space).

[0078] It should be understood that the embodiments of the present disclosure only require that all operators in a split group are located in the same split space, but do not require that all operators located in the same split space in the calculation graph must be divided into a split group. For example, only part of the operators can be selected for splitting, and the above "grouping" is only performed on these operators that need to be split.

[0079] S102, splitting each split group.

[0080] After obtaining the split groups, the split groups are respectively subjected to "splitting operation".

[0081] The splitting operation (S102) of any split group specifically includes:

[0082] S1021, performing linear transformation on the polyhedron corresponding to at least part of the operators in the split group according to a transformation algorithm.

[0083] Any operation can be subjected to "linear transformation". Since the operators are corresponding to the polyhedrons, linear transformation is performed on an operator (operation), which is equivalent to linear transformation on the polyhedron corresponding to the operator in the n-dimensional space to obtain a new polyhedron after transformation. Of course, since it is linear transformation, the new polyhedron is still located in the n-dimensional space, but its specific shape, position, orientation, etc. can change.

[0084] When performing the splitting operation on any split group, referring to Figure 5 , Figure 6 , the polyhedrons of at least part of the operators in the split group are subjected to linear transformation, so as to change the shape, position, orientation, etc. of the polyhedrons corresponding to the operators (but still in the split space). Of course, referring to Figure 5 , Figure 6 , the polyhedrons of part of the operators in the split group can not be subjected to linear transformation.

[0085] S1022, splitting each polyhedron in the split group into k+1 sub-polyhedrons along the k hyperplanes in the split space of the split group.

[0086] wherein k is an integer greater than or equal to 1; each sub-polytope corresponds to an operator, and multiple sub-polytopes in the same relative position with respect to each hyperplane belong to a fusion group, and sub-polytopes in different relative positions with respect to each hyperplane belong to different fusion groups.

[0087] Referring to Figure 5 , Figure 6 After linear transformation of at least part of the polytopes of the operators, k hyperplanes are set in the cutting space (k is an integer greater than or equal to 1), Figure 5 , Figure 6 Each polytope in the cutting space (at least part of which is a linearly transformed polytope) is cut into k+1 parts (k is an integer greater than or equal to 1) by the k hyperplanes. Figure 5 , Figure 6 For example, in the case of cutting into "two halves", i.e., into two sub-polytopes.

[0088] wherein multiple sub-polytopes in the same relative position with respect to each hyperplane are divided into a "fusion group", for example, all sub-polytopes between two specific hyperplanes belong to one fusion group, and multiple sub-polytopes outside the two outermost hyperplanes belong to two fusion groups, respectively.

[0089] For example, when there are multiple hyperplanes, different hyperplanes can be parallel to each other.

[0090] For example, when k is equal to 2, each polytope is cut into two sub-polytopes by one hyperplane, and all sub-polytopes on the same side of the hyperplane are counted as one "fusion group", and sub-polytopes on both sides of the hyperplane belong to different "fusion groups". Figure 5 , Figure 6 For example, referring to the sub-polytopes on the upper and lower sides of the hyperplane in

[0091] wherein each operator corresponds to one polytope, so each polytope also corresponds to one operator, i.e., when a polytope of an operator is cut into two (or more) sub-polytopes, the two (or more) sub-polytopes also correspond to two (or more) "new operators", respectively, so that the "cutting" of the polytope is equivalent to the "splitting" of the corresponding operator.

[0092] That is, by cutting the polytopes in the cutting group, each operator in the cutting group is split into two (or more) "new operators"; and the multiple new operators cut by each cutting group belong to two (or more) "fusion groups", respectively, and each fusion group has multiple new operators.

[0093] A hyperplane in a space is a plane of dimension one less than the dimension of the space. For example, in a 2-dimensional space, a hyperplane is a "line", and in a 3-dimensional space, a hyperplane is a "plane" in the usual sense. Figure 5 In a 2-dimensional space, a hyperplane is a "line", and in a 3-dimensional space, a hyperplane is a "plane" in the usual sense. Figure 5 In a 3-dimensional space, a hyperplane is a "plane" in the usual sense.

[0094] S103, mapping the computation graph after the cutting of the cutting group.

[0095] In the mapping, the operators of the k+1 fusion groups corresponding to the same cutting group are respectively mapped to the k+1 processing units.

[0096] As described above, the cutting of each cutting group is equivalent to the splitting of the operators therein, and thus a new computation graph including new operators is obtained, and the new computation graph can be mapped. That is, the operators in the new computation graph (at least part of which are new operators) are respectively mapped to the processing units (such as processing cores), and the operators (sub-polyhedrons) of the same fusion group are mapped to the same processing core.

[0097] In the mapping of the new computation graph, it should also be ensured that all operators (which are all new operators) in any fusion group obtained by cutting one cutting group are mapped to the same processing unit (such as a processing core), and the operators in the multiple fusion groups split from one cutting group are respectively mapped to multiple different processing units (which is equivalent to "fusion" of the new operators in the same processing unit).

[0098] In the embodiments of the present disclosure, the sub-polyhedrons are cut by linearly transforming the polyhedrons corresponding to part of the operators, which is equivalent to splitting the operators in each cutting group, and the new operators are in different fusion groups. By respectively mapping the operators of multiple (such as two) fusion groups from one cutting group to multiple (such as two) processing units, the mapping of the computation graph can be realized. The above process is simple in operation and can ensure that the amount of data to be transmitted between different processing cores is small after the splitting and mapping (fusion) of the operators according to the process, thereby improving the running efficiency.

[0099] For the same operator, the amount of data to be transmitted between the new operators obtained after splitting in different ways can be different.

[0100] For example, the above operator A can be split into operator A1 and operator A2 with the following code, and the above operator B can be split into operator B1 and operator B2 with the following code:

[0101] Operator A1:

[0102] for i:1to 2

[0103] for j:1to 6

[0104] a[i][j] = 1;

[0105] Operator A2:

[0106] for i:3to 4

[0107] for j:1to 6

[0108] a[i][j] = 1;

[0109] Operator B1:

[0110] for i:1 to 3

[0111] for j:1to 4

[0112] b[i][j] = a[j][i];

[0113] Operator B2:

[0114] for i:4to 6

[0115] for j:1to 4

[0116] b[i][j] = a[j][i].

[0117] After mapping operators A1 and B1 to one processing unit and operators A2 and B2 to another processing unit, since operator B1 needs the calculation result of operator A2 and operator B2 needs the calculation result of operator A1, it can be known that the number of data copies that need to be transmitted unidirectionally between the two processing units is 6.

[0118] And reference Figure 5 If the method of this disclosure embodiment is followed, first the polyhedron of operator B ( Figure 5 Linear transformation is performed on a rectangle (specifically, a rectangle). Figure 5 Specifically, rotation), then using a hyperplane ( Figure 5 Specifically, the polyhedrons of operator A and operator B (using a straight line) are divided into four sub-polyhedra. The codes for operators A1 and A2 remain unchanged, while the codes for operators B1' and B2' are as follows:

[0119] Operator B1':

[0120] for i:1 to 6

[0121] for j:1to 2

[0122] b[i][j] = a[j][i];

[0123] Operator B2':

[0124] for i:1 to 6

[0125] for j:3to 4

[0126] b[i][j] = a[j][i].

[0127] Therefore, after mapping A1 and operator B1' to one processing unit (i.e., one fusion group), and mapping operator A2 and operator B2' to another processing unit (i.e., another fusion group), it can be seen that there is no longer any need for data transmission between the two processing units, thereby reducing the amount of data transmission.

[0128] It should be understood, with reference Figure 5 In two-dimensional space, the polyhedra corresponding to operators A and B, and the subpolyhedra obtained by their decomposition, should actually be "partially coincident," but for clarity, therefore... Figure 5 They are represented separately in the text.

[0129] In some embodiments, performing a linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm (S1021) includes:

[0130] S10211, using formula P′ i =P i T A i For the polyhedron P corresponding to the i-th operator in the cutting group i Perform a linear transformation.

[0131] Among them, P′ i Let T denote the polyhedron obtained after the transformation, and A denote the transpose. i Indicates the use of P i The transformation matrix is ​​an n*n dimensional matrix for performing the transformation, where n represents the dimension of the partition space of the partition group, and n is an integer greater than or equal to 2.

[0132] As one embodiment of this disclosure, a preset transformation matrix A can be used. i For the polyhedron P of operator i i Perform a linear transformation (where transpose is used to maintain dimensional consistency during the linear transformation) to achieve the transformation of polyhedron P. i Linear transformations (such as rotations).

[0133] In some embodiments, performing a linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm (S1021) includes:

[0134] S10212, by formula P' i = P i T A i +B i The polyhedron P i corresponding to the i-th operator in the split group is linearly transformed.

[0135] Wherein, P' i represents the polyhedron obtained after transformation, T represents transposition, A i represents an n*n dimensional transformation matrix used for transforming P i , B i represents an n dimensional transformation vector used for transforming P i , and n represents the dimension number of the split space of the split group, n being an integer greater than or equal to 2.

[0136] As another way of the embodiment of the present disclosure, in addition to transforming the polyhedron P i using the transformation matrix A i , it can also be added with the transformation vector B i , so as to realize the "movement" of the polyhedron.

[0137] Wherein, it should be understood that one polyhedron P i is actually composed of a plurality of (including infinite) "points (P 1 , P i 2 …P i m )" (m is the number of points), or a polyhedron P i is a specific expression; and linearly transforming one polyhedron P i is equivalent to linearly transforming each point therein (or linearly transforming the expression thereof), that is, the linear transformation of the polyhedron P i is equivalent to transforming each point in the polyhedron P i jT = P i jT A i or P i jT = P i jT A i +B i linearly transform each point (j = 1, 2, …, m) therein.

[0138] Specifically, the plurality of polyhedrons in one split group can be represented as the following set {P1, P2, …, P i,…}, so when linear transformation is performed, the corresponding transformation matrix A and transformation vector B can be set for each polyhedron, i.e. the sets {A1, A2, …, A i ,…} and {B1, B2, …, B i ,…} are obtained respectively, and the two sets are used to perform linear transformation on each polyhedron respectively.

[0139] Of course, it should be understood that if a polyhedron P does not need to be transformed in a certain aspect, its corresponding transformation matrix A and / or transformation vector B can be values that do not actually cause the polyhedron to change.

[0140] In some embodiments, the hyperplane is parallel to at least one dimension direction of the partitioned space.

[0141] Referring to Figure 8 , the hyperplane for partitioning can be "parallel to at least one dimension of the corresponding partitioned space (e.g. Figure 9 parallel to the j-th dimension)" to simplify the operator obtained by partitioning.

[0142] Of course, the hyperplane used can also be in other forms.

[0143] In some embodiments, in the process of partitioning each partition group, after each polyhedron in the k hyperplanes in the partitioned space of the partition group is partitioned into k+1 sub-polyhedra (S1022), the process further includes:

[0144] S1023, when the mapping condition is not met, changing the transformation algorithm, and returning to the step of performing linear transformation on the polyhedra corresponding to at least part of the operators in the partition group according to the transformation algorithm.

[0145] Due to the complexity of the operator and the polyhedron obtained therefrom, it is difficult to guarantee that after one linear transformation and partitioning, a sub-polyhedron (new algorithm) with performance meeting the requirements can be obtained.

[0146] Therefore, after each partitioning, a judgment can be made, and if the result of the current partitioning is unqualified, the transformation algorithm is reselected, i.e. a different linear conversion mode is reselected (such as reselecting the above sets {A1, A2, …, A i ,…} and / or {B1, B2, …, B i ,…} to perform linear conversion, and re-partitioning (i.e. loop processing).

[0147] It should be understood that if the mapping condition is met after a certain partitioning, the subsequent steps (such as S103) can be continued.

[0148] In some embodiments, changing the transformation algorithm (S1023) includes:

[0149] S10231, change the transformation algorithm in a manner that can reduce the inter-group data transmission amount.

[0150] The inter-group data transmission amount is the total data amount that needs to be transmitted between any two fused groups of the split group during the computation graph running.

[0151] As one of the manners of the embodiments of the present disclosure, when the transformation algorithm needs to be reselected, the selection can be performed in a manner that can "optimize" the original transformation algorithm, that is, gradually improve the performance of the selected transformation algorithm through "iterative loop".

[0152] The above "optimization" standard is that, relative to the old transformation algorithm, the newly selected transformation algorithm should tend to reduce the total data amount that needs to be transmitted between any two operators of the fused groups (inter-group data transmission amount) obtained by splitting, that is, reduce the data amount that should be transmitted between any two processing units after mapping (that is, the data amount that should be transmitted between different processing units).

[0153] The specific standard of "reducing the inter-group data transmission amount" can be diverse, for example, it can be required that the inter-group data transmission amount corresponding to any two fused groups is reduced, or the total amount of the inter-group data transmission amount corresponding to all fused groups is reduced, etc.

[0154] In some embodiments, changing the transformation algorithm in a manner that can reduce the inter-group data transmission amount includes changing the transformation algorithm in a direction that can reduce the inter-group data transmission amount through a gradient descent algorithm.

[0155] Further, the transformation algorithm can be optimized in a direction that can reduce the inter-group data transmission amount through a gradient descent algorithm, for example, the above sets {A1, A2, …, A i ,…} and / or {B1, B2, …, B i ,…} are processed through a gradient descent algorithm, and the more specific goal is to make the total f(p') after transformation small enough, that is, f(p'A i +B i ) for all points of all polyhedrons is small enough, where f is a loss function.

[0156] It should be understood that it is also feasible to select the transformation algorithm through other manners, for example, the transformation algorithm can be "randomly" selected each time until a required transformation algorithm is obtained.

[0157] It should be understood that the result of the splitting operation can also be changed through other manners, for example, different hyperplanes can also be reselected for splitting.

[0158] In some embodiments, the mapping condition includes at least one of the following:

[0159] The inter-group data transmission amount is less than a predetermined threshold.

[0160] The inter-group data transmission amount converges;

[0161] The process of returning to the step of performing linear transformation on the polyhedron corresponding to at least part of the operators in the split group according to the transformation algorithm reaches a predetermined number of times;

[0162] The inter-group data transmission amount is the total data transmission amount between the operators of any two fusion groups of the split group during the computation graph running.

[0163] Specifically, the conditions for ending the splitting process are various, for example, the inter-group data transmission amount after splitting can be less than a predetermined threshold (i.e., the splitting effect meets the requirements), or the inter-group data transmission amount converges in the loop (i.e., the splitting effect tends to the splitting effect), or the loop reaches a predetermined number of times, and the like, which will not be described in detail here.

[0164] The specific standard of "the inter-group data transmission amount is less than a predetermined threshold" can be various, for example, it can be required that the inter-group data transmission amount corresponding to any two fusion groups is less than a predetermined threshold, or the total amount of the inter-group data transmission amount corresponding to all fusion groups "combined" is less than a predetermined threshold, and the like.

[0165] In a second aspect, the present disclosure provides an electronic device.

[0166] With reference to ​ The electronic device 500 of the embodiment of the present disclosure includes:

[0167] at least one processor 501;

[0168] a memory 502 in communication connection with the at least one processor 501;

[0169] The memory 502 stores one or more computer programs that can be executed by the at least one processor 501, and the one or more computer programs are executed by the at least one processor 501 to enable the at least one processor 501 to perform the mapping method described above.

[0170] In a third aspect, the present disclosure provides a computer-readable storage medium.

[0171] With reference to ​ The computer-readable storage medium 600 of the embodiment of the present disclosure stores a computer program, and the computer program, when executed by a processor (including a processing core), implements the mapping method described above.

[0172] The computer-readable storage medium of the embodiment of the present disclosure can be a volatile or non-volatile computer-readable storage medium.

[0173] The embodiment of the present disclosure further provides a computer program product, comprising computer readable code or a nonvolatile computer readable storage medium carrying computer readable code, when the computer readable code is run in a processor of an electronic device, the processor in the electronic device performs the mapping method described above.

[0174] Those of ordinary skill in the art understand that all or some of the steps in the methods disclosed above, the functions of the modules / units in the systems and devices can be implemented as software, firmware, hardware and appropriate combinations thereof. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable storage medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0175] As known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital versatile disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. Furthermore, it is known to those of ordinary skill in the art that communication media typically includes computer readable program instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and can include any information delivery medium.

[0176] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0177] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computing / processing device, partly on the user's computing / processing device, as a stand-alone software package, partly on the user's computing / processing device and partly on a remote computing / processing device or entirely on the remote computing / processing device or server. In the latter scenario, the remote computing / processing device can be connected to the user's computing / processing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing / processing device, for example, through the Internet using an Internet Service Provider. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0178] The computer program product described herein can be embodied in a specific manner by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied in a specific manner as a computer storage medium, and in another optional embodiment, the computer program product is embodied in a specific manner as a software product, such as a software development kit (SDK), and the like.

[0179] The computer program product described herein can be embodied in a specific manner by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied in a specific manner as a computer storage medium, and in another optional embodiment, the computer program product is embodied in a specific manner as a software product, such as a software development kit (SDK), and the like.

[0180] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data storage cycles that change state. The instructions can be executed by one or more processors of a computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process such that the instructions which execute via the one or more processors of the computer or other programmable data processing devices create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0181] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0182] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical functions ("instructions"). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0183] Example embodiments have been disclosed and, although a specific terminology is employed, it is merely for the purpose of description and the terms should be interpreted as being illustrative only and in a generic sense, and not for the purpose of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics or aspects described in relation to a particular embodiment can be used alone or in combination with other embodiments, unless explicitly stated otherwise. Thus, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted for elements without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A mapping method, characterized in that, include: At least one partitioning group is divided in the computation graph to be mapped; the computation graph includes multiple operators, each operator corresponds to a polyhedron, each partitioning group includes multiple operators in the computation graph, and all polyhedra corresponding to all operators in the same partitioning group are located in the same partitioning space; wherein, the polyhedra being located in the same partitioning space means that the partitioning space corresponding to each polyhedron has the same number of dimensions and the same dimension meaning; Each of the aforementioned segments is then segmented; Map the computational graph after it has been segmented into groups; The step of segmenting each of the aforementioned groups includes: A linear transformation is performed on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm; Each polyhedron is divided into k+1 sub-polyhedra by k hyperplanes in the partition space of the partition group, where k is an integer greater than or equal to 1; each sub-polyhedron corresponds to an operator, multiple sub-polyhedra in the same relative position relative to each hyperplane belong to one fusion group, and sub-polyhedra in different relative positions relative to each hyperplane belong to different fusion groups. In the mapping, the operators corresponding to the k+1 fusion groups of the same partition group are mapped to k+1 processing units respectively. The step of performing a linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm is used to reduce the amount of inter-group data transmission in the fusion group obtained by segmenting the segmentation group.

2. The method according to claim 1, characterized in that, The hyperplane is parallel to at least one dimension of the partition space.

3. The method according to claim 1, characterized in that, In the process of dividing each of the division groups, after each polyhedron is divided into k+1 sub-polyhedra by k hyperplanes in the division space along the division group, the process further includes: If the mapping condition is not met, change the transformation algorithm and return to the step of performing a linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm.

4. The method according to claim 3, characterized in that, The change transformation algorithm includes: The transformation algorithm is modified in a way that reduces the amount of data transmitted between groups; the amount of data transmitted between groups is the total amount of data that needs to be transmitted between the operators of any two fusion groups of the segmentation group when the computation graph is running.

5. The method according to claim 4, characterized in that, The algorithm for changing to a method that reduces the amount of data transmitted between groups includes: The gradient descent algorithm is used to reduce the amount of data transmitted between groups.

6. The method according to claim 3, characterized in that, The mapping conditions include at least one of the following: The inter-group data transmission volume is less than a predetermined threshold; the inter-group data transmission volume is the total amount of data that needs to be transmitted between the operators of any two fusion groups of the segmentation group when the computation graph is running. The inter-group data transmission volume converged; The process of returning to the step of performing linear transformation on the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm reaches a predetermined number of times.

7. The method according to claim 1, characterized in that, The linear transformation of the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm includes: Through formula P i ′ =P i T A i For the polyhedron P corresponding to the i-th operator in the segmentation group i Perform a linear transformation; where P i ′ Let T denote the polyhedron obtained after the transformation, and A denote the transpose. i Indicates the use of P i The transformation matrix is ​​an n*n dimensional matrix for performing the transformation, where n represents the dimension of the segmentation space of the segmentation group, and n is an integer greater than or equal to 2.

8. The method according to claim 1, characterized in that, The linear transformation of the polyhedra corresponding to at least some of the operators in the segmentation group according to the transformation algorithm includes: Through formula P i ′ =P i T A i +B i For the polyhedron P corresponding to the i-th operator in the segmentation group i Perform a linear transformation; where P i ′ Let T denote the polyhedron obtained after the transformation, and A denote the transpose. i Indicates the use of P i The transformation matrix B is an n*n dimensional matrix used for the transformation. i Indicates the use of P i The transformation vector is an n-dimensional vector, where n represents the dimension of the partition space of the partition group, and n is an integer greater than or equal to 2.

9. An electronic device, characterized in that, include: At least one processor; A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the mapping method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the mapping method as described in any one of claims 1 to 8.

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