Method and Electronic Device for Dynamically Enhancing Memory Error Correction Capability

Abstract

A method for dynamically enhancing the memory error correction ability, the method comprising: obtaining and transmitting memory data to a pool controller; establishing a memory status table according to the memory data; determining a target area in a leaf switch that needs ECC enhancement, and calculating the size of the parity space required for the ECC enhancement; and selecting a target area corresponding to the size of the parity space to store the newly added parity data after the ECC enhancement. The present invention also provides an electronic device, which provides an ECC function for a memory without an ECC function, or dynamically enhances the ECC strength for a memory with insufficient ECC error detection strength.

Description

Technical Field

[0001] The present invention relates to a computer device, and in particular, to a method and an electronic device for dynamically enhancing the memory error correction ability. Background Art

[0002] A disaggregated memory appliance is managed by a pool controller for each memory switch. Each switch manages and users' various dual in-line memory modules (DIMMs) to form a memory pool, which can be used in a data center.

[0003] By means of additional parity data and error correcting code (ECC) algorithms, memory (volatile and non-volatile) can be made to have the ability to detect and correct errors. The strength of the correction ability is related to the algorithm adopted by ECC and the size of the parity size. In other words, ECC is a mechanism in memory to detect whether there are data errors. Through an algorithm, parity data can be generated, and then the correctness of the data can be verified by this parity data. Various ECC algorithms have different correction capabilities (ECC levels) for error bits. Generally speaking, the stronger the ability to correct error bits, the more error bits can be detected and repaired, and the more parity data required by the algorithm.

[0004] However, the disaggregated memory device contains various types of memories with different speeds. Some of the memories have ECC check functions, while some do not. Memories without ECC functions do not have data protection functions. Although memories with ECC functions have simple data protection functions, they may not necessarily meet the protection strength required for the current memory. Summary of the Invention

[0005] In view of the above, it is necessary to provide a method and an electronic device for dynamically enhancing the memory error correction ability, which provide ECC functions for memories without ECC functions, or dynamically increase the strength of ECC for memories with insufficient ECC error detection strength.

[0006] An embodiment of the present invention provides a method for dynamically enhancing the memory error correction ability, which is applied to an electronic device. The method includes: obtaining and transmitting memory data to a pool controller; establishing a memory status table according to the memory data; determining a target area in a leaf switch that needs to perform ECC enhancement, and calculating the size of the parity space required for the ECC enhancement; and selecting a target area corresponding to the size of the parity space to store the newly added parity data after the ECC enhancement.

[0007] An embodiment of the present invention further provides an electronic device, including: a leaf switch for obtaining memory data; and a pool controller for obtaining the memory data from the leaf switch and establishing a memory status table according to the memory data. The pool controller further includes: an ECC capability adjustment module for determining a target area in the leaf switch that needs to perform ECC enhancement, and calculating the size of the parity space required for the ECC enhancement; and a parity storage discrimination module for selecting a target area corresponding to the size of the parity space to store the newly added parity data after the ECC enhancement.

[0008] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed, the steps of the method for dynamically enhancing the memory error correction ability as described above are implemented.

[0009] The method and electronic device for dynamically enhancing the memory error correction ability according to the embodiments of the present invention provide ECC protection for memories without ECC functions, and dynamically adjust the increase and decrease of the ECC strength according to the error rate of each memory, so as to meet the requirements of the next-generation data center and enhance more powerful reliability, availability, and serviceability (RAS) services for the memory pool. Description of the Drawings

[0010] Figures 1A to 1E It is a flowchart of the steps of the method for dynamically enhancing the memory error correction ability according to the embodiments of the present invention.

[0011] Figure 2 It shows a schematic diagram of the hardware architecture of the electronic device according to the embodiments of the present invention.

[0012] Figure 3 It shows a functional block diagram of the electronic device according to the embodiments of the present invention.

[0013] Description of the Main Element Symbols

[0014] Electronic device 200 Processor 210 Memory 220 System with dynamically enhanced memory error correction capability 230 Pool controller 310 ECC capability adjustment module 311 Parity storage discrimination module 312 Leaf switch 320、330

[0015] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. Specific Embodiments

[0016] In order to more clearly understand the above objects, features, and advantages of the present invention, the present invention will be described in detail below with reference to the drawings and specific embodiments. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.

[0017] In the following description, many specific details are set forth in order to fully understand the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0019] It should be noted that the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the said features. In addition, the technical solutions between the various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions conflicts or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0020] The main features of the method for dynamically enhancing the memory error correction ability of the embodiments of the present invention are as follows:

[0021] (1) Obtain the size and response time of the parity data, and save the parity data to another memory area with a slower access speed and a larger remaining space; and

[0022] (2) Real-time statistically calculate the error rate of the memory, and dynamically adjust the strength of the error correcting code (ECC) according to the error rate. When the error rate of a memory increases and the ECC strength is dynamically increased, suspend the data writing to the memory, verify the data in the memory according to the previous ECC algorithm, then calculate new parity data according to the new ECC algorithm and save it, and delete the previous parity data.

[0023] Figures 1A to 1E It is a flowchart of the method steps for dynamically enhancing the memory error correction ability in an embodiment of the present invention, which is applied to an electronic device. According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.

[0024] Memory initial stage (Init Stage)

[0025] Reference Figure 1A , step S11, the memory leaf switch reads memory data, for example, the size of the dual in-line memory module (DIMM), the service life, etc.

[0026] Step S12, the memory leaf switch performs memory training and testing to obtain the ECC ability, bad part information, and response time of each DIMM.

[0027] Step S13, the memory leaf switch transfers the above relevant data to the pool controller.

[0028] Step S14, the pool controller establishes a memory status table as follows:

[0029]

[0030] Step S15, the ECC ability (Level) adjustment module first promotes the DIMMs without ECC protection, that is, determines which areas need to be ECC promoted and calculates the size of the parity space required after adjustment.

[0031] Step S16, the parity storage discrimination module selects the target area corresponding to the size of the parity space to store the newly added parity data after ECC promotion.

[0032] Memory write stage (Write Stage)

[0033] Reference Figure 1B , step S21, the host writes the memory data to the memory pool.

[0034] Step 22, the pool controller determines which leaf switch the memory data is to be stored in, for example, the first leaf switch.

[0035] Step S23, the first leaf switch receives the memory data and stores it in the corresponding space.

[0036] Step S24, the first leaf switch calculates the corresponding ECC parity according to the adjusted ECC, and transmits the ECC parity back to the pool controller.

[0037] Step S25, the parity storage discrimination module in the pool controller finds a suitable position and stores the ECC parity in the target leaf switch.

[0038] Memory read stage (Read Stage)

[0039] Reference Figure 1C , Step S31, the host requests to read a piece of data from the memory pool, and the pool controller notifies the relevant leaf switch.

[0040] Step S32, the leaf switch reads the data, and at the same time calculates the ECC parity corresponding to the data and transmits it back to the pool controller.

[0041] Step S33, the pool controller compares the ECC parity transmitted back by the leaf switch with the ECC parity read back from elsewhere during the write phase, and verifies the correctness of the data.

[0042] Step S34, if the comparison is correct, the pool controller transmits the correct data back to the host, otherwise it starts the ECC correction program and records it.

[0043] Selection of parity data storage location

[0044] Store it in the memory space with the lowest cost on the premise of not causing latency (Latency).

[0045] Reference Figure 1D , Step S41, because the size of the data is much larger than the size of the ECC parity, first calculate the time for the data to be transmitted from the DIMM to the pool controller. The formula is as follows:

[0046] Data_ResponseTime = (Data from DIMM to LeafSwitch + Time from LeafSwitchto Pool Controller).

[0047] Step S42, calculate the size of the parity required for the data and the response time of the parity. The formula is as follows:

[0048] Parity_Size = ECC_Algorithm(Data_Size); and

[0049] Parity_ResponseTime = (Byte Data from DIMM to Switch + Time from Leaf toPool Controller).

[0050] Step S43. To reduce the impact of the same-bit occupation of high-speed DIMMs on the overall performance, without causing additional latency, select a lower-cost memory space from the free memory space to store this data (store it in a memory area with slower speed and larger remaining capacity). A lower-cost memory space means that a memory area with slower speed and larger capacity is preferentially stored, so as to avoid system latency caused by a large number of same-bits occupying high-speed memory.

[0051] Error Monitor and Dynamic ECC Enhancement

[0052] Reference Figure 1E , Step S51. The pool controller monitors and statistics the error conditions of each memory and records them in a table.

[0053] Step S52. When a relatively high error occurs in a certain memory, determine to enhance the ECC strength.

[0054] Step S53. The ECC capability adjustment module calculates the required parity space for each memory after the enhancement.

[0055] Step S54. The pool controller notifies the leaf switch to enhance the ECC capability of this memory.

[0056] Step S55. Data writing to this memory is paused. The pool controller first uses the parity data to verify the correctness of the data in the memory.

[0057] Step S56. The leaf switch then calculates new parity data according to the new ECC capability algorithm and transmits it to the pool controller.

[0058] Step S57. The pool controller finds the destination to store the new parity data after enhancing the ECC according to the rules of the parity storage discrimination module. The new leaf switch receives the new parity data and stores it.

[0059] Step S58. The pool controller notifies the leaf switch storing the original parity data that the old parity area has become invalid and releases the space.

[0060] Step S59. The ECC capability enhancement step is completed, and the memory can read and write data again.

[0061] Figure 2 It shows a schematic diagram of the hardware architecture of the electronic device according to an embodiment of the present invention. The electronic device 200, for example, a server, but not limited to, can communicate with each other through a system bus to connect a processor 210, a memory 220, and a system 230 for dynamically enhancing the memory error correction capability. Figure 2Only the electronic device 200 with components 210 - 230 is shown, but it should be understood that it is not required to implement all the shown components, and more or fewer components can be alternatively implemented.

[0062] The memory 220 at least includes one type of readable storage medium, and the readable storage medium includes flash memory, hard disk, multimedia card, card - type memory (e.g., SD or DX memory, etc.), random access memory (RAM), static random access memory (SRAM), read - only memory (ROM), electrically erasable programmable read - only memory (EEPROM), programmable read - only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 220 can be an internal storage unit of the electronic device 10, such as the hard disk or memory of the electronic device 200. In other embodiments, the memory can also be an external storage device of the electronic device 200, such as a plug - in hard disk equipped on the electronic device 200, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. Of course, the memory 220 can also include both the internal storage unit of the electronic device 200 and its external storage devices. In this embodiment, the memory 220 is generally used to store the operating system installed on the electronic device 200 and various application software, such as the program code of the system 230 for dynamically enhancing memory error correction ability, etc. In addition, the memory 220 can also be used to temporarily store various data that have been output or will be output.

[0063] The processor 210 can be a Central Processing Unit (CPU), controller, microcontroller, microprocessor, or other data - processing chips in some embodiments. The processor 210 is generally used to control the overall operation of the electronic device 200. In this embodiment, the processor 210 is used to run the program code stored in the memory 220 or process data, for example, run the system 230 for dynamically enhancing memory error correction ability, etc.

[0064] It should be noted that Figure 2 This is only an example to illustrate the electronic device 200. In other embodiments, the electronic device 200 can also include more or fewer components, or have a different component configuration.

[0065] Figure 3FIG. 0 is a functional block diagram of an electronic device according to an embodiment of the present invention, which is used to execute a method for dynamically enhancing memory error correction capabilities. The method for dynamically enhancing memory error correction capabilities according to an embodiment of the present invention can be implemented by a computer program in a storage medium, for example, the memory 220 in the electronic device 200. When the computer program implementing the method of the present invention is loaded into the memory 220 by the processor 210, the processor 210 that drives the line device 200 executes the method for dynamically enhancing memory error correction capabilities according to an embodiment of the present invention.

[0066] The electronic device 200 according to an embodiment of the present invention includes a pool controller 310, an ECC capability adjustment module 311, a parity storage discrimination module 312, and leaf switches 320, 330.

[0067] The leaf switch 320 reads memory data, for example, the size of a dual in-line memory module (DIMM), the years of use,.. etc.

[0068] The leaf switch 320 performs memory training and testing to obtain the ECC capabilities, bad area information, and response times of each DIMM.

[0069] The leaf switch 320 transmits the above-related data to the pool controller 310.

[0070] The pool controller 310 establishes a memory status table as follows:

[0071]

[0072]

[0073] The ECC capability adjustment module 311 first promotes the DIMMs without ECC protection, that is, determines which areas need to be ECC promoted and calculates the required parity space size after adjustment.

[0074] The parity storage discrimination module 312 selects a target area corresponding to the parity space size to store the newly added parity data after ECC promotion.

[0075] Memory write stage (Write Stage)

[0076] A host (not shown) writes memory data to the memory pool.

[0077] The pool controller 310 determines whether to store the memory data in the leaf switch 310 or 320, for example, the leaf switch 310.

[0078] The leaf switch 310 receives the memory data and stores it in the corresponding space.

[0079] The leaf switch 310 calculates the corresponding parity according to the adjusted ECC and returns the ECC parity to the pool controller 300.

[0080] The parity storage discrimination module 312 in the pool controller 300 finds a suitable location to store the ECC parity in the target leaf switch, for example, leaf switch 320.

[0081] Memory read stage (Read Stage)

[0082] The host (not shown) requests to read a piece of data from the memory pool, and the pool controller 300 notifies the relevant leaf switch 310 or 320, for example, leaf switch 320.

[0083] The leaf switch 320 reads the data and calculates the ECC parity corresponding to the data and returns it to the pool controller 300 at the same time.

[0084] The pool controller 300 compares the ECC parity returned by the leaf switch 320 with the ECC parity read back from elsewhere during the write phase and verifies the correctness of the data.

[0085] If the comparison is correct, the pool controller 300 returns the correct data to the host (not shown), otherwise it starts the ECC correction program and records it.

[0086] Selection of parity data storage location

[0087] Store in the memory space with the lowest cost on the premise of not causing latency.

[0088] Since the size of the data is much larger than the size of the ECC parity, the parity storage discrimination module 312 first calculates the time for the data to be transferred from the DIMM to the pool controller. The formula is as follows:

[0089] Data_ResponseTime = (Data from DIMM to LeafSwitch + Time from LeafSwitch to Pool Controller).

[0090] The parity storage discrimination module 312 calculates the size of the parity required for the data and the response time of the parity. The formula is as follows:

[0091] Parity_Size = ECC_Algorithm(Data_Size); and

[0092] Parity_ResponseTime = (Byte Data from DIMM to Switch + Time from Leaf to Pool Controller).

[0093] To reduce the impact of the overall performance caused by the same-bit occupancy of high-speed DIMMs, the same-bit storage discrimination module 312 selects a lower-cost memory space for storage (stored in a memory area with slower speed and larger remaining capacity) from the free memory space on the premise of not causing additional latency. The lower-cost memory space means that the memory area with slower speed and larger capacity is preferentially stored, thus avoiding system latency caused by a large number of same-bits occupying high-speed memory.

[0094] Error Monitor and Dynamic ECC Enhancement

[0095] The pool controller 300 monitors and counts the error conditions of each memory and records them in a table.

[0096] When a relatively high error occurs in a certain memory, the ECC capability adjustment module 311 determines to increase the ECC strength.

[0097] The ECC capability adjustment module 311 calculates the parity space required for each memory after the upgrade.

[0098] The pool controller 300 notifies the leaf switch 320 to increase the ECC capability of this memory.

[0099] Data writing to this memory is paused, and the pool controller 300 first uses the parity data to verify the correctness of the data in the memory.

[0100] The leaf switch 320 then calculates the new parity data according to the new ECC capability algorithm and transmits it to the pool controller 300.

[0101] The pool controller 300 finds the destination storage for the new parity data after the ECC upgrade according to the rules of the same-bit storage discrimination module. The new leaf switch receives the new parity data and stores it.

[0102] The pool controller 300 notifies the leaf switch 320 storing the original parity data that the old parity area has become invalid and releases the space.

[0103] The ECC capability upgrade step is completed, and the memory can read and write data again.

[0104] If the modules / units integrated in the electronic device 200 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of the present invention, it can also be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory, random access memory, electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0105] It can be understood that the above-described module division is only a logical function division, and there can be other division methods in actual implementation. In addition, in each embodiment of the present application, the functional modules can be integrated in the same processing unit, or each module can exist physically alone, or two or more modules can be integrated in the same unit. The above-mentioned integrated modules can be implemented in the form of hardware, or in the form of hardware plus software functional modules.

[0106] The efficacy of the method for dynamically enhancing the memory error correction ability in the embodiments of the present invention is as follows:

[0107] (1) The Root Controller and the leaf switch cooperate with each other to provide ECC protection for the memory without ECC function under the premise of available space;

[0108] (2) Provide appropriate space to store Parity data according to the Error checking intensity required by each memory to enhance the data error correction ability; and

[0109] (3) When the Root Controller configures sufficient space to store parity data, it also takes into account the memory usage rate and response time to reduce the impact on performance and achieve a balance between performance and reliability.

[0110] Those of ordinary skill in the art can make other corresponding changes or adjustments according to the actual needs generated by combining the technical solutions and concepts provided by the embodiments of the present invention, and these changes and adjustments shall fall within the protection scope of the claims of the present invention.

Claims

1. A method for dynamically enhancing the memory error correction ability, which is applied to an electronic device, and is characterized in that The method includes: The memory leaf switch reads memory data, where the memory data at least includes the size and service life of a dual in-line memory module (DIMM); The memory leaf switch performs memory training and testing to obtain data of each dual in-line memory module, where the data at least includes error correction code (ECC) capability, bad area information, and response time; The memory leaf switch transmits the memory data and the data of the dual in-line memory module DIMM to the pool controller; The pool controller establishes a memory status table according to the memory data and the data of the dual in-line memory module DIMM, where the memory status table stores the memory data of the memory leaf switch, at least including the size of the dual in-line memory module DIMM, page size, frequency, and current protection of the dual in-line memory module DIMM; Determine the target area in the memory leaf switch that needs ECC improvement, and calculate the size of the parity space required for the ECC improvement; and Select a target area corresponding to the size of the parity space to store the newly added parity data after the ECC improvement.

2. The method for dynamically enhancing the memory error correction ability as described in claim 1, wherein It further includes: The host writes the memory data into the memory pool; The pool controller determines that the memory data is stored in the first leaf switch; The first leaf switch receives the memory data and stores it in the corresponding space; The first leaf switch calculates the corresponding ECC parity according to the adjusted ECC and transmits the ECC parity back to the pool controller; and The parity storage discrimination module in the pool controller finds a matching position and stores the ECC parity in the target leaf switch.

3. The method for dynamically enhancing the memory error correction ability according to claim 2, wherein It further includes: The host reads a piece of data from the memory pool, and the pool controller notifies the second leaf switch; The second leaf switch reads the data, and at the same time calculates the ECC parity corresponding to the data and transmits it back to the pool controller; The pool controller compares the ECC parity transmitted back by the second leaf switch with the ECC parity stored elsewhere during the write phase and verifies the correctness of the data; And If the comparison is correct, the pool controller transmits the correct data back to the host, otherwise starts the ECC correction program and records it.

4. The method for dynamically enhancing the memory error correction ability according to claim 3, characterized in that It further includes: Calculate the time for the data to be transmitted from the dual in-line memory module (DIMM) to the pool controller; Calculate the size of the parity and the response time of the parity required for the data; And Select a memory space with a lower cost to store the data.

5. The method for dynamically enhancing the memory error correction ability according to claim 4, wherein It further includes: The pool controller monitors and statistics the error conditions of each memory; When a certain memory has a higher error, determine to perform ECC strength improvement; The ECC capability adjustment module calculates the parity space required for each memory after improvement; The pool controller notifies the first leaf switch to improve the ECC capability of its memory; Data writing to this memory is paused, and the pool controller uses the parity data to verify the correctness of the data in the memory; The first leaf switch calculates new parity data according to the new ECC capability algorithm and transmits it to the pool controller; The pool controller finds the target area in the second leaf switch to store the new parity data after the ECC improvement according to the rules of the parity storage discrimination module; and The pool controller notifies the first leaf switch to release the space area that originally stored the parity data.

6. An electronic device, characterized in that, Comprising: A leaf switch for obtaining memory data, where the memory data at least includes the size and service life of a dual in-line memory module (DIMM), and simultaneously performing memory training and testing to obtain data of each dual in-line memory module, where the data at least includes error correction code (ECC) capability, bad area information, and response time; and A pool controller for obtaining the memory data and the data of the dual in-line memory module (DIMM) from the leaf switch, and establishing a memory status table according to the memory data and the data of the dual in-line memory module (DIMM), where the memory status table stores the memory data of the leaf switch, at least including the size of the dual in-line memory module (DIMM), page size, frequency, current protection of the dual in-line memory module (DIMM), and also includes; An ECC capability adjustment module for determining the target area in the leaf switch that needs to perform ECC enhancement, and calculating the size of the parity space required for the ECC enhancement; and A parity storage discrimination module for selecting a target area corresponding to the size of the parity space to store the newly added parity data after the ECC enhancement.

7. The electronic device according to claim 6, wherein Further comprising: A first leaf switch; Wherein, the pool controller determines to store the memory data in the first leaf switch, where the host writes the memory data into the memory pool; The first leaf switch is used to receive the memory data and store it in the corresponding space, calculate the corresponding ECC parity according to the adjusted ECC, and return the ECC parity to the pool controller; and The parity storage discrimination module in the pool controller finds a matching location and stores the ECC parity in the target leaf switch.

8. The electronic device according to claim 7, wherein Further comprising: A second leaf switch; Wherein, the host reads a piece of data from the memory pool, and the pool controller notifies the second leaf switch; The second leaf switch is used to read the data, and simultaneously calculate the ECC parity corresponding to the data and return it to the pool controller; The pool controller compares the ECC parity returned by the second leaf switch with the ECC parity read back and stored elsewhere during the write phase, and verifies the correctness of the data; and If the comparison is correct, the pool controller returns the correct data to the host, otherwise starts the ECC correction program and records it.

9. The electronic device according to claim 8, wherein, The parity storage discrimination module calculates the time for the data to be transmitted from the dual in-line memory module (DIMM) to the pool controller, calculates the size of the parity required for the data and the response time of the parity, and selects a memory space with a lower cost to store the data.

10. The electronic device according to claim 9, characterized in that, Further comprising: The pool controller monitors and counts the error conditions of each memory. When a certain memory has a high error rate, it determines to perform an ECC strength enhancement; The ECC capability adjustment module calculates the parity space required for each memory after the enhancement; The pool controller notifies the first leaf switch to enhance the ECC capability of its memory, suspends writing data to this memory, and the pool controller uses the parity data to verify the correctness of the data in the memory; The first leaf switch calculates new parity data according to the new ECC capability algorithm and transmits the new parity data to the pool controller; and The pool controller finds the destination area in the second leaf switch according to the rules of the parity storage discrimination module to store the new parity data after enhanced ECC, and notifies the first leaf switch to release the space area that originally stored the parity data.

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