Computing device and computing method

Abstract

Embodiments of the invention relate to computing devices and computing methods. In some examples, a computing device in a memory includes a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a current-based nine-transistor SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switch transistor, controlled by an input signal on an input line, associated with the column of memory cells in which the memory cell resides. The current source includes a switch transistor controlled by the state of the six-transistor SRAM cell, and a current regulation transistor to produce a current level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line in each successive column of memory cells increases by a factor of 2.

Description

TECHNICAL FIELD

[0001] Embodiments of the invention relate to computing devices and computing methods. BACKGROUND

[0002] The present disclosure relates generally to in-memory computing, or computing-in-memory (“CIM”), and more specifically to memory arrays for use in data processing, such as a multiply-accumulate (“MAC”) operation. In-memory computing or computing-in-memory systems store information located in the main random access memory (RAM) of a computer and perform computations at the level of memory cells, rather than moving large amounts of data between the main RAM and data storage at each computational step. In-memory computing allows for real-time analysis of data as the stored data is stored in RAM, allowing for faster reporting and decision making in business applications and machine learning applications, as the stored data is accessed more quickly. Efforts are being made to improve the performance of in-memory computing systems. SUMMARY

[0003] According to an aspect of embodiments of the present invention, there is provided a computing device comprising: a memory array comprising a plurality of memory cells grouped in rows and columns of memory cells, each memory cell comprising a memory unit for storing data, a current source comprising a first switching device and a current generator device, and a second switching device; a plurality of input lines, each input line connected to the second switching devices in a respective row and for transmitting an input signal to the second switching devices in the row; a plurality of output lines, each output line associated with a respective column of memory units; and a plurality of current controllers, each current controller connected to the current generator devices in a respective column of memory cells by a current control line and for setting a current level generated by the current generator devices in the respective column of memory cells; wherein the second switching devices in each column of memory cells are for connecting or disconnecting the current source in the memory cells to the output line associated with the column in dependence on an input signal received from the input lines, and the first switching devices in each memory cell are for allowing or preventing current from the current generator device in dependence on data stored in the memory unit in the memory cell.

[0004] According to another aspect of embodiments of the present application, there is provided a computing device comprising: a plurality of input lines; a plurality of output lines; a plurality of control signal generators; a plurality of current control lines, each connected to a respective one of the plurality of control signal generators; and a plurality of memory cells logically arranged in a two-dimensional array of rows and columns, each row associated with a respective one of the plurality of input lines, and each column associated with a respective one of the plurality of output lines and current control lines. The memory cells comprise: a memory unit having at least two memory states; a first switch transistor for receiving a signal indicative of the memory state from the memory unit and being turned on or off depending at least in part on the memory state; a second switch transistor for receiving an input from the input line associated with the memory cell and being turned on or off depending at least in part on the input signal; and a current regulating transistor for receiving a control signal from the control signal generator associated with the memory cell through the current control line associated with the memory cell and generating a level of current depending at least in part on the control signal; the first switch transistor and the second switch transistor and the current regulating transistor being connected to pass the current to the output line, the level of current being determined by a combination of the memory state, the input signal and the control signal.

[0005] According to yet another aspect of embodiments of the present application, there is provided a method of computing comprising: storing a plurality of digits of a multi-digit word in a plurality of respective memory elements, each digit having a value and a bit value; turning on or off a plurality of current sources depending on the value of the digit stored in the respective memory element, each current source being associated with a respective one of the memory elements; applying a control signal to each current source to set a level of current provided by the current source depending on the bit value of the digit stored in the respective memory element; and applying an input signal through an input line to activate a plurality of switching devices, each switching device being associated with a respective one of the memory elements to allow current provided by the respective current source to flow to an output line associated with the memory element. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be emphasized that various components are not drawn to scale and are merely intended for illustrative purposes. In fact, the dimensions of the various components can be arbitrarily increased or decreased for the sake of a clearer discussion.

[0007] Figure 1 is a schematic diagram of an in-memory computing system according to some embodiments, including a four-bit precision weight computing subsystem, with a 9-transistor ("9T") (current-based static random access memory ("SRAM")) including a current source for each memory element.

[0008] Figure 2is a schematic diagram of an in-memory computing system similar to that shown in Figure 1

[0009] Figure 3 is a schematic diagram of an in-memory computing system similar to that shown in Figure 1

[0010] Figure 4 is a schematic diagram of an in-memory computing system similar to that shown in Figure 3

[0011] Figure 5 is a schematic diagram of an in-memory computing system similar to that shown in

[0012] Figure 6A shows a successive approximation register (“SAR”) ADC for use with a current-based SRAM, according to some embodiments.

[0013] Figure 6B shows summing weighted inputs using a current-based SRAM and using pulse counting as input, according to some embodiments.

[0014] Figure 7 shows generating a digital signal corresponding to an analog input weighted sum using a time-domain ADC, according to some embodiments.

[0015] Figure 8 shows a computing process, according to some embodiments.

[0016] Figure 9 summarizes a computing process, according to some embodiments.

[0017] Figure 10 shows a CIM operation, according to some embodiments. DETAILED DESCRIPTION

[0018] ​​​The following disclosure provides a number of different embodiments or examples for implementing different features of the present application. Specific embodiments or examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, the formation of a first component over or on a second component can include embodiments in which the first component and the second component are formed in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. Furthermore, the application can be repeated with variations and / or modifications in various examples. This repetition is for simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.

[0019] The specific examples shown in the present disclosure relate to in-memory computing. An example of an application of in-memory computing is a multiply-accumulate (“MAC”) operation, in which an input array of numbers is multiplied (weighted) by respective elements of an array (e.g., column) of other numbers (e.g., weights) and the products are summed (accumulated) to produce an output sum. This is mathematically similar to the dot product (or scalar product) of two vectors, in which the components of the two vectors are multiplied pairwise and the products of the component pairs are summed. In certain artificial intelligence (AI) systems, such as artificial neural networks, an array of numbers can be weighted by multiple columns of weights. The weighting by each column produces a respective output sum. Thus, an output array of sums is produced from the input array of numbers by the weights in a matrix of multiple columns.

[0020] A commonly used type of integrated circuit memory is a static random access memory (SRAM) device. A typical SRAM memory device has an array of memory cells. In some examples, each memory cell uses six transistors (6T) connected between a higher reference potential and a lower reference potential (e.g., ground) such that one of two storage nodes can be occupied by information to be stored, with complementary information stored at the other storage node. Each bit of storage in an SRAM cell is stored on four of the transistors, which form two cross-coupled inverters. Two other transistors are connected to a memory cell word line (WL’) to control access to the memory cell by selectively connecting the cell to its bit line (BL). When the word line is enabled, a sense amplifier connected to the bit line senses and outputs the stored information. Input / output (I / O) circuitry connected to the bit line is typically used in processing the memory cell data.

[0021] According to some aspects of the present disclosure, a compute-in-memory (CIM) system includes a memory array in which, in addition to a conventional (e.g., 6T SRAM) memory cell, each memory cell has a controlled current source with a current regulation transistor and a switch transistor controlled by a memory node (Q or QB, where the voltage corresponding to the stored value is held) and used to pass current through the current regulation transistor. The current regulation transistors in each column of memory cells are controlled by a current control voltage on a common current control line. In some embodiments, the current control voltages for different columns differ by a power of 2 factor, so that the current in each current source is proportional to the place value of the bit stored in the corresponding memory cell in that column (2 0 , 2 1 , 2 3 , etc.). Each memory cell also has a switch transistor (WLC) used to connect the controlled current source to a current sum bit line (BL). The switch transistors (WLC) for each row of memory cells are controlled (turned on and off) by a common CIM word line (WL). In some embodiments, each memory cell includes a conventional memory cell that is a 6T SRAM and the controlled current source and WLC, and this forms a nine-transistor (“9T”) current-based SRAM cell suitable for storing digital information in a conventional manner as well as performing CIM.

[0022] According to certain aspects of the present disclosure, multi-bit inputs can be implemented with a pulse train on the WL (the number of pulses corresponding to the input value) or a single pulse (whose width corresponds to the input value). For example, in some embodiments, a 4-bit input can be used, although other bit widths are within the scope of the present disclosure. For example, an input of 0 is represented by 0 (00002) WL pulses, an input of 3 10 (00112) is represented by 3 WL pulses, an input of 15 10 (11112) is represented by 15 WL pulses.

[0023] In some embodiments, an input signal can be multiplied by a multi-bit (e.g., four-bit) weight (i.e., weight value) arranged in a column. The input of the multi-bit weight accumulation can be implemented by charging the bit lines of all cells in the column corresponding to each bit of the multi-bit weight; thus, the voltage on each BL indicates the sum of the currents from each cell connected to the BL, and thus the sum of the inputs, each weighted by the binary weight associated with the column. Thus, a multiply-accumulate function is performed on the BLs, and the total BL current is proportional to the bit-wise multiplication of the weight bits and the multi-bit input. The currents of all BLs corresponding to the column of the multi-bit weight are then added together to produce an analog signal (e.g., a voltage or signal over a period of time), whose value is thus the sum of the multi-bit input weighted by the multi-bit weight, respectively. Since the current control voltage of each column corresponds to the bit value of the column, the most significant bits (MSBs) of the weight contribute more to the final current sum than the least significant bits (LSBs) of the weight. Thus, the final analog signal reflects the correct meaning of each RBL. For example, for a column of four-bit weights, the contribution to the final voltage (or length of time) from the largest MSB will be eight (2 3 ) times the contribution from the LSB; the contribution from the second MSB will be four (2 2 ) times the contribution from the LSB; the contribution from the third MSB (or second LSB) will be two (2 1 ) times the contribution from the LSB.

[0024] In certain further embodiments, an analog-to-digital converter (ADC), such as a successive approximation register (“SAR”) ADC or a time-domain ADC, is used in some examples to convert the final analog signal to a multi-bit digital output.

[0025] Reference is made to Figure 1 and Figure 10 , before providing an overview of some example embodiments, which further illustrate detailed aspects of these embodiments, below. In certain applications, such as artificial intelligence, a model system is proposed. A set of inputs (e.g., numbers) is provided to the model system, which processes the inputs and generates an output. The output is compared to a desired output, and if the output is not close enough to the desired output, the model system is adjusted, and the process is repeated until the output of the model system is close enough to the desired output. For example, to have a machine that can read, a snippet of a set of letters can be provided to the model system. The system takes the snippet (input) and processes the snippet according to an algorithm and outputs the letter that the system determines it received. If the output letter is different from the input letter, the system can be adjusted and tested again until the percentage of times the output matches the input is high enough.

[0026] For some applications, a model system can be a multiplicative system that processes a set of inputs by multiplying each input by a value (sometimes called a "weight") and summing the products together (accumulating). The system can comprise a two-dimensional array of elements arranged in rows and columns, each element storing weights and capable of receiving inputs and producing an output that is the arithmetic product of the inputs and the stored weights. The model system can sum the outputs of each row of inputs provided to an element and the outputs of each column of the element.

[0027] For example, Figure 10 The system (1000) shown has a two-dimensional array (3x3 in this example) (1010) or cells (1020) of elements, each storing weights. Each cell (1020) is connected to an input line WL, and cells in each column are connected to the same output line BL. Figure 10 In the diagram, each unit is represented by the symbol for a resistor, because if you want to use... Figure 1 The 9T current-based SRAM cell (120) shown replaces the resistive element, generating an output current (Y) in the bit line BL. A Y B Y C The relationship between the input voltage (X0, X1, X2) of the resistive element and the output current is similar to the relationship between the input pulse and the output current. That is, in the case of the resistive element (1020), each current Y j (j=0,1,2) is the input voltage X i and the corresponding conductance G in column j ij The sum of the products between them, or, in the case of the SRAM element (1020), the sum of the currents Y. j (j = 0, 1, 2) is the sum of the products between the input signal indicating the number and the corresponding binary weight in the j-th column.

[0028] like Figure 1 As shown, each cell (120) has a node Q, which is held by an SRAM cell at a voltage indicating the value (weight) stored in the cell. Figure 1 As can be easily understood from the diagram, for each cell, with a binary "1" at input WL and the current regulating transistor turned on, if Q is "1", cell (110) will draw current from BL; if Q is "0", there is no current. For a binary "0" at WL', cell (110) will not draw current regardless of the value of Q. If the amount of current drawn (i.e., a certain amount of charge drawn) is higher than a threshold in a given time period, it is considered an output "1". Therefore, the output of a single cell (110) is given in the following table:

[0029]

[0030] As can be seen from the table, the output is the product of the input and the weight.

[0031] Furthermore, because the cells (110) in the same column share the same BL, the current in the BL is the sum of the currents of all the cells (110) connected to it. Thus, the current in each BL represents the sum of the binary products of the input (WL) and the respective stored weight. Moreover, since the current through each current regulation transistor is proportional to the gate voltage at the current regulation control line (CL (190)), the total current in each BL is proportional to the voltage on the respective CL.

[0032] Referring again to Figure 1 , in a system using multi-bit (in this example, four-bit) weights for the multiply-accumulate operation, each input (WL) is provided to multiple (e.g., four) cells (110) that store one bit of the multi-bit weight, respectively. Each BL is connected to a column of cells (110) that have the same bit value (i.e., 2 0 , 2 1 , 2 2 , 2 3 , etc.). In this example, the voltage on the CL corresponding to BL[0], BL[1], BL[2], and BL[3] is 1, 2, 4, and 8 times the voltage on the CL corresponding to BL[0], respectively. Thus, the total current in each BL is multiplied by the factors 1, 2, 4, and 8 (i.e., 2 0 , 2 1 , 2 2 , 2 3 ) relative to the total current on BL[0]. Thus, the total current in each BL[j] is proportional to the bit value (2 j ) of that BL. Thus, the total current in each BL[j] is proportional to the sum of the products between the input and the jth digit (a multiple of the bit value of the BL) of the multi-bit weight.

[0033] Furthermore, referring additionally to Figure 5 , because the BLs are connected in parallel, the total current through the resistor (510) is the sum of the currents of all the BLs of each column of the multi-bit weight (W n or W n+1 ). Thus, it is apparent that the total current is the sum of all the input signals multiplied by (weighted by) the respective multi-bit weight.

[0034] Finally, according to Ohm’s law, as Figure 5 illustrated and described in more detail below, the multi-bit weight (W n or W n+1The sum of the currents of all BLs in each column of the signal is converted into a voltage, and the converted signal is converted into a digital output by an analog-to-digital converter (ADC) to obtain a digital output corresponding to the sum of the products between the inputs and the corresponding multi-bit weights stored in the cell (110). In some embodiments, such as Figure 7 The example shown, and in more detail below, also demonstrates how multi-weighted (W) systems can be used. n or W n+1 The sum of the currents of all BLs in each column of the time domain is converted into a time-domain signal (i.e., pulse width or pulse count), which can then be converted into a digital signal by a counter.

[0035] In addition, such as Figure 1 As shown, since each memory cell (120) in the CIM system (100) has 6T SRAM cells, the CIM system (100) itself can be simply used as a memory array, using bit lines BL' and BLB' as data lines and WL' as write lines. Optionally, bit lines BL' and BLB' can be used to write data to (enabled by WL') memory cells (120), and bit line BL can be used to read data from memory cells (120) (enabled by WL).

[0036] For a more detailed explanation of the above system and its operation, please refer to [reference needed]. Figure 1 In some embodiments, the CIM system (100) includes a two-dimensional (“2D”) array (110) of memory cells (120) arranged in rows and columns. Each memory cell (120) includes a 6T SRAM cell (130), a controlled current source (150), and a CIM current switching transistor (WLC (160)). The 2D memory array (110) also includes a set of CIM word lines (WL (170)) one per row; a set of CIM bit lines (BL (180)) one per column; and a set of current regulation control lines (CL (190)).

[0037] In this case, each 6T SRAM cell (130) includes: a first inverter (132) formed by a series connection (i.e., source-drain current path in series) of a P-type metal-oxide-semiconductor (MOS) field effect transistor (PMOS) (142) and an n-type MOS field effect transistor (NMOS) (144) between a high reference voltage (such as VDD) and a low reference voltage (such as ground); a second inverter (134) formed by a series connection of a PMOS (146) and a NMOS (148) between a high reference voltage (such as VDD) and a low reference voltage (such as ground); and two write access transistors (136, 138), in this example, NMOS. The inverters (132, 134) are inversely coupled, i.e., the output (Q, QB) (i.e., junction between source / drain current paths) of one is coupled to the input (i.e., gate) of the other (QB, Q); the write access transistors (136, 138) each have their source / drain current paths connected between respective junctions of the inversely coupled inverters (132, 134) and respective bit lines (BL', BLB'), and the gates of the write access transistors (136, 138) are connected to a word line (WL').

[0038] Each controlled current source (150) in this example includes a current switch transistor (152) and a current regulation transistor (154) connected in series with each other. The controlled current source (150) is further connected in series with a CIM current switch transistor (WLC (160)). The gate of the current switch transistor (152) is connected to one of the storage nodes (Q, QB) (e.g., the inverted node QB). The gate of the current regulation transistor is connected to a regulation current control line (190). The gate of the CIM current switch transistor (WLC (160)) is connected to a CIM write line (WL (170)).

[0039] In this example, the current switch transistor (152), the current regulation transistor (154), and the CIM current switch transistor (WLC (160)) are all NMOS. Other types of transistors and connections can be used, as shown in the following examples. For example, PMOS can be used; the gate of the current source switch transistor (152) can be connected to the non-inverted output (Q) of the 6T memory cell (130).

[0040] In a CIM operation, a multi-bit weight is written to the 6T SRAM cell, which can be done by conventional methods, each cell (130) storing either a “1” or a “0”. To compute the weighted sum of inputs, the gate of the current regulation transistor (154) is biased by a current regulation control line (CL (190)). As described above, due to each memory cell (120), any instant-to-bit line BL[j] or from-bit line BL[j] cell current Icell is the product of the input signals on the WLs and the bit values stored in the cells. The cell current is further proportional to the gate voltage on the CL (190). Thus, the total current in each BL (180) is proportional to the sum of all the input signals multiplied by the respective weights stored in that column, and to the voltage on the CL of that column.

[0041] In some embodiments, such as the device (200) shown in Figure 1 The example shown stores a multi-bit weight (4 bits in this example) in each row (4 bits wide in this example). In this example, from left to right, the bits are arranged from least significant bit (LSB) to most significant bit (MSB). Thus, from left to right, each column has bit values of 1, 2, 4, and 8. Correspondingly, from left to right, the bias voltage on the respective CLS (190) also has relative values of 1, 2, 4, and 8. The result is that the total current on each BL is proportional to the sum of the product of the input on the WLs and the weight stored in the (j)th column, position 2 j .

[0042] The example given above assumes that the current through the current regulation transistor (154) is proportional to the gate voltage, but this proportional condition is not necessary; other gate voltages can suitably achieve the desired BL current ratio of the same sum of the product of the input on the WLs and the weight stored in each column's respective memory cell (120).

[0043] In some embodiments, the gate current on the CL is provided by a precision power supply (current source or current source), such as a zero-temperature-coefficient circuit ("ZTC") or NMOS or PMOS current mirror. In some embodiments of the CIM operation, such as when data is not being read from or written to any cell, a lower voltage for VDD (e.g., 2 volts) is acceptable to ensure that the cell (130) will correctly hold data. In this case, the SRAM can be set to a power-reduced hold mode to conserve power.

[0044] Other configurations of the computing device are possible. For example, in some embodiments, such as the device (200) shown in Figure 2 which is the same as the device in Figure 1 , except that the source of the current regulation transistor (154) of each cell 120 is connected to the storage node (in this case Q) of the 6T cell 130. With this configuration, BL leakage current is reduced.

[0045] In some embodiments, such as the device (300) shown in Figure 3 which is the same as the device in Figure 1 , except that PMOS transistors (352, 354) are used in the current source (150) in each cell (120) instead of NMOS transistors (152, 154).

[0046] In some embodiments, such as Figure 4 The device (400) shown is related to Figure 3 The components are the same, except that the drain of the current-regulating transistor (354) in each cell 120 is connected to the storage node (Q) of the 6T cell 130. With this configuration, the BL leakage current is reduced.

[0047] refer to Figure 5 In some embodiments, multi-bit weights (W) n W n+1 The current I of all BL(180) in each column of (etc.) j Summing and current I j A voltage (∑I) is generated through resistor (510). j R, where R is the resistance of resistor (510). As described above, the current and (and therefore the voltage) are proportional to the sum of the inputs multiplied by their respective multi-bit weights. The voltage is then applied to the input line (520) of the ADC (550), which produces a digital output (560) that is proportional to the weighted sum of the inputs. This results in in-memory computation.

[0048] In some embodiments, the aforementioned output voltages from multiple columns with multi-bit weights can be fed to the same ADC (550) via corresponding input lines (520, 530, 540). In particular, in some embodiments, a high-speed successive approximation register, such as... Figure 6A The example SAR ADC (600) is shown. Current-based CIM enables the conversion to be performed in a single ADC operation, rather than N ADC operations (one per bit line). The structure and operation of this SAR ADC are known and will not be described in detail here. In short, capacitors with a capacitance ratio of powers of 2 (e.g., for a 5-bit converter, C, C / 2, C / 4, C / 8, C / 16, plus a “pseudo” capacitor of C / 16) are connected at a common terminal (620), which is connected to the input (inverting) of a comparator (610). In some embodiments, the other input (non-inverting) of the comparator (610) is connected to ground. The other end of the capacitor is connected to the input voltage V. in Then connect to ground (630). Afterward, the non-common terminals of the capacitors are sequentially switched, from the maximum capacitance to the minimum capacitance, and from ground to the reference voltage V. Ref And depending on whether the voltage at the common terminal is positive or negative, the comparator's output is 0 or 1. Depending on the comparator's output, just connected to V... Ref The capacitor is reconnected to ground or remains connected to V. Ref The output of the comparator (610) for these steps is V.in The digital approximation, the MSBs are produced first and the LSBs last.

[0049] For an N-bit SAR ADC, it typically takes N+1 clock cycles to perform the sampling and bit-by-bit comparison steps. Thus, for example, for a 5-bit SAR ADC as shown in Figure 6A 6 clock cycles are needed to complete the analog-to-digital conversion of the analog signal.

[0050] With current-based SRAM, all cells in the same bit column of a multi-bit weight and all bit columns in the same column perform current summation simultaneously. Further, in some embodiments, as shown in Figure 6B each input number on the WL is represented by a pulse train, the number of pulses being proportional to the input number. For example, input 0 (00002) produces 0 pulses, input 3 10 (00112) produces 3 RWL pulses, input 15 10 (11112) produces 15 RWL pulses, and so on. Alternatively, a single pulse can also be used, where the pulse width is proportional to the input number. For example, input 1 (00012) produces one pulse of unit width, input 3 10 (00112) produces three pulses of unit width, input 15 10 (11112), produces 15 pulses of unit width, and so on. In some embodiments, when performing CIM, if the input signal sampling period is sufficient to include the entire pulse count or pulse width, then the signal at the input (520, 530, 540) is proportional to the sum of the products between the multi-bit input signal and the corresponding multi-bit weights. In such CIM operation, for an N-bit input, it takes N clock cycles to sample the input and N+1 clock cycles to convert the analog CIM output to a digital output, as described above. That is, the CIM operation takes 2N+1 clock cycles to complete. For an N-bit input, a single ADC operation (including multiple clock cycles (e.g., 11 for a 5-bit conversion)) is needed. In contrast, in a conventional multi-bit CIM operation, N ADC operations (one for each input bit) are needed. Thus, according to some embodiments, less power consumption and delay is achieved through the current-based CIM circuit and its operation, such as shown in Figure 6B

[0051] In some embodiments, such as the example shown in Figure 7 the combined BL current of each column of multi-bit weights in a computing device (700) similar to the device shown in Figure 5 may be converted to a digital signal using a time-domain ADC. In some embodiments, the time-domain ADC includes a SAR ADC, as shown in Figure 7 ​The capacitor (710) and comparator (750) are shown connected in series. The combined BL current is fed through line (720) to the capacitor (710). V Ref and the voltage on the capacitor (710) is applied to an input of the comparator (750). The capacitor is charged to the reference voltage V Ref in time that is inversely proportional to the current, and this time can be measured, for example, by a counter (not shown) connected to and operated by the comparator (750). That is, the counter runs until the capacitor voltage reaches V Ref and the output of the comparator (750) switches state and stops the counter. Thus, the count is a digital representation of the analog input.

[0052] Similar to the above example of a SAR ADC, for an N-bit input, a single ADC operation is required, rather than N ADC operations (one for each input bit).

[0053] More generally, in some embodiments, as outlined in Figure 8 the computational method (800) comprises: (810) storing a set of digits of a multi-digit number in a set of respective memory elements, each digit having a value and a bit value; (820) switching on or off a set of current sources depending on the value of the digit stored in the respective memory element, each current source being associated with a respective one of the memory elements; (830) applying a control signal to each current source to set a current level provided by the current source according to the bit value of the digit stored in the respective memory element; and (840) applying an input signal through an input line to activate a set of switching devices, each switching device being associated with a respective one of the memory elements, to allow a current provided by the respective current source to flow to an output line associated with the memory element.

[0054] Other variations of the above disclosed can be employed. For example, other types of memory cells other than SRAM cells can be used. For example, instead of 6T SRAM cells, non-volatile memory (NVM) cells such as FeRAM, FeFET, and flash memory can be used.

[0055] The various examples disclosed herein have certain advantages over conventional devices and methods. For example, as outlined above, Figure 9As shown in the example system in FIG. 1, because memory elements can be accessed as traditional memory as well as CIM elements, the use of external memory (such as external DRAM) can be reduced or eliminated. The design with certain embodiments provides flexibility. For example, SRAM or NVM CI can be used. SRAM has the advantage of fast write and high write endurance; NVM has the advantage of non-volatility, small footprint, low leakage, and the ability to instantaneously turn on the device. In-memory computing based on SRAM can result in reduced energy consumption. With SRAM, online update of the weights of the CIM (i.e., writing new weight values into the memory while computing the output based on the old weight values) is also feasible. In artificial neural network applications, iterations of MAC operations are typically required, each iteration using a different set of weight values. Because the speed of non-volatile memory arrays is relatively slow, multiple arrays are needed to store multiple sets of weight values. In contrast, with the SRAM cells disclosed in certain embodiments above, because of the high speed of such memory cells, a single SRAM array can be reloaded with successive sets of weight values in neural network operations.

[0056] In some embodiments, as Figure 9As shown, the weight values of the CIM of a CIM device, such as an integrated circuit (900), can be updated from a memory module, which in some embodiments can be on-chip memory (910). In some embodiments, the weight values can be stored in compressed mode and decompressed by a decompression module (920) before being provided to the SRAM array (930) of the CIM. Compression and decompression systems and methods are well known. For example, Sun, “Efficient Methods and Hardware for Deep Learning,” Stanford University (2017) (available at http: / / purl.stanford.edu / qf934gh3708), which is hereby incorporated by reference herein. Deep Compression consists of pruning, quantized training, and variable length encoding, which can compress deep neural networks by orders of magnitude with little loss in prediction accuracy. This large compression enables machine learning to run on mobile devices. Deep Compression is a three-stage process that reduces the model size of deep neural networks while preserving the original accuracy. First, we can prune the network by removing redundant connections, which only keeps the connections that provide the most information. Next, we quantize the weights and let multiple connections share the same weight. Thus, only the effective weights and indices need to be stored, and each parameter can be represented with fewer bits. Finally, we can apply variable length encoding (Huffman encoding) to exploit the non-uniform distribution of effective weights and represent the weights using a variable length code table without loss in training accuracy. Our most important insight is that pruning and quantized training can compress neural networks without interfering with each other, thus yielding surprisingly high compression ratios. Deep Compression makes the storage requirement very small (megabyte space), and all the weights can be cached on-chip without off-chip DRAM. Dynamic random access memory is not only slow but also has high energy consumption, so Deep Compression makes the model much more efficient.

[0057] In some embodiments, a computing device comprises: a memory array comprising a plurality of memory cells grouped in rows and columns of memory cells, each memory cell comprising a memory unit to store data, a current source comprising a first switching device and a current generator device, and a second switching device; a plurality of input lines, each input line connected to the second switching device in a respective row and to transmit an input signal to the second switching device in the row; a plurality of output lines, each output line associated with a respective column of memory units; and a plurality of current controllers, each current controller connected to the current generator device in a respective column of memory cells by a current control line and to set a current level generated by the current generator device in the respective column of memory cells; wherein the second switching device in each column of memory cells is to connect or disconnect the current source in the memory cell to the output line associated with the column in accordance with an input signal received from the input line, and the first switching device in each memory cell is to allow or prevent current from the current generator device in accordance with data stored in the memory unit in the memory cell.

[0058] In some embodiments, the plurality of current controllers are to set the current level generated by the current generator device in each successive column of memory cells to increase by a factor of 2.

[0059] In some embodiments, in each memory cell: the memory unit comprises a static random access memory (SRAM) cell to store a signal at a storage node, the first switching device comprises a first transistor having a gate connected to the storage node, the current generator device comprises a second transistor having a gate connected to a current control line associated with the column in the memory cell, the second switching device comprises a third transistor having a gate connected to an input line associated with the row of the memory cell.

[0060] In some embodiments, each SRAM cell is a six-transistor SRAM.

[0061] In some embodiments, the first transistor and the third transistor are to allow or prevent current generated by the second transistor to flow to the output line in accordance with a combination of the signal stored at the storage node and an input signal received at the gate of the third transistor.

[0062] In some embodiments, each memory unit is to store a signal indicative of a weight value, each input signal is indicative of an input digit, and the first and second switching devices and the current source are collectively to provide current to the output line associated with the memory cell, a level of the current being indicative of a product of the weight value stored in the memory unit and the input digit indicated by the input signal.

[0063] In some embodiments, for each memory cell: the memory unit is an SRAM cell having two storage nodes for storing corresponding signals indicative of binary values that are complementary to each other, wherein the series combination of the first transistor, the second transistor, and the third transistor has two ends, one of the two ends is connected to the output line, and wherein the gate of the first transistor is connected to one of the storage nodes.

[0064] In some embodiments, the other end of the series combination is connected to the other one of the storage nodes.

[0065] In some embodiments, the computing device further comprises an analog-to-digital converter ("ADC"), wherein the plurality of output lines are connected to each other and are used to generate a signal indicative of a combined current of the plurality of output lines, wherein the ADC is used to receive the signal and convert the signal to a digital signal.

[0066] In some embodiments, the ADC comprises a successive approximation register ADC.

[0067] In some embodiments, the ADC comprises a time-domain ADC.

[0068] In some embodiments, each memory cell further comprises a data input / output line and a data enable line for enabling the memory unit to receive data through the data input / output line and allow data to be retrieved from the memory unit through the data input / output line.

[0069] In some embodiments, a computing device, comprising: a plurality of input lines; a plurality of output lines; a plurality of control signal generators; a plurality of current control lines, each control line connected to a respective one of the plurality of control signal generators; and a plurality of memory cells logically arranged in rows and columns of a two-dimensional array, each row associated with a respective one of the plurality of input lines, each column associated with a respective one of the plurality of output lines and current control lines, the memory cells comprising: a memory unit having at least two memory states; a first switch transistor for receiving a signal indicative of the memory state from the memory unit and being turned on or off depending at least in part on the memory state; a second switch transistor for receiving an input from the input line associated with the memory cell and being turned on or off depending at least in part on the input signal; and a current regulation transistor for receiving a control signal from the control signal generator associated with the memory cell through the current control line associated with the memory cell and generating a level of current depending at least in part on the control signal; the first transistor and the second switch transistor and the current regulation transistor connected to pass the current to the output line, the level of the current determined by a combination of the memory state, the input signal, and the control signal.

[0070] In some embodiments, each memory state corresponds to a numerical weight value, and the input signal corresponds to a numerical input value, wherein the first transistor and the second switch transistor and the current regulating transistor are connected to pass current to the output line, the level of the current being proportional to the product of the numerical weight value corresponding to the memory state and the numerical input value corresponding to the input signal.

[0071] In some embodiments, the first transistor and the second switch transistor and the current regulating transistor are connected to form a series combination having two ends, one of the two ends being connected to the output line, wherein the memory cell has a storage node, the memory cell being configured to store a signal indicative of a memory state, wherein the first switch transistor has a gate connected to the storage node, the second transistor has a gate connected to the input line, and the current regulating transistor has a gate connected to the current control line.

[0072] In some embodiments, a plurality of current controllers are used to increase the current level produced by the current regulating transistor in each successive column of memory cells by a factor of two.

[0073] In some embodiments, the computing device further comprises an ADC having an input, wherein the plurality of output lines are connected together at a common node, the common node being connected to the input of the ADC.

[0074] In some embodiments, the common node is further connected to a resistor or a capacitor.

[0075] In some embodiments, a computing method comprises storing a plurality of digits of a multi-digit number in a plurality of respective memory elements, each digit having a value and a bit value; turning on or off a plurality of current sources in accordance with the values of the digits stored in the respective memory elements, each current source being associated with a respective one of the memory elements; applying a control signal to each current source to set a current level provided by the current source in accordance with the bit values of the digits stored in the respective memory elements; and applying an input signal through an input line to activate a plurality of switching devices, each switching device being associated with a respective one of the memory elements, to allow current provided by the respective current source to flow to an output line associated with the memory element.

[0076] In some embodiments, applying the input signal comprises applying a string of a plurality of pulses having a pulse count or a single pulse having a pulse width, and obtaining from the current provided to the output line an amount proportional to the product of the pulse count or the pulse width and the stored multi-digit number.

[0077] The foregoing summary has outlined features of several embodiments so that those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A computing device, comprising: A memory array includes a plurality of memory cells grouped in rows and columns of memory cells, each of the memory cells including a memory unit for storing data, a current source including a first switching device and a current generator device, and a second switching device; Multiple input lines, each of the input lines being connected to the second switching device in a corresponding row and used to transmit an input signal to the second switching device in the row; Multiple output lines, each of which is associated with a corresponding column of the memory unit; as well as Multiple current controllers, each of which is connected via a current control line to the current generator device in a corresponding column of the memory cell, and is used to set the current level generated by the current generator device in the corresponding column of the memory cell; Wherein, based on the input signal received from the input line, the second switching device in each column of the memory cell is used to connect or disconnect the current source in the memory cell to the output line associated with the column, and based on the data stored in the memory cell, the first switching device in each memory cell is used to allow or prevent current from the current generator device. In each memory cell: the memory cell includes a static random access memory cell for storing signals at a storage node; the first switching device includes a first transistor having a gate connected to the storage node; the current generator device includes a second transistor having a gate connected to a current control line associated with a column of the memory cell; and the second switching device includes a third transistor having a gate connected to the input line associated with a row of the memory cell.

2. The computing device according to claim 1, wherein, The plurality of current controllers are used to set the current level generated by the current generator device in each consecutive column of the memory cell by a factor of 2.

3. The computing device according to claim 1, wherein, Each of the plurality of current controllers includes a current regulating transistor for receiving a control voltage via the current control line associated with the memory cell and generating the current level at least in part based on the control voltage.

4. The computing device according to claim 1, wherein, Each of the static random access memory cells is a six-transistor static random access memory.

5. The computing device according to claim 3, wherein, Based on the combination of the signal stored in the storage node and the input signal received at the gate of the third transistor, the first transistor and the third transistor are used to allow or prevent the current generated by the second transistor from flowing to the output line.

6. The computing device according to claim 1, wherein, Each memory unit is used to store a signal indicating a weight value, each input signal indicates an input number, and the first and second switching devices, along with the current source, are used to provide current to the output line associated with the memory unit, the level of which indicates the product of the weight value stored in the memory unit and the input number indicated by the input signal.

7. The computing device according to claim 3, wherein, For each of the memory cells: the memory cell is a static random access memory cell with two storage nodes for storing corresponding signals that are complementary to each other and indicate binary values, wherein the series combination of the first transistor, the second transistor and the third transistor has two ends, one of which is connected to the output line, and wherein the gate of the first transistor is connected to one of the storage nodes.

8. The computing device according to claim 7, wherein, The other end of the cascaded combination is connected to another of the storage nodes.

9. The computing device of claim 1, further comprising an analog-to-digital converter, wherein a plurality of output lines are connected to each other and are used to generate a signal indicating a combined current of the plurality of output lines, wherein the analog-to-digital converter is used to receive the signal and convert the signal into a digital signal.

10. The computing device according to claim 9, wherein, The analog-to-digital converter includes a successive approximation register analog-to-digital converter.

11. The computing device according to claim 9, wherein, The analog-to-digital converter includes a time-domain analog-to-digital converter.

12. The computing device according to claim 1, wherein, Each memory cell also includes a data input / output line and a data enable line for enabling the memory cell to receive data via the data input / output line and allowing data to be retrieved from the memory cell via the data input / output line.

13. A computing device, comprising: Multiple input lines; Multiple output lines; Multiple control signal generators; Multiple current control lines, each of the control lines being connected to a corresponding one of the multiple control signal generators; and A plurality of memory cells are arranged in a row and column logical array in a two-dimensional array, each row being associated with a corresponding input line among the plurality of input lines, and each column being associated with a corresponding output line and a current control line. The memory cells include: A memory unit having at least two memory states; A first switching transistor is configured to receive a signal indicating the state of the memory from the memory unit, and to be turned on or off at least in part according to the state of the memory; A second switching transistor is configured to receive an input signal from the input line associated with the memory cell, and to be turned on or off at least partially according to the input signal; and A current regulating transistor is configured to receive a control signal from a control signal generator associated with the memory cell via a current control line associated with the memory cell, and to generate a current level at least in part based on the control signal. The first switching transistor, the second switching transistor, and the current regulating transistor are connected to deliver current to the output line, the level of which is determined by a combination of the memory state, the input signal, and the control signal. Each memory state corresponds to a numerical weight value, and the input signal corresponds to a numerical input value. The first switching transistor, the second switching transistor, and the current regulating transistor are connected to deliver current to the output line, the level of which is proportional to the product of the numerical weight value corresponding to the memory state and the numerical input value corresponding to the input signal.

14. The computing device according to claim 13, wherein, Each memory cell also includes a data input / output line and a data enable line for enabling the memory cell to receive data via the data input / output line and allowing data to be retrieved from the memory cell via the data input / output line.

15. The computing device according to claim 14, wherein, The first switching transistor, the second switching transistor, and the current regulating transistor are connected to form a series combination with two ends, one of which is connected to the output line. The memory unit has a storage node for storing a signal indicating the state of the memory. The first switching transistor has a gate connected to the storage node, the second switching transistor has a gate connected to the input line, and the current regulating transistor has a gate connected to the current control line.

16. The computing device according to claim 15, wherein, The plurality of control signal generators are used to set the current level generated by the current regulating transistor in each consecutive column of the memory cell by a factor of 2.

17. The computing device of claim 16, further comprising an analog-to-digital converter having an input, wherein the plurality of output lines are connected together at a common node, the common node being connected to the input of the analog-to-digital converter.

18. The computing device of claim 17, wherein the common node is further connected to a resistor or a capacitor.

19. A calculation method, comprising: Multiple bits of a multi-bit number are stored in multiple corresponding memory elements, each bit having a value and a bit value; Based on the value of the bits stored in the respective memory elements, multiple current sources are switched on or off, each current source being associated with a corresponding memory element; A control signal is applied to each of the current sources to set the current level provided by the current source according to the bit value of the number of bits stored in the corresponding memory element. as well as An input signal is applied via an input line to activate a plurality of switching devices, each of which is associated with a corresponding memory element to allow current supplied by a corresponding current source to flow to the output line associated with the memory element. The application of the input signal includes applying a series of pulses with a pulse count or a single pulse with a pulse width, and obtaining an amount proportional to the product of the pulse count or the pulse width and the stored majority digits from the current supplied to the output line.

20. The method according to claim 19, wherein, Applying the control signal to each of the current sources includes applying a gate voltage to the corresponding current regulating transistor.

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