Memory device and method of operating a memory device

Abstract

This document provides a memory device and a method for operating the memory device. The memory device may include: a memory block including a plurality of memory cells; and peripheral circuitry configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a programming operation, wherein during a verification operation included in the programming operation, the peripheral circuitry may be configured to: allow a selected word line among the plurality of word lines to float, and reduce the potential of the selected word line to a preparatory level by reducing the potential of the word line adjacent to the selected word line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0006942, filed on January 18, 2021, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to electronic devices, and more particularly to memory devices and methods of operating memory devices. Background Technology

[0004] Recently, the paradigm for computing environments has shifted to ubiquitous computing, enabling computer systems to be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems employing memory devices; in other words, they use data storage devices. These data storage devices are used as either main memory or secondary memory devices in portable electronic devices.

[0005] The advantages of data storage devices that utilize memory devices are that, due to the absence of mechanical drives, a) excellent stability and durability, b) very high information access speeds, and c) low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs).

[0006] Memory devices can be classified into volatile memory devices and non-volatile memory devices.

[0007] This type of non-volatile memory device has relatively low write and read speeds, but retains the data stored within it even when power supply is interrupted. Therefore, non-volatile memory devices are used to store data that must be retained regardless of whether power is available. Representative examples of non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified into NOR and NAND types. Summary of the Invention

[0008] Various embodiments of this disclosure relate to a memory device capable of adjusting (e.g., rapidly adjusting) the potential of a selected word line to a potential corresponding to a target level, and a method of operating the memory device.

[0009] One embodiment of this disclosure may provide a memory device. The memory device may include: a memory block comprising a plurality of memory cells; and peripheral circuitry configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a programming operation, wherein during a verification operation included in the programming operation, the peripheral circuitry is configured to: allow a selected word line among the plurality of word lines to float, and reduce the potential of the selected word line to a preparatory level by reducing the potential of word lines adjacent to the selected word line.

[0010] One embodiment of this disclosure may provide a memory device. The memory device may include: a memory block comprising a plurality of memory cells; and peripheral circuitry configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a read operation, wherein during the read operation, the peripheral circuitry is configured to: allow a selected word line among the plurality of word lines to float, and reduce the potential of the selected word line to a preparatory level by reducing the potential of word lines adjacent to the selected word line.

[0011] One embodiment of this disclosure may provide a memory device. The memory device may include: a memory block comprising a plurality of memory cells; and peripheral circuitry configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a read operation, wherein during the read operation, the peripheral circuitry is configured to: allow a selected word line among the plurality of word lines to float, and increase the potential of the selected word line to a first preparatory level by increasing the potential of the word line adjacent to the selected word line.

[0012] One embodiment of this disclosure provides a method for operating a memory device. The method may include: applying a programming voltage to a selected word line and applying a first pass voltage to a word line adjacent to the selected word line; reducing the potential of the selected word line to a first level; allowing the selected word line to float; and while the selected word line is floating, reducing the potential of the adjacent word line by applying a second pass voltage, which is a set voltage lower than the first pass voltage, to the adjacent word line, wherein the potential of the floating selected word line is set to a preparatory level lower than the first level based on coupling with the adjacent word line.

[0013] One embodiment of this disclosure provides a method for operating a memory device. The method may include: applying a first through voltage to a plurality of word lines; reducing the potential of a selected word line among the plurality of word lines to a first level; allowing the selected word line to float; and while the selected word line is floating, reducing the potential of adjacent word lines by applying a second through voltage, lower than the first through voltage, to word lines adjacent to the selected word line among the plurality of word lines, wherein the potential of the floating selected word line is set to a preparatory level lower than the first level based on coupling with adjacent word lines.

[0014] One embodiment of this disclosure provides a method for operating a memory device. The method may include: applying a first read voltage to a selected word line and applying a first pass voltage to a word line adjacent to the selected word line; allowing the selected word line to float and increasing the potential of the floating selected word line to a first preparatory level higher than the first read voltage by applying a second pass voltage higher than the first pass voltage to the adjacent word line; and applying a second read voltage higher than the first read voltage to the selected word line.

[0015] One embodiment of this disclosure may provide an apparatus. The apparatus may include: a storage region configured to store instructions, and at least one processor configured to execute instructions to control a verification operation included in a programming operation, wherein the at least one processor is configured to: control the verification operation to allow a selected word line among a plurality of word lines to float, and while the selected word line is floating, reduce the potential of word lines adjacent to the selected word line to reduce the potential of the selected word line to a preparatory level based on coupling with the adjacent word lines.

[0016] One embodiment of this disclosure may provide an apparatus. The apparatus may include: a storage region configured to store instructions, and at least one processor configured to execute instructions to control a read operation, wherein the at least one processor is configured to: control the read operation to allow a selected word line among a plurality of word lines to float, and while the selected word line is floating, reduce the potential of word lines adjacent to the selected word line to reduce the potential of the selected word line to a preparatory level based on coupling with the adjacent word lines. Attached Figure Description

[0017] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0018] Figure 2 It is a diagram. Figure 1 A diagram of a memory device.

[0019] Figure 3 It is a diagram. Figure 2A diagram of the memory blocks.

[0020] Figure 4 This is a diagram illustrating an example of a memory block with a 3D structure.

[0021] Figure 5 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0022] Figure 6 This is a signal waveform diagram used to illustrate a method of operating a memory device according to an embodiment of the present disclosure.

[0023] Figure 7 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0024] Figure 8 This is a signal waveform diagram used to illustrate a method of operating a memory device according to an embodiment of the present disclosure.

[0025] Figure 9 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0026] Figure 10 This is a signal waveform diagram used to illustrate a method of operating a memory device according to an embodiment of the present disclosure.

[0027] Figure 11 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0028] Figure 12 This is a signal waveform diagram used to illustrate a method of operating a memory device according to an embodiment of the present disclosure.

[0029] Figure 13 This is a diagram illustrating one embodiment of a memory system.

[0030] Figure 14 This is a diagram illustrating one embodiment of a memory system.

[0031] Figure 15 This is a diagram illustrating one embodiment of a memory system.

[0032] Figure 16 This is a diagram illustrating one embodiment of a memory system. Detailed Implementation

[0033] Specific structural or functional descriptions of embodiments of this disclosure, as illustrated in this specification or application, are provided to describe embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be practiced in various forms and should not be construed as limited to the embodiments described in the specification or application.

[0034] Various embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown so that those skilled in the art can practice the technical spirit of the present disclosure.

[0035] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0036] refer to Figure 1 The memory system 1000 may include a memory device 1100 for storing data and a memory controller 1200 for controlling the memory device 1100 under the control of the host 2000.

[0037] The host 2000 can communicate with the memory system 1000 using interface protocols, such as Peripheral Component Interconnect Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). Furthermore, the interface protocol between the host 2000 and the memory system 1000 is not limited to the examples above and can be one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Digital Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0038] The memory controller 1200 can control the overall operation of the memory system 1000 and the data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 can program or read data by controlling the memory device 1100 in response to a request received from the host 2000. During a programming operation, the memory controller 1200 can transmit the command CMD, address ADD, and data DATA to be programmed corresponding to the programming operation to the memory device 1100. Furthermore, during a reading operation, the memory controller 1200 can receive data DATA read from the memory device 1100, temporarily store the data DATA, and transmit the temporarily stored data DATA to the host 2000.

[0039] The memory device 1100 can perform programming operations (i.e., storage), reading operations, or erasure operations under the control of the memory controller 1200.

[0040] In one embodiment, the memory device 1100 may include, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus DRAM (RDRAM), or Flash memory.

[0041] Figure 2 It is a diagram. Figure 1 A diagram of a memory device.

[0042] refer to Figure 2 The memory device 1100 may include a memory cell array 100 in which data is stored. The memory device 1100 may include peripheral circuitry 200 configured to perform programming operations for storing data in the memory cell array 100, read operations for outputting the stored data, and erase operations for erasing the stored data. The memory device 1100 may include control logic 300, which is controlled by a memory controller (e.g., in...). Figure 1 Under the control of the memory controller 1200, the peripheral circuit 200 is controlled.

[0043] The memory cell array 100 may include multiple memory blocks MB1 to MBk 110 (where k is a positive integer). Local lines LL and bit lines BL1 to BLm (where m is a positive integer) may be coupled to each memory block in the memory blocks MB1 to MBk 110. For example, the local line LL may include a first select line, a second select line, and a plurality of word lines disposed between the first select line and the second select line. Furthermore, the local line LL may include dummy lines disposed between the first select line and the word line and between the second select line and the word line. Here, the first select line may be a source select line, and the second select line may be a drain select line. For example, the local line LL may include a word line, a drain select line, and a source select line, and a source line SL. For example, the local line LL may also include dummy lines. For example, the local line LL may also include pipe lines. The local line LL may be coupled to each memory block in the memory blocks MB1 to MBk 110, and the bit lines BL1 to BLm may be collectively coupled to the memory blocks MB1 to MBk 110. Memory blocks MB1 to MBk 110 can each be implemented in a two-dimensional (2D) or three-dimensional (3D) structure. For example, memory cells in memory block 110 with a 2D structure can be arranged horizontally on a substrate. For example, memory cells in memory block 110 with a 3D structure can be stacked vertically on a substrate.

[0044] The peripheral circuitry 200 can perform programming, reading, and erasing operations on the selected memory block 110 under the control of the control logic 300. For example, the peripheral circuitry 200 may include a voltage generation circuitry 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuitry 250, a pass / fail check circuitry 260, and a source line driver 270.

[0045] In response to the operation signal OP_CMD, the voltage generation circuit 210 can generate various operating voltages Vop for programming, reading, and erasing operations. Furthermore, in response to the operation signal OP_CMD, the voltage generation circuit 210 can selectively discharge the local line LL. For example, under the control of the control logic 300, the voltage generation circuit 210 can generate various voltages, such as programming voltage, verification voltage, reading voltage, pass voltage, and multiple set voltages.

[0046] In response to the row decoder control signal AD_signals, row decoder 220 can transmit an operating voltage Vop to a local line LL coupled to the selected memory block 110. For example, during a programming voltage application operation included in a programming operation, in response to the row decoder control signal AD_signals, row decoder 220 can apply a programming voltage generated by voltage generation circuit 210 to the selected word line in local line LL to store charge in the selected memory cell, and row decoder 220 can apply a pass voltage generated by voltage generation circuit 210 to an unselected word line. The applied pass voltage allows charge in the memory cell of the unselected word line to be discharged. Furthermore, during a verification operation included in the programming operation (which determines whether the memory cell in the selected word line has been programmed), in response to the row decoder control signal AD_signals, row decoder 220 can sequentially apply a plurality of verification voltages generated by voltage generation circuit 210 to the selected word line in local line LL, and row decoder 220 can apply a pass voltage generated by voltage generation circuit 210 to an unselected word line. A typical programming verification operation stores a target threshold voltage in a page buffer coupled to each data line (e.g., bit lines BL1 to BLm) and applies a ramp voltage to the control gate of the memory cell being verified. When the ramp voltage reaches the threshold voltage to which the memory cell has been programmed, the memory cell is turned on, and sensing circuitry, such as pass / fail check circuitry 260, can detect the current on the bit line coupled to the memory cell. If the ramp voltage at the time of current detection is greater than or equal to the target threshold voltage, further programming is disabled. Furthermore, during a read operation, in response to the row decoder control signal AD_signals, row decoder 220 can sequentially apply multiple read voltages generated by voltage generation circuitry 210 to selected word lines in the local line LL, and row decoder 220 can apply a pass voltage generated by voltage generation circuitry 210 to unselected word lines.

[0047] Page buffer group 230 may include multiple page buffers PB1 to PBm 231 coupled to bit lines BL1 to BLm. Page buffers PB1 to PBm 231 may operate in response to the page buffer control signal PBSIGNALS. For example, during a programming operation, page buffers PB1 to PBm 231 may temporarily store data to be programmed and may adjust the potential levels of bit lines BL1 to BLm based on the temporarily stored data. Furthermore, during a read operation or a program verification operation, page buffers PB1 to PBm 231 may sense the voltage or current of bit lines BL1 to BLm.

[0048] In response to the column address CADD, the column decoder 240 can transfer data between the input / output circuitry 250 and the page buffer group 230. For example, the column decoder 240 can exchange data with the page buffers PB1 to PBm 231 via the data lines DL, or it can exchange data with the input / output circuitry 250 via the column lines CL.

[0049] The input / output circuit 250 can input from the memory controller (e.g., Figure 1 The command CMD and address ADD received by the 1200 are transmitted to the control logic 300, or data DATA can be exchanged with the column decoder 240.

[0050] During a read operation or a program verification operation, the pass / fail check circuit 260 can generate a reference current in response to the enable bit VRY_BIT<#>, and can compare the sensed voltage VPB received from the page buffer group with the reference voltage generated by the reference current, and then output a pass signal PASS or a failure signal FAIL. The sensed voltage VPB can be a voltage controlled based on the number of memory cells determined to have passed the program verification operation.

[0051] The source line driver 270 can be coupled to a memory cell included in the memory cell array 100 via the source line SL, and can control the voltage to be applied to the source line SL. The source line driver 270 can receive a source line control signal CTRL_SL from the control logic 300, and can control the voltage to be applied to the source line SL in response to the source line control signal CTRL_SL.

[0052] In response to the command CMD and address ADD, the control logic 300 can control the peripheral circuit 200 by outputting the operation signal OP_CMD, the line decoder control signal AD_signals, the page buffer control signal PBSIGNALS, and the enable bit VRY_BIT<#>.

[0053] During the verification operation included in the programming operation, control logic 300 can control voltage generation circuit 210 and line decoder 220 to set the potential (or otherwise considered voltage value) of the selected word line to a preparatory level by reducing the potential level of the word lines adjacent to the selected word line while the selected word line is allowed to float, and then a verification voltage is applied to the selected word line. As used herein, word lines adjacent to the selected word line refer not only to the nearest neighbor word line on either side of the selected word line, but also to the second nearest neighbor word line on either side of the selected word line, and may also refer to word lines other than the second nearest neighbor word line on either side of the selected word line.

[0054] Furthermore, during a verification or read operation, control logic 300 can control voltage generation circuit 210 and line decoder 220 so that a plurality of verification voltages or read voltages are sequentially increased and applied to the selected word line. Control logic 300 can also control voltage generation circuit 210 and line decoder 220 to increase the potential of the selected word line by increasing the through voltage to be applied to the unselected word line adjacent to the selected word line while the selected word line is allowed to float.

[0055] To decrease or increase (e.g., rapidly decrease or increase) the potential level of a selected word line during a verification or read operation, the memory device described above according to embodiments of this disclosure can adjust the potential of the selected word line to a preparatory level by allowing the selected word line to float and subsequently decreasing or increasing the potential of word lines adjacent to the selected word line, and can adjust the potential of the selected word line to a target level by applying a verification voltage or a read voltage to the selected word line. According to one embodiment of this disclosure, this operation of decreasing or increasing the potential of the word lines(plural) adjacent to the selected word line allows the memory device disclosed herein to operate faster (i.e., at least programming, reading, and / or erasing) than existing memory devices, while maintaining the desired stability of the data stored therein, even when the power supply is interrupted.

[0056] Figure 3 It is a diagram. Figure 2 A diagram of the memory blocks.

[0057] refer to Figure 3 Multiple word lines arranged parallel to each other between the first select line and the second select line can be coupled to memory block 110. Here, the first select line can be the source select line SSL, and the second select line can be the drain select line DSL. Specifically, memory block 110 can include multiple strings ST coupled between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be coupled to strings ST individually, and the source lines SL can be coupled to strings ST collectively. Strings ST can be configured similarly, and therefore, strings ST coupled to the first bit line BL1 will be described in detail by way of example.

[0058] A string ST may include a source select transistor SST, multiple memory cells F1 to F16, and a drain select transistor DST, which are coupled in series between the source line SL and the first bit line BL1. A single string ST may include at least one source select transistor SST and at least one drain select transistor DST, and the string ST may include more memory cells than the memory cells F1 to F16 shown in the figure.

[0059] The source of the source select transistor SST can be coupled to the source line SL, and the drain of the drain select transistor DST can be coupled to the first bit line BL1. Memory cells F1 to F16 can be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings of ST can be coupled to the source select line SSL, the gates of the drain select transistors DST included in different strings of ST can be coupled to the drain select line DSL, and the gates of memory cells F1 to F16 can be coupled to multiple word lines WL1 to WL16 respectively. A group of memory cells in different strings of ST that are coupled to the same word lines can be referred to as a "physical page (PPG)". Therefore, memory block 110 can include the same number of physical pages PPG as the number of word lines WL1 to WL16.

[0060] Figure 4 This is a diagram illustrating an example of a memory block with a 3D structure.

[0061] refer to Figure 4 The memory cell array 100 may include multiple memory blocks MB1 to MBk 110. Each memory block 110 may include multiple strings ST11 to ST1m and ST21 to ST2m (in... Figure 4 The middle is shown as with Figure 3 The PPG shown is similar to a linear extension group of memory cells MC1 to MCn. In one embodiment, each string in strings ST11 to ST1m and ST21 to ST2m can be formed in an 'I' or 'U' shape. In the first memory block MB1, m strings can be arranged in the row direction (e.g., the X direction). Although in Figure 4 In the illustration, two strings are shown arranged in the column direction (e.g., the Y direction), but this embodiment is only an illustration of one embodiment, and in other embodiments, three or more strings may be arranged in the column direction (e.g., the Y direction).

[0062] Each of the strings ST11 to ST1m and ST21 to ST2m may include at least one source selection transistor SST, a first memory cell to an nth memory cell MC1 to MCn, and at least one drain selection transistor DST.

[0063] The source select transistor SST of each string can be coupled between the source line SL and the memory cells MC1 to MCn. The source select transistors of strings arranged in the same row can be coupled to the same source select line. The source select transistors of strings ST11 to ST1m arranged in the first row can be coupled to the first source select line SSL1. The source select transistors of strings ST21 to ST2m arranged in the second row can be coupled to the second source select line SSL2. In other embodiments, the source select transistors of strings ST11 to ST1m and ST21 to ST2m can be jointly coupled to a single source select line.

[0064] The first memory cell to the nth memory cell MC1 to MCn in each string can be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell to the nth memory cell MC1 to MCn can be coupled to the first word line to the nth word line WL1 to WLn, respectively.

[0065] In one embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the corresponding string can be stably controlled. Therefore, the reliability of the data stored in memory block 110 can be improved.

[0066] The drain select transistor (DST) of each string can be coupled between the corresponding bit line and memory cells MC1 to MCn. The DSTs of strings arranged in the row direction can be coupled to drain select lines extending along the row direction. The DSTs of strings ST11 to ST1m in the first row can be coupled to the first drain select line DSL1. The DSTs of strings ST21 to ST2m in the second row can be coupled to the second drain select line DSL2.

[0067] Figure 5 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0068] Figure 6 This is a signal waveform diagram used to illustrate a method of operating a memory device according to an embodiment of the present disclosure.

[0069] Reference Figures 2 to 6 A method for operating a memory device according to an embodiment of the present disclosure is described.

[0070] In embodiments of this disclosure, programming operations for the memory device will be described below.

[0071] At step S510, the programming voltage Vpgm can be applied to the selected word lines Sel and WL. For example, the voltage generation circuit 210 can generate and output a first pass voltage Vpass1, and the line decoder 220 can apply the first pass voltage Vpass1 to the word lines WL1 to WLn of the selected memory block (e.g., MB1). Subsequently, the voltage generation circuit 210 can generate and output the programming voltage Vpgm, and the line decoder 220 can apply the programming voltage Vpgm to the selected word lines Sel and WL (e.g., WL2) of the selected memory block MB1. Here, the first pass voltage Vpass1 is applied to the unselected word lines WL1 and WL3 to WLn among the word lines WL1 to WLn.

[0072] In step S520, after the potential of the selected word line Sel WL has decreased to the first level V1, the selected word line Sel WL is allowed to float. For example, the line decoder 220 can decrease the potential of the selected word line Sel WL to the first level V1. For example, the first level V1 can be ground. Subsequently, the line decoder 220 can control the selected word line Sel WL to float.

[0073] At step S530, the potential of the floating selected word line Sel WL can be reduced to the preparatory level Vpre by reducing the potential of the word line Adj WLs adjacent to the selected word line Sel WL to the level of the second pass voltage Vpass2. The adjacent word lines Adj WLs can include word lines adjacent to the selected word line Sel WL in the direction of the source line SL, and word lines adjacent to the selected word line Sel WL in the direction of bit lines BL1 to BLm. For example, the voltage generation circuit 210 can generate and output a second pass voltage Vpass2 that is a set voltage ΔV lower than the first pass voltage Vpass1, and the line decoder 220 can apply the second pass voltage Vpass2 to the unselected word lines including the adjacent word lines Adj WLs. As the potential of the adjacent word line Adj WLs decreases from the potential of the first pass voltage Vpass1 to the potential of the second pass voltage Vpass2, due to the coupling with the adjacent word line Adj WLs (e.g., through capacitive coupling between the selected word line Sel WL and the adjacent word line Adj WLs), the potential of the selected word line Sel WL can decrease to a preparatory level Vpre that is lower than the first level V1.

[0074] At step S540, a first verification voltage Vverify1 with a target level can be applied to the selected word line SelWL. For example, the first verification voltage Vverify1 can be a negative voltage (i.e., a voltage lower than the first level V1 or the second verification voltage Vverify2). For example, the voltage generation circuit 210 can generate and output the first verification voltage Vverify1, and the line decoder 220 can apply the first verification voltage Vverify1 to the selected word line SelWL. The potential of the selected word line SelWL can be adjusted to a preparatory level Vpre at step S530, and then can be adjusted (e.g., easily and quickly) to the level of the first verification voltage Vverify1, which is the target level.

[0075] In the state where the first verification voltage Vverify1 is applied to the selected word line Sel WL, the page buffer group 230 can perform a verification operation corresponding to the first verification voltage Vverify1 for the programming state by sensing the potential level or current of the bit lines BL1 to BLm.

[0076] At step S550, the second verification voltage Vverify2 and the third verification voltage Vverify3 can be sequentially applied to the selected word line SelWL. When the second verification voltage Vverify2 is applied to the selected word line SelWL, the page buffer group 230 can perform a verification operation corresponding to the second verification voltage Vverify2 for the programming state by sensing the potential level or current of bit lines BL1 to BLm. Furthermore, when the third verification voltage Vverify3 is applied to the selected word line SelWL, the page buffer group 230 can perform a verification operation corresponding to the third verification voltage Vverify3 for the programming state by sensing the potential level or current of bit lines BL1 to BLm.

[0077] Figure 7 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0078] Figure 8 This is a signal waveform diagram used to illustrate a method of operating a memory device according to an embodiment of the present disclosure.

[0079] The following will refer to Figures 2 to 4 , Figure 7 and Figure 8 A method for operating a memory device according to an embodiment of the present disclosure is described.

[0080] In one embodiment of this disclosure, the programming operation of the memory device will be described below.

[0081] At step S710, the programming voltage Vpgm can be applied to the selected word lines Sel and WL. For example, the voltage generation circuit 210 can generate and output a first pass voltage Vpass1, and the line decoder 220 can apply the first pass voltage Vpass1 to the word lines WL1 to WLn of the selected memory block (e.g., MB1). Subsequently, the voltage generation circuit 210 can generate and output the programming voltage Vpgm, and the line decoder 220 can apply the programming voltage Vpgm to the selected word lines Sel and WL (e.g., WL2) of the selected memory block MB1. Here, the first pass voltage Vpass1 is applied to the unselected word lines WL1 and WL3 to WLn among the word lines WL1 to WLn.

[0082] In step S720, the potential of the selected word line Sel WL can be reduced to a first level V1, and the potential of the word line Adj WLs adjacent to the selected word line Sel WL can be increased to a second level V2. The second level V2 is higher than the potential of the first pass voltage Vpass1. The adjacent word lines Adj WLs can include word lines adjacent to the selected word line Sel WL in the direction of the source line SL, and word lines adjacent to the selected word line Sel WL in the direction of the bit lines BL1 to BLm. For example, the line decoder 220 can reduce the potential of the selected word line Sel WL to the first level V1. For example, the first level V1 can be a ground level. The voltage generation circuit 210 can generate and output a voltage with the second level V2, and the line decoder 220 can apply the voltage with the second level V2 to the adjacent word lines Adj WLs. Here, the first pass voltage Vpass1 can be continuously applied to the remaining unselected word lines.

[0083] At step S730, the selected word line Sel WL can be allowed to float, and a second pass voltage Vpass2 can be applied to the adjacent word line Adj WLs, thus reducing the potential of the selected word line Sel WL. Therefore, the potential of the floating selected word line Sel WL can be reduced to a preparatory level Vpre, which is lower than the first level V1.

[0084] For example, the line decoder 220 can control the selected word line Sel WL to float. Subsequently, the voltage generation circuit 210 can generate and output a second pass voltage Vpass2 that is lower than the first level V1 by a set voltage ΔV, and the line decoder 220 can apply the second pass voltage Vpass2 to the unselected word lines, including the adjacent word lines Adj WLs. As the potential of the adjacent word lines Adj WLs decreases from the first level V1 to the potential of the second pass voltage Vpass2, the potential of the selected word line Sel WL can decrease to a preparatory level Vpre that is lower than the first level V1 due to coupling with the adjacent word lines Adj WLs.

[0085] At step S740, a first verification voltage Vverify1 with a target level can be applied to the selected word line SelWL. For example, the first verification voltage Vverify1 can be a negative voltage (i.e., a voltage lower than the first level V1 or the second verification voltage Vverify2). For example, the voltage generation circuit 210 can generate and output the first verification voltage Vverify1, and the line decoder 220 can apply the first verification voltage Vverify1 to the selected word line SelWL. The potential of the selected word line SelWL can be adjusted to a preparatory level Vpre at step S730, and then can be adjusted (e.g., easily and quickly) to the level of the first verification voltage Vverify1, which is the target level.

[0086] In the state where the first verification voltage Vverify1 is applied to the selected word line Sel WL, the page buffer group 230 can perform a verification operation corresponding to the first verification voltage Vverify1 for the programming state by sensing the potential level or current of the bit lines BL1 to BLm.

[0087] At step S750, the second verification voltage Vverify2 and the third verification voltage Vverify3 can be sequentially applied to the selected word line SelWL. When the second verification voltage Vverify2 is applied to the selected word line SelWL, the page buffer group 230 can perform a verification operation corresponding to the second verification voltage Vverify2 for the programming state by sensing the potential level or current of bit lines BL1 to BLm. Furthermore, when the third verification voltage Vverify3 is applied to the selected word line SelWL, the page buffer group 230 can perform a verification operation corresponding to the third verification voltage Vverify3 for the programming state by sensing the potential level or current of bit lines BL1 to BLm.

[0088] Figure 9This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0089] Figure 10 This is a signal waveform diagram used to illustrate a method of operating a memory device according to an embodiment of the present disclosure.

[0090] The following will refer to Figures 2 to 4 , Figure 9 and Figure 10 A method for operating a memory device according to an embodiment of the present disclosure is described.

[0091] In one embodiment of this disclosure, a read operation of the memory device will be described below.

[0092] At step S910, a first pass voltage can be applied to multiple word lines WL1 to WLn of the selected memory block (e.g., MB1). For example, voltage generation circuit 210 can generate and output the first pass voltage Vpass1, and line decoder 220 can apply the first pass voltage Vpass1 to word lines WL1 to WLn of the selected memory block (e.g., MB1).

[0093] At step S920, the potential of the selected word line Sel WL can be reduced to a first level V1, after which the selected word line Sel WL can be allowed to float. For example, the line decoder 220 can discharge the potential level of the selected word line Sel WL to the first level V1, which is a ground level, after which the selected word line Sel WL can be allowed to float.

[0094] At step S930, the potential of the selected word line Sel WL can be reduced by applying a second through voltage Vpass2, which is lower than the first through voltage Vpass1 by a set voltage ΔV, to the word lines Adj WLs adjacent to the selected word line Sel WL. Therefore, the potential of the floating selected word line Sel WL can be reduced to a preparatory level Vpre, which is lower than the first level V1. The adjacent word lines Adj WLs can include word lines adjacent to the selected word line Sel WL in the direction of the source line SL, and word lines adjacent to the selected word line Sel WL in the direction of bit lines BL1 to BLm.

[0095] For example, voltage generation circuit 210 can generate and output a second pass voltage Vpass2 that is lower than a set voltage ΔV by the first pass voltage Vpass1, and line decoder 220 can apply the second pass voltage Vpass2 to the unselected word lines, including adjacent word lines Adj WLs. As the potential of the adjacent word lines Adj WLs decreases from the potential of the first pass voltage Vpass1 to the potential of the second pass voltage Vpass2, the potential of the selected word line Sel WL can decrease to a preparatory level Vpre that is lower than the first level V1 due to coupling with the adjacent word lines Adj WLs.

[0096] At step S940, a first read voltage Vread1 having a target level can be applied to the selected word line SelWL. For example, the first read voltage Vread1 can be a negative voltage (i.e., a voltage lower than the first level V1 or the second read voltage Vread2). For example, the voltage generation circuit 210 can generate and output the first read voltage Vread1, and the line decoder 220 can apply the first read voltage Vread1 to the selected word line SelWL. The selected word line SelWL can be adjusted to a preparatory level Vpre at step S930, and then can be adjusted (e.g., easily and quickly) to the level of the first read voltage Vread1, which is the target level.

[0097] In the state where the first read voltage Vread1 is applied to the selected word line Sel WL, the page buffer group 230 can perform a data read operation corresponding to the first read voltage Vread1 by sensing the potential level or current of the bit lines BL1 to BLm.

[0098] At step S950, the second read voltage Vread2 and the third read voltage Vread3 can be sequentially applied to the selected word line SelWL. When the second read voltage Vread2 is applied to the selected word line SelWL, the page buffer group 230 can perform a read operation corresponding to the second read voltage Vread2 by sensing the potential level or current of bit lines BL1 to BLm. Furthermore, when the third read voltage Vread3 is applied to the selected word line SelWL, the page buffer group 230 can perform a read operation corresponding to the third read voltage Vread3 by sensing the potential level or current of bit lines BL1 to BLm.

[0099] Figure 11 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0100] Figure 12 This is a signal waveform diagram used to illustrate a method of operating a memory device according to an embodiment of the present disclosure.

[0101] Reference Figures 2 to 4 , Figure 11 and Figure 12 A method for operating a memory device according to an embodiment of the present disclosure is described.

[0102] In one embodiment of this disclosure, a read operation of the memory device will be described below.

[0103] At step S1110, a first read voltage Vread1 can be applied to the selected word line Sel WL, and a first pass voltage Vpass1 can be applied to the unselected word lines WL1 to WLn, including adjacent word lines Adj WLs. Adjacent word lines Adj WLs can include word lines adjacent to the selected word line Sel WL in the direction of the source line SL, and word lines adjacent to the selected word line Sel WL in the direction of bit lines BL1 to BLm.

[0104] In the state where the first read voltage Vread1 is applied to the selected word line Sel WL, the page buffer group 230 can perform a data read operation corresponding to the first read voltage Vread1 by sensing the potential level or current of the bit lines BL1 to BLm.

[0105] At step S1120, the selected word line Sel WL can be allowed to float, and subsequently, a second pass voltage Vpass2, which is higher than the first pass voltage Vpass1 by a set voltage ΔV11, can be applied to the adjacent word line Adj WLs. Therefore, the potential of the floating selected word line Sel WL increases to a first preparatory level Vpre1, which is higher than the potential of the first read voltage Vread1.

[0106] For example, voltage generation circuit 210 can generate and output a second pass voltage Vpass2 that is higher than the first pass voltage Vpass1 by a set voltage ΔV11, and line decoder 220 can apply the second pass voltage Vpass2 to adjacent word lines AdjWLs. As the potential of adjacent word lines AdjWLs increases from the potential of the first pass voltage Vpass1 to the potential of the second pass voltage Vpass2, due to coupling with adjacent word lines AdjWLs, the potential of the selected word line SelWL can increase to a first preparatory level Vpre1 ​​that is higher than the potential of the first read voltage Vread1.

[0107] Here, the first pass voltage Vpass1 or the second pass voltage Vpass2 can be applied to the remaining unselected word lines, except for the adjacent word lines Adj WLs.

[0108] At step S1130, a second read voltage Vread2 can be applied to the selected word line Sel WL. For example, the voltage generation circuit 210 can generate and output a second read voltage Vread2 that is higher than the first read voltage Vread1, and the line decoder 220 can apply the second read voltage Vread2 to the selected word line Sel WL. Since the potential of the selected word line Sel WL increases from a first preparatory level Vpre1 ​​(which is higher than the potential of the first read voltage Vread1) to the potential of the second read voltage Vread2, the potential of the selected word line Sel WL can increase (e.g., increase rapidly) to the target level.

[0109] When the second read voltage Vread2 is applied to the selected word line Sel WL, the page buffer group 230 can perform a data read operation corresponding to the second read voltage Vread2 by sensing the potential level or current of the bit lines BL1 to BLm.

[0110] At step S1140, the selected word line Sel WL can be allowed to float, and subsequently, a third pass voltage Vpass3, which is higher than the second pass voltage Vpass2 by a set voltage ΔV12, can be applied to the adjacent word line Adj WLs. Therefore, the potential of the floating selected word line Sel WL can be increased to a second preparatory level Vpre2, which is higher than the potential of the second read voltage Vread2.

[0111] For example, voltage generation circuit 210 can generate and output a third pass voltage Vpass3 that is higher than the second pass voltage Vpass2 by a set voltage ΔV12, and line decoder 220 can apply the third pass voltage Vpass3 to adjacent word lines AdjWLs. As the potential of adjacent word lines AdjWLs increases from the potential of the second pass voltage Vpass2 to the potential of the third pass voltage Vpass3, due to coupling with adjacent word lines AdjWLs, the potential of the selected word line SelWL can increase to a second preparatory level Vpre2 that is higher than the potential of the second read voltage Vread2.

[0112] Here, the first pass voltage Vpass1 or the third pass voltage Vpass3 can be applied to the remaining unselected word lines, except for the adjacent word lines Adj WLs.

[0113] At step S1150, a third read voltage Vread3 can be applied to the selected word line Sel WL. For example, the voltage generation circuit 210 can generate and output a third read voltage Vread3 that is higher than the second read voltage Vread2, and the line decoder 220 can apply the third read voltage Vread3 to the selected word line Sel WL. Since the potential of the selected word line Sel WL increases from a second preparatory level Vpre2 (which is higher than the second read voltage Vread2) to the potential of the third read voltage Vread3, the potential of the selected word line Sel WL can increase (e.g., increase rapidly) to the target level.

[0114] When the third read voltage Vread3 is applied to the selected word line Sel WL, the page buffer group 230 can perform a data read operation corresponding to the third read voltage Vread3 by sensing the potential level or current of the bit lines BL1 to BLm.

[0115] In the above embodiments of this disclosure, although it has been described that the potential of adjacent word lines Adj WLs has been increased by set voltages ΔV11 and ΔV12 at steps S1120 and S1140, this disclosure may increase the potential of adjacent word lines Adj WLs by different voltages at steps S1120 and S1140.

[0116] In the above embodiments of this disclosure, although the read operation has been described by way of example, it can be applied in the same way to the verification operation included in the programming operation.

[0117] Figure 13 This is a diagram illustrating one embodiment of a memory system.

[0118] refer to Figure 13 The memory system 30000 can be implemented as, for example, a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. Under the control of the processor 3100, the memory controller 1200 can control data access operations of the memory device 1100, such as programming, erasing, or reading operations.

[0119] Under the control of the memory controller 1200, the data programmed into the memory device 1100 can be output via the display 3200.

[0120] Radio transceiver 3300 can exchange radio signals via antenna ANT. For example, radio transceiver 3300 can convert radio signals received via antenna ANT into signals that can be processed by processor 3100. Therefore, processor 3100 can process the signals output from radio transceiver 3300 and can transmit the processed signals to memory controller 1200 or display 3200. Memory controller 1200 can program the signals processed by processor 3100 into memory device 1100. In addition, radio transceiver 3300 can convert signals output from processor 3100 into radio signals and output the radio signals to external devices via antenna ANT. Input device 3400 can be used to input control signals for controlling the operation of processor 3100 or data to be processed by processor 3100. Input device 3400 can be implemented as a pointing device (such as a touchpad or computer mouse), keypad, or keyboard. The processor 3100 can control the operation of the display 3200 so that data output from the memory controller 1200, data output from the radio transceiver 3300, or data output from the input device 3400 can be output via the display 3200.

[0121] In one embodiment, the memory controller 1200, capable of controlling the operation of the memory device 1100, can be implemented as part of the processor 3100 or as a separate chip from the processor 3100. Furthermore, the memory controller 1200 can be... Figure 1 The memory controller 1200 illustrated in the figure can be implemented as an example, and the memory device 1100 can be implemented through... Figure 2 An example of the memory device 1100 shown in the figure is used for implementation.

[0122] Figure 14 This is a diagram illustrating one embodiment of a memory system.

[0123] refer to Figure 14 The memory system 40000 can be implemented in, for example, personal computers, tablet PCs, netbooks, e-readers, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, or MP4 players.

[0124] The memory system 40000 may include a memory device 1100 and a memory controller 1200, the memory controller 1200 being able to control the data processing operations of the memory device 1100.

[0125] The processor 4100 can output data stored in the memory device 1100 via the display 4300 based on data input through the input device 4200. For example, the input device 4200 can be implemented as a pointing device (such as a touchpad or computer mouse), a keypad, or a keyboard.

[0126] The processor 4100 can control the overall operation of the memory system 40000 and can also control the operation of the memory controller 1200. In one embodiment, the memory controller 1200, which is capable of controlling the operation of the memory device 1100, can be implemented as part of the processor 4100 or as a separate chip provided from the processor 4100. Furthermore, the memory controller 1200 can... Figure 1 The memory controller 1200 illustrated in the figure can be implemented as an example, and the memory device 1100 can be implemented through... Figure 2 An example of the memory device 1100 shown in the figure is used for implementation.

[0127] Figure 15 This is a diagram illustrating one embodiment of a memory system.

[0128] refer to Figure 15 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet PC equipped with a digital camera.

[0129] The memory system 50000 may include a memory device 1100 and a memory controller 1200, the memory controller 1200 being able to control data processing operations of the memory device 1100, such as programming operations, erasing operations, or reading operations.

[0130] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals, and the converted digital signals can be transmitted to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signals can be output via the display 5300, or stored in the memory device 1100 via the memory controller 1200. Furthermore, under the control of the processor 5100 or the memory controller 1200, the data stored in the memory device 1100 can be output via the display 5300.

[0131] In one embodiment, the memory controller 1200, capable of controlling the operation of the memory device 1100, may be implemented as part of the processor 5100 or as a separate chip from the processor 5100. Furthermore, the memory controller 1200 can be... Figure 1The memory controller 1200 illustrated in the figure can be implemented as an example, and the memory device 1100 can be implemented through... Figure 2 An example of the memory device 1100 shown in the figure is used for implementation.

[0132] Figure 16 This is a diagram illustrating one embodiment of a memory system.

[0133] refer to Figure 16 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

[0134] The memory controller 1200 can control data exchange between the memory device 1100 and the card interface 7100. In one embodiment, the card interface 7100 may be, but is not limited to, a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface. Furthermore, the memory controller 1200 can... Figure 1 The memory controller 1200 illustrated in the figure can be implemented as an example, and the memory device 1100 can be implemented through... Figure 2 An example of the memory device 1100 shown in the figure is used for implementation.

[0135] Furthermore, according to the protocol of host 60000, card interface 7100 can exchange data between host 60000 and memory controller 1200. In one embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Here, card interface 7100 can refer to hardware capable of supporting protocols used by host 60000, software installed in the hardware, or signal transmission methods executed by the hardware.

[0136] When the memory system 70000 is coupled to the host interface 6200 of the host 60000 (such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box), under the control of the microprocessor 6100, the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200.

[0137] This disclosure uses the coupling phenomenon between the selected word line and its adjacent word lines to adjust the potential of the selected word line, and then adjusts the potential of the selected word line to a target potential, thereby adjusting (e.g., rapidly adjusting) the potential of the selected word line to a potential corresponding to the target level.

[0138] In the embodiments discussed above, all steps may be selectively performed or skipped. Furthermore, the steps in each embodiment may not always be performed sequentially, and may be performed randomly. Moreover, the embodiments disclosed in this specification and accompanying drawings are intended to help those skilled in the art to better understand this disclosure, and are not intended to limit the scope of this disclosure. In other words, those skilled in the art to which this disclosure pertains will be able to readily understand that various modifications are possible based on the technical scope of this disclosure.

[0139] The methods, processes, and / or operations described herein can be executed by code or instructions to be executed by a computer, processor, controller, or other signal processing device (such as the memory controller 1200 described above). The computer, processor, controller, or other signal processing device can be the computer, processor, controller, or other signal processing device described herein, or elements other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0140] When implemented at least in part as software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features (such as the memory controller 1200 described above) may include, for example, memory or other storage devices for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device.

Claims

1. A memory device, comprising: A memory block comprises multiple memory cells; as well as The peripheral circuitry is configured to apply multiple operating voltages to multiple word lines of the memory block during programming operations. During the verification operation included in the programming operation, the peripheral circuitry is configured to: allow a selected word line among the plurality of word lines to float, and reduce the potential of the selected word line to a preparatory level by reducing the potential of the word line adjacent to the selected word line.

2. The memory device of claim 1, wherein during the verification operation, the peripheral circuitry is configured to: Reduce the potential of the selected word line to a first level; The selected word line is allowed to float; as well as While the selected word line is floating, the potential of the adjacent word line is reduced from a first pass voltage level to a second pass voltage level, the second pass voltage level being a set voltage lower than the first pass voltage level.

3. The memory device of claim 1, wherein during the verification operation, the peripheral circuitry is configured to: The potential of the selected word line is reduced to a first level, and the potential of the adjacent word line is controlled to a second level; Allow the selected word line to float; as well as While the selected word line is floating, the potential of the adjacent word line is reduced from the second level to a pass voltage level, which is a set voltage lower than the second level.

4. The memory device of claim 1, wherein the potential of the floating selected word line is reduced to the preparatory level based on coupling with the adjacent word line.

5. The memory device of claim 1, wherein the peripheral circuitry is configured to sequentially apply one or more verification voltages to the selected word line after the potential of the selected word line has decreased to the preparatory level.

6. The memory device of claim 5, wherein, in the one or more verification voltages, the first verification voltage is a negative voltage.

7. A memory device, comprising: A memory block comprises multiple memory cells; as well as The peripheral circuitry is configured to apply multiple operating voltages to multiple word lines of the memory block during a read operation. During the read operation, the peripheral circuitry is configured to allow a selected word line among the plurality of word lines to float, and to reduce the potential of the selected word line to a preparatory level by reducing the potential of the word line adjacent to the selected word line.

8. The memory device of claim 7, wherein during the read operation, the peripheral circuitry is configured to: Reduce the potential of the selected word line to a first level; Allow the selected word line to float; as well as While the selected word line is floating, the potential of the adjacent word line is reduced from a first pass voltage level to a second pass voltage level, the second pass voltage being a set voltage lower than the first pass voltage.

9. The memory device of claim 7, wherein the potential of the floating selected word line is reduced to the preparatory level based on coupling with the adjacent word line.

10. The memory device of claim 7, wherein the peripheral circuitry is configured to sequentially apply one or more read voltages to the selected word line after the potential of the selected word line has decreased to the preparatory level.

11. The memory device of claim 10, wherein, among the one or more read voltages, the first read voltage is a negative voltage.

12. A memory device, comprising: A memory block comprises multiple memory cells; as well as The peripheral circuitry is configured to apply multiple operating voltages to multiple word lines of the memory block during a read operation. During the read operation, the peripheral circuitry is configured to allow a selected word line among the plurality of word lines to float, and to increase the potential of the selected word line to a first preparatory level by increasing the potential of the word line adjacent to the selected word line.

13. The memory device of claim 12, wherein the peripheral circuitry is configured to: A first read operation is performed by applying a first read voltage to the selected word line having the first preparatory level; and After the first read operation, the selected word line is allowed to float, and the potential of the selected word line is increased to a second preparatory level higher than the first read voltage by increasing the potential of the adjacent word lines.

14. A method of operating a memory device, comprising: A programming voltage is applied to the selected word line, and a first pass voltage is applied to the word line adjacent to the selected word line; Reduce the potential of the selected word line to a first level; Allow the selected word line to float; as well as While the selected word line is floating, the potential of the adjacent word line is reduced by applying a second through voltage, which is lower than the first through voltage, to the adjacent word line. Based on the coupling with the adjacent word line, the potential of the floating selected word line is set to a preparatory level that is lower than the first level.

15. The method of claim 14, further comprising: One or more verification voltages are sequentially applied to the selected word line.

16. The method of claim 15, wherein in the one or more verification voltages, the first verification voltage is a negative voltage.

17. A method of operating a memory device, comprising: Apply the first voltage to multiple word lines; Reduce the potential of the selected word line among the plurality of word lines to a first level; Allow the selected word line to float; as well as While the selected word line is floating, the potential of the adjacent word lines is reduced by applying a second through voltage, which is lower than the first through voltage, to the word lines adjacent to the selected word line among the plurality of word lines. Based on the coupling with the adjacent word line, the potential of the floating selected word line is set to a preparatory level that is lower than the first level.

18. The method of claim 17, further comprising: One or more read voltages are sequentially applied to the selected word line.

19. The method of claim 18, wherein in the one or more read voltages, the first read voltage is a negative voltage.

20. A method of operating a memory device, comprising: A first read voltage is applied to the selected word line, and a first pass voltage is applied to the word line adjacent to the selected word line; The selected word line is allowed to float, and the potential of the floating selected word line is increased to a first preparatory level higher than the first read voltage by applying a second pass voltage higher than the first pass voltage to the adjacent word line. as well as A second read voltage, which is higher than the first read voltage, is applied to the selected word line.

21. The method of claim 20, further comprising: The selected word line is allowed to float, and the potential of the floating selected word line is increased to a second preparatory level higher than the second read voltage by applying a third pass voltage higher than the second pass voltage to the adjacent word line. as well as A third read voltage, which is higher than the second read voltage, is applied to the selected word line.

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