Test system and test method

Abstract

A test system is disclosed. The test system includes a test machine, a first voltage stabilization circuit and a device to be tested. The test machine generates a first operating voltage and a control signal. The first voltage stabilization circuit transmits a second operating voltage associated with the first operating voltage to a socket board. The device to be tested is actuated using the second operating voltage received through the socket board. The first voltage stabilization circuit is also used to control the second operating voltage to have a first voltage potential according to the control signal when the device to be tested is actuated. A test method is also disclosed herein. The test system and test method proposed in this case stabilize the operating voltage of a high-speed low-power memory, and accordingly provide a wide output gating window for the low-power memory device.

Description

Technical Field

[0001] The present invention relates to a testing system and a testing method, and more particularly to a testing system and a testing method for compensating the operating voltage of a memory device. Background Art

[0002] Low power double data rate memory (LPDDR) has been widely used in memory devices for better power performance. This type of memory operates at a relatively low voltage as opposed to the traditional operating voltage (e.g., 2.5 volts). In some methods, when performing high-speed testing, such as a read operation on an LPDDR device, the voltage drop caused by the surge current (read / write) required in the LPDDR device causes the output strobe (pass) window to shrink. Summary of the invention

[0003] One embodiment of the present invention is a test system, which includes a tester, a first voltage stabilization circuit, and a device to be tested. The tester generates a first operating voltage and a control signal. The first voltage stabilization circuit transmits a second operating voltage related to the first operating voltage to a socket board. The device to be tested is actuated using the second operating voltage received through the socket board. The first voltage stabilization circuit is also used to control the second operating voltage to have a first voltage potential according to the control signal when the device to be tested is actuated.

[0004] In some embodiments, the first voltage potential is equal to a voltage potential of the first operating voltage.

[0005] In some embodiments, the first voltage stabilization circuit is further used to compare the second operating voltage with an initial voltage, the initial voltage being indicated by a control signal, and the first voltage stabilization circuit is further used to adjust the voltage potential of the second operating voltage to have a first voltage potential equal to the first operating voltage in response to the comparison.

[0006] In some embodiments, the first voltage stabilization circuit includes a comparison circuit for comparing the second operating voltage with an initial voltage indicated by a control signal and used to generate a feedback signal; and an adjustment circuit for raising the voltage potential of the second operating voltage to the first voltage potential according to the feedback signal.

[0007] In some embodiments, the first voltage potential is equal to a voltage potential of the first operating voltage.

[0008] In some embodiments, the test system further includes a test interface board electrically coupled to the test machine, wherein the first voltage stabilization circuit and the socket board are integrated in the test interface board.

[0009] In some embodiments, the test system further includes a plurality of first power supplies for generating a first operating voltage to a first voltage stabilization circuit; a second voltage stabilization circuit for transmitting a third operating voltage to a device to be tested through a socket board; and a plurality of second power supplies for generating a fourth operating voltage to the second voltage stabilization circuit to generate a third operating voltage.

[0010] In some embodiments, the second voltage stabilization circuit includes an adjustment circuit for adjusting the voltage potential of the third operating voltage to a second voltage potential, and the second voltage potential is equal to the fourth operating voltage.

[0011] In some embodiments, the test system further includes a second voltage stabilization circuit for transmitting a third operating voltage to the socket board and for controlling a voltage potential of the third operating voltage to be the same as a fourth operating voltage, wherein the third operating voltage is associated with the fourth operating voltage received by the second voltage stabilization circuit.

[0012] In some embodiments, the device under test is a low power double data rate memory device.

[0013] Another embodiment of the present case is related to a testing method, comprising the following steps: operating the device to be tested at a first operating voltage; comparing the voltage potential of the first operating voltage with a first initial voltage through a first comparison circuit; and when the voltage potential of the first operating voltage is different from the first initial voltage, adjusting the voltage potential of the first operating voltage to have the first initial voltage through a first adjustment circuit.

[0014] In some embodiments, the testing method further includes generating a second operating voltage to the voltage stabilization circuit through at least one power supply to generate the first operating voltage, wherein a voltage potential of the second operating voltage is equal to the first initial voltage.

[0015] In some embodiments, the testing method further includes generating a feedback signal to a first adjustment circuit through a first comparison circuit in response to the comparison; and raising a voltage level of the first operating voltage through the first adjustment circuit.

[0016] In some embodiments, the testing method further includes operating the device to be tested at a second operating voltage different from the first operating voltage; and controlling the voltage potential of the second operating voltage through a voltage stabilization circuit to be equal to a second initial voltage, wherein the second initial voltage is provided to the voltage stabilization circuit by a testing machine.

[0017] In some embodiments, the testing method further includes operating the device to be tested at a second operating voltage; comparing the voltage potential of the second operating voltage with a second initial voltage different from the first initial voltage through a second comparison circuit; and adjusting the voltage potential of the second operating voltage to have a second initial voltage through a second adjustment circuit in response to the comparison.

[0018] In some embodiments, adjusting the voltage potential of the first operating voltage includes increasing the voltage potential of the first operating voltage by a first adjustment circuit when the voltage potential of the first operating voltage is less than the first initial voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] An embodiment of the present invention is described in the accompanying Figure 1 The following detailed description is best understood when read together. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0020] Figure 1 is a diagram of a test system according to some embodiments.

[0021] Figure 2 According to another embodiment Figure 1 Diagram of the test system.

[0022] Figure 3 is a diagram of a test system according to some embodiments.

[0023] Figure 4 is a diagram of a test system according to some embodiments.

[0024] Figure 5 is a flow chart of a testing method according to some embodiments. DETAILED DESCRIPTION

[0025] The spirit of the present invention will be discussed in the following drawings and detailed description, and those skilled in the art will be able to change and modify the disclosure of the present invention without departing from the spirit and scope of the present invention.

[0026] It should be understood that, in this document and in the claims, when an element is considered to be "connected" or "coupled" to another element, it can refer to being directly connected or coupled to another element, and there may be other parts in between. Conversely, when an element is considered to be "directly connected" or "directly coupled" to another element, there will be no other elements in between. In addition, "electrically connected" or "connected" can be used to indicate that two or more elements operate or act on each other.

[0027] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the embodiment.

[0028] It should be understood that the terms "comprising," "including," "having," "having," etc. used herein are open ended and mean "including, but not limited to."

[0029] It should be understood that “and / or” used herein includes any and all combinations of one or more associated items.

[0030] It should be understood that, in this document and the appended claims, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the present case, and will not be interpreted in an idealized manner. Or overly formal meaning, unless explicitly defined herein.

[0031] Please refer to Figure 1 , Figure 1 FIG. 1 is a diagram of a test system 10 according to some embodiments. For illustration, the test system 10 includes a test machine 100 and a test interface board 200. In some embodiments, the test system 10 is implemented by automatic test equipment (ATE) that automatically tests a device under test (DUT) 300. The test machine 100 includes, for example, a microcomputer or a microprocessor-based system. Figure 1 As shown, the test machine 100 is electrically connected to the test interface board 200 and is used to generate an operating voltage V1, a control signal CS, and a test pattern TP to the test interface board 200 to test the device under test 300. In some embodiments, the test machine 100 includes a programmable power supply (PPS, not shown) or multiple power supplies (not shown) to generate the operating voltage V1.

[0032] For illustration, the test system 10 further includes a voltage stabilization circuit 210 and a device socket board 220. In some embodiments, the device to be tested 300 is mounted on a socket (not shown) of the device socket board 220. The voltage stabilization circuit 210 and the device socket board 220 are integrated into the test interface board 200. In some embodiments, the device socket board 220 is implemented by a device specific adapter (DSA) and is designed according to the type of the device to be tested 300. When the type of the device to be tested 300 is changed, the device socket board 220 is replaced by a socket board corresponding to the changed type of the device to be tested 300. Furthermore, the device socket board 220 includes at least one test module (not shown).

[0033] In some embodiments, the test machine 100 reads an external server (not shown) through, for example, a PCI interface (not shown). The external server provides a required user interface (or alternatively, predetermined) to provide an environment for a user to create a suitable test program for the characteristics of the device under test 300 to be tested. Further, the server provides a user interface to transmit the test program to the test machine 100 and receive the test results from the test machine 100 to analyze the test results. In some embodiments, the test machine 100 compares the output of the device under test 300 with the expected value to determine the error of the device under test 300. In some embodiments, the server is a processing device, such as a personal computer, a desktop device, a handheld mobile device, a microprocessor, a system based on a microprocessor or a programmable consumer electronic device, a minicomputer, a mainframe computer and / or a personal mobile computing device, but the feasible embodiments are not limited to the above.

[0034] Continued reference Figure 1 In operation, the voltage stabilization circuit 210 and the device socket board 220 are used to transmit signals through the test interface board 200. For example, during testing, the tester 100 inputs the test pattern TP to the device under test 300 through the device socket board 220 of the test interface board 200. The tester 100 also transmits the control signal CS and the operating voltage V1 to the test interface board 200, and the voltage stabilization circuit 210 is used to transmit the operating voltage V2 to the device socket board 220, wherein the operating voltage V2 is associated with the operating voltage V1, so that the device under test 300 is used to operate at the operating voltage V2 received through the device socket board 220. When the device under test 300 is actuated under the test condition, the voltage stabilization circuit 210 is also used to control the operating voltage V2 to have a specific voltage potential according to the control signal CS.

[0035] As described above, in some embodiments, the voltage stabilization circuit 210 controls the operating voltage V2 to have a voltage potential equal to the operating voltage V1. For example, the device under test 300 is a low power double data rate memory device (LPDDR), and the device under test 300 is subjected to a high-speed test, for example, 3200 Mbps. The tester 100 generates a voltage potential of the operating voltage V1 of approximately 1.14 volts to the voltage stabilization circuit 210 through the test interface board 200, and the voltage stabilization circuit 210 also transmits the operating voltage V2 of approximately 1.14 volts to the device under test 300 through the device socket board 220 of the test interface board 200.

[0036] In addition, in some embodiments, the voltage stabilization circuit 210 is further configured to compare the operating voltage V2 with an initial voltage, the initial voltage being indicated by the control signal CS, and the voltage stabilization circuit 210 is configured to adjust the operating voltage V2 to have a voltage potential equal to the operating voltage V1 in response to the comparison. For example, in the embodiment discussed previously, the control signal CS indicates that the initial voltage is approximately 1.14 volts. Therefore, the voltage stabilization circuit 210 compares the operating voltage V2 with the initial voltage. When the voltage potential of the operating voltage V2 is different from the initial voltage, for example, the initial voltage is approximately 1.12 volts, then in response to the comparison, the voltage stabilization circuit 210 adjusts the operating voltage V2 to approximately 1.14 volts.

[0037] For illustration, the voltage stabilization circuit 210 includes a comparison circuit 211 and an adjustment circuit 212. Figure 1 As shown. In some embodiments, the comparison circuit 211 is used to compare the operating voltage V2 with the initial voltage, the initial voltage is indicated by the control signal CS, and the comparison circuit 211 is used to generate a feedback signal FS to the adjustment circuit 212. The adjustment circuit 212 is used to adjust the voltage level V2 of the operating voltage V2 to a voltage level having the initial voltage according to the feedback signal FS. For example, when the operating voltage V2 is equal to the initial voltage, the feedback signal disables the adjustment circuit 212. Conversely, when the operating voltage V2 (e.g., about 1.12 volts) is less than the initial voltage (e.g., about 1.14 volts), the feedback signal FS is used as a logic signal to enable the adjustment circuit 212. The adjustment circuit 212 pulls up the operating voltage V2 from about 1.12 volts to about 1.14 volts according to the feedback signal FS. In other words, using the configuration of the comparison circuit 211 and the adjustment circuit 212 in the voltage stabilization circuit 210, the variation of the voltage level of the operating voltage V2 received by the device under test 300 can be compensated.

[0038] In some embodiments, the comparison circuit 211 and the adjustment circuit 212 include (a plurality of) amplifiers, transistors or other suitable components. In different embodiments, the voltage stabilization circuit 210 is implemented by a voltage regulator.

[0039] In some methods, when a stability test of repeated write and read operations is performed on a DUT that is a LPDDR device, the DUT requires a significantly increased current for operation in a short period of time, which causes a voltage drop in an operating voltage (e.g., one corresponding to the VDD2 voltage in the memory device). Therefore, in some embodiments, an output strobe pass window of the memory device is relatively reduced. For example, when the operating voltage VDD2 is approximately 1.14 volts, the output strobe pass window is approximately 125 picoseconds (i.e., the memory device successfully operates under a configuration where the operating voltage VDD2 is 1.14 volts and the flash time falls within a range of 0.325 nanoseconds to 0.45 nanoseconds). However, when the operating voltage VDD2 drops to approximately 1.13 volts, the output strobe pass window becomes approximately 100 picoseconds (i.e., the memory device successfully operates under a configuration where the operating voltage VDD2 is 1.13 volts and the flash time falls within a range of 0.325 nanoseconds to 0.425 nanoseconds). Furthermore, when the operating voltage VDD2 drops to about 1.11V, the output gating window becomes about 25 picoseconds (ie, the memory device successfully operates under the configuration where the operating voltage VDD2 is 1.11V and the flash time falls within 0.325ns to 0.35ns).

[0040] Compared to these methods, the voltage stabilization circuit 210 compensates for the voltage drop of the operating voltage V2. Therefore, using the configuration of the present invention, the output gating window remains unchanged during the stability test without any loss.

[0041] In addition, in some embodiments, based on some experimental data, the output gating window of the LPDDR device is about 160 picoseconds at a speed of about 3200 Mbps and in conjunction with the voltage stabilization circuit 210 of the present invention, while the output gating window of the LPDDR device without the voltage stabilization circuit 210 is about 130 picoseconds. Therefore, using the configuration of the present invention, the output gating window is improved by about 23% (i.e., (160-130) / 130).

[0042] In various embodiments, based on some experimental data, the output strobe window of the LPDDR device is about 70 picoseconds at a speed of about 4267 Mbps and in conjunction with the voltage stabilization circuit 210 of the present invention. In contrast, the LPDDR device without the voltage stabilization circuit 210 cannot operate under this condition. Therefore, using the configuration of the present invention, the output strobe window is open at about 4267 Mbps.

[0043] Figure 1The configuration and the values ​​of the operating voltage, operating speed, and output gating window are given for the sake of example. Different implementations are also within the scope of the present invention.

[0044] Please refer to Figure 2 , Figure 2 According to another embodiment Figure 1 FIG10 is a diagram of a test system. Figure 1 For ease of understanding, Figure 2 Similar components in the embodiment are marked with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail above will be omitted here.

[0045] and Figure 1 In contrast, the test system 10 further includes a plurality of voltage stabilization circuits 210 and a plurality of device socket boards 220 coupled to a plurality of DUTs 300. In some embodiments, the devices to be tested 300 are tested in the same batch with the same test pattern TP and operate under the reference Figure 2 The operating voltage V2 is shown.

[0046] Figure 2 The configuration is given for illustrative purposes. Figure 2 Various implementations are within the expected scope of an embodiment of the present invention.

[0047] Please refer to Figure 3 , Figure 3 FIG. 1 is a diagram of a test system 30 according to some embodiments. Figure 1 to Figure 2 For ease of understanding, Figure 3 Similar components in the drawings are marked with the same reference numerals.

[0048] like Figure 3 As shown, Figure 2 In contrast, the test system 30 includes power supplies 4101-410n, 4201-420n, and 4301-430n. For illustration, the power supplies 4101-410n are coupled in parallel to each other and used to generate an operating voltage VDD2 to a first circuit in the voltage stabilization circuit 210. The first circuit in the voltage stabilization circuit 210 transmits the operating voltage V2 to the device under test 300 accordingly. Similarly, the power supplies 4201-420n are coupled in parallel to each other and used to generate an operating voltage VDD1 to a second circuit in the voltage stabilization circuit 210. The second circuit in the voltage stabilization circuit 210 transmits the operating voltage V3 to the device under test 300 accordingly. The power supplies 4301-430n are coupled in parallel to each other and used to generate an operating voltage VDDQ to a third circuit in the voltage stabilization circuit 210. The third circuit in the voltage stabilization circuit 210 transmits the operating voltage V4 to the device under test 300 accordingly.

[0049] In some embodiments, the first circuit in the voltage stabilization circuit 210 is used to transmit the operating voltage V2 to the device under test 300 through the test interface board 200, and the operating voltage V2 is related to the operating voltage VDD2. The first circuit in the voltage stabilization circuit 210 is also used to control the operating voltage V2 to be equal to the voltage potential of the operating voltage VDD2. For illustration, the comparison circuit 211 of the first circuit in the voltage stabilization circuit 210 compares the operating voltage VDD2 with the operating voltage V2, and the adjustment circuit 212 of the voltage stabilization circuit 210, in response to the comparison, adjusts the voltage potential of the operating voltage V2 to be equal to the voltage potential of the operating voltage VDD2. The configuration of the second circuit and the third circuit in the voltage stabilization circuit 210 is similar to that of the first circuit in the voltage stabilization circuit 210. Therefore, repeated discussion is omitted here.

[0050] In some embodiments, the operating voltages VDD1, VDD2, and VDDQ can be considered as three operating voltages in the LPDDR device, where the operating voltages VDD1 and VDD2 are power supplies for the core circuit and the operating voltage VDDQ is a power supply for the input / output interface. The operating voltages VDD1, VDD2, and VDDQ are known to those of ordinary skill in the art. In some embodiments, the operating voltages VDD1, VDD2, and VDDQ are approximately 1.7 volts, 1.1 volts, and 1.1 volts, respectively. In other words, at least two of the voltage stabilization circuits 210 are used to transmit two substantially different operating voltages.

[0051] Figure 3 The configuration is given for illustrative purposes. Figure 2 Various implementations of are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, Figure 3 Each voltage stabilization circuit 210 within the test system 30 has only one power supply.

[0052] Please refer to Figure 4 , Figure 4 FIG. 4 is a diagram of a test system 40 according to some embodiments. Figures 1 to 3 For ease of understanding, Figure 4 Similar components in the drawings are marked with the same reference numerals.

[0053] Compared to Figure 3 , power supplies 4101-410n, 4201-420n, and 4301-430n are included in the test machine 100. In some embodiments, Figure 4 Each of the voltage stabilization circuits 210 in is referred to, for example, Figure 1 The voltage stabilization circuit 210 in the configuration. The control signals CS1-CS3 are referenced, for example, Figure 1The control signal CS in the configuration is therefore, Figure 4 The voltage stabilization circuit 210 in the embodiment is used to transmit the operating voltages V2-V4 in response to the control signals CS1-CS3.

[0054] In some embodiments, based on some experimental data, the output gating window of the LPDDR device is about 170 picoseconds at a speed of about 3200 Mbps and in cooperation with the operating voltages VDD2 and VDDQ of the voltage stabilization circuit 210 in the present embodiment; in contrast, the output gating window of the LPDDR device without the voltage stabilization circuit 210 is about 130 picoseconds. Therefore, using the configuration of the present embodiment, the output gating window is improved by about 30% (i.e., (170-130) / 130).

[0055] In various embodiments, based on some experimental data, the output strobe window of the LPDDR device is about 60 picoseconds at a speed of about 4267 Mbps and in conjunction with the operating voltages VDD2 and VDDQ of the voltage stabilization circuit 210 of the present invention. In contrast, the LPDDR device without the voltage stabilization circuit 210 cannot operate under this condition. Therefore, using the configuration of the present invention, the output strobe window is open at about 4267 Mbps.

[0056] Figure 4 The configuration is given for illustrative purposes. Figure 2 Various implementations are within the expected scope of an embodiment of the present invention.

[0057] Please refer to Figure 5 , Figure 5 FIG. 5 is a flow chart of a test method 500 for a test system, such as the test system 10, 30, or 40, according to some embodiments. It should be understood that the test method 500 may be performed by Figure 5 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchangeable. Throughout the various views and illustrative embodiments, similar reference numbers are used to designate similar elements. The test method 500 includes steps 510-530 and will be referred to as Figure 4 The test system 40 is described in detail.

[0058] In step 510, the device to be tested 300 operates at the operating voltage V2 received through the device socket board 220 of the test interface board 200, such as Figure 4 shown.

[0059] In some embodiments, the test method 500 further includes the following operation: generating an operating voltage VDD2 to one of the voltage stabilization circuits 210 through at least one of the power supplies 4101-410n to generate an operating voltage V2. The operating voltage VDD2 is equal to the initial voltage indicated by the control signal CS1.

[0060] In step 520 , the comparison circuit 211 in the voltage stabilization circuit 210 compares the voltage potential of the operating voltage V2 with the initial voltage indicated by the control signal CS1 .

[0061] In some embodiments, the testing method 500 further includes generating a feedback signal FS to the adjustment circuit 212 through the comparison circuit 211 in response to the comparison.

[0062] In step 530 , when the operating voltage V2 is different from the initial voltage (ie, equal to the voltage level of the operating voltage VDD2 ), the adjusting circuit 212 adjusts the operating voltage V2 to have the initial voltage.

[0063] In some embodiments, when the voltage level of the operating voltage V2 is lower than the initial voltage, the testing method 500 further includes increasing the voltage level of the operating voltage V2 to the operating voltage VDD2 (ie, equal to the operating voltage VDD2 ) by the adjusting circuit 212 .

[0064] In some embodiments, the test method 500 further includes operating the device under test 300 at an operating voltage V3 different from the operating voltage V2, and controlling the operating voltage V3 to be equal to another initial voltage (i.e., equal to the voltage potential of the operating voltage VDD1) through the voltage stabilization circuit 210. The other initial voltage is indicated by the control signal CS2. Figure 4 As shown, another initial voltage is provided from the tester 100 to the voltage stabilization circuit 210 via the control signal CS2.

[0065] In some embodiments, the test method 500 further includes comparing the operating voltage V3 with another initial voltage (i.e., the other initial voltage is equal to the voltage potential of the operating voltage VDD1) by the comparison circuit 211 in the voltage stabilization circuit 210, and adjusting the operating voltage V3 to have the voltage potential of the operating voltage VDD1 by the adjustment circuit 212 in response to the comparison. The comparison circuit 211 receives the operating voltage VDD1.

[0066] Unless it is explicitly stated that the means is for performing a certain function, or the steps are for performing a certain function, no element in the patent claims should be construed as a functional means.

[0067] Through the operations of the above different embodiments, the test system and test method of the present invention stably operate at the operating voltage of the high-speed low-power memory and correspondingly provide a wide output gating window of the low-power memory device.

[0068] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of an embodiment of the present invention. Those skilled in the art should understand that they can easily use an embodiment of the present invention as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not deviate from the spirit and scope of an embodiment of the present invention, and such equivalent constructions can be variously changed, replaced and substituted herein without departing from the spirit and scope of an embodiment of the present invention.

[0069]

Explanation of symbols

[0070] 10: Test system

[0071] 100:Testing machine

[0072] 200: Test interface board

[0073] 210: Voltage stabilization circuit

[0074] 211: Comparison circuit

[0075] 212: Adjustment circuit

[0076] 220: Install socket board

[0077] 300: Device to be tested

[0078] V1: Operating voltage

[0079] V2: Operating voltage

[0080] CS: Control signal

[0081] FS: Feedback signal

[0082] TP:Test Pattern

[0083] 4101-410n,4201-420n,4301-430n: Power supply

[0084] VDD1, VDD2: operating voltage

[0085] V3, V4: operating voltage

[0086] VDDQ: Operating voltage

[0087] CS1, CS2: control signal

[0088] 500:Test Method

[0089] 510,520,530: steps.

Claims

1. A testing system, characterized in that: Include: A test machine, used to generate a first operating voltage and a control signal; A first voltage stabilization circuit, used for transmitting a second operating voltage associated with the first operating voltage to the socket board; as well as a device to be tested, configured to be actuated by the second operating voltage received through the socket board, The first voltage stabilization circuit is further used to control the second operating voltage to have a first voltage potential according to the control signal when the device under test is activated. The first voltage stabilization circuit is further used to compare the second operating voltage with an initial voltage, which is specified by the control signal, and the first voltage stabilization circuit is further used to adjust the voltage potential of the second operating voltage to have a first voltage potential equal to the first operating voltage in response to the comparison.

2. The test system according to claim 1, wherein the first voltage stabilization circuit comprises: The comparison circuit is used for comparing the second operating voltage with an initial voltage, the initial voltage being specified by the control signal, and for generating a feedback signal; and The adjustment circuit is used for raising the voltage potential of the second operation voltage to the first voltage potential according to the feedback signal.

3. The test system according to claim 1, further comprising: The test interface board is electrically coupled to the test machine, wherein the first voltage stabilization circuit and the socket board are integrated in the test interface board.

4. The test system according to claim 1, wherein: Also includes: A plurality of first power supplies for generating the first operating voltage to the first voltage stabilizing circuit; A second voltage stabilization circuit, used for transmitting a third operating voltage to the device under test through the socket board; as well as A plurality of second power supplies are used to generate a fourth operating voltage to the second voltage stabilizing circuit to generate the third operating voltage.

5. The test system according to claim 4, wherein the second voltage stabilization circuit comprises: The adjusting circuit is used for adjusting the voltage potential of the third operating voltage to a second voltage potential, and the second voltage potential is equal to the fourth operating voltage.

6. The test system according to claim 1, further comprising: The second voltage stabilizing circuit is used for transmitting a third operating voltage to the socket board and controlling a voltage potential of the third operating voltage to be the same as a fourth operating voltage, wherein the third operating voltage is associated with the fourth operating voltage received by the second voltage stabilizing circuit. 7 . The test system according to claim 1 , wherein the device under test is a low power double data rate memory device.

8. A testing method, characterized in that: Include: Operating the device under test at a first operating voltage; comparing the voltage potential of the first operating voltage with the first initial voltage by a first comparison circuit of the first voltage stabilization circuit; as well as When the voltage potential of the first operating voltage is different from the first initial voltage, the voltage potential of the first operating voltage is adjusted to have the first initial voltage by the first adjusting circuit of the first voltage stabilizing circuit according to a control signal, One of the testers is used to generate the control signal and specify the first initial voltage of the first voltage stabilization circuit through the control signal.

9. The testing method according to claim 8, further comprising: A second operating voltage is generated by at least one power supply to a voltage stabilization circuit to generate the first operating voltage, wherein a voltage potential of the second operating voltage is equal to the first initial voltage.

10. The testing method according to claim 8, wherein: Also includes: In response to the comparison, generating a feedback signal to the first adjustment circuit through the first comparison circuit; and The voltage potential of the first operating voltage is increased by the first adjustment circuit.

11. The testing method according to claim 8, further comprising: operating the device under test at a second operating voltage different from the first operating voltage; and The voltage potential of the second operating voltage is controlled by a voltage stabilization circuit to be equal to the second initial voltage. The second initial voltage is provided to the voltage stabilization circuit by a tester.

12. The testing method according to claim 8, wherein: Also includes: Operating the device under test at a second operating voltage; comparing the voltage potential of the second operating voltage with a second initial voltage different from the first initial voltage by a second comparison circuit; as well as The voltage potential of the second operating voltage is adjusted to have the second initial voltage by a second adjustment circuit in response to the comparison.

13. The testing method according to claim 8, wherein adjusting the voltage level of the first operating voltage comprises: When the voltage potential of the first operating voltage is less than the first initial voltage, the voltage potential of the first operating voltage is increased by the first adjustment circuit.

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