Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same, the semiconductor structure comprising: a first wafer, a plurality of first dielectric layers and air layers between the first dielectric layers formed on the surface of the first wafer; and a plurality of support structures located between the first dielectric layers and the air layers for supporting the first dielectric layers, the bottom surface of the support structure being lower than the bottom surface of the first air layer and higher than the bottom surface of the first first dielectric layer. The semiconductor structure and the method for forming the same described in the present application form an air layer in the buried oxide layer of the RF-SOI device, reduce the dielectric constant of the buried oxide layer, thereby reducing the capacitance between the silicon film and the silicon substrate, and can improve the linearity of the RF-SOI device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Silicon-on-Insulator (SOI) is composed of three layers: "silicon film / insulating layer / silicon substrate". The top silicon film (referred to as silicon film) is used to make semiconductor devices such as CMOS, and the middle insulating buried layer (usually silicon dioxide, referred to as buried oxide layer, BOX layer) is used to isolate the device from the silicon substrate.

[0003] SOI devices have smaller parasitic capacitance, lower leakage current, and lower soft error rate than bulk silicon devices, so they are increasingly used in the semiconductor field. For example, in order to solve the substrate noise problem and reduce substrate inductance loss, SOI technology is used to manufacture radio frequency (RF) integrated circuits. However, with the increase in circuit frequency and precision, the current RF-SOI is also difficult to meet the requirements.

[0004] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the invention

[0005] The present application provides a semiconductor structure and a method for forming the same, which can improve the linearity of an RF-SOI device.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a first wafer; forming a stacked layer on the surface of the first wafer, the stacked layer comprising a plurality of alternately stacked first dielectric layers and second dielectric layers, wherein the starting layer and the top layer of the stacked layer are both first dielectric layers; forming a plurality of supporting structures in the stacked layer for supporting the first dielectric layer, the bottom surface of the supporting structure being lower than the bottom surface of the first layer of the second dielectric layer and higher than the bottom surface of the first layer of the first dielectric layer.

[0007] In some embodiments of the present application, the method for forming the semiconductor structure also includes: providing a second wafer, the second wafer including a second substrate and a protective dielectric layer surrounding the second substrate; bonding the second wafer to the top layer of the stacked layer; and removing a portion of the second wafer to form a silicon-on-insulator structure.

[0008] In some embodiments of the present application, the material of the second substrate includes single crystal silicon.

[0009] In some embodiments of the present application, the method for removing part of the second wafer includes: injecting hydrogen at a set depth of the second substrate of the second wafer to form an injection layer before bonding; annealing the second substrate; bonding with the side closer to the injection layer as the bonding interface during bonding; and after bonding, peeling off the part of the second wafer that is higher than the injection layer along the injection layer.

[0010] In some embodiments of the present application, the method for forming the semiconductor structure also includes: removing the second substrate and the protective dielectric layer outside the active area; etching part of the stacked layers outside the active area to remove part of the starting layer to form a groove; removing the second dielectric layer to form an air layer; filling the groove and the air layer on the side of the supporting structure away from the active area to form an isolation structure.

[0011] In some embodiments of the present application, a method for filling the air layer on the side of the groove and the support structure away from the active area to form an isolation structure includes: depositing an isolation material layer on the air layer on the side of the groove and the support structure away from the active area, wherein the isolation material layer is higher than the surface of the second substrate; and removing the isolation material layer above the surface of the second substrate.

[0012] In some embodiments of the present application, the method of removing the isolation material layer above the surface of the second substrate includes a chemical mechanical polishing process and a cleaning process.

[0013] In some embodiments of the present application, the method for forming the plurality of support structures includes: etching the stacked layers to remove part of the starting layer to form a plurality of through holes that are not connected to each other; depositing a support material layer in the plurality of through holes and on the surface of the stacked layers; and using a chemical mechanical polishing process to remove the support material layer above the top layer of the stacked layers.

[0014] In some embodiments of the present application, the first wafer includes a first substrate and a trap-rich layer located on a surface of the first substrate, and the stacked layer is located on a surface of the trap-rich layer.

[0015] In some embodiments of the present application, the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes silicon nitride.

[0016] In some embodiments of the present application, the number of stacked layers of the stacked layers is three to nine.

[0017] In some embodiments of the present application, the support structures are distributed in an array in the stacked layers.

[0018] Another aspect of the present application provides a semiconductor structure, including: a first wafer, a plurality of first dielectric layers and air layers located between the plurality of first dielectric layers are formed on the surface of the first wafer; a plurality of supporting structures, located between the plurality of first dielectric layers and the air layers and used for supporting the plurality of first dielectric layers, wherein the bottom surface of the supporting structure is lower than the bottom surface of the first air layer and higher than the bottom surface of the first first dielectric layer.

[0019] In some embodiments of the present application, a protective dielectric layer and a second substrate located on the protective dielectric layer are also formed on the plurality of first dielectric layers.

[0020] In some embodiments of the present application, the material of the second substrate includes single crystal silicon.

[0021] In some embodiments of the present application, isolation structures are further formed on both sides of the plurality of first dielectric layers, and the support structure is located between the plurality of first dielectric layers and the isolation structure.

[0022] In some embodiments of the present application, the first wafer includes a first substrate and a trap-rich layer located on a surface of the first substrate, and the plurality of first dielectric layers are located on a surface of the trap-rich layer.

[0023] In some embodiments of the present application, the material of the first dielectric layer includes silicon oxide.

[0024] In some embodiments of the present application, the stacked number of the plurality of first dielectric layers is two to five.

[0025] In some embodiments of the present application, the support structures are distributed in the plurality of first dielectric layers in an array manner.

[0026] The semiconductor structure and the method for forming the same described in the present application form an air layer in the buried oxide layer of the RF-SOI device, thereby reducing the dielectric constant of the buried oxide layer and thus reducing the capacitance between the silicon film and the silicon substrate, thereby improving the linearity of the RF-SOI device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0028] Figure 1 is a schematic diagram of a semiconductor structure;

[0029] Figure 2 A circuit diagram of a semiconductor structure;

[0030] Figures 3 to 19 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0032] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0033] Figure 1 A schematic diagram of a semiconductor structure.

[0034] refer to Figure 1 As shown, the silicon-on-insulator device is mainly composed of three layers: a silicon film 130 , an insulating layer 120 , and a silicon substrate 100 .

[0035] The top silicon film 130 is used to make semiconductor devices such as CMOS. Figure 1 As shown, a source 140 and a drain 150 may be formed in the silicon film 130 , and a gate 160 may be formed on the surface of the silicon film 130 .

[0036] The middle insulating layer 120 (usually silicon dioxide, referred to as buried oxide layer, BOX layer) is used to isolate the device from the silicon substrate 100 .

[0037] A trap-rich layer 110 may be formed on the surface of the silicon substrate 100. The trap-rich layer 110 can capture free carriers to avoid abnormal capacitance characteristics of the SOI substrate.

[0038] Figure 2 A circuit diagram of a semiconductor structure.

[0039] refer to Figure 2 As shown, C sb and C db are the junction capacitance of the source and drain respectively; C gs and C gb are the capacitance from gate to source and drain respectively; C sx and Cdx are the capacitances from source and drain to substrate, respectively.

[0040] Key Parameters of RF-SOI off It can be obtained by the following formula:

[0041]

[0042] C off Can affect the linearity of RF-SOI. For example, the isolation strength can be obtained by the following formula:

[0043]

[0044] According to formula (1) and formula (2), it can be obtained that reducing C sx and C dx You can reduce C off , thereby improving the isolation strength of RF-SOI and the linearity of RF-SOI. sx and C dx are the capacitances from source and drain to substrate, respectively, reducing C sx and C dx This can be achieved by reducing the dielectric constant of the buried oxide.

[0045] Based on the above content, the present application provides a semiconductor structure and a method for forming the same, which forms an air layer with a dielectric constant lower than that of silicon dioxide in the buried oxide layer of the RF-SOI device, thereby reducing the dielectric constant of the buried oxide layer as a whole, thereby reducing the capacitance between the silicon wafer and the silicon substrate, and improving the linearity of the RF-SOI device.

[0046] Figures 3 to 19 The semiconductor structure and the method for forming the semiconductor structure described in the present application are described in detail below in conjunction with the accompanying drawings.

[0047] An embodiment of the present application provides a method for forming a semiconductor structure, comprising: providing a first wafer; forming a stacked layer on the surface of the first wafer, the stacked layer comprising a plurality of alternately stacked first dielectric layers and second dielectric layers, wherein the starting layer and the top layer of the stacked layer are both first dielectric layers; forming a plurality of supporting structures in the stacked layer for supporting the first dielectric layer, the bottom surface of the supporting structure being lower than the bottom surface of the first-layer second dielectric layer and higher than the bottom surface of the first-layer first dielectric layer.

[0048] refer to Figure 3 As shown, a first wafer 200 is provided. The first wafer 200 can be used as a silicon substrate in an SOI structure.

[0049] In some embodiments of the present application, the first wafer 200 includes a first substrate 201 and a trap-rich layer 202 located on the surface of the first substrate 201. The trap-rich layer 202 can capture free carriers to avoid abnormal capacitance characteristics of the SOI substrate.

[0050] In some embodiments of the present application, the first substrate 201 is a semiconductor substrate, and its material is, for example, silicon or germanium, etc. In some embodiments of the present application, the material of the first substrate 201 can also be a semiconductor material doped with impurity particles (such as phosphorus, boron, etc.).

[0051] refer to Figure 4 As shown, a stacked layer 210 is formed on the surface of the first wafer 200 (that is, the surface of the trap-rich layer 202), and the stacked layer 210 includes a plurality of alternately stacked first dielectric layers 211 and second dielectric layers 212, wherein the starting layer and the top layer are both the first dielectric layer 211. The stacked layer 210 can be used as an insulating layer (also called a buried oxide layer) in the SOI structure, and is used to isolate the first wafer 200 and a silicon thin film subsequently formed on the stacked layer 210.

[0052] Since the second dielectric layer 212 needs to be removed later to form an air layer, the first dielectric layer 211 needs to sandwich the second dielectric layer 212 , so the starting layer and the top layer are both the first dielectric layer 211 .

[0053] In some embodiments of the present application, the material of the first dielectric layer 211 includes silicon oxide. The function of the first dielectric layer 211 is isolation. Therefore, other suitable materials with lower dielectric constants can also be selected. The material of the second dielectric layer 212 includes silicon nitride. The function of the second dielectric layer 212 is as a sacrificial layer of the air layer, which needs to be removed in subsequent processes. Therefore, other materials that are relatively large compared to silicon oxide etching can also be selected.

[0054] In some embodiments of the present application, the stacked layers 210 have three to nine layers, for example, three, five, seven or nine layers.

[0055] refer to Figures 5 to 8 A plurality of support structures 220 are formed in the stacked layer 210 for supporting the first dielectric layer 211 . The bottom surface of the support structure 220 is lower than the bottom surface of the first second dielectric layer 212 and higher than the bottom surface of the first first dielectric layer 211 .

[0056] refer to Figure 5As shown, the stacked layer 210 is etched until part of the starting layer is removed to form a plurality of disconnected through holes 221. The bottom surface of the through hole 221 is lower than the bottom surface of the first second dielectric layer 212 and higher than the bottom surface of the first first dielectric layer 211 to avoid damaging the first wafer 200.

[0057] refer to Figure 6 As shown, Figure 6 2 is a top view of the stacked layer 210. The plurality of through holes 211 may be evenly distributed in the stacked layer 210, and the plurality of through holes 211 may be distributed in an array.

[0058] In some embodiments of the present application, the number and size of the plurality of through holes 211 may be set according to requirements of the active area.

[0059] refer to Figure 7 As shown, a support material layer 220a is deposited in the plurality of through holes 221 and on the surface of the stacked layer 210; Figure 8 As shown, a support material layer 220 a higher than the top layer of the stacked layer 210 is removed by a chemical mechanical polishing process to form a support structure 220 in the stacked layer 210 .

[0060] In some embodiments of the present application, the support structure 220 is distributed in an array in the stacked layer 210. In some embodiments of the present application, the support structure 220 is evenly distributed in the stacked layer 210. The support structure 220 is used to support the remaining first dielectric layer 211 after the second dielectric layer 212 is subsequently removed to form an air layer, so the even distribution can improve the support effect and prevent the air layer from collapsing.

[0061] In some embodiments of the present application, the material of the support structure 220 is an insulating material with a low dielectric constant, and the material of the support structure 220 may be the same as the material of the first dielectric layer 211 .

[0062] refer to Fig. 9 As shown, a second wafer 230 is provided, and the second wafer 230 includes a second substrate 231 and a protective dielectric layer 232 surrounding the second substrate 231. The second wafer 230 is used as a top silicon film of the SOI structure, and specifically, the second substrate 231 is used as the top silicon film.

[0063] The protective dielectric layer 232 is used to protect the second substrate 231. The protective dielectric layer 232 is formed by, for example, oxidation on the surface of the second substrate 231.

[0064] In some embodiments of the present application, the material of the second substrate 231 includes single crystal silicon.

[0065] refer to Fig.10 As shown, before bonding, an ion implantation process is used to implant hydrogen at a set depth (the set depth is the set thickness of the top silicon film) of the second substrate 231 of the second wafer 230 to form an implantation layer 233 .

[0066] refer to Fig.11 As shown, the second wafer 230 is bonded to the top layer of the stacked layer 220 on the first wafer 210. During bonding, the side closer to the injection layer 233 is used as the bonding interface, and the second substrate 231 close to the bonding interface is retained as the top silicon film.

[0067] refer to Fig.12 , removing part of the second wafer 230 to form a silicon-on-insulator (SOI) structure. In the SOI structure, the first wafer 200 is used as a bottom silicon substrate; the stacked layer 210 is used as an intermediate insulating layer; and the second wafer 230 is used as a top silicon film.

[0068] The method for removing part of the second wafer 230 includes: annealing the second substrate 231 to expand the injected particles of the injection layer 233 and tear the second substrate 231; and peeling off the second wafer 230 higher than the injection layer 233 along the injection layer 233 after bonding.

[0069] refer to Fig.13 As shown, the second substrate 231 and the protective dielectric layer 232 outside the active area are removed. The active area is a pre-set area for forming active devices. The purpose of removing the second substrate 231 outside the active area is to ensure that the second substrate 231 can be completely located above the air layer, that is, between the isolation structures 220.

[0070] refer to Fig.14 As shown, part of the stacked layers outside the active area are etched until part of the starting layer is removed to form a trench 240. The trench 240 is used to form an isolation structure.

[0071] refer to Fig.15 As shown, the second dielectric layer 212 is removed to form an air layer 241. After the second dielectric layer 212 is removed, the support structure 220 can support the first dielectric layers 211 to prevent them from collapsing. The method of removing the second dielectric layer 212 is, for example, wet etching or dry etching.

[0072] refer to Figures 16 to 18 As shown, the air layer filling the trench 240 and the side of the support structure away from the active region forms an isolation structure 250. The isolation structure 250 is used to isolate adjacent active regions.

[0073] refer to Fig.16As shown, an isolation material layer 250 a is deposited in the trench 240 and the air layer on the side of the support structure away from the active area, and the isolation material layer 250 a is higher than the surface of the second substrate 231 .

[0074] refer to Fig.17 and Fig.18 , remove the isolation material layer 250a above the surface of the second substrate 231.

[0075] refer to Fig.17 First, the isolation material layer 250a is ground to a relatively thin thickness using a chemical mechanical polishing process. The second substrate 231 is used to form the top silicon film of the device, and its quality requirements are relatively high. If the chemical mechanical polishing process is directly used to grind to the second substrate 231, the second substrate 231 may be damaged and its performance may be affected.

[0076] refer to Fig.18 As shown, a cleaning process is used to remove the remaining isolation material layer, exposing the surface of the second substrate 231 to form the isolation structure 250.

[0077] refer to Fig.19 As shown, a gate layer 260 is formed on the surface of the second substrate 231; a source 270 and a drain 280 are formed in the second substrate 231 on both sides of the gate layer 260. The gate layer 260 may also include a gate oxide layer and a spacer (not shown in the figure).

[0078] refer to Figure 1 The semiconductor structure shown and Fig.19 The semiconductor structure provided by the embodiment of the present application shown in the figure, Figure 1 The insulating layer 120 and Fig.19 The stacked layer 210 in the SOI structure also serves as the intermediate insulating layer in the SOI structure. However, the stacked layer 210 provided in the embodiment of the present application is composed of an air layer 241 and a first dielectric layer 211, and the first dielectric layer 211 is, for example, silicon oxide. The dielectric constant of air is 1, while the dielectric constant of silicon oxide is 3.9, so using a combination of an air layer and silicon oxide as the intermediate insulating layer can greatly reduce the dielectric constant of using silicon oxide as the intermediate insulating layer.

[0079] 1) Reducing the dielectric constant can reduce the capacitance from the source and drain (active area) to the semiconductor substrate (even by three quarters), thereby improving isolation performance; 2) The air layer can reduce the electrical coupling from the source and drain (active area) to the semiconductor substrate, further improving the influence of parasitic charges at the oxide / substrate interface; 3) Reducing electrical coupling can also facilitate the manufacture of high-quality inductors and high-performance coplanar waveguide transmission lines; 4) Reducing electrical coupling can also reduce the second / third harmonic power and improve the linearity of RF-SOI devices; 5) The structure of the first wafer and stacked layers can reduce the high resistivity requirements for the first substrate, which is beneficial to e-chuck absorption during the SOI device manufacturing process.

[0080] The semiconductor structure and the method for forming the same described in the present application form an air layer in the buried oxide layer of the RF-SOI device, reduce the dielectric constant of the buried oxide layer, thereby reducing the capacitance between the silicon wafer and the silicon substrate, and can improve the linearity of the RF-SOI device.

[0081] The embodiment of the present application also provides a semiconductor structure, referring to Fig.19 As shown, it includes: a first wafer 200, a plurality of first dielectric layers 211 and air layers 241 located between the plurality of first dielectric layers 211 are formed on the surface of the first wafer 200; a plurality of supporting structures 220, located between the plurality of first dielectric layers 211 and the air layers 241 and used for supporting the plurality of first dielectric layers 211, the bottom surface of the supporting structure 241 is lower than the bottom surface of the first air layer and higher than the bottom surface of the first first dielectric layer.

[0082] refer to Fig.19 As shown, the semiconductor structure described in the embodiment of the present application is, for example, an SOI structure, and the first wafer 200 can be used as a silicon substrate in the SOI structure.

[0083] In some embodiments of the present application, the first wafer 200 includes a first substrate 201 and a trap-rich layer 202 located on the surface of the first substrate 201. The trap-rich layer 202 can capture free carriers to avoid abnormal capacitance characteristics of the SOI substrate.

[0084] In some embodiments of the present application, the first substrate 201 is a semiconductor substrate, and its material is, for example, silicon or germanium, etc. In some embodiments of the present application, the material of the first substrate 201 can also be a semiconductor material doped with impurity particles (such as phosphorus, boron, etc.).

[0085] Continue to refer Fig.19As shown, a stacked layer 210 is formed on the surface of the first wafer 200, and the stacked layer 210 includes a plurality of first dielectric layers 211 and an air layer 241 located between the plurality of first dielectric layers 211. The plurality of first dielectric layers 211 and the air layer 241 can be used as an insulating layer (also called a buried oxide layer) in the SOI structure, and are used to isolate the first wafer 200 and a silicon thin film subsequently formed on the stacked layer 210.

[0086] In some embodiments of the present application, the material of the first dielectric layer 211 includes silicon oxide. The function of the first dielectric layer 211 is isolation, so other suitable materials with lower dielectric constants may also be selected.

[0087] In some embodiments of the present application, the stacked number of the plurality of first dielectric layers 211 is two to five layers, for example, two layers, three layers, four layers or five layers.

[0088] Continue to refer Fig.19 As shown, several support structures 220 are formed in the several first dielectric layers 211 and the air layer 241 for supporting the first dielectric layer 211 . The bottom surface of the support structure 220 is lower than the bottom surface of the first second dielectric layer 212 and higher than the bottom surface of the first first dielectric layer 211 .

[0089] In some embodiments of the present application, the number and size of the plurality of support structures 220 may be set according to the requirements of the active area.

[0090] In some embodiments of the present application, the support structure 220 is distributed in an array in the stacked layer 210. In some embodiments of the present application, the support structure 220 is evenly distributed in the stacked layer 210. The support structure 220 is used to support the first dielectric layer 211, so even distribution can improve the support effect and avoid air layer collapse.

[0091] In some embodiments of the present application, the material of the support structure 220 is an insulating material with a low dielectric constant, and the material of the support structure 220 may be the same as the material of the first dielectric layer 211 .

[0092] Continue to refer Fig.19 As shown, a second wafer 230 is also formed on the first dielectric layers 211, and the second wafer 230 includes a protective dielectric layer 232 and a second substrate 231 located on the surface of the protective dielectric layer 232. The second wafer 230 can be used as the top silicon film of the SOI structure, and specifically, the second substrate 231 is used as the top silicon film.

[0093] In some embodiments of the present application, the material of the second substrate 231 includes single crystal silicon.

[0094] Continue to refer Fig.19 As shown, in some embodiments of the present application, isolation structures 250 are further formed on both sides of the plurality of first dielectric layers 211. The isolation structures 250 are used to isolate adjacent active regions.

[0095] Continue to refer Fig.19 As shown, a gate layer 260 is formed on the surface of the second substrate 231; a source 270 and a drain 280 are formed in the second substrate 231 on both sides of the gate layer 260. The gate layer 260 may also include a gate oxide layer and a sidewall spacer (not shown in the figure).

[0096] refer to Figure 1 The semiconductor structure shown and Fig.19 The semiconductor structure provided by the embodiment of the present application shown in the figure, Figure 1 The insulating layer 120 and Fig.19 The stacked layer 210 in the SOI structure also serves as the intermediate insulating layer in the SOI structure. However, the stacked layer 210 provided in the embodiment of the present application is composed of an air layer 241 and a first dielectric layer 211, and the first dielectric layer 211 is, for example, silicon oxide. The dielectric constant of air is 1, while the dielectric constant of silicon oxide is 3.9, so using a combination of an air layer and silicon oxide as the intermediate insulating layer can greatly reduce the dielectric constant of using silicon oxide as the intermediate insulating layer.

[0097] The semiconductor structure and the method for forming the same described in the present application form an air layer in the buried oxide layer of the RF-SOI device, reduce the dielectric constant of the buried oxide layer, thereby reducing the capacitance between the silicon wafer and the silicon substrate, and can improve the linearity of the RF-SOI device.

[0098] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0099] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may also be present.

[0100] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0101] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0102] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a first wafer; Forming a stacking layer on the surface of the first wafer, the stacking layer comprising a plurality of alternately stacked first dielectric layers and second dielectric layers, wherein the starting layer and the top layer of the stacking layer are both the first dielectric layer; A plurality of support structures are formed in the stacked layers for supporting the first dielectric layer, wherein the bottom surface of the support structure is lower than the bottom surface of the first second dielectric layer and higher than the bottom surface of the first first dielectric layer, the first second dielectric layer is the second dielectric layer closest to the first wafer, and the first first dielectric layer is the first dielectric layer closest to the first wafer; Providing a second wafer, wherein the second wafer includes a second substrate and a protective dielectric layer surrounding the second substrate; bonding the second wafer to the top layer of the stack; removing a portion of the second wafer to form a silicon-on-insulator structure; removing the second substrate and the protective dielectric layer outside the active area; Etching part of the stacked layers outside the active area until part of the starting layer is removed to form a trench; removing the second dielectric layer to form an air layer; An air layer filling the trench and a side of the support structure away from the active area forms an isolation structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second substrate includes single crystal silicon.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method of removing a portion of the second wafer includes: Before bonding, hydrogen is injected into the second substrate of the second wafer at a set depth to form an injection layer; performing annealing treatment on the second substrate; During bonding, the side closer to the injection layer is used as the bonding interface for bonding; After bonding, a portion of the second wafer higher than the injection layer is peeled off along the injection layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method of filling the trench and the air layer on the side of the support structure away from the active area to form an isolation structure includes: Depositing an isolation material layer in the air layer on the side of the trench and the support structure away from the active area, wherein the isolation material layer is higher than the surface of the second substrate; The isolation material layer above the surface of the second substrate is removed.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method of removing the isolation material layer above the surface of the second substrate includes a chemical mechanical polishing process and a cleaning process.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the plurality of support structures comprises: Etching the stacked layers until a portion of the starting layer is removed to form a plurality of mutually disconnected through holes; Depositing a support material layer in the plurality of through holes and on the surface of the stacked layer; A layer of support material above a top layer of the stack of layers is removed using a chemical mechanical polishing process.

7. The method for forming a semiconductor structure according to claim 1, wherein: The first wafer includes a first substrate and a trap-rich layer located on a surface of the first substrate, and the stacked layer is located on a surface of the trap-rich layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes silicon nitride.

9. The method for forming a semiconductor structure according to claim 1, wherein: The stacking number of the stacking layers is three to nine.

10. The method for forming a semiconductor structure according to claim 1, wherein: The support structures are distributed in the stacked layers in an array.

11. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 10, characterized in that: include: A first wafer, wherein a plurality of first dielectric layers and air layers between the plurality of first dielectric layers are formed on a surface of the first wafer; A plurality of supporting structures are located between the plurality of first dielectric layers and the air layer and are used to support the plurality of first dielectric layers. The bottom surface of the supporting structure is lower than the bottom surface of the first air layer and higher than the bottom surface of the first first dielectric layer.

12. The semiconductor structure according to claim 11, wherein: A protective dielectric layer and a second substrate located on the protective dielectric layer are also formed on the plurality of first dielectric layers.

13. The semiconductor structure according to claim 12, wherein: The material of the second substrate includes single crystal silicon.

14. The semiconductor structure according to claim 11, wherein: Isolation structures are also formed on both sides of the plurality of first dielectric layers, and the support structure is located between the plurality of first dielectric layers and the isolation structure.

15. The semiconductor structure according to claim 11, wherein: The first wafer includes a first substrate and a trap-rich layer located on a surface of the first substrate, and the plurality of first dielectric layers are located on a surface of the trap-rich layer.

16. The semiconductor structure according to claim 11, wherein: The material of the first dielectric layer includes silicon oxide.

17. The semiconductor structure according to claim 11, wherein: The stacking number of the plurality of first dielectric layers is two to five.

18. The semiconductor structure according to claim 11, wherein: The support structures are distributed in the plurality of first dielectric layers in an array manner.

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