Systems and methods for implementing a scalable system

Abstract

The present disclosure relates to systems and methods for implementing scalable systems. The present invention describes a multi-chip system (100) and architecture for modular expansion. In some embodiments, bonding bars (150) are used to couple adjacent chips (102, 104). For example, a communication bar (150) can be used to couple logic chips (104), and a memory bar (150) can be used to couple multiple memory chips (102) to a logic chip (104).

Description

[0001] Related Patent Applications

[0002] This application is a divisional application of a patent application for an invention titled "Systems and Methods for Enabling Scalable Systems" with international application number PCT / US2019 / 024647, international filing date of March 28, 2019, date of entry into the Chinese national phase of September 30, 2020, and Chinese national application number 201980024144.1.

[0003] This patent application claims the priority of U.S. Provisional Application 62 / 656,584, filed on April 12, 2018, which is incorporated herein by reference. Technical Field

[0004] The embodiments described herein relate to scalable systems, and more particularly to scalable logic components and modular memories. Background Art

[0005] Scalable systems require both logic components and memories that can be increased in a practical and cost-effective manner. In addition, they should reasonably allow the logic components and memories to be independently scaled to allow for adjustments to computing, memory bandwidth, and storage capacity according to system requirements. Dynamic random access memory (DRAM) has long been a product of the computer and electronics industries. With the emergence of a large number of end-market applications starting from desktop computers, mobile electronic devices, data centers, and networked platforms, competing memory platforms have rapidly evolved according to specific requirements such as bandwidth, capacity, power, latency, and footprint. However, increasing one parameter is typically achieved by trading off other parameters. For example, increasing DRAM bandwidth is usually accompanied by a loss of other parameters.

[0006] For a long time, the low-power double data rate (LPDDR) standard has been adopted in various markets, including mobile electronics, to meet performance and capacity requirements. LPDDR platforms and the next generation (LPDDR-x) typically include an arrangement of memory chips or packages around a system-on-chip (SOC), which may include a central processing unit (CPU) and / or a graphics processing unit (GPU). To meet the demand for increased bandwidth, various 3D solutions have been proposed, including stacked DRAM dies such as high-bandwidth memory (HBM) and hybrid memory cube (HMC). Brief Description of the Drawings

[0007] Figure 1 Schematic top view illustration of a plurality of memory chips arranged around a system-on-chip.

[0008] Figure 2Schematic top view illustration of a multi-chip system with an extended logic component according to an embodiment.

[0009] Figure 3 Schematic top view and side view illustrations of a multi-chip system with an extended logic component according to an embodiment.

[0010] Figure 4 Schematic top view illustration of an extended logic die with on-die inter-die wiring according to an embodiment.

[0011] Figure 5 Schematic top view illustration of an extended logic component with 2.5D inter-chip wiring according to an embodiment.

[0012] Figure 6 Schematic top view illustration of an extended logic component with 2.5D inter-chip wiring and a bridge according to an embodiment.

[0013] Figure 7 Schematic top view illustration of a hybrid extended logic component with both on-die inter-die wiring and 2.5D inter-chip wiring according to an embodiment.

[0014] Figure 8 Schematic top view illustration of a modular extension of a logic component with an added periphery according to an embodiment.

[0015] Figure 9 Schematic top view illustration of the connection of an extended logic component according to an embodiment.

[0016] Figure 10A Schematic top view illustration of the connection overhead of a logic component according to an embodiment.

[0017] Figure 10B Schematic top view illustration of the connection overhead of an extended logic component according to an embodiment.

[0018] Figure 11A Schematic top view illustration of the connection overhead of a logic component according to an embodiment.

[0019] Figure 11B Schematic top view illustration of the connection overhead of an extended logic component with a connection bar according to an embodiment.

[0020] Figure 12A Schematic top view illustration of the 3D extension of a logic chip with a connection bar according to an embodiment.

[0021] Figure 12BSchematic top view illustration of a planar expansion of a logic chip with a connecting bar according to an embodiment.

[0022] Figure 13 Schematic top view illustration of a multi-chip system with expanded logic components, memory, and high capacity according to an embodiment.

[0023] Figure 14 Schematic top view illustration of a multi-chip system with expanded logic components, memory, and short logic connections according to an embodiment.

[0024] Figure 15 Schematic cross-sectional side view illustration of a bonding bar metal wiring layer according to an embodiment.

[0025] Figure 16 Schematic top view illustration of an expanded system with inter-die wiring according to an embodiment.

[0026] Figure 17 Schematic top view illustration of a bonding bar wiring according to an embodiment.

[0027] Figure 18A Schematic cross-sectional side view and top view illustrations of a bonding bar and wiring according to an embodiment.

[0028] Figure 18B Schematic cross-sectional side view illustration of a BGA-side mounted bonding bar according to an embodiment.

[0029] Figure 18C Schematic top view illustration of an optical connecting bar according to an embodiment.

[0030] Figure 19 Schematic top view illustration of a bonding bar with a hammerhead shape according to an embodiment.

[0031] Figure 20 Schematic top view illustration of a bonding bar including a repositioned die logic component according to an embodiment.

[0032] Figure 21 Schematic top view illustration of an interface bar active region according to an embodiment.

[0033] Figure 22 Schematic top view and cross-sectional side view illustrations of a bonding bar with multiple discrete active components according to an embodiment.

[0034] Figure 23 Schematic top view illustration of an expanded system including a memory bar bridge according to an embodiment.

[0035] Figure 24 Schematic top view illustration of an extended system including an extended region, according to one embodiment.

[0036] Figures 25 to 26 Schematic top view illustration of a bonding bar having different form factors, according to an embodiment.

[0037] Figure 27 Schematic top view and cross-sectional side view illustrations of a bonding bar having discrete active regions and a head region, according to one embodiment.

[0038] Figure 28 Schematic top view and cross-sectional side view illustrations of a bonding bar package, according to one embodiment.

[0039] Figure 29A Schematic top view illustration of an extended system having a bridge for connecting a logic chip to a memory bar, according to one embodiment.

[0040] Figure 29B According to one embodiment Figure 29A Schematic cross-sectional side view illustration of an extended system.

[0041] Figure 30 Schematic top view illustration of an extended system having board wiring for connecting a logic chip to a memory bar, according to one embodiment.

[0042] Figure 31A Schematic top view illustration of a stacked package extended system, according to one embodiment.

[0043] Figures 31B - 31C Schematic cross-sectional side view illustrations of various stacked package extended systems, according to one embodiment.

[0044] Figure 32A Schematic top view illustration of a 3D extended system, according to one embodiment.

[0045] Figure 32B According to one embodiment along Figure 32A Schematic cross-sectional side view illustration taken along line B-B. DETAILED DESCRIPTION

[0046] Embodiments describe multi-chip systems and structures for modular expansion. In some embodiments, bonding bars are used to couple adjacent chips. In one aspect, the bonding bars can increase the total capacity and available perimeter for inter-chip connections. In another aspect, the bonding bars can be used to increase the bandwidth of inter-chip communication and reduce latency.

[0047] In a specific implementation, the bonding strip can be used as a connection strip between logic chips. In such specific implementations, the bonding strip can be oriented towards communication to meet bandwidth, power, latency, and cost goals. Logic chips such as system-on-chip (SOC) may include a central processing unit (CPU) or a graphics processing unit (GPU). Additionally, the logic chip periphery can be formatted to enable memory integration and other input / output (I / O) to other devices. The bonding strip can support metal stacks and logic components (e.g., transistor types) compatible with communication functions. The bonding strip can be packaged in various configurations, including chip-on-wafer (CoW) and 2.5D packaging technologies. For example, CoW can also be in a 2.5D or 3D arrangement. Here, individual chips are bonded together (chip-to-chip), or bonded to an interposer (chip-interposer-chip). The bonding technology can be microbumps (dense I / O), or ACF, or hybrid bonding (metal-to-metal) that supports very dense I / O, or even optical bonding. Instead of individual chips, wafer-to-wafer (W2W) bonding is also possible and can be used according to the application. For example, CoW may involve a support wafer or panel with a larger split area than the chips mounted on the support wafer, while W2W may involve equal split wafer or panel areas. 2.5D packaging can use smaller dense interconnects to connect between two chips. The die for 2.5D packaging can be a shorter length passive bridge or a longer length arranged as a bonding strip. These bonding strips provide options for balancing bandwidth, power, complexity, heat, and power delivery, as well as other architectural requirements. Additionally, the bonding strip can be active silicon (or other device technologies such as GaAs). The bonding strip can also be encapsulated in a molding compound and optionally include multiple components connected by a bridge. Thus, the bonding strip for 2.5D packaging can also be formed and packaged separately using 2.5D packaging. Larger bonding strips may also have special requirements for assembly onto a substrate to manage mechanical stress and other assembly issues. The connection between the chip and the bonding strip can use solder (microbumps) or ACF and hybrid bonding (metal-to-metal). In some exemplary specific implementations, CoW integration can be used for performance logic components with dense I / O using microbumps or even more dense hybrid bonding. In some specific implementations, CoW integration can include hybrid bonding of silicon dies with an interposer. In some embodiments, CoW integration can include silicon dies connected to back-end-of-line (BEOL) interconnect devices in a chip-like manner. For example, the silicon die can have a partial BEOL stack structure and interconnect devices, where a subsequent second-level BEOL stack structure connects the silicon die in a chip-like manner. The silicon die can be embedded in an inorganic gap-fill (e.g., oxide) material, on which the second-level BEOL stack structure is formed. In some embodiments, 2.5D packaging can be used for chipset lighting functions with moderate bandwidth and latency requirements.

[0048] In a specific implementation, the bonding strip can be used as a memory strip to couple a set of memory chips to a logic chip. The set of memory chips can be laterally separated. Additionally, the laterally separated memory chips can each be encapsulated, or be part of a die stack or module with multiple dies. Thus, the laterally separated chips according to the embodiments can be part of laterally separated packages, die stacks, or modules. In one aspect, the bonding strip can enable the logic chip to communicate with various types of DRAM chips including LPDDR-x, DDR, HMB, etc. According to the embodiments, the memory chips are not limited to DRAM, or variants of LPDDR-x, DDR, HBM, etc. Similarly, the logic chip can include multiple functions such as, but not limited to, SOC, CPU, GPU, cache, signal processor, glue logic components, etc., and can be based on silicon or other technologies (e.g., GaAs). The bonding strip can include a local controller compatible with the memory type, and a physical interface (PHY) compatible with the memory (e.g., PHY analog and PHY digital controllers). In some specific implementations, the memory strip is packaged in configurations such as 2.5D packaging, multi-chip module (MCM), and MCM with a bridge. Additionally, the memory strip can be packaged in various shapes for routing, such as an L-shape.

[0049] According to the embodiments, configurations for modular expansion of logic components and / or memory are shown. In one aspect, on-chip resources can be used for logic component expansion. For example, on-chip wiring can be used to connect multiple dies on the same silicon layer. Such available on-chip resources can facilitate high-density, low-power expansion, and can also utilize CoW technology.

[0050] In another aspect, a bonding strip can be used for die expansion from a logic component to a logic component. Such a bonding strip or communication strip can include active silicon, increasing the area for logic connection, and providing expansion flexibility (e.g., SOC + CPU + GPU + others). Various cost control implementations can be included. For example, logic components can be moved from the logic chip to the communication strip to reduce the cost of the logic chip. The communication strip can also provide voltage shifting capabilities. Additionally, the communication strip can include discrete extended section regions, tapered structures, or hammerhead structures to reduce silicon cost as more dies are realized per wafer.

[0051] On the other hand, bonding strips can be used to increase the periphery of a logic chip for memory expansion. Such bonding strips or memory strips can facilitate expansion to large storage capacities. Additionally, a chain of memory strips can be used to further increase the capacity. According to embodiments, metal layer prioritization and merging can be used for latency management, especially for memory chips located relatively far from the logic chip. Similar to the through-silicon vias, various cost control measures can be included. Notably, the memory strip can be compatible with a variety of memory types including LPDDR-x, DDR, HBM, etc. In some embodiments, the memory strip can include a physical interface (PHY) and a memory (e.g., DRAM) controller. The memory strip can also provide voltage shifting capabilities.

[0052] In various embodiments, the description is made with reference to the accompanying drawings. However, certain embodiments may be implemented without one or more of these specific details or without combination with other known methods and configurations. In the following description, numerous specific details such as specific configurations, dimensions, and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known components, semiconductor processes, and manufacturing techniques are not described in particular detail so as not to unnecessarily obscure the embodiments. The phrase "in one embodiment" as referred to throughout the specification means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrase "in one embodiment" appearing multiple times throughout the specification is not necessarily referring to the same embodiment. Additionally, the specific features, structures, configurations, or characteristics can be combined in any suitable manner in one or more embodiments.

[0053] As used herein, the terms "on", "above", "to", "between", and "upon" may refer to the relative position of one layer with respect to other layers. One layer "on", "above", or "upon" another layer or bonded "to" another layer or in "contact" with another layer can be in direct contact with the other layer or can have one or more intervening layers. One layer "between" multiple layers can be in direct contact with the multiple layers or can have one or more intervening layers.

[0054] Figure 1FIG. 0 is a schematic top view illustration of a plurality of memory chips 102 (e.g., DRAM) around a logic chip 104 (e.g., SOC) disposed on a board 106 (e.g., printed circuit board (PCB) or multi-chip module (MCM)) in a conventional memory system. It has been observed that such systems may suffer from a limited logic chip 104 bonding area (e.g., the peripheral length of the SOC) with the memory chips 102. This limited area / periphery may constrain the ability to expand the storage capacity of the system. Additionally, it has been observed that direct chip attachment of the logic chip 104 and / or memory chips 102 to the board 106 may be problematic due to a coefficient of thermal expansion (CTE) mismatch, which may result in coarser pitch I / O and lower pin counts.

[0055] Figure 2 FIG. 4 is a schematic top view illustration of a multi-chip system 100 with an extended logic component according to one embodiment. Such a configuration can simplify the interconnect hierarchy of more conventional memory systems using CTE matching and without mechanically pinning a large silicon (or interposer) to a highly mismatched substrate (e.g., board 106). Additionally, the system can increase the logic chip periphery and the memory chip junctions with the SOC. In the illustrated embodiment, one or more logic chips 104 (e.g., SOC) and memory chips 102 can be mounted on a CTE matching substrate 120, such as glass, silicon, interposer, matched metal stable substrate, MCM substrate, etc. This CTE matching can allow for finer pitch bumping or anisotropic conductive film (ACF) attachment of the memory chips 102 and / or logic chips 104, and allow for greater silicon chip integration. A close CTE match with silicon can be obtained, for example, using glass, silicon, or an organic material with a large inorganic (e.g., glass) content. As used herein, the term "CTE matching" means that the "effective CTE" of a "composite material" or "composite topology" with different components matches the CTE of another single material or the effective CTE of another composite material. Inside a composite material, each of its components has its own CTE and elastic modulus. A non-limiting example of a so-called "composite material" can be an MCM substrate having multiple material layers. Another example of a "composite material" can be a memory (e.g., DRAM) chip or package as silicon, molding compound, and a memory package substrate. In such examples, the "effective CTE" of the MCM substrate can be designed to match the effective CTE of the memory chip or package to minimize overall MCM warping. The memory chip or package can also be considered a "composite topology" on the substrate. In a larger system example, all components on top of a (e.g., MCM) substrate can be considered a "composite topology". The effective CTE of the composite topology can be calculated, and the MCM substrate is designed to have an effective CTE that matches the effective CTE of the composite topology.

[0056] According to an embodiment, the substrate may be characterized by a composite coefficient of thermal expansion (CTE) that matches within + / - 4 ppm / C, or even more specifically within + / - 2 ppm / C, of the effective CTE of the composite topology on the substrate. The effective CTE and CTE matching depend on temperature. For example, silicon has a CTE of approximately 2.6 ppm / C at 20 °C and approximately 3.6 ppm / C at 250 °C.

[0057] An example of CTE matching for a silicon-based composite topology is to have the effective CTE of the package substrate (e.g., an MCM substrate) close to 3 ppm / C. In this case, glass cores as well as other high modulus and low CTE cores are suitable options for the MCM or package substrate. For an MCM composite topology with both a silicon SOC and multiple memory (e.g., DRAM) packages, the overall effective CTE of the composite topology on top of the MCM substrate can be calculated using finite element method (FEM) simulation. In the temperature range of 20 °C to 150 °C, typical values of the effective CTE of the composite topology can be in the range of 3 ppm / °C to 10 ppm / °C. At higher temperatures, such as close to the solder reflow temperature of 250 °C, the effective CTE of the composite topology including the molding compound may have an even higher effective CTE due to the increase in the CTE of the molding compound above its glass transition temperature (Tg), which is typically around 125 °C. For example, at temperatures above the Tg of the molding compound (e.g., 150 °C to 250 °C), the effective CTE of the DRAM package can be in the range of 8 ppm / C to 18 ppm / C, depending on the molding compound material properties and its relative volume to the DRAM die. By appropriately selecting the material properties of the MCM substrate as well as the appropriate material properties and geometric parameters (such as DRAM die thickness) of the DRAM package, the effective CTE of the MCM substrate can be matched to the DRAM package.

[0058] Additional components 108 such as disks, and the connection of components 110 such as local area network (LAN), wireless, optical devices, etc. can also be mounted on the substrate 120. In one embodiment, the substrate 120 is flexibly connected to the board 106 using a flexible circuit 112 instead of a rigid connection. Figure 2 The system 100 can additionally provide high bandwidth and high cost-performance memory expansion. For example, a long peripheral SOC can be obtained by using on-chip resources, CoW technology, or connecting smaller logic chips 104 (e.g., SOC) with through-silicon vias. Additionally, memory bars can be used to extend the connection of the memory chips 102 to the logic chips 104 with high bandwidth and reduced latency and power loss.

[0059] In another embodiment, the multi-chip system 100 includes routing and attachment through the MCM (including the substrate 120 and silicon chips mounted thereon) to the board 106 (e.g., PCB, other MCMs, modules, etc.). The attachment can be a suitable structure that allows for assembly and at the same time does not apply stress to the silicon chips on top. Such systems that allow the substrate 120 to be mounted on a PCB can employ sockets with pins, solder, etc. to manage mechanical stress.

[0060] Figure 3 Schematic top and side views of a multi-chip system with an extended logic component according to one embodiment are illustrated. Similar to Figure 2 the embodiment shown, the system 100 can include a single large logic chip 104 or multiple logic chips 104. The increased perimeter can facilitate the positioning of a greater number of memory chips 102. Additionally, due to the increased perimeter, the routing length to each memory chip 102 can be reduced, which can further improve the I / O speed. To increase strength and to control any CTE mismatch, stiffeners 122 (e.g., rings) can be placed on or in the substrate 120. As illustrated in the cross-sectional side view, the substrate 120 can include a plurality of vias 124 (or interconnect devices) leading to the back side. The memory chips 102 (or packages or die stacks) and the logic chips 104 can be mounted with solder bumps 105 (including micro-bumps), thereby allowing very large scale integration (VLSI) and fine pitch I / O due to CTE matching. As shown, attachment to the board 106 with a flexible circuit 112 allows the substrate 120 to be fixed to the board 106 using a suitable loose mechanical coupling 113 such as an adhesive film (or pressure sensitive adhesive).

[0061] Now referring to the appendix Figures 4 to 7 , which provides schematic top views and corresponding cross-sectional side views of various extended logic components according to embodiments. Figure 4 Schematic top view of an extended logic die with on-chip die-to-die routing according to one embodiment is illustrated. As shown, the logic chip 104 includes two dies 103, which can be routed together using on-chip routing 130 (such as using a common back-end-of-line (BEOL) process to form a stacked structure with M0 - Mn metal layers). In one embodiment, each die 103 can have its own metal seal ring 132, where the on-chip routing 130 extends through the seal ring 132. In Figure 4 the embodiment shown, the two dies 103 share the same silicon layer and are interconnected with the on-chip stacked structure (on-chip routing 130). Additionally, the two dies 103 can be provided separately cut or kept together.

[0062] Figure 5Schematic top view and corresponding cross-sectional side view illustrations of an extended logic component with 2.5D inter-die wiring according to one embodiment. As shown, logic chips 104 are connected together in a chip-on-wafer (CoW) package 107. In some embodiments, the logic chips may be embedded in molding compound (shown as shaded material). In other embodiments, the logic chips 104 are embedded in an inorganic gap-fill material (e.g., oxide shown as shaded material). The logic chips 104 may be bonded to the wiring layer 136 using micro-bumps, hybrid bonding, or the wiring layer 136 may be a second-level BEOL stack structure formed on the logic chips 104 (e.g., dielets). The logic chips 104 may be from different wafers (same or different technologies). In such a configuration, the wiring layer 136 may be used to connect two discrete logic chips 104. In one embodiment, the wiring layer 136 is an interposer or a second-level BEOL stack structure. In such embodiments, multiple micro-bumps or hybrid bonding may be utilized to mount two discrete logic chips 104 on the wiring layer 136 (interposer). For example, the wiring layer 136 may be a silicon substrate interposer for connection with the logic chips 104 (with vias for backside connection).

[0063] Figure 6 Schematic top view and corresponding cross-sectional side view illustrations of an extended logic component with 2.5D inter-die wiring and bridges according to one embodiment. Figure 6 Substantially similar to Figure 5 As shown, where bridges 140 are added within the wiring layer 136 (interposer). For example, the bridges 140 may be silicon bars with wiring layers. In one embodiment, different from the wiring layer 136 being formed by a silicon interposer, the wiring layer may include a dielectric material with dielectric vias and embedded bridges 140. In one embodiment, the bridges 140 may include active silicon, similar to through-silicon vias. In one embodiment, the bridges 140 are passive.

[0064] Figure 7 Schematic top view and corresponding cross-sectional side view illustrations of a hybrid extended logic component with on-die inter-die wiring and 2.5D inter-die wiring according to one embodiment. Figure 7 Substantially similar to Figure 5 As shown, where some on-die wiring 130 is added in combination with the wiring layer 136.

[0065] Now refer to Figure 8 , which provides schematic top view illustrations of various configurations for modular expansion of a logic component with increased peripherals according to one embodiment. As shown, various logic chips 104 (or die 103) may be used but are not limited to reference Figures 4 to 7Any of the illustrated and described exemplary configurations is extended to have die-to-die or chip-to-chip interconnect devices (generally shown as thick oval lines), including passive and active connection bars. Other on-chip network (NOC) topologies may also be used. As shown, when additional chips / dies are connected, the periphery can be increased. In other embodiments, the logic chip 104 is connected to the bonding bar or connection bar 160, as described in further detail herein. Figure 8 Also shown therein is an additional bonding bar or memory bar 150 that may extend from the logic chip 104. As described in further detail herein, the memory bar 150 can be used to couple the logic chip to an additional memory chip 102, thereby further increasing the connection density to the periphery of the logic chip 104.

[0066] Figure 9 Schematic top view illustration of an extended logic component connection according to one embodiment. The exemplary illustration provided has four logic chips 104, but this is intended to be exemplary and the embodiment is not limited thereto. As shown, each logic chip 104 can be connected. Additionally, the logic chip can have connections to external components.

[0067] Figure 10A Schematic top view illustration of the connection overhead of a logic component according to one embodiment. Figure 10B Schematic top view illustration of the connection overhead of an extended logic component according to one embodiment. As shown, each logic chip 104 can include areas reserved for inter-logic-chip connectors 162 and for external I / O connectors 164. Alternatively, the connectors 162 and 164 can be general-purpose ports. Generally speaking, for high performance, high-bandwidth interconnect devices can use serializer / deserializer (SerDes) technology, and the area and power loss of these ports can be significant. In the case of including wiring in a multi-chip module (MCM) or PCB, the on-chip area submitted may be larger than the area effectively used on the logic chip 104. Figures 11A to 11B An alternative logic component connection overhead according to one embodiment is shown, wherein the extended logic component connection overhead has one or more connection bars 160. As shown, each of the logic chips 104 can be manufactured to have similar built-in connectors 162, 164. In the illustrated embodiment, the total area reserved for the connectors 162, 164 can be significantly reduced, so less overhead is required in the logic chip 104. Additionally, the bandwidth and power are more scalable. One or more connection bars 160 can be used to connect multiple logic chips.

[0068] Now refer to Figures 12A to 12B , Figure 12A Schematic top view of a 3D extension of a logic chip with a connection bar 160 according to one embodiment, and Figure 12BSchematic top view of a planar expansion of a logic chip with a connection bar 160 according to an embodiment. As shown, the connection bar 160 can be used to provide modularity to various combinations of a logic chip 104 including a CPU, GPU, cache, signal processor, glue logic components, etc., as well as an SOC. In Figure 12A the embodiment shown, the connection bar 160 can be placed above / below the logic chip 104. In Figure 12B the embodiment shown, the connection bar 160 can be placed laterally adjacent to the logic chip 104.

[0069] The connection bar 160 according to the embodiment can be used to provide high-bandwidth, low-power, scalable connectivity between two or more chips. Using the connection bar allows for flexible positioning of I / O terminals on the logic die without having to be at the die / chip edge. Additionally, there is flexibility in the start and end positions. In some embodiments, the connection bar 160 can include active silicon blocks and can provide flexibility and design convenience to the logic chip 104.

[0070] Now refer to Figures 13 to 14 , which provides a schematic top view illustration of a multi-chip system with expanded logic components and memory according to an embodiment. As shown in each figure, the logic chips 104 are electrically connected optionally, for example, using any arrangement of Figures 4 to 7 . Additionally, the logic chips 104 can be electrically connected to the connection bar 160. The logic chips / dies can also be connected to the connection bar 160 using a combination of Figures 4 to 7 . Other connection bars that complete the "X" connection can be implemented using cross switches or jumpers between them. Additionally, groups of memory chips 102 are coupled to the logic chips 104 using memory bars 150, which can be optionally placed in series to increase memory density. Thus, according to the embodiment, the connectivity organization, even the bandwidth and latency, can be customized. Additionally, the logic chips 104 do not need to be pre-submitted to provide maximum bandwidth and wiring resources. Specifically, Figure 13 the arrangement in Figure 14 can be for high storage capacity, with the drawback of relatively more latency between the logic chips 104, while specifically, Figure 13 the arrangement in Figure 18C can be used for short logic component connections, less latency, and relatively small storage capacity. Referring back to Figure 13 , a long bonding bar that can be flexible is also shown. For example, such a long bonding bar can be the connection bar 160 for inter-logic component connections or the memory bar 150 for memory connections. As described in further detail with reference to Figure 18C , such a long bonding bar can be an optical interconnect.

[0071] Figure 15Schematic cross-sectional side view illustration of a bonding bar metal wiring layer according to one embodiment. As described above, both the communication bar 160 and the memory bar 150 can be more generally characterized as bonding bar 1500. In the illustrated embodiment, the bonding bar 1500 includes a substrate 1502 and a wiring layer 1510. The substrate 1502 can be formed of a semiconductor material such as silicon to support front-end semiconductor manufacturing of devices. Thus, the silicon substrate 1502 can include active silicon 1504 (or other materials) to include features such as logic components, repeaters, flip-flops, caches, memory compressors and decompressors, controllers, local processing elements, etc. If appropriate, other non-silicon technologies such as but not limited to GaAs, and even optical interconnect technologies (many of which are supported by silicon) can also be used for the substrate 1502. The wiring layer 1510 can include one or more metal layers and dielectric layers. The wiring layer 1510 can be formed using thin film technology or conventional BEOL processing techniques such as metal inlay, etc. The wiring layer 1510 can include a lower wiring layer M A , an intermediate wiring layer M B , M C , and an upper wiring layer M D and other wiring layers. As shown, the wiring layers can optionally have different thicknesses, where M D is the thickest, and M A is the thinnest. In some embodiments, quality of service can be used to organize metal usage based on requirements such as latency, power, etc. In one embodiment, high-priority communications with low latency requirements can be on higher (thicker) layers, while bulk communications with a larger latency range can be in lower (thinner) layers. In one embodiment, longer connections to chips located further away from the bonding bar 1500 or further along the longitudinal length of the bonding bar 1500 can be formed with higher (thicker) layers, while shorter connections within the bonding bar 1500 can be formed with lower layers. In some embodiments, the bonding bar 1500 (e.g., communication bar 160 or memory bar 150) includes vias (e.g., through-silicon vias) that extend through the substrate 1502. For example, the vias can be similar to Figure 18A the vias 166 shown.

[0072] Referring again Figures 13 to 14 , in one embodiment, a multi-chip system includes a first chip (e.g., logic chip 104), a bonding bar 1500 (e.g., memory bar 150) coupled to the first chip, and a second chip (e.g., memory chip 102) coupled to the bonding bar. The bonding bar includes a wiring layer 1510 that optionally extends a substantial portion of the longitudinal length of the bonding bar 1500. Referring back Figure 11B, specifically, in other embodiments, the wiring layer 1510 may not necessarily extend over a substantial portion of the longitudinal length of the bonding strip 1500. Thus, such configurations depend on the particular implementation. Still referring to Figures 13 to 15 , the wiring layer 1510 includes a plurality of metal layers, which include a lower wiring layer (e.g., M A ) and an upper wiring layer (e.g., M D , or any wiring layer above M A ), and the upper wiring layer is characterized by a wider wiring than the lower wiring layer. In one embodiment, the second chip (e.g., memory chip 102) is electrically coupled to the first chip (e.g., the same memory chip 102) via a first wire that extends a substantial distance along the longitudinal length in the upper wiring M D . A third chip (e.g., another memory chip 102) may be electrically coupled to the first chip (104) via a second wire in the lower wiring layer MA, where the first wire is wider than the second wire, and the second chip (102) is positioned farther from the first chip (104) than the third chip (102). Thus, the second chip may be a second memory chip 102 positioned farther from the logic chip 104 than the first memory chip 102, and both are connected to the logic chip 104 via the same memory strip 150.

[0073] According to an embodiment, the bonding strip 1500 is not only for wiring but may also include active silicon. Figure 16 is a schematic top view illustration of an extended system with inter-die wiring according to an embodiment. The specific embodiment shown is similar to Figure 5 or Figure 7 wherein a plurality of logic chips 104 are connected together to a wiring layer 136 (or an interposer). Each logic chip 104 may also include a die-to-die input / output (I / O) region 1602 and an on-chip wiring tunnel 1604. The actual die-to-die wiring 1610 is located on the wiring layer 136 (interposer). Thus, each logic chip 104 includes a die region for the on-chip wiring tunnel 1604, which may include resources such as wires, repeaters, flip-flops, etc. Each logic chip 104 (or die) may additionally include a high-performance logic region 1607 that may be located near adjacent logic chips 104. The high-performance logic region 1607 may also be partitioned out.

[0074] Figure 17 is a schematic top view illustration of bonding strip wiring according to an embodiment. As shown, the bonding strip may be a connection strip 160 that couples a plurality of logic chips 104. The logic chips 104 are connected to Figure 16The difference in those shown is that the area previously reserved for the on-chip wiring tunnel 1604 can be repositioned as the wiring tunnel 1704 to the connection bar 160. This provides greater flexibility for designing the high-performance logic region 1607. Additionally, the die-to-die wiring 1610 is moved to the connection bar 160. Thus, the wiring layer 136 (interposer) can optionally be omitted or supplemented with the connection bar 160. In one embodiment, the connection bar 160 is located in the wiring layer 136, similar to Figure 6 shown. Further, the position of the I / O region 1602 is flexible, and the I / O region 1602 does not have to be located at the die edge. The connection bar 160 can optionally include vias for I / O and power / ground connections (see Figure 18A ).

[0075] Figure 18A is a schematic cross-sectional side view and top view illustration of a bonding bar and wiring according to one embodiment. In the specific embodiment shown, the bonding bar can be the connection bar 160 that couples multiple logic chips 104. As shown, the logic chips 104 and the connection bar 160 can be connected by a plurality of solder bumps 105 (including micro-bumps). The connection bar 160 can include active devices such as a deserialiser 1812, a serializer 1814, and a plurality of channels 1820 extending between the deserialiser 1812 and the serializer 1814. The channels 1820 can be coupled to active devices 1822 such as repeaters, flip-flops, etc. The corresponding logic chips 104 can additionally include transceivers 1802 and receivers 1804. In one embodiment, the bonding bar or connection bar 160 includes a deserialiser 1812, a serializer 1814, and a plurality of repeaters (e.g., active devices 1822) located between the deserialiser and the serializer. In suitable cases, the connection bar 160 can also support other signalling schemes such as pulse amplitude modulation (PAM), simultaneous bi-directional (SBD), low swing differential, etc. In suitable cases, the connection bar 160 can support other non-silicon technologies such as, but not limited to, GaAs. According to an embodiment, the connection bar 160 can provide level conversion capabilities as needed. Additionally, for longer interconnect devices, optical interconnect devices can be used as the connection bar 160. Figure 18CSchematic top view illustration of an optical connection bar according to an embodiment. For example, the connection bar 160 may be an optical interconnection device including one or more waveguides 1850 that are bonded to transmitters / receivers in the first logic chip / die 104 / 103 and transmitters / receivers in the second logic chip. The optical transmitter may be located in the electro-optical converter component 1852. The optical transmitter may be a suitable type such as a laser, a light-emitting diode, or other light source, a modulator, etc. The optical receiver may be located in the opto-electronic converter component 1854. The optical receiver may also be selected based on optical link requirements from a variety of photodetectors (avalanche photodiodes, p-i-n photodiodes, etc.) and conversion electronics. Such optical connection bars may be optical-exclusive or may be mixed with tele-signaling. For example, depending on requirements, tele-signaling may be used for shorter distances, while optical signaling is used for longer distances. Additionally, the waveguides may be flexible, allowing for mechanical release (from mechanical stress) or system integration (non-planar options), and options up to longer distances. Such optical connection bars may have non-rigid waveguides 1850 (e.g., fiber-like) that allow for mechanical twisting. This flexibility may allow for rotation, folding, etc., allowing for more system options.

[0076] Refer again to Figure 18A , according to an embodiment, a higher raw data rate may be achieved using a deserializer 1812, serializer 1814 architecture. According to an embodiment, efficiency may be further improved by providing an alternative spare channel 1820 between the deserializer 1812 and the serializer 1814. In the event of a failure in one channel, the spare channel may be switched on. For example, the failure may be a hard failure such as a wire break or short circuit, or a soft failure such as an edge wire that causes the voltage of all channels to increase compared to other wires in the same link. The spare channel may be switched in and may result in a lower voltage, and thus power may be restored when the voltage can be reduced.

[0077] Now specifically refer to Figure 18ACross-sectional side view of which provides a 2.5D packaging implementation where the connection bar 160 connects two logic chips 104. As shown, the connection bar 160 is encapsulated in an insulating material 1838 (e.g., molding compound) and routed through a redistribution layer (RDL) 1832. In the illustrated implementation, the logic chips 104 are encapsulated in a molding compound 1840, where the redistribution layer (RDL) 1832 is located on the front side of the logic chips 104. For example, the RDL 1832 can be formed using thin film processing techniques. The connection bar 160 can be mounted on the RDL 1832 using solder bumps 105 (e.g., micro-bumps), which are optionally encapsulated with an underfill material 1830 between the connection bar 160 and the RDL 1832. The insulating material 1838 is formed above the connection bar 160. Then the insulating material 1838 can be optionally planarized, after which the RDL 1834 is formed and the solder bumps 105 are placed. In Figure 18A Only one direction is shown, but the connector can extend in two directions. Additionally, the capabilities in the two directions can be the same or different depending on the application.

[0078] Still referring to Figure 18A , in some embodiments, the 2.5D packaging structure 1835 can include conductive pillars 1836 that extend between the RDLs 1832, 1834. For example, these can be formed in a via-first technology where the conductive pillars 1836 are electroplated and then the insulating material 1838 is applied, or can be formed in a via-last technology where vias are etched into the insulating material 1838 and then the conductive pillars 1836 are deposited or grown. Additionally, the connection bar 160 can also include vias 166 for backside connection to the RDL 1834.

[0079] As a cost-saving option, the use of additional RDL 1832 and insulating material 1838 (e.g., molding compound) can be avoided. In Figure 18B the illustrated embodiment, the connection bar 160 or device can be directly attached to the outside of a wiring layer 1839 (e.g., including multiple RDLs and dielectric layers) on the solder bump 105 side (e.g., ball grid array BGA side). There may be some trade-offs in pin density. The connection bar 160 can still have the option of TSV166 and its connection to the solder bumps 105.

[0080] According to embodiments, the connection bar 160 can be passive or include active silicon. Additionally, the use of the connection bar 160 can form a short connection length (e.g., within the size range of the solder bumps 105) between the connection bar 160 and the wiring in the logic chips 104, which can reduce the voltage requirements for power gain. Additionally, simple coding can be used to increase the effective bandwidth of the connection.

[0081] Although Figure 18AThe illustrated embodiments are specific to the 2.5D package structure 1835, but the embodiments are not limited thereto and can be extended to other packaging solutions such as CoW where the signal density may be higher. For example, the logic chip 104 and the interposer bar 160 can be implemented into Figures 5 to 7 various CoW structures for connecting the logic chip 104.

[0082] In some aspects, various cost control implementations may be included. For example, logic components can be moved from the logic chip 104 to the interposer bar 160 to reduce the cost of the logic chip 104. Additionally, the interposer bar can include discrete extended section regions, tapered structures, or hammerhead-shaped structures to reduce the silicon cost. Figure 19 is a schematic top view illustration of a bonding bar having a hammerhead shape according to one embodiment. As shown, the bonding bar can be the interposer bar 160 that connects multiple logic chips 104. As described above, the interposer bar 160 can have a chip-to-chip connection 162 region that is reserved for bonding with the die-to-die input / output (I / O) region 1602 of the logic chip 104. This region can be larger than the region required for routing or repositioning logic components. In one embodiment, the interposer bar includes a head component 170 and an extended section 172 that extends along the longitudinal length of the bonding bar 160, where the head component 170 is wider than the extended section 172. For example, the extended section 172 can include a repeater or the like. In this way, the amount of silicon cost can be reduced. In other embodiments, the extended section 172 is passive rather than active.

[0083] Figure 20 is a schematic top view illustration of a bonding bar including relocated die logic components according to one embodiment. In one aspect, a logic component on the active logic chip 104 may increase the area, and it may be difficult to provide redundancy for such logic components, especially for the active logic chip 104 such as an SOC, which is in contrast to array elements such as GPUs where it may be easier to provide spare parts with area efficiency. According to the embodiment, a portion of such logic components 2010 can be relocated to the interposer bar 160 where space is available. This can improve the efficiency of the logic chip 104. By way of example, the logic components 2010 can include non-I / O-intensive or ultra-high-power random logic components (e.g., glue logic components). In another implementation, the necessary logic components remain as a component on the main logic area of the first logic die, while the additional logic components required for the second component (e.g., spare part) can be moved to the interposer bar. In other embodiments, the redundant logic components remain in the main logic chip 104. However, the logic components required once or several times (not every operation instance of the logic chip 104) can be moved to the interposer bar 160. Alternatively, such logic components can be separate but connected using the interposer bar 160.

[0084] Figure 21 is a schematic top view illustration of a bonding strip active region according to one embodiment. According to some embodiments, the bonding strip or via strip 160 may include a head component 170 for supporting chip-to-chip connectors and solder bumps 105 (e.g., micro-bumps), and an extension section 172. In some embodiments, these may be integral components or discrete components. In one embodiment, the head component 170 and the extension section 172 are encapsulated in an insulating material 174. Alternatively, Figure 21 the region shown as insulating material 174 in may be non-active silicon. In some embodiments, additional cost savings may be achieved by dividing the active silicon region of the extension section into discrete active components 176. Figure 22 is a schematic top view and corresponding cross-sectional side view illustration of a bonding strip having multiple discrete active components 176 according to one embodiment. Such a configuration may provide lower cost (by reducing the active silicon region), scalable bandwidth strips without changing the silicon (by increasing the width of the components 176 and re-integrating into a wider strip), lower power (by selecting appropriate technologies and voltages, and possibly combining process corner components), improved power noise (by including decoupling capacitors in the strip). In one embodiment, the bonding strip or via strip 160 includes one or more discrete head components 170 and one or more discrete active components 176 (e.g., active silicon die), wherein the discrete head components 170 and the one or more discrete active components 176 are electrically coupled to a wiring layer 180. In this regard, the active silicon region may be significantly reduced. By way of example, the component 176 may be a simple repeater, retimer, or other more complex structure such as a crossbar switch. Additionally, the via strip may be dual-port, point-to-point, or have several ports.

[0085] The discrete head components 170 and the one or more discrete active components 176 may be (encapsulated) in an insulating layer 174. Various packaging methods may be used to form the via strip 160, including CoW, 2.5D packaging. The discrete head components 170 and the discrete active components 176 may be bonded to the wiring layer 180, for example, with micro-bumps (not shown), or alternatively, the wiring layer 180 may be formed over the encapsulated discrete head components 170 and discrete active components 176.

[0086] So far, the bonding bar is generally described, and several specific examples are given with reference to the connection bar 160. It should be understood that although there may be some differences due to function, many of the ideas are equally applicable to both the memory bar 150 and the connection bar 160. For example, the connection bar 160 can be passive or active, where the main activity is the repeater. Other areas may be less intensively used, so several cost-saving implementations are adopted, although the cost-saving implementations may also be applicable to the memory bar 150. Another difference may be that the memory bar 150 can support a physical interface (PHY) / controller that requires space. In addition, the memory bar 150 may also include a cache below, and wiring on the top. Therefore, by comparison, the memory bar 150 silicon can be effectively used. The memory bar 150 may also include additional functions, devices such as memory compressors and decompressors, reliability enhancements (such as chip hunting), controllers for non-volatile memory (as a memory extension), and local processing elements (close to the memory).

[0087] Figure 23 is a schematic top view illustration of an expanded system 100 including a memory bar bridge 190 according to one embodiment. In an exemplary embodiment, the system includes a plurality of chips and bars supported by a substrate 120 such as glass, silicon, an interposer, etc. The system includes a first logic die 103 coupled to a second logic die 103, a first set of laterally separated memory chips 102 connected to the first logic die 103, and a second set of memory chips 102 connected to the second logic die 103. As shown in FIG. Figures 4 to 7 As described above, the logic die 103 may be formed from the same piece of silicon, or may be included in a separate logic chip 104. In one embodiment, the first logic die 103 and the second logic die 103 share the same silicon layer and are interconnected with on-chip wiring 130, similar to the reference Figure 4 In one embodiment, the first logic die 103 and the second logic die 103 are discrete chips and are connected to a shared wiring layer 136 (or interposer). For example, the shared wiring layer 136 may include a silicon bridge 140 connecting the first logic die and the second logic die. The silicon bridge may be passive or contain active silicon. In one embodiment, the first logic die and the second logic die are logic chips 104 and are connected to a connecting bar 160. For example, the connecting bar may include a deserializer 1812, a serializer 1814, and a plurality of repeaters (active devices 1822) located between the deserializer and the serializer. The connecting bar 160 may be a packaged component. In one embodiment, the connecting bar 160 includes a discrete active component 176 (also covering a discrete active section 172) and a discrete header component 170 encapsulated in an insulating layer 174, and a wiring layer 180 connecting the discrete active component 176 and the discrete header component 170.

[0088] According to an embodiment, a scalable system is described where the periphery of logic chip 104 is increased to the memory chips 102. Additionally, these systems can be scaled to have high bandwidth, low latency, and be power and cost optimized. The periphery of logic chip 104 can be extended not only by connecting multiple logic chips 104, but also by utilizing memory strips 105 for peripheral extension. In Figure 23 the embodiment shown, some of the memory chips 102 can be directly routed to the logic chip 104 using wiring 121. The storage capacity can also be extended with memory strips 150, and additional memory chips 102 are routed to the memory strips 150 using wiring 123. The memory strips 150 can also be extended using high density bridges 190, which can be similar to silicon dice with wiring layers.

[0089] It should be understood that although the above description is made with reference to memory chips 102, it should be understood that the term includes configurations with stacked memory dies and memory packages. Thus, the embodiments can be compatible with a variety of memories, such as but not limited to LPDDR-x, HBM, HMC, etc.

[0090] The memory strip 150 according to an embodiment can support physical interfaces (PHY) / controllers that require space together with the logic die 104. Additionally, the memory strip 150 can also include a cache below and wiring on the upper part. The memory strip 150 can also include additional functions, such as devices like memory compressors and decompressors, reliability enhancements (such as chip kill), controllers for non-volatile memory (as memory expansion), and local processing elements (close to the memory). According to an embodiment, the connection strip 150 can provide level conversion capabilities as needed.

[0091] In a specific embodiment, the memory strip 150 can include error correction code (ECC) to enhance reliability, availability, and serviceability (RAS). Specifically, the ECC can correct errors in the memory chips 102 caused by soft errors, such as electrical or magnetic interference, which cause a single bit of dynamic random access memory (DRAM) to spontaneously flip to the opposite state. In contrast, conventional LPDDR-x memory systems may not include ECC on the external I / O. The memory strip 150 according to an embodiment can store ECC data, which can be combined with the main data from the DRAM (e.g., memory chips 102). Parity or cyclic redundancy check (CRC) of the data can also be stored on the memory strip 150. These can help detect errors. In case of an error, the data can be re-requested from the memory. In one embodiment, part of the memory can be protected by ECC (e.g., operating system, critical software), while other memory is protected by parity or CRC.

[0092] According to an embodiment, the system may include wiring 123 to an extended area of miscellaneous component 2400, as Figure 24 shown. The extension may be to a variety of miscellaneous components 2400, such as spare memory, alternative memory expansion, and spare die or variable retention time (VRT) support. In one embodiment, the miscellaneous component 2400 is a spare memory chip 102 or package for efficiency and RAS. A spare channel (or channel) group may be provided in the active logic chip 104 and the memory bar 150 to provide full redundancy for the memory chip 102 or package. In such embodiments, the system may be tested after assembly to check for faulty die, chips, packages. If a particular memory die or channel (or channel) is detected, a replacement may be populated. Alternatively, a complete memory chip 102 or package may be added. Additionally, spare components may be initially populated during assembly. The spare components are activated and logged during testing. Then, the controller maps the faulty device / chip and maps the spare component to the faulty device / chip.

[0093] In one embodiment, the miscellaneous component 2400 is a spare die to assist VRT checking. Thus, the spare die may be used to detect potential DRAM errors and take appropriate measures. In such embodiments, the application data is located in the spare die. The vacant memory chip 102 (DRAM) is VRT tested and may be marked such that the device can be isolated, repaired, or partially vacant. Alternatively, the tested memory chip 102 is kept cool to assist in maintaining retention time, margin.

[0094] In one embodiment, the miscellaneous component 2400 is an alternative memory component for memory expansion. For example, the alternative memory component can be a non-volatile memory (NVM), such as but not limited to flash memory and phase change memory (PCM). The memory bar 150 may include interface / logic components for supporting NVM, and the interface / logic can provide a significantly increased capacity for uses such as program code storage, static storage, etc. Additionally, NVM can be less expensive, but also slower and less reliable. In one embodiment, NVM may have a strict write or read incidence (such as once a day) or wear limit. In one embodiment, the NVM can provide a quick checkpoint service (under operating system / software control). Once prompted, all memory contents can be extracted and stored in the NVM. Another use can be for extended memory for a search engine (where reads are prioritized over writes), where less information can be retained here. However, a long memory carriage can have longer latency and use more power. However, the average latency and power can be relevant to many applications. Additionally, logic components on the software or memory bar (or controller) can allocate memory such that generally, frequently used memory lines / pages / blocks can be closer to the logic chip (e.g., SOC), while less frequently used lines are farther away.

[0095] According to an embodiment, various cost control solutions can be implemented into the bonding bar or memory bar 150 design. Figures 25 to 26 FIG. is a schematic top view illustration of a bonding bar with different form factors according to an embodiment. Figure 25 is similar to that previously described and shown for Figure 19 the hammerhead-shaped memory bar 150 of the connection bar 160 in. As shown, the memory bar 150 may include a head component 170 and an extension section 172 extending from the head component 170 along the longitudinal length of the memory bar. The hammerhead-shaped structure can optimize the silicon area and avoid bottlenecks caused by high I / O density, where the head component 170 is wider than the extension section 172. Figure 26 FIG. is an illustration of a tapered memory bar 150 design that can save silicon costs. In this configuration, the width of the extension section 172 gradually decreases along the longitudinal length. This may be reasonable because the number of interfaces, channels, and logic components required when the memory chips 102 are maintained along the longitudinal length is reduced. In one embodiment, the wiring layer 1510 (see Figure 15 ) includes at least a lower wiring layer M A and an upper wiring layer M D . The wiring layer 1510 can extend a significant portion of the longitudinal length of the memory bar. As shown, the wiring layers can optionally have different thicknesses, where M D is the thickest, and M Ais the thinnest. The memory chip 102 farthest from the active logic chip 104 can be electrically coupled to the active chip through a first wire that extends a significant distance along the longitudinal length in the upper wiring layer M D while the chip 102 positioned closer to the active logic chip 104 can be electrically coupled to the active chip through a second wire in the lower wiring layer M A of the.

[0096] Figure 27 is a schematic top view and cross-sectional side view illustration of a bonding strip having discrete active regions and a head region according to one embodiment. According to some embodiments, the bonding strip or memory strip 150 may include a head component 170 for supporting a PHY connection, hybrid bonding, anisotropic conductive film (ACF), high-density metal-to-metal bonding (CoW), or other high-density attachment to the logic chip 104 and solder bumps 105 (e.g., micro-bumps), and an extension section 172. In some embodiments, these may be integral components or discrete components. In one embodiment, the head component 170 and the extension section 172 are encapsulated in an insulating material 174. Alternatively, Figure 27 the region shown as the insulating material 174 in may be inactive silicon. The head component 170 may be coupled to the logic chip 104 through wiring 129, which may optionally be located on the substrate 120. In a similar configuration, as shown and described with reference to Figure 30 the components of the memory strip 150 may be arranged in an L-shaped configuration.

[0097] Various packaging methods can be used to form the memory strip 150, including CoW, 2.5D packaging. The discrete head component 170 and the discrete extension section 172 can be bonded to the wiring layer 180 using, for example, micro-bumps (not shown), hybrid bonding, anisotropic conductive film (ACF), high-density metal-to-metal bonding (CoW), or other high-density attachment, or alternatively, the wiring layer 180 can be formed over the packaged discrete head component 170 and discrete active component 176.

[0098] Now specifically refer to Figure 28 , Figure 22The wiring layer 180 can be a 2.5D packaging structure 2835, which includes high-density bridge members 200 and optionally one or more high-density bridge members 190. As shown, the head component 170 and one or more active regions 172 are encapsulated in an insulating material 174 (e.g., molding compound), and optionally wired with a redistribution layer (RDL) 2832. In the specific embodiment shown, the high-density bridge members 200, 190 are encapsulated in an insulating material 2838, where an optional redistribution layer (RDL) 2832 connects the head component 170, the extension section 172, and the high-density bridge members 200, 190. For example, the RDL 2832 can be formed using thin-film processing techniques. The high-density bridge members 200, 190 can be mounted on the RDL 2832 using a suitable technique such as but not limited to solder bumps 105 (e.g., micro-bumps), which are optionally encapsulated with an underfill material 2830 between the high-density bridge members 200, 190 and the RDL 2832. The insulating material 2838 is formed above the via bar 160. Then the insulating material 1838 can be optionally planarized, after which an optional RDL 2834 is formed and solder bumps 105 are placed.

[0099] Still referring to Figure 28 , in some embodiments, the 2.5D packaging structure 2835 can include conductive pillars 2836 extending between the RDLs 2832, 2834. For example, these can be formed in a via-first technology, where the conductive pillars 2836 are electroplated and then the insulating material 2838 is applied, or can be formed in a via-last technology, where vias are etched into the insulating material 2838 and then the conductive pillars 2836 are deposited or grown. Although Figure 28 the embodiment shown is specific to the 2.5D packaging structure 2835, the embodiment is not limited thereto and can be extended to other packaging solutions such as CoW. Additionally, the high-density bridge members 200, 190 can also support through-silicon vias.

[0100] The multi-chip system according to the embodiment can be assembled using various packaging solutions. Referring briefly back to Figures 2 to 3 , the system 100 can include a multi-chip module (MCM) having a glass core substrate 120 with a CTE matched to silicon, e.g., to keep the mismatch with the logic chip 104 and the memory chip 102 in the composite topology small, and to allow fine-pitch flip-chip integration, allow a thinner core of the substrate 120, and reduce the overall z-height. In addition, the flexible circuit 112 to the board 106 can reduce the z-height by reducing or eliminating the height caused by the ball grid array (BGA) attachment. Additionally, the BGA attachment thermal temperature is avoided, as well as the warpage associated with the BGA. The stiffener 122 can also improve the warpage at low temperatures and the warpage associated with handling.

[0101] Now refer to Figures 29A to 29B , which provides a schematic top view and a cross-sectional side view illustration of an extended system having a bridge for connecting a logic chip to a memory strip according to one embodiment. As shown, the system may include a substrate 120, such as an MCM substrate. For example, the substrate 120 may optionally include a core 2910 (e.g., a glass core), a top wiring layer 125, an optional bottom wiring layer 127, and optional vias 124 extending between the top wiring layer 125 and the bottom wiring layer 127. The substrate 120 may be formed of a variety of materials, such as but not limited to glass, silicon, an interposer, a matched metal stable substrate, etc. The core 2910 may be formed of a variety of materials, such as but not limited to a glass core, a metal core, etc. As shown, the bridge 2900 (e.g., a local high-density bridge) may be located within the wiring layer 125, where the logic chip 104 and the memory strip 150 are mounted on the wiring layer 125 (e.g., using flip chips and solder bumps), and the bridge 2900 electrically couples the logic chip 104 and the memory strip 150. This may be a direct coupling, and / or a coupling using additional wiring in the wiring layer 125. Such a configuration may be used to improve the connectivity (e.g., bandwidth, power complexity) of the substrate 120. As Figure 29A shown, the memory strip 150 may be coupled to a plurality of memory chips 102, which are mounted on the wiring layer 125 and electrically coupled to the memory strip 150 through wiring 123 in the wiring layer 125. In one embodiment, the bridge 2900 (e.g., a high-density bridge) includes active components. For example, the bridge may include active silicon.

[0102] Figure 30 is a schematic top view illustration of an extended system 100 having substrate wiring 129 in the wiring layer 125 for connecting the logic chip 104 to the memory strip 150 according to one embodiment. Thus, the wiring on the substrate 120 is used to electrically connect to the memory strip 150, which is different from the Figures 29A to 29B bridge 2900. As Figure 30 shown, the logic chip 104 and the memory strip 150 are mounted on the wiring layer 125 (e.g., using flip chips and solder bumps), and are electrically coupled through the wiring 129 in the wiring layer 125. Similarly, a plurality of memory chips 102 may be mounted on the wiring layer 125 and electrically coupled to the memory strip 150 through the wiring 123 in the wiring layer 125. The specific embodiment shown may relate to a 2.5D package of the memory strip 150, but this may also be manufactured using a CoW-like attachment. For example, the micro-bumps used to attach the memory strip 150 may be replaced by a more dense hybrid bonding. The dielectric for the hybrid bonding may be oxide-based. The example is similar to Figure 12A . The CoW-like attachment may also support a hammerhead or tapered structure as appropriate.

[0103] Specifically, Figure 30 the memory bar 150 shown can be formed using a 2.5D packaging configuration similar to that shown and described with reference to Figure 27 , including a head component 170, an extension section 172, and a high-density bridge 200. Notably, the components can be arranged in an L-shaped configuration, which can increase the perimeter of the logic die 104, improve the packaging density of the memory chips 102, and thus reduce the cost of the memory bar 150. Additionally, the vertically oriented head component 170 increases the area between the edge of the logic die 104 and the head component 170, which can allow for the integration of more wiring 129 traces and higher bandwidth.

[0104] Now refer to Figures 31A to 31C , which shows various 2.5D stacked package (PoP) configurations for an expansion system. Figure 31A is a schematic top view of a PoP expansion system according to one embodiment, while Figures 31B to 31C is a cross-sectional side view illustration of a different implementation taken along the wiring (arrows) shown in Figure 31A . Specifically, Figure 31B the implementation shown can replace the substrate 120 or be used in combination with the substrate 120. Figure 31C The implementation shown can be used in combination with the substrate 120. Specifically refer to Figures 31A to 31B , the system 100 includes a lower RDL 3102, a first molding layer 3110 on the lower RDL 3102, and the memory bar 150 is encapsulated in the first molding layer 3110. A second RDL 3124 can be formed above the encapsulated memory bar 150 and the first molding layer 3110. In one embodiment, the memory bar 150 is a flip chip bonded to the second RDL 3124 using solder bumps 105. A second molding layer 3120 is above the second RDL 3124 and the first molding layer 3110, and the logic chip 104 can be encapsulated in the second molding layer 3120. A plurality of vias 3112 can connect the lower RDL 3102 and the second RDL 3124. Additionally, a second plurality of vias 3122 can be formed through the second molding layer 3120. In the implementation shown, a plurality of memory chips 102 are mounted on top of the second molding layer 3120. The plurality of memory chips 102 can be electrically coupled to the logic chip 104 through the memory bar 150 and the plurality of vias 3122. As described herein, the memory chips 102 can be a single memory device, a stack, or a module.

[0105] Now refer to Figure 31A and Figure 31C, in one embodiment, the system includes a memory bar 150 encapsulated in a first molding layer 3210. The logic chip 104 and multiple memory chips 102 are all mounted on top of a second molding layer. For example, they can be connected to the memory bar 150 and optionally the RDL formed on the first molding layer 3210. A bottom RDL can also be optionally formed under the first molding layer 3120 and the encapsulated memory bar 150. The encapsulation structure can be optionally bonded to the substrate 120, for example, using flip chips and solder bumps 105. As Figure 31C shown, in such a configuration, the heights of the logic chip 104 and the memory chips 102 are not cumulative, which can contribute to a low z-height encapsulation configuration.

[0106] According to an embodiment, bonding bars 1500 (such as the communication bar 160 and the memory bar 150) can be combined to form an extended memory system, and can be encapsulated using the configurations described and shown previously. For example, referring again to Figures 13 to 14 , in one embodiment, the memory system includes a first logic chip 104, a second logic chip 104, and a communication bar 160 coupling the first logic chip 104 and the second logic chip 104. A first memory bar 150 is coupled to the first logic chip 104, and a second memory bar 150 is coupled to the second logic chip 104. A first group of laterally separated memory chips 102 is coupled to the first memory bar 150, and a second group of laterally separated memory chips 102 is coupled to the second memory bar 150.

[0107] The memory bars can also be bridged. For example, referring again to Figure 23 , the system can additionally include a third memory bar 150 and a third group of laterally separated memory chips 102 coupled to the third memory bar 150. Additionally, a bridge 190 couples the second memory bar 150 to the third memory bar 150. In other configurations, such as Figure 28 shown, the memory bar 150 can include multiple extension segments 172 coupled to one or more bridges 190.

[0108] According to an embodiment, the first logic chip and the second logic chip 104, and the first group of laterally separated memory chips and the second group of laterally separated memory chips 102 can be mounted on the substrate 120. Although shown as rectangular herein, it should be understood that the substrate can have any suitable shape. As Figures 2 to 3 shown, the substrate 120 can be coupled to the board 106 using a flexible circuit 112. As described herein, the communication bar 160 and the memory bar 150 can be encapsulated independently or together with the system. In a particular embodiment, such as Figures 29A to 29B and Figure 30 shown, the first memory bar and the second memory bar 150 are mounted on the substrate 120. In other embodiments, such asFigures 31B to 31C In the 2.5D - PoP structure shown, the first memory strip 150 and the second memory strip 150 are encapsulated in the first molding layer, the first logic chip 104 and the second logic chip 104 are mounted on top of the first molding layer, and the first and second sets of laterally separated memory chips 102 are mounted on top of the first molding layer 3120, and the first and second sets of laterally separated memory chips 102 are mounted on top of the first molding layer.

[0109] Figure 32A It is a schematic top - view illustration of a 3D extended system according to one embodiment. Figure 32B is according to one embodiment along Figure 32A A schematic cross - sectional side - view illustration taken along line B - B. As shown, a semi - rigid flexible circuit 3200 including a base portion 3210 (e.g., a base plate) and one or more side portions 3212 (e.g., side plates) can be connected by a flexible connector 3214 that provides a horizontal - to - vertical conversion. The base portion 3210 can be mounted on the substrate 120 using suitable techniques (such as but not limited to micro - bumps). Memory chips 102 can be mounted on one or both sides of the side portion 3212 (as shown). Such a 3D arrangement can significantly increase the memory capacity and add some associated z - height to the system. In other embodiments, a more rigid 3D structure can be used, e.g., similar to a dual - in - line memory module (DIMM) with pin connections, sockets, etc. In some embodiments, the flexible connector 3214 can be further folded such that the memory chips (devices) 102 are now parallel to the substrate 120 and the memory chips (devices) 102 are now stacked on the base portion 310. This configuration can help control the z - height, which increases the storage capacity.

[0110] In the above description, various multi - chip system 100 configurations are described where a large substrate 120 can be effectively CTE - matched with multiple chips, modules, strips mounted on or assembled within the substrate 120. These configurations can provide mechanical reliability. Such a substrate 120 can additionally be used to provide a basis for attaching mechanical handling and heat - dissipation solutions.

[0111] In such large - scale systems, cooling can be an important factor. Cooling plates, two - phase (e.g., heat pipes), liquid cooling, loop heat pipes, and micro - channels are possible options. Other options can be considered, including immersion in liquids (such as mineral oil, custom hydrocarbons, or others). Additionally, the liquid can be cooled as the storage capacity can be very high and the cooling solution can be extended to cover it.

[0112] The exemplary substrate 120 can be a glass core, organic, metal-stabilized core (such as a copper-invar-copper or molybdenum (CTE-matched and with a higher Young's modulus) substrate), or a CTE-matched glass or organic material. Such large substrates 120 can be mechanically or weakly coupled to other substrates such as board 106 through sockets, soft solders, flexible circuits, etc. Such CTE-matched substrates 120 can also reduce the thickness of the system, thus keeping the z-height small. For larger substrates 120, mechanical stiffeners 122 can also be appropriately and strategically added at their surface locations to enhance the stiffness for mechanical handling capabilities and reduce warping. The stiffeners 122 can be metal, a package substrate core, or other high elastic modulus materials with appropriate CTE.

[0113] In utilizing various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming an extended system. Although the embodiments have been described in language specific to structural features and / or method acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed should rather be understood as exemplary embodiments for the claims.

Claims

1. A multi-chip system, the multi-chip system comprising: A first chip, the first chip comprising: A first edge of the first chip, a second edge of the first chip, a third edge of the first chip, a fourth edge of the first chip; A first plurality of first ports, supporting inter-chip connections adjacent to a first corner of the first chip formed by the first edge of the first chip and the second edge of the first chip; A second port of the first chip, supporting an external input / output connection adjacent to the third edge of the first chip; Wherein, compared with a second corner of the first chip formed by the first edge of the first chip and the fourth edge of the first chip, the first plurality of first ports are closer to the first corner of the first chip, and compared with a third corner of the first chip formed by the second edge of the first chip and the third edge of the first chip, the first plurality of first ports are closer to the first corner of the first chip; A second chip, the second chip comprising: A second plurality of first ports, supporting inter-chip connections adjacent to a first corner of the second chip formed by a first edge of the second chip and a second edge of the second chip; A second port of the second chip, supporting an external input / output connection adjacent to a third edge of the second chip; Wherein, compared with a second corner of the second chip formed by the first edge of the second chip and the fourth edge of the second chip, the second plurality of second ports are closer to the first corner of the second chip, and compared with a third corner of the second chip formed by the second edge of the second chip and the third edge of the second chip, the second plurality of first ports are closer to the first corner of the second chip; and Inter-die wiring, the inter-die wiring connecting at least one of the first plurality of first ports to at least one of the second plurality of first ports.

2. The multi-chip system according to claim 1, wherein the third edge of the first chip is orthogonal to the third edge of the second chip.

3. The multi-chip system according to claim 1, wherein the first chip is a first logic chip and the second chip is a second logic chip.

4. The multi-chip system according to claim 3, wherein the second port of the first chip is connected to one or more memory chips.

5. The multi-chip system according to claim 4, wherein the second port of the second chip is connected to one or more second memory chips.

6. The multi-chip system according to claim 3, wherein the second port of the first chip is a general-purpose port additionally supporting inter-chip connections, and the second port of the second chip is a general-purpose port additionally supporting inter-chip connections.

7. The multi-chip system according to claim 3, wherein at least one of the first plurality of first ports and at least one of the second plurality of second ports both support external input / output connections.

8. The multi-chip system according to claim 1, wherein the inter-die wiring is located within an interposer.

9. The multi-chip system according to claim 1, wherein the inter-die wiring is located within a bonding strip spanning the first chip and the second chip.

10. The multi-chip system according to claim 9, wherein the bonding strip is surrounded by an insulating material.

11. The multi-chip system according to claim 10 further includes a plurality of conductive posts extending through the insulating material.

12. The multi-chip system according to claim 11 further includes a redistribution layer between the bonding strip and the first chip and the second chip.

13. The multi-chip system according to claim 11 further includes: a third chip, the third chip including: a third plurality of first ports supporting inter-chip connections adjacent to a first corner of the third chip formed by a first edge and a second edge of the third chip; a second port of the third chip supporting an external input / output connection adjacent to a third edge of the third chip; and a second inter-die wiring connecting at least one of the second plurality of first ports to at least one of the third plurality of third ports.

14. The multi-chip system according to claim 13, wherein the third edge of the second chip is orthogonal to the third edge of the third chip.

15. The multi-chip system according to claim 13, wherein the second port of the third chip is a universal port additionally supporting inter-chip connections.

16. The multi-chip system according to claim 13 further includes: a fourth chip, the fourth chip including: a fourth plurality of first ports supporting inter-chip connections adjacent to a first corner of the fourth chip formed by a first edge and a second edge of the fourth chip; a second port of the fourth chip supporting an external input / output connection adjacent to a third edge of the fourth chip; and a third inter-die wiring connecting at least one of the third plurality of first ports to at least one of the fourth plurality of first ports; and a fourth inter-die wiring connecting at least one of the fourth plurality of first ports to at least one of the first plurality of first ports.

17. The multi-chip system according to claim 16, wherein the third edge of the third chip is orthogonal to the third edge of the fourth chip.

18. The multi-chip system according to claim 16, wherein the second port of the fourth chip is a universal port additionally supporting inter-chip connections.

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