An electrical test structure and a wafer containing the same

Abstract

The present invention discloses an electrical test structure and a wafer containing the same. The electrical test structure of an embodiment of the present invention includes: a substrate, including first active areas arranged in row and column directions respectively, and the widths of the first active areas in the row direction are different; a gate structure arranged in the column direction formed above the first active area, the widths of the gate structures in the column direction are different and the gate structure extends in the row direction so as to overlap with the projection of the first active area in the row direction on the substrate to form a MOS tube, and the first active areas on both sides of the overlapping area respectively constitute the source and drain of the MOS tube; a source test pad, the sources of the same row are electrically connected to the same source test pad; a drain test pad, the drains of the same column are electrically connected to the same drain test pad; a gate test pad, each gate structure is electrically connected to the corresponding gate test pad; a liner, arranged outside the area where the MOS tube is located; a liner test pad, the liner is electrically connected to the liner test pad.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to an electrical test structure and a wafer comprising the same. Background Art

[0002] Electrical testing is an essential monitoring method for mature large-scale integrated circuit manufacturing. The measurement of electrical parameters can be used to measure whether the device performance meets the standards and provide parameter modeling (SpiceModel) during the product development stage, and can also be used to monitor the stability of the production line process during the mass production stage.

[0003] In the R&D stage, in order to improve the modeling, the electrical test structure generally includes a large number of size matrices, so the number of SpiceModel test structures is very large. Generally, there are more than 100 test structures of different sizes for the same type of device (the most important of which are more than 100 MOS devices with different parameters). A large number of test structures have to occupy limited layout space, and often several die areas are required to set up test structures.

[0004] In the mass production stage, it is also necessary to set up typical device electrical test structures on the cutting path to monitor the stability of the process. As more and more functions are integrated into a single chip, the types of devices are also increasing, and more and more device performance needs to be monitored. However, in order to improve the utilization rate of wafers, the cutting path space is developing in a smaller and smaller direction. Therefore, how to effectively compress the area of ​​the test structure is a problem that needs to be solved urgently.

[0005] In order to solve this problem, the following methods are mainly used in actual production: 1) Deleting the test structure during layout design can reduce the area occupied by the test structure, but once an abnormality occurs and the data needs to be analyzed, it will become difficult to analyze the problem due to the lack of corresponding monitoring data. 2) Since a test structure requires multiple test pads (PADs, also called welding pads, pads, etc.), generally even a test structure (hereinafter referred to as "device") needs to be connected to multiple PADs, and the area occupied by a PAD is basically the same as the area occupied by the corresponding device. Therefore, the test structure can be reasonably arranged so that as many test devices as possible share the test pad, thereby achieving the effect of reducing the area occupied by the test structure. At present, the test structure basically realizes that the source, gate and bulk share the same PAD. However, in terms of the area occupied by the single device structure itself, it has not been reduced, so there is still room for further optimization. Summary of the invention

[0006] In order to solve at least one of the above technical problems, the present invention adopts the following technical solution:

[0007] A first aspect of the present invention provides an electrical test structure, comprising:

[0008] A substrate, comprising first active regions arranged in row and column directions, wherein the widths of the first active regions in the row direction are different;

[0009] A gate structure arranged in a column direction is formed above the first active region, wherein the widths of the gate structures in the column direction are different and the gate structure extends in the row direction so as to overlap with the projection of the first active region in the row direction on the substrate to form a MOS tube, wherein the first active regions on both sides of the overlapping region respectively constitute the source and drain of the MOS tube;

[0010] Source test pads, sources in the same row are electrically connected to the same source test pad;

[0011] A drain test pad, drains in the same column are electrically connected to the same drain test pad;

[0012] a gate test pad, each gate structure being electrically connected to a corresponding gate test pad;

[0013] A liner electrode is arranged outside the area where the MOS tube is located;

[0014] A liner test pad is provided, wherein the liner is electrically connected to the liner test pad.

[0015] In an optional embodiment, the electrical test structure further includes:

[0016] The second active region is arranged between the sources of the MOS tubes in each row, so that the MOS tubes in the same row share the source.

[0017] In an optional embodiment, the electrical test structure further includes:

[0018] The third active region is arranged between the first active regions adjacent to the Nth MOS tube and the N+1th MOS tube in each column, so that all the MOS tubes in the Nth row and the N+1th row share a source, where N is an odd number.

[0019] In an optional embodiment, the electrical test structure further includes:

[0020] The source lead-out structure is arranged on each row of sources to electrically connect the sources in the same row to the corresponding source test pads, wherein the resistance value of the source lead-out structure is smaller than the resistance value of the source (ie, the first active area serving as the source).

[0021] In an optional embodiment, the electrical test structure further includes:

[0022] A source lead hole, arranged on a side close to the source test pad;

[0023] The source metal lead electrically connects the source lead structure to the corresponding source test pad through the source lead hole.

[0024] In an optional embodiment, the electrical test structure further includes:

[0025] Drain lead hole, corresponding to the drain setting of each MOS tube;

[0026] A drain metal lead, electrically connecting the drains in the same column to the drain test pads corresponding to the column through the drain lead holes in the same column;

[0027] A gate lead hole is provided corresponding to each gate;

[0028] The gate metal lead electrically connects the gate to the corresponding gate test pad through the gate lead hole.

[0029] In an optional embodiment, the electrical test structure is arranged in a cutting street, and the column direction is a width direction of the cutting street.

[0030] In an alternative embodiment,

[0031] The source test pad is arranged in the row direction, and the sources of all MOS tubes are connected to the same source test pad;

[0032] Each gate test pad is arranged along the row direction on a side of the area where the MOS tube is located opposite to the source test pad;

[0033] Each drain test pad is arranged along the row direction at one side of the source test pad;

[0034] The liner test pad is arranged on one side of the gate test pad.

[0035] In an optional embodiment, the electrical test structure is disposed in a die region surrounded by a scribe line.

[0036] In an alternative embodiment,

[0037] The source test pads are arranged in the row direction, wherein the sources of at least two adjacent rows are electrically connected to the same source test pad, and different source test pads are arranged along the column direction;

[0038] The gate test pads are arranged in the row direction, wherein different gate test pads are arranged along the column direction;

[0039] The drain test pads are arranged in the column direction, wherein different drain test pads are arranged along the row direction.

[0040] A second aspect of the present invention provides a wafer, comprising:

[0041] A tube die is disposed in the tube die area; and

[0042] The test structure according to the first aspect.

[0043] The beneficial effects of the present invention are as follows:

[0044] Through the embodiments of the present invention, multiple test structures of different sizes are concentrated in the same device area, so that the equivalent occupied area of ​​a device can be reduced, effectively improving the utilization rate of the wafer, and test devices of different sizes are concentrated in the same device area, so that testing is convenient. Furthermore, by designing the layout of the test pad, the utilization rate of the wafer is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0046] Figure 1 A schematic diagram of a wafer including a die area and a dicing lane according to an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of an electrical property test structure on a dicing line according to the prior art;

[0048] Figure 3 for Figure 2 The enlarged schematic diagram of the area selected by the dotted box in the middle;

[0049] Figure 4 A schematic diagram of a Spice Model device electrical property test structure in a tube core region according to the prior art;

[0050] Figure 5 for Figure 4 The enlarged schematic diagram of the area selected by the dashed box in the middle;

[0051] Figure 6 A schematic diagram of an electrical test structure on a scribe line according to an embodiment of the present invention;

[0052] Figure 7 for Figure 6 The enlarged schematic diagram of the area selected by the dashed box in the middle;

[0053] Figure 8 is a schematic diagram of an electrical property test structure on a scribe line according to another embodiment of the present invention;

[0054] Fig. 9 is a schematic diagram of an electrical property test structure on a scribe line according to yet another embodiment of the present invention; and

[0055] Fig.10The figure is a schematic diagram of a Spice Model device electrical property test structure in a die area according to an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to explain the present invention more clearly, the present invention is further described below in conjunction with embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content specifically described below is illustrative rather than restrictive, and the protection scope of the present invention should not be limited thereto.

[0057] The terms “on”, “formed on” and “disposed on” in the present disclosure may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0058] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various parts, components, elements, regions, layers and / or parts, these parts, components, elements, regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and / or part from another.

[0059] like Figure 1 As shown, semiconductor integrated circuits are completed on a wafer through various processes such as patterning processes. During the wafer manufacturing process, due to the size limitation of the exposure field of the photolithography machine, the wafer can be divided into multiple repeated exposure areas (shots) 10. The size of the exposure area is determined based on the capabilities of the photolithography machine and the effective utilization rate of the wafer. The size of the chip is often smaller than this area, so an exposure area can include multiple tube core areas 100 (die), and finally prepare chips with different functions. A cutting road 105 is formed between the tube core areas to separate the tube core 100 after the process is completed to obtain a bare chip.

[0060] Figure 2 This is a schematic diagram of the traditional electrical test structure, which is mainly used to monitor the stability of the production line. When designing the layout, the entire test structure is placed in Figure 1 In the scribe line 105 shown. Figure 2 The test structure shown includes 10 PADs, all of which are arranged at equal intervals along the length of the cutting path. Between the PADs is a device area for setting devices. The 10 PADs include 7 drain PADs 200, 1 source PAD 205, 1 gate PAD 210, and 1 liner PAD 215. In addition, each drain PAD is connected to the drain of a device, so Figure 1 The test structure in includes only 7 devices.

[0061] Figure 3 The device area between PADs ( Figure 2 The enlarged view of the dotted box in the figure. Figure 3 As shown in FIG. 1 , for a conventional MOS device (test device), its test requires four ports: source 206, drain 202, gate 212, and liner 216. Each port needs to be connected to a PAD to input / output a test signal. Figure 2 As shown, all devices share the source, gate, and liner, and each device only needs to occupy a drain PAD and a device area. Although this method is currently the best solution in terms of saving the area of ​​the test structure unit and minimizing the number of PADs. However, this solution does not solve the problem of low utilization of the device area. For example, the length and width of a typical device are only microns or even nanometers, while the typical width of a cutting path is 60 or 80 microns and the length is about 100 microns. In other words, a large amount of area in the device area is wasted, and there is still room for optimization.

[0062] The traditional Spice Model device test structure also has similar problems. Unlike the electrical test structure arrangement on the cutting path, the Spice Model test structure has a large number and therefore needs to occupy the die area, so its device and PAD layout is more flexible. Figure 4 It is a relatively compact arrangement at present. Although one device 405 still needs four PADs 400 to work, one PAD can be shared with four devices 405 above, below, left and right of it, so its PAD arrangement has been optimized to the limit. Figure 5 Show Figure 4 The enlarged view of the area shown in the dotted box includes the drain 402, the source 406, the gate 412 and the liner 416. Figure 4 The arrangement method is also that one device occupies one device area. However, the size of Spice Model devices is very large, which also causes a large waste of wafer area, compresses the effective area of ​​the die, and increases R&D and manufacturing costs.

[0063] Definition or description

[0064] In the present invention, the test structure includes a test device and a PAD.

[0065] Similarly, the device region (domain) is the area occupied by the test device, that is, the area between two adjacent PADs; the device region (domain) area is the area occupied by the test device. The area occupied by the test structure is the test region (domain).

[0066] Example 1 - Electrical property test structure of devices on the cutting path

[0067] Figure 6FIG. 4 is a top view of an electrical test structure according to this embodiment. Figure 7 for Figure 6 The enlarged view of the device area in the dotted box. Figure 2 Compared with the traditional test structure, Figure 6 The test structure shown also selects 10 PADs, including 4 drain PADs 500 arranged along the row direction (x direction in the figure, i.e., the length direction of the cutting path); 1 source PAD 505 arranged in the row direction; 4 gate PADs 510 arranged in the row direction; and 1 liner PAD 515.

[0068] In the device area, such as Figure 7 As shown, the test structure of this embodiment includes:

[0069] The substrate comprises first active regions 520 arranged along row and column directions, wherein the widths of the first active regions in the row direction (x direction in the figure) are different.

[0070] Adjacent first active regions 520 are isolated and insulated by isolation regions 522 (eg shallow trench isolation STI).

[0071] exist Figure 7 In the example shown, four first active regions 520 are arranged in the same row and the width W1 of the first active region (the dimension along the row direction, that is, the length of the channel of the MOS tube formed by overlapping with the gate formed later) becomes narrower from left to right; four first active regions are arranged in the same column, and the widths of the first active regions 520 in the same column are the same, but the present invention is not limited to this, and the widths of the four first active regions 520 in the column direction may also be different, similar to the situation in the row direction.

[0072] A gate structure 525 is formed above the first active region 520 and arranged along the column direction (y direction in the figure, i.e., the width direction of the cutting path), wherein the widths of the gate structures 525 in the column direction are different and the gate structures 525 extend in the row direction so as to overlap with the projection of the first active region 520 in the row direction on the substrate to form a MOS tube, wherein the first active regions 520 located on both sides of the overlapping region respectively constitute the source 5200 and the drain 5205 of the MOS tube.

[0073] exist Figure 7 In the example shown, four gate structures are shown. The first gate structure on the first row overlaps with the projection relationship of the four first active regions on the row to form four MOS transistors. The gate structures on the second to fourth rows respectively form four MOS transistors with the four first active regions on the corresponding rows. In the column direction, the width W2 (i.e., the width of the channel of the formed MOS transistor) from the first gate structure to the fourth gate structure becomes narrower and narrower.

[0074] It should be noted that in this embodiment, the length direction of the cutting path is defined as the row direction, and the width direction of the cutting path is defined as the column direction. However, this is merely an artificial regulation. On the contrary, defining the length direction of the cutting path as the column direction and the width direction of the cutting path as the row direction is also within the protection scope of the present invention.

[0075] Those skilled in the art will understand that before the process of manufacturing the gate structure on the substrate, a gate insulating layer (not shown in the figure) needs to be manufactured to perform electrical isolation in a direction perpendicular to the substrate. This is well known to those skilled in the art and will not be described in detail here.

[0076] Similarly, after the gate structure is fabricated, an interlayer dielectric layer (not shown) is formed above the gate structure to electrically isolate the gate structure from subsequently formed structures in a direction perpendicular to the substrate. This is well known to those skilled in the art and will not be described in detail herein.

[0077] The test structure of this embodiment also includes:

[0078] The drain lead hole 530 is provided corresponding to the drain 5205 of each MOS tube;

[0079] A drain metal lead 535 electrically connects the drain 5205 in the same column to the drain PAD corresponding to the column through the drain lead holes 530 in the same column;

[0080] A gate lead hole 540 is provided corresponding to each gate;

[0081] A gate metal lead 545 electrically connects the gate to the corresponding gate PAD through the gate lead hole 540;

[0082] A source lead hole 550 is provided corresponding to each source electrode;

[0083] The source metal lead 555 electrically connects the sources 5200 in the same row to the corresponding source PADs through the source lead holes 550 .

[0084] exist Figure 7 In the example shown, the drain metal lead 535 connects the four drains 5205 on the same column together through a drain lead hole 530 that penetrates the interlayer dielectric layer above the drain.

[0085] Similarly, the source metal lead 555 connects the four sources 5200 on the same row together through the source lead hole 550 that penetrates the interlayer dielectric layer above the source. For the test structure of the present invention, each row of sources 5200 can be connected to the same source PAD, but it is not required that all four rows of sources are connected to the same source PAD.

[0086] For 10 PADs, Figure 2 The conventional test unit shown can only accommodate 7 devices, while the test structure of the present invention can accommodate 16 devices, which is equivalent to reducing the area occupied by each device by 1.28 times on average.

[0087] More preferably, if Figure 6 As shown in FIG. 1 , all 16 source electrodes 5200 are connected to the same source electrode PAD 505 arranged in the row direction (the length direction of the cutting path). Each gate PAD 510 is arranged on the side of the device region opposite to the source electrode PAD 505 along the row direction; each drain electrode PAD 500 is arranged on the side of the source electrode PAD along the row direction. Figure 2 The PAD layout shown is similar. In this way, the test structure is further optimized in the PAD area.

[0088] Therefore, the test structure of the present invention can integrate 16 devices of different length / width sizes in one device area of ​​the traditional test structure. The active area is arranged along the x direction, which is consistent with the PAD arrangement direction, so the number of active areas is relatively flexible and has no restrictions, and can be selected according to actual needs. The gate structure is arranged along the y direction, and the y direction is generally limited by the width of the cutting path. Taking a 60-micron wide cutting path as an example, the width of the polysilicon gate of a long channel device is generally selected to be 10 microns, and the spacing between adjacent polysilicon gates is generally less than 1 micron. Therefore, the number of polysilicon gates arranged along the y direction can generally be around 5 to 10.

[0089] The test structure according to the present invention further includes a liner 560 connected to the liner PAD 515 . The liner PAD 515 can be arranged in the same row as the plurality of gate PADs 510 ; or the plurality of gate PADs 510 can be arranged between the liner PAD 515 and the source PAD505 .

[0090] Since all devices in the test structure of the present invention are in the same device area, one substrate PAD is sufficient, which further compresses the area of ​​the test area.

[0091] From the above manufacturing process, the test structure of the present invention is fully compatible with the original process and will not increase the process difficulty. Compared with the original test structure, the device density of the test structure on the same area can be increased by about one time, effectively compressing the test area.

[0092] The test structure of the present invention can realize the centralized arrangement of devices of the same type with different sizes in the same device area, which greatly facilitates the test.

[0093] It should be noted that in Figure 7In the case where each MOS tube is isolated by an isolation region, since the drain metal lead 535 and the source metal lead 555 are intersected in space, and each drain and each source need to be led out through a lead hole. In terms of process, the source metal lead 550 and the drain metal lead 535 need to be staggered in the vertical space. This is relatively easy to achieve in terms of process, because for the process platform below 0.18um, the back-end metal process generally has multiple layers of metal separated in the vertical space. We only need to select two different metal layers, such as metal lead 550 selects metal1 process, and drain metal lead 535 selects Metal2 process.

[0094] In a preferred embodiment of the present invention, Figure 8 As shown, the test structure of the present invention further includes a second active region 565, which is arranged between the sources of the MOS transistors in each row, so that the MOS transistors in the same row share the source. Figure 7 In this example, the active regions serving as sources on the same row separated by the isolation region are connected to each other. Figure 8 As shown, the second active region 565 connects the four sources 5200 in the same row together. Figure 7 The structure shown in (each source requires a source lead hole), Figure 8 In the case shown in FIG. 5 , it is only necessary to form a source lead hole 550 on the source electrode close to the source PAD side (as far away as possible from the corresponding drain metal lead). Figure 8 The design makes the back-end wiring more flexible. The source metal line and the drain metal line can be selected from the same layer of metal or from the same layer of metal. Figure 7 Likewise, choose different layers of metal.

[0095] More preferably, in order to further improve the test efficiency and the accuracy of the test results, Fig. 9 As shown, the test structure of this embodiment further includes a third active region, which is arranged between the first active regions adjacent to the Nth MOS tube and the N+1th MOS tube in each column, so that the Nth MOS tube and the N+1th MOS tube share a source, and further all the MOS tubes in the Nth row and the N+1th row share a source, where N is an odd number.

[0096] For example, in Fig. 9In the example shown, for each column, the first active regions adjacent to the MOS tubes on the first row and the MOS tubes on the second row are connected together through the third active region 570-1, and the first active regions adjacent to the MOS tubes on the third row and the MOS tubes on the fourth row are connected together through another third active region 570-2. When in use, the adjacent first active regions are used as the source of the MOS tubes. That is, the 4 MOS tubes on the first row and the 4 MOS tubes on the second row share the source; the 4 MOS tubes on the third row and the 4 MOS tubes on the fourth row share the source. In this case, the number of source lead holes is further reduced.

[0097] More preferably, the common source extends toward the source PAD to form a protrusion 575 away from the corresponding drain metal lead, and a source lead hole 550 is formed on the protrusion 575 to enhance process reliability.

[0098] More preferably, when the process platform includes a low-resistance silicide process, Fig. 9 In the example, a source lead-out structure 580 (low-resistance silicide) is covered on the third active area, and the sources in the same row are electrically connected to the corresponding source test pads, wherein the resistance value of the source lead-out structure is less than the resistance value of the source (i.e., the first active area used as the source). The manufacturing process of the source lead-out structure can be formed simultaneously by the silicide process, and no additional process is required. Such a design can achieve lower resistance connection of active areas of different devices in the same row, so that the measurement of devices at different positions in the device area is closer to the intrinsic value, and different source area resistances will not be introduced due to different positions.

[0099] In this case, the source metal lead only needs to be connected to the source lead-out structure 580 through the source lead hole 550 .

[0100] Similarly, in Figure 8 A similar source lead-out structure may also be formed on the common source shown, which will not be described in detail here.

[0101] Embodiment 2 - Spice Model device electrical property test structure in the die area.

[0102] Because the Spice Model electrical test structure occupies a dedicated die area to arrange the required device test structure, its arrangement is different from the test structure set on the cutting path in the following ways: 1) There are many devices of the same type but different sizes; 2) The arrangement is more flexible, without horizontal or vertical size restrictions.

[0103] like Fig.10 As shown, in the device area, the test structure of this embodiment includes:

[0104] The substrate comprises first active regions 620 arranged in row and column directions, respectively, wherein the widths of the first active regions in the row direction are different.

[0105] exist Fig.10 In the example shown, 10 first active regions 620 are arranged in the same row and the width of the first active region (the dimension along the row direction, i.e., the channel length of the MOS tube formed with the gate to be formed later) becomes narrower and narrower; 10 first active regions 620 are arranged in the same column, and the width of the first active regions 620 in the column direction is the same, however, the present invention is not limited to this, and the widths of the 10 active regions in the column direction may also be different, similar to the situation in the row direction.

[0106] A gate structure 625 is formed above the first active region 620 and arranged along the column direction (y direction in the figure), wherein the widths of the gate structures 625 in the column direction are different and the gate structures 625 extend in the row direction so as to overlap with the projection of the first active region 620 in the row direction on the substrate to form a MOS tube, wherein the first active regions 620 on both sides of the overlapping region respectively constitute the source and drain of the MOS tube.

[0107] exist Fig.10 In the example shown, 10 gate structures are shown. The first gate structure on the first row overlaps with the projection relationship of the 10 active regions on the row to form 10 MOS transistors. The gate structures on the 2nd to 10th rows respectively form 10 MOS transistors with the 10 active regions on the corresponding rows. In the column direction, the widths of the first to tenth gate structures (i.e., the channel widths of the formed MOS transistors) become narrower and narrower.

[0108] exist Fig.10 In the example shown, something like Fig. 9 In the case of the second active region and the third active region, a common source structure is formed, and a source lead-out structure also exists. However, the present invention is not limited thereto, and the test structure of this embodiment may also be similar to Figure 7 or Figure 8 structure to obtain corresponding technical effects.

[0109] It should also be noted that in this embodiment, the direction in which the gate structure extends is defined as the row direction, and the direction perpendicular thereto is defined as the column direction. However, the present invention is not limited thereto, and the direction in which the gate structure extends may be defined as the column direction, and the direction perpendicular thereto may be defined as the row direction. Regardless of how it is defined, it is within the protection scope of the present invention.

[0110] The test structure of this embodiment also includes:

[0111] Drain test pads 600 are arranged in the column direction, wherein different drain test pads are arranged in the row direction, and wherein the drain is electrically connected to the corresponding drain test pad through the corresponding drain lead hole 630 and the drain metal lead 635;

[0112] Source test pads 605 are arranged in the row direction, wherein the sources of at least two adjacent rows are electrically connected to the same source test pad through source lead holes 650 and source metal leads 655, and different source test pads 605 are arranged in the column direction;

[0113] The gate test pads 610 are arranged in the row direction, wherein different gate test pads are arranged in the column direction, and wherein the gate structure is electrically connected to the corresponding gate test pads through the corresponding gate lead holes 640 and the gate metal leads 645 .

[0114] In order to compare the area occupied by a single device, we assume that the device area (the spacing area between PADs) is the same as the PAD area and both are recorded as unit area 1. Figure 4 The test structure shown occupies an area of ​​13*15=195, with a maximum of 42 devices, and a single device occupies an equivalent area of ​​4.64. The test structure according to this embodiment occupies an area of ​​13*15=195, but 100 devices are set, and a single device occupies an equivalent area of ​​1.95. This is equivalent to a 60% reduction in the area occupied by a single device.

[0115] In addition, due to the large number of devices, the traditional Spice Model test structure often requires that some device test structures be placed in different die areas, and searching for a specific device requires searching against the final layout (JDV), which causes great inconvenience for testing. The test structure according to this embodiment can place a large number of devices of the same type in the same test structure, which is convenient and fast during testing.

[0116] The test structure according to this embodiment further includes a pad 660 connected to the pad PAD 615 .

[0117] Since all devices in the test structure of this embodiment are in the same device area, one liner PAD is sufficient, which further compresses the area of ​​the test area and saves the available area of ​​the wafer.

[0118] Generally speaking, the electrical test parameters of MOS tubes mainly include turn-on voltage Vt, saturation current Idsat, standby leakage current Ioff and source-drain breakdown voltage BVds.

[0119] To this end, this embodiment provides a method for testing electrical parameters, using the electrical testing structure of the above embodiment, including:

[0120] Select the MOS tube of the size to be tested;

[0121] Apply a static DC signal, such as grounding, to the source test pad, the gate liner test pad and the liner test pad of the selected MOS tube;

[0122] Apply a changing input signal to the drain test pad of the selected MOS tube.

[0123] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the embodiments here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

Claims

1. An electrical test structure, characterized in that: include: A substrate, comprising first active regions arranged in row and column directions, wherein the widths of the first active regions in the row direction are different; A gate structure arranged in a column direction is formed above the first active region, wherein the widths of the gate structures in the column direction are different and the gate structure extends in the row direction so as to overlap with the projection of the first active region in the row direction on the substrate to form a MOS tube, wherein the first active regions on both sides of the overlapping region respectively constitute the source and drain of the MOS tube; Source test pads, sources in the same row are electrically connected to the same source test pad; A drain test pad, drains in the same column are electrically connected to the same drain test pad; a gate test pad, each gate structure being electrically connected to a corresponding gate test pad; A liner electrode is arranged outside the area where the MOS tube is located; A liner test pad is provided, wherein the liner is electrically connected to the liner test pad.

2. The electrical test structure according to claim 1, characterized in that: Also includes: The second active region is arranged between the sources of the MOS tubes in each row, so that the MOS tubes in the same row share the source.

3. The electrical test structure according to claim 2, characterized in that: Also includes: The third active region is arranged between the first active regions adjacent to the Nth MOS tube and the N+1th MOS tube in each column, so that all the MOS tubes in the Nth row and the N+1th row share a source, where N is an odd number.

4. The electrical test structure according to claim 2, characterized in that: Also includes: The source lead-out structure is arranged on the source electrodes of each row, and electrically connects the source electrodes of the same row to the corresponding source test pads, wherein the resistance value of the source lead-out structure is smaller than the source resistance value.

5. The electrical test structure according to claim 3, characterized in that: Also includes: The source lead-out structure is arranged on the source electrodes of each row, and electrically connects the source electrodes of the same row to the corresponding source test pads, wherein the resistance value of the source lead-out structure is smaller than the source resistance value.

6. The electrical test structure according to claim 4, characterized in that: Also includes: A source lead hole, arranged on a side close to the source test pad; The source metal lead electrically connects the source lead structure to the corresponding source test pad through the source lead hole.

7. The electrical test structure according to claim 5, characterized in that: Also includes: A source lead hole, arranged on a side close to the source test pad; The source metal lead electrically connects the source lead structure to the corresponding source test pad through the source lead hole.

8. The electrical test structure according to claim 1, characterized in that: Also includes: Drain lead hole, corresponding to the drain setting of each MOS tube; A drain metal lead, electrically connecting the drains in the same column to the drain test pads corresponding to the column through the drain lead holes in the same column; A gate lead hole is provided corresponding to each gate; The gate metal lead electrically connects the gate to the corresponding gate test pad through the gate lead hole.

9. The electrical test structure according to any one of claims 1 to 8, characterized in that: The electrical test structure is arranged in the cutting path, and the row direction is the width direction of the cutting path.

10. The electrical test structure according to claim 9, characterized in that: The source test pad is arranged in the row direction, and the sources of all MOS tubes are connected to the same source test pad; Each gate test pad is arranged along the row direction on a side of the area where the MOS tube is located opposite to the source test pad; Each drain test pad is arranged along the row direction at one side of the source test pad; The liner test pad is arranged on one side of the gate test pad.

11. The electrical test structure according to any one of claims 1 to 8, characterized in that: The electrical test structure is arranged in a die area surrounded by a dicing street.

12. The electrical test structure according to claim 11, characterized in that: The source test pads are arranged in the row direction, wherein the sources of at least two adjacent rows are electrically connected to the same source test pad, and different source test pads are arranged along the column direction; The gate test pads are arranged in the row direction, wherein different gate test pads are arranged along the column direction; The drain test pads are arranged in the column direction, wherein different drain test pads are arranged along the row direction.

13. A wafer, characterized in that: include: A tube die is arranged in the tube die area; as well as A test structure according to any one of claims 1 to 12.

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