A low parasitic inductance and high heat dissipation efficiency embedded power module packaging structure

Abstract

The present invention relates to the technical field of power semiconductor device packaging, and aims to provide an embedded power module packaging structure with low parasitic inductance and high heat dissipation efficiency. It includes a top insulating layer, a top metal pattern layer, a solder layer, a device layer, a bottom metal pattern layer and a bottom insulating layer arranged in sequence from top to bottom; the device layer includes at least two MOSFET power chips and a plurality of metal connection blocks, and an insulating filler is filled between the MOSFET power chips and the metal connection blocks to isolate them from each other; the drain of the power chip is connected to the top metal pattern layer through the solder layer, and its source and gate are electrically connected to the bottom metal pattern layer respectively; the upper and lower surfaces of the metal connection block are electrically connected to the top metal pattern layer and the bottom metal pattern layer respectively. The present invention reduces the packaging volume and weight of the power module by embedding the power chip in the insulating material, and improves the power density of the module. There is no need to use bonding wires and electrode leads, which effectively reduces the parasitic inductance of the power module.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor device packaging, and more specifically, to an embedded power module packaging structure with low parasitic inductance and high heat dissipation efficiency. Background Art

[0002] Efficient and high-quality power conversion is the goal of the development of power electronics technology, so power modules are required to develop in the direction of small, light, high efficiency and high power. Under this development trend, the new generation of wide bandgap semiconductor devices represented by silicon carbide have shown superior performance such as fast switching speed and high thermal conductivity, which is conducive to its high-frequency and high-temperature applications and plays a very important role in significantly improving the power density of the converter.

[0003] The typical packaging structure based on substrate and bonding wire is used in most power modules currently in production (such as Figure 1 As shown). Its working principle is: the bottom of the chip is connected to the copper-clad ceramic substrate (DBC) through solder, and the top is connected to the DBC through bonding wires. The bonding wires and the upper copper tracks of the DBC are electrically interconnected, and the DBC realizes electrical insulation and thermal management. In this packaging structure, the bonding wires have a large parasitic inductance, and the heat generated by the power device can only be discharged through the bottom of the package. The high-frequency application of power devices makes them more sensitive to parasitic parameters, and more serious problems such as overvoltage, parasitic oscillation and EMI will occur under the same parasitic inductance; the increase in power level also causes the device to generate higher heat when working. Under a single heat dissipation path, the heat cannot be discharged in time, which will affect the overall reliability of the power module. Therefore, the traditional packaging method can no longer meet the needs of high-frequency and high-temperature applications of power modules. In order to solve the above problems, technicians in this field have successively proposed technologies such as DBC+PCB hybrid packaging, three-dimensional packaging, and chip front plane interconnection packaging, but these packaging processes have problems such as complex structure and high cost, so it is difficult to promote and apply them in actual production.

[0004] As packaging technology has become a bottleneck for the development of power modules towards high frequency and high temperature, it is necessary to develop new solutions with low parasitic inductance and efficient cooling to promote the development of power modules. Summary of the invention

[0005] The technical problem to be solved by the present invention is to overcome the deficiencies in the prior art and provide an embedded power module packaging structure with low parasitic inductance and high heat dissipation efficiency.

[0006] To solve the technical problem, the solution of the present invention is:

[0007] Provided is an embedded power module packaging structure with low parasitic inductance and high heat dissipation efficiency, comprising a top insulating layer, a top metal pattern layer, a solder layer, a device layer, a bottom metal pattern layer and a bottom insulating layer arranged in sequence from top to bottom; the top insulating layer and the bottom insulating layer both have partial openings, and the exposed portions of the top metal pattern layer and the bottom metal pattern layer at the opening positions serve as top electrode terminals and bottom electrode terminals, respectively;

[0008] The device layer includes at least two MOSFET power chips and a plurality of metal connection blocks, and an insulating filler is filled between the MOSFET power chips and the metal connection blocks to isolate them from each other;

[0009] The drain of the MOSFET power chip is connected to the top metal pattern layer through a solder layer, and its source and gate are electrically connected to the bottom metal pattern layer respectively; the upper and lower surfaces of the metal connection block are electrically connected to the top metal pattern layer and the bottom metal pattern layer respectively.

[0010] As a preferred solution of the present invention, the insulating filler also extends to fill between the MOSFET power chip and the bottom metal pattern layer, and a blind hole is provided in the insulating filler between the two, and the inner wall of the blind hole has a metal plating layer; the source and gate are electrically connected to the bottom metal pattern layer through the metal plating layer respectively.

[0011] As a preferred embodiment of the present invention, the insulating filler also extends to fill between the metal connecting block and the bottom metal pattern layer, and a blind hole is provided in the insulating filler between the two; the inner wall of the blind hole has a metal coating, and the metal connecting block is electrically connected to the bottom metal pattern layer through the metal coating.

[0012] As a preferred solution of the present invention, the upper surface of the metal connection block is connected to the top metal pattern layer through a solder layer.

[0013] As a preferred solution of the present invention, the height of the metal connecting block is equal to that of the MOSFET power chip.

[0014] As a preferred embodiment of the present invention, the insulating filler also extends to fill the vacant parts of the top metal pattern layer and connects with the lower surface of the top insulating layer; or, the insulating filler also extends to fill the vacant parts of the bottom metal pattern layer and connects with the upper surface of the bottom insulating layer.

[0015] As a preferred embodiment of the present invention, the top insulating layer further extends downward to fill the vacant parts of the top metal pattern layer, and connects with the insulating filler in the device layer; or, the bottom insulating layer further extends upward to fill the vacant parts of the top metal pattern layer, and connects with the insulating filler in the device layer.

[0016] As a preferred solution of the present invention, the embedded power module packaging structure is an overall multi-layer plate structure.

[0017] As a preferred solution of the present invention, there are multiple top electrode terminals and multiple bottom electrode terminals respectively.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. The present invention reduces the packaging volume and weight of the power module and improves the power density of the module by embedding the power chip in the insulating material.

[0020] 2. The present invention does not require the use of bonding wires and electrode leads, thereby effectively reducing the parasitic inductance of the power module.

[0021] 3. The present invention adopts a chip face-down placement method, which further reduces the parasitic inductance of the gate and source, effectively improves the switching speed of the power device, and reduces the interference of the driving signal.

[0022] 4. The present invention has double-sided electrode terminals, which can further integrate components such as decoupling capacitors into the power module, thereby further improving the performance of the power module and having strong flexibility.

[0023] 5. In the present invention, the metal connection block structure enhances the current carrying capacity of the module and avoids overcurrent temperature rise; the design of the double-sided metal pattern layer enables the power module to achieve double-sided heat dissipation, thereby improving the heat dissipation efficiency of the power module.

[0024] 6. Based on the above advantages, the present invention is suitable for the application of power modules in high power density, high frequency and high temperature working environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a typical packaging structure based on a substrate and bonding wires in the prior art.

[0026] Figure 2 It is a schematic diagram of an embedded power module packaging structure with low parasitic inductance and efficient thermal management drawn according to an embodiment of the present invention.

[0027] Figure 1 Explanation of the reference numerals in the figures: 1-1 packaging material; 1-2 power chip; 1-3 bonding wire; 1-4 copper-clad ceramic substrate (DBC); 1-5 heat dissipation substrate; 1-6 DBC solder; 1-7 solder.

[0028] Figure 2Explanation of the reference numerals in the figure: 1 power module; 2 MOSFET power chip; 201 source; 202 gate; 203 drain; 3 metal connection block; 301 upper surface of metal connection block; 302 lower surface of metal connection block; 4 top metal pattern layer; 5 bottom metal pattern layer; 6 solder layer; 7 blind hole; 8 device layer; 9 top insulating layer; 10 bottom insulating layer; 11 top electrode terminal; 12 bottom electrode terminal. DETAILED DESCRIPTION

[0029] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings. In order to more clearly illustrate the technical solutions in the embodiments of the present application, the accompanying drawings required for the description of the embodiments are briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work. The specific embodiments further describe the present invention, but the protection scope of the present invention is not limited thereto.

[0030] like Figure 2 As shown, the embedded power module packaging structure of the present invention includes: a top insulating layer 9, a top metal pattern layer 4, a solder layer 6, a device layer 8, a bottom metal pattern layer 5 and a bottom insulating layer 10 arranged in sequence from top to bottom, so that the power module presents a multi-layer plate structure as a whole. Among them, the top insulating layer 9 and the bottom insulating layer 10 both have partial openings. The exposed portions of the top metal pattern layer 4 and the bottom metal pattern layer 5 at the opening position serve as the top electrode terminal 11 and the bottom electrode terminal 12, respectively.

[0031] The device layer 8 includes at least two MOSFET power chips 2 and a plurality of metal connection blocks 3, and an insulating filler is filled between the MOSFET power chips 2 and the metal connection blocks 3 to isolate them from each other; wherein the drain 203 of the MOSFET power chip 2 is connected to the top metal pattern layer 4 through the solder layer 6, and its source 201 and gate 202 are electrically connected to the bottom metal pattern layer 5 respectively; the upper and lower surfaces of the metal connection block 3 are electrically connected to the top metal pattern layer 4 and the bottom metal pattern layer 5 respectively. The insulating filler is also extended to fill between the MOSFET power chip 2 and the bottom metal pattern layer 5, a blind hole is provided in the insulating filler between the two, the inner wall of the blind hole has a metal plating layer, and the source 201 and gate 202 are electrically connected to the bottom metal pattern layer 5 respectively through the metal plating layer. Similarly, the insulating filler is also extended to fill between the metal connection block 3 and the bottom metal pattern layer 5, a blind hole is provided in the insulating filler between the two; the inner wall of the blind hole has a metal plating layer, and the metal connection block 3 is electrically connected to the bottom metal pattern layer 5 through the metal plating layer. The upper surface of the metal connection block 3 is connected to the top metal pattern layer 4 through the solder layer 6. The metal connection block 3 may be optionally at the same height as the MOSFET power chip 2, so the blind holes under the two also have the same height.

[0032] Optionally, the insulating filler also extends to fill the vacant portion of the top metal pattern layer 4 and is in contact with the lower surface of the top insulating layer 9 (eg, Figure 2 Alternatively, the insulating filler also extends to fill the vacant portion of the bottom metal pattern layer 5 and is in contact with the upper surface of the bottom insulating layer 10 (not shown in the figure). Optionally, the top insulating layer 9 also extends downward to fill the vacant portion of the top metal pattern layer 4 and is in contact with the insulating filler in the device layer 8 (not shown in the figure); Alternatively, the bottom insulating layer 10 also extends upward to fill the vacant portion of the top metal pattern layer 4 and is in contact with the insulating filler in the device layer 8 (not shown in the figure). Figure 2 shown).

[0033] In the present invention, the front side of the MOSFET power chip 2 is provided with a source 201 and a gate 202 facing downward, and the back side is provided with a drain 203 facing upward; as a prior art, optional example products include CREE's CPM2-1200-0080B and the like. Multiple MOSFET power chips 2 can form different electrical connection relationships to achieve corresponding power module functions. The front side of the MOSFET power chip 2 faces downward, which can shorten the distance between the chip source 201 and the gate 202 and the terminals and the circuit board on the lower surface of the module, thereby reducing the parasitic inductance of the gate loop. Specifically, the MOSFET power chip 2 can be silicon-based or silicon carbide-based, or it can be other power chips such as IGBT.

[0034] The top metal pattern layer 4 and the bottom metal pattern layer 5 refer to patterned metal layers for achieving electrical connection; the specific patterns are determined according to the module function and the chip connection method. Figure 2 The example in the figure is a half-bridge structure consisting of two chips connected in series.

[0035] The metal connection block 3 is used to realize the electrical connection between the top metal pattern layer 4 and the bottom metal pattern layer 5. The specific configuration depends on the function of the power module and can be flexibly changed according to different functions. Figure 2 The function of the "separately set" metal connection block 3 on the right side of the middle is to lead the electrode on the lower surface of the right side of the module to the terminal on the top surface to integrate components such as decoupling capacitors. When connecting to the metal pattern layer, the upper and lower surfaces of the metal connection block 3 are connected using a solder layer and a metal plating layer poured into the blind hole, respectively. This connection method is related to the implementation process.

[0036] There may be a plurality of top electrode terminals 11 and a plurality of bottom electrode terminals 12 , respectively. The specific number and position are determined according to the functions and requirements of the power module, and the present invention does not impose any limitation thereto. Figure 2 In the figure, a half-bridge module consisting of two MOSFETs connected in series is taken as an example. Five electrode terminals of the half-bridge structure are set at the bottom, and two electrode terminals are set at the top to connect the absorption capacitor. In actual production, the specific position of the terminal is determined by the metal pattern layer design scheme. As an application example, the bottom electrode terminal 12 can be used to connect a circuit board, and the top electrode terminal 11 can be connected to components such as a decoupling capacitor.

[0037] An exemplary description of the manufacturing process of the embedded power module packaging structure in the present invention:

[0038] 1. Making a top metal pattern layer on the carrier;

[0039] 2. Weld the chip and metal connection block;

[0040] 3. Laminating plastic packaging material and bottom metal pattern layer;

[0041] 4. Drilling and blind hole metallization;

[0042] 5. Remove the carrier, process the top and bottom insulation layers, and process the terminal surface.

[0043] In summary, the present invention uses PCB processes such as micro vias and electroplating, and realizes a packaging structure with low parasitic inductance and high heat dissipation efficiency through a chip embedded design with no bonding wires, no electrode leads, and double-sided heat dissipation, while having the advantages of low cost, high flexibility, and easy development. The power module based on embedded packaging has the advantages of small size, light weight, no bonding wires, double-sided heat dissipation, etc., and is a solution with great development potential.

Claims

1. A low parasitic inductance and high heat dissipation efficiency embedded power module packaging structure, characterized in that: It comprises a top insulating layer (9), a top metal pattern layer (4), a solder layer (6), a device layer (8), a bottom metal pattern layer (5) and a bottom insulating layer (10) which are arranged in sequence from top to bottom; The top insulating layer (9) and the bottom insulating layer (10) both have local openings, and the exposed portions of the top metal pattern layer (4) and the bottom metal pattern layer (5) at the openings serve as the top electrode terminal (11) and the bottom electrode terminal (12), respectively. The device layer (8) comprises at least two MOSFET power chips (2) and a plurality of metal connection blocks (3), and an insulating filler is filled between the MOSFET power chips (2) and the metal connection blocks (3) to isolate them from each other; The drain electrode (203) of the MOSFET power chip (2) is connected to the top metal pattern layer (4) through a solder layer (6), and the source electrode (201) and the gate electrode (202) thereof are respectively electrically connected to the bottom metal pattern layer (5); and the upper and lower surfaces of the metal connection block (3) are respectively electrically connected to the top metal pattern layer (4) and the bottom metal pattern layer (5).

2. The embedded power module packaging structure according to claim 1, characterized in that: The insulating filler is also extended to fill between the MOSFET power chip (2) and the bottom metal pattern layer (5), and a blind hole is provided in the insulating filler between the two; the inner wall of the blind hole has a metal plating layer, and the source (201) and the gate (202) are respectively electrically connected to the bottom metal pattern layer (5) through the metal plating layer.

3. The embedded power module packaging structure according to claim 1, characterized in that: The insulating filler also extends to fill between the metal connection block (3) and the bottom metal pattern layer (5), and a blind hole is provided in the insulating filler between the two; the inner wall of the blind hole has a metal plating layer, and the metal connection block (3) is electrically connected to the bottom metal pattern layer (5) through the metal plating layer.

4. The embedded power module packaging structure according to claim 1, characterized in that: The upper surface of the metal connection block (3) is connected to the top metal pattern layer (4) via a solder layer (6).

5. The embedded power module packaging structure according to claim 1, characterized in that: The metal connection block (3) is equal in height to the MOSFET power chip (2).

6. The embedded power module packaging structure according to claim 1, characterized in that: The insulating filler also extends to fill the vacant part of the top metal pattern layer (4) and is connected to the lower surface of the top insulating layer (9); or, the insulating filler also extends to fill the vacant part of the bottom metal pattern layer (5) and is connected to the upper surface of the bottom insulating layer (10).

7. The embedded power module packaging structure according to claim 1, characterized in that: The top insulating layer (9) further extends downward to fill the vacant portion of the top metal pattern layer (4), and is connected to the insulating filler in the device layer (8); or the bottom insulating layer (10) further extends upward to fill the vacant portion of the top metal pattern layer (4), and is connected to the insulating filler in the device layer (8).

8. The embedded power module packaging structure according to claim 1, characterized in that: The embedded power module packaging structure is in the form of a multi-layer plate as a whole.

9. The embedded power module packaging structure according to claim 1, characterized in that: There are a plurality of top electrode terminals (11) and a plurality of bottom electrode terminals (12).

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