Thin Film Transistor and Method for Preparing the Same

Abstract

An embodiment of the present invention discloses a thin film transistor and a method for manufacturing the same. The thin film transistor includes: a substrate; a first metal layer disposed on the substrate; a first insulating layer covering the first metal layer; a semiconductor layer disposed on the first insulating layer and provided with a groove; a transparent conductive layer disposed on the semiconductor layer and including a first transparent electrode and a second transparent electrode located on both sides of the groove; a second metal layer disposed on the transparent conductive layer and including a first metal electrode and a second metal electrode corresponding to the first transparent electrode and the second transparent electrode respectively; a second insulating layer disposed on the second metal layer and filling the groove, the second insulating layer being provided with a through hole; a pixel electrode disposed on the second insulating layer and connected to the second metal layer through the through hole; the distance between the first transparent electrode and the second transparent electrode in the channel direction is less than the distance between the first metal electrode and the second metal electrode in the channel direction. The thin film transistor disclosed by the present invention can improve the charging efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a thin film transistor and a method for manufacturing the same. Background Art

[0002] As the resolution and refresh rate of liquid crystal displays continue to increase, the pixel loading also increases accordingly, and the problem of insufficient charging may occur in liquid crystal displays. For example, when the resolution of a liquid crystal display reaches 7680RGB*4320 and the refresh rate reaches 120HZ, the charging time of the liquid crystal display is only 1.93 us, resulting in the problem of insufficient charging and ultimately abnormal display of the liquid crystal display screen. Summary of the Invention

[0003] Embodiments of the present invention disclose a thin film transistor and a method for manufacturing the same, which can improve the charging efficiency and avoid the problem of abnormal display of the screen caused by insufficient charging in existing liquid crystal displays.

[0004] Specifically, in a first aspect, an embodiment of the present invention discloses a thin film transistor, including: a substrate; a first metal layer disposed on the substrate and including a gate electrode; a first insulating layer disposed on the substrate and covering the first metal layer; a semiconductor layer disposed on a side of the first insulating layer away from the first metal layer and provided with a groove; a transparent conductive layer disposed on a side of the semiconductor layer away from the first insulating layer and including a first transparent electrode and a second transparent electrode located on both sides of the groove; a second metal layer disposed on a side of the transparent conductive layer away from the semiconductor layer and including: a first metal electrode and a second metal electrode respectively corresponding to the first transparent electrode and the second transparent electrode; a second insulating layer disposed on a side of the second metal layer away from the transparent conductive layer and filling the groove, wherein the second insulating layer is provided with a through hole; and a pixel electrode disposed on a side of the second insulating layer away from the second metal layer and connected to the second metal layer through the through hole; wherein, the first transparent electrode and the first metal electrode form a source electrode, the second transparent electrode and the second metal electrode form a drain electrode, and a distance between the first transparent electrode and the second transparent electrode in a channel direction is less than a distance between the first metal electrode and the second metal electrode in the channel direction.

[0005] In an embodiment of the present invention, the first metal electrode completely covers the first transparent electrode, and the second metal electrode completely covers the second transparent electrode.

[0006] In an embodiment of the present invention, the semiconductor layer includes: a first semiconductor layer disposed on a side of the first insulating layer away from the first metal layer; a second semiconductor layer disposed on a side of the first semiconductor layer away from the first insulating layer; wherein the groove penetrates through the second semiconductor layer and extends into the first semiconductor layer.

[0007] In an embodiment of the present invention, the drain electrode includes: a drain main body portion and a first drain extension portion and a second drain extension portion laterally extending from the drain main body portion; the source electrode includes: a source main body portion and a source extension portion laterally extending from the source main body portion, wherein the source extension portion is located between the first drain extension portion and the second drain extension portion..

[0008] In an embodiment of the present invention, the transparent conductive layer and the second metal layer are etched via the same mask to form the source electrode and the drain electrode.

[0009] Second, a method for manufacturing a thin film transistor disclosed in an embodiment of the present invention includes: forming a first metal layer on a substrate, wherein the first metal layer includes a gate electrode; forming a first insulating layer on the substrate, wherein the first insulating layer covers the first metal layer; forming a semiconductor layer on the first insulating layer; forming a transparent conductive layer on the semiconductor layer; forming a second metal layer on the transparent conductive layer; patterning the second metal layer to form a first metal electrode and a second metal electrode; patterning the transparent conductive layer to form a first transparent electrode and a second transparent electrode respectively corresponding to the first metal electrode and the second metal electrode; patterning the semiconductor layer to form a groove located between the first transparent electrode and the second transparent electrode; forming a second insulating layer on the second metal layer, wherein the second insulating layer fills the groove; patterning the second insulating layer to form a through hole penetrating through the second insulating layer; and forming a pixel electrode on the second metal layer, wherein the pixel electrode extends into the through hole to connect to the second metal layer; wherein, the first transparent electrode and the first metal electrode form a source electrode, the second transparent electrode and the second metal electrode form a drain electrode, and a distance between the first transparent electrode and the second transparent electrode in a channel direction is less than a distance between the first metal electrode and the second metal electrode in the channel direction.

[0010] In an embodiment of the present invention, the step of sequentially stacking and forming a transparent conductive layer and a second metal layer on the semiconductor layer includes: forming the transparent conductive layer on the semiconductor layer; forming the second metal layer on the transparent conductive layer, and the second metal layer completely covers the transparent conductive layer; the step of patterning the transparent conductive layer to form a first transparent electrode and a second transparent electrode corresponding to the first metal electrode and the second metal electrode respectively includes: patterning the transparent conductive layer to form a first transparent electrode completely covered by the first metal electrode and a second transparent electrode completely covered by the second metal electrode.

[0011] In an embodiment of the present invention, the step of forming a semiconductor layer on the first insulating layer includes: forming the first semiconductor layer on the first insulating layer; forming the second semiconductor layer on the first semiconductor layer; the step of patterning the semiconductor layer to form a groove between the first transparent electrode and the second transparent electrode includes: patterning the first semiconductor layer and the second semiconductor layer to form the groove that penetrates the second semiconductor layer and extends into the first semiconductor layer.

[0012] In an embodiment of the present invention, the step of patterning the second metal layer to form a first metal electrode and a second metal electrode, and the step of patterning the transparent conductive layer to form a first transparent electrode and a second transparent electrode corresponding to the first metal electrode and the second metal electrode respectively include: using the same mask to etch the second metal layer and the transparent conductive layer respectively to form the source electrode and the drain electrode.

[0013] In an embodiment of the present invention, the drain electrode includes: a drain main body portion, a first drain extension portion and a second drain extension portion that laterally extend from the drain main body portion; the source electrode includes: a source main body portion and a source extension portion that laterally extends from the source main body portion, wherein the source extension portion is located between the first drain extension portion and the second drain extension portion.

[0014] The above technical solution of the present invention may have one or more of the following beneficial effects: On the one hand, by providing a transparent conductive layer between the semiconductor layer and the second metal layer, the first transparent electrode of the transparent conductive layer and the first metal electrode of the second metal layer form a source electrode, the second transparent electrode of the transparent conductive layer and the second metal electrode of the second metal layer form a drain electrode, and the distance between the first transparent electrode and the second transparent electrode in the channel direction is set to be less than the distance between the first metal electrode and the second metal electrode in the channel direction, which can reduce the channel length of the thin film transistor, thereby improving the charging speed and effectively avoiding the problem of abnormal picture display caused by insufficient charging of the existing liquid crystal display; On the other hand, by arranging the source electrode extension part between the first drain electrode extension part and the second drain electrode extension part, that is, using the electrode with a smaller self-capacitance of the thin film transistor as the source electrode to connect the data line, the area of the source electrode is reduced, the capacitance of the source electrode is decreased, thereby reducing the pixel load and further improving the charging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solution of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1a It is a partial structural schematic diagram of a thin film transistor disclosed in the first embodiment of the present invention.

[0017] Figure 1b It is a structural schematic diagram of a thin film transistor disclosed in the first embodiment of the present invention.

[0018] Figure 2 It is another partial structural schematic diagram of a thin film transistor disclosed in the first embodiment of the present invention.

[0019] Figure 3 It is a partial structural schematic diagram of the source electrode and the drain electrode in a thin film transistor disclosed in the first embodiment of the present invention.

[0020] Figure 4 It is a flow schematic diagram of a method for manufacturing a thin film transistor disclosed in the second embodiment of the present invention.

[0021] Figure 5a It is a structural schematic diagram showing an example after forming a gate electrode in the second embodiment of the present invention;

[0022] Figure 5b It is a structural schematic diagram showing an example after forming a first insulating layer in the second embodiment of the present invention.

[0023] Figure 5cSchematic diagram for illustration of a structure after forming a semiconductor layer according to the second embodiment of the present invention.

[0024] Figure 5d Schematic diagram for illustration of a structure after forming a second metal layer according to the second embodiment of the present invention.

[0025] Figure 5e Schematic diagram for illustration of a structure after patterning the second metal layer, transparent conductive layer, and semiconductor layer according to the second embodiment of the present invention.

[0026] Figure 5f Schematic diagram for illustration of a structure after forming a second insulating layer and a through hole according to the second embodiment of the present invention.

[0027] Figure 5g Schematic diagram for illustration of a structure after forming a pixel electrode according to the second embodiment of the present invention. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0030]

First Embodiment

[0031] Refer to Figure 1a and Figure 1b , the first embodiment of the present invention discloses a thin film transistor 100, including: a substrate 110, a first metal layer, a first insulating layer 130, a semiconductor layer 140, a transparent conductive layer 150, a second metal layer 160, a second insulating layer 170, and a pixel electrode 180.

[0032] Among them, the first metal layer is disposed on the substrate 110 and includes a gate electrode 121, that is, the gate electrode 121 is disposed on the substrate 110. The first insulating layer 130 is disposed on the substrate 110 and covers the first metal layer, that is, the first insulating layer 130 covers the gate electrode 121. The semiconductor layer 140 is disposed on a side of the first insulating layer 130 away from the first metal layer 120 and is provided with a groove 141. The transparent conductive layer 150 is disposed on a side of the semiconductor layer 140 away from the first insulating layer 130 and includes a first transparent electrode 151 and a second transparent electrode 152 located on both sides of the groove 141. Here, it can be understood that the transparent conductive layer 150 completely covers the semiconductor layer 140 and partially covers the first insulating layer 130. The second metal layer 160 is disposed on a side of the transparent conductive layer 150 away from the semiconductor layer 140 and includes: a first metal electrode 161 and a second metal electrode 162 corresponding to the first transparent electrode 151 and the second transparent electrode 152 respectively. The second insulating layer 170 is disposed on a side of the second metal layer 160 away from the transparent conductive layer 150 and fills the groove 141, wherein the second insulating layer 170 is provided with a through hole 171. The pixel electrode 180 is disposed on a side of the second insulating layer 170 away from the second metal layer 160 and is connected to the second metal layer 160 through the through hole 171. Among them, the first transparent electrode 151 and the first metal electrode 161 form a source electrode 191, the second transparent electrode 152 and the second metal electrode 162 form a drain electrode 192, and a distance L1 between the first transparent electrode 151 and the second transparent electrode 152 in the channel direction is less than a distance L2 between the first metal electrode 161 and the second metal electrode 162 in the channel direction.

[0033] Specifically, the material of the substrate 110 is, for example, glass, quartz, organic polymer, etc. The first metal layer is a conductive metal thin film layer, and its material can be, for example, molybdenum, aluminum, copper, titanium, tungsten, etc., that is, the material of the gate electrode 121 is, for example, molybdenum, aluminum, copper, titanium, tungsten, etc. In addition to including the gate electrode 121, the first metal layer also includes, for example, a scanning line (not shown in the figure) of the array substrate and a common voltage line (not shown in the figure) of the array substrate, and the scanning line is connected to the gate electrode 121. The first insulating layer 130 is, for example, a silicon nitride layer or a silicon oxide layer. Of course, the present invention is not limited thereto, and other materials having an insulating function are applicable to the first insulating layer 130. The material of the transparent conductive layer 150 is, for example, a transparent conductive oxide such as ITO or IZO, that is, the material of the first transparent electrode 151 and the second transparent electrode 152 is, for example, a transparent conductive oxide such as ITO or IZO. The material of the second metal layer 160 is, for example, molybdenum, aluminum, copper, titanium, tungsten, etc., that is, the material of the first metal electrode 161 and the second metal electrode 162 is, for example, molybdenum, aluminum, copper, titanium, tungsten, etc. It is, for example, the same as the material of the first metal layer, and of course, it can also be different from the material of the first metal layer.

[0034] Among them, the first metal electrode 161 and the first transparent electrode 151 form the source electrode 191, and the second metal electrode 162 and the second transparent electrode 162 form the drain electrode 192. In addition, the second metal layer 160 and the transparent conductive layer 150 also form the data lines (not shown in the figure) of the array substrate, which are connected to the source electrode 191. It can be understood here that the data lines also include two layers, namely the transparent conductive layer and the second metal layer. Of course, the present invention is not limited thereto, and the data lines can also be formed only by the second metal layer. The second insulating layer 170 is, for example, a silicon nitride layer or a silicon oxide layer. Of course, the present invention is not limited thereto, and other materials having an insulating effect are applicable to the second insulating layer 170. The filling of the groove 141 by the second insulating layer 170 mentioned herein can be understood as that the second insulating layer 170 fills the gaps between the first metal electrode 161 and the second metal electrode 162 and between the first transparent electrode 151 and the second transparent electrode 152 and then fills the groove 141. The pixel electrode 180 is composed of, for example, a conductive metal oxide, such as ITO. Of course, the present invention is not limited thereto, and other conductive materials are also applicable to the pixel electrode 180.

[0035] According to the charging formula of the thin film transistor (a known formula in the prior art), increasing the channel width or decreasing the channel length will improve its charging ability. However, increasing the channel width will cause problems such as increasing capacitance and inductance, thereby increasing the load and reducing the aperture ratio. In the embodiment of the present invention, by providing a transparent conductive layer 150, such as an ITO layer or an IZO layer, between the second metal layer 160 and the semiconductor layer 140, the channel length can be reduced, and thus the charging ability can be improved. For example, the thickness of the transparent conductive layer 150, such as the ITO layer (about 600 Å), is thinner than that of the second metal layer 160 (thickness about 3000 Å). The resolution of exposure, development, and etching of the transparent conductive layer 150 can be less than that of the second metal layer. The exposure resolution of the transparent conductive layer 150 is, for example, 2 μm, and the exposure resolution of the second metal layer is, for example, 4 μm. Then, in the etching process, the etching CD of the ITO layer only loses 0.25 μm, while the etching CD of the second metal layer loses 2 μm. Therefore, compared with the thin film transistor in the prior art in which the source electrode and the drain electrode are only formed by the second metal layer, the thin film transistor disclosed in the first embodiment of the present invention has a reduced channel length and improved charging ability by providing a transparent conductive layer 150 between the second metal layer 160 and the semiconductor layer 140 and making the distance L1 between the first transparent electrode 151 and the second transparent electrode 152 in the channel direction less than the distance L2 between the first metal electrode 161 and the second metal electrode 162 in the channel direction.

[0036] Furthermore, as Figure 2As shown, the semiconductor layer 140 includes, for example, a first semiconductor layer 142 and a second semiconductor layer 143. Among them, the first semiconductor layer 142 is disposed on a side of the first insulating layer 130 away from the first metal layer 120, the second semiconductor layer 143 is disposed on a side of the first semiconductor layer 142 away from the first insulating layer 130, and the groove 141 penetrates through the second semiconductor layer 143 and extends into the first semiconductor layer 142. Among them, the first semiconductor layer is, for example, an a-Si layer, and the second semiconductor layer is, for example, an n + -a-Si layer. Among them, the transparent conductive layer 150 is disposed on a side of the second semiconductor layer 143 away from the first semiconductor layer 142, and the second metal layer 160 is disposed on a side of the transparent conductive layer 150 away from the second semiconductor layer 143.

[0037] Here, it should be supplemented that regarding the ohmic contact between ITO and the a-Si layer: Theoretically, there are two main factors affecting the formation of an ohmic contact between a metal and a semiconductor: the work functions of the metal and the semiconductor and the surface state density of the semiconductor; from the perspective of the influence of the work function on the contact between the metal and the semiconductor, to form an ohmic contact, for an n-type semiconductor, it is required that Wm is much smaller than Ws, so that an n-type back barrier layer is formed between the metal and the semiconductor. However, due to the influence of surface states in a-Si:H, the influence of the work function on the formation of an ohmic contact is weakened. Even if Wm is much smaller than Ws, a good ohmic contact cannot be formed between the metal and the semiconductor. In actual production, the principle of the tunneling effect is mainly used to fabricate an ohmic contact on the semiconductor. From the perspective of the work function, for the n-type semiconductor a-Si:H, the metal work function should be smaller than the semiconductor work function. The following are the work functions of each metal: Al 4.28 eV, Cu 4.65 eV. The measured value of the work function of ITO obtained from Baidu literature is 4.5 eV. ITO is between Al and Cu. Therefore, the n +- a-Si of the currently used thin-film transistors is also applicable to ITO.

[0038] Furthermore, as shown in the figure, the first metal electrode 161 completely covers the first transparent electrode 151, and the second metal electrode 162 completely covers the second transparent electrode 152.

[0039] Further, the transparent conductive layer 150 and the second metal layer 160 are etched to form the source electrode 191 and the drain electrode 192 via the same mask, respectively. By etching the transparent conductive layer and the second metal layer via the same mask to obtain the source electrode and the drain electrode, the preparation efficiency of the thin film transistor can be improved and the preparation process can be simplified. It can be understood here that when patterning the second metal layer 160, for example, a photoresist is coated on the second metal layer 160, and the photoresist is exposed and developed to obtain a patterned photoresist layer. Then, using the patterned photoresist layer as a mask, the second metal layer 160 and the transparent conductive layer 150 are etched respectively to form the first metal electrode 161, the second metal electrode 162, the first transparent electrode 151, and the second transparent electrode 152, and the first metal electrode 161 completely covers the first transparent electrode 151, and the second metal electrode 162 completely covers the second transparent electrode 152. It is worth mentioning here that when etching the transparent conductive layer 150 and the second metal layer 160 based on the same mask, since the loss of etching the second metal layer is much greater than that of the transparent conductive layer 150, the distance L1 of the first transparent electrode 151 and the second transparent electrode 152 along the channel direction can be made smaller than the distance L2 of the first metal electrode 161 and the second metal electrode 162 along the channel direction, thereby reducing the channel length and improving the charging efficiency.

[0040] In other embodiments of the present invention, as Figure 3 shown, the drain electrode 192 includes, for example, a drain main body portion 1921 and a first drain extension portion 1922 and a second drain extension portion 1923 that extend laterally from the drain main body portion 1921. The source electrode 191 includes, for example, a source main body portion 1911 and a source extension portion 1912 that extends laterally from the source main body portion 1911, and the source extension portion 1912 is located between the first drain extension portion 1922 and the second drain extension portion 1923. The source extension portion 1912, the first drain extension portion 1922, and the second drain extension portion 1923 here are, for example, two-layer structures, that is, they include a transparent conductive layer and a second metal layer.

[0041] It can be understood here that the load of the array substrate includes two parts: resistance and capacitance. From the calculation formulas of capacitance and resistance (existing known formulas), as the resolution increases, the capacitance of the gate electrode and the source electrode increases; in the existing thin film transistors, the area of the source electrode located in the semiconductor region is much larger than that of the drain electrode, so the area of the source electrode and the data line connected to the source electrode is large, and the capacitance is large, resulting in an increase in load and seriously affecting the charging efficiency; the thin film transistor disclosed in the embodiment of the present invention reduces the area of the source electrode. Specifically, the source extension portion is located between the first drain extension portion and the second drain extension portion, that is, the electrode with a smaller self-capacitance of the thin film transistor is used as the source electrode to connect the data line, thereby reducing the load and improving the charging efficiency.

[0042] It is worth mentioning that in other embodiments of the present invention, a transparent conductive layer may be provided only between the second metal layer and the semiconductor layer, and the electrode with a smaller self-capacitance is not used as the source electrode to improve the charging efficiency; of course, in other embodiments of the present invention, the transparent conductive layer may not be provided between the second metal layer and the semiconductor layer, and only the electrode with a smaller self-capacitance of the thin film transistor is used as the source electrode to connect the data line to improve the charging efficiency.

[0043] In summary, the thin film transistor 100 disclosed in the embodiments of the present invention, by providing a transparent conductive layer between the semiconductor layer and the second metal layer, enables the first transparent electrode of the transparent conductive layer and the first metal electrode of the second metal layer to form the source electrode, and the second transparent electrode of the transparent conductive layer and the second metal electrode of the second metal layer to form the drain electrode. And setting the distance between the first transparent electrode and the second transparent electrode in the channel direction to be less than the distance between the first metal electrode and the second metal electrode in the channel direction can reduce the channel length of the thin film transistor, thereby improving the charging speed, and effectively avoiding the problem of abnormal picture display caused by insufficient charging of the existing liquid crystal display; further, by arranging the source electrode extension part between the first drain electrode extension part and the second drain electrode extension part, the area of the source electrode is reduced, that is, the electrode with a smaller self-capacitance of the thin film transistor is used as the source electrode to connect the data line, reducing the capacitance of the source electrode, thereby reducing the pixel load and further improving the charging efficiency.

[0044]

Second Embodiment

[0045] See Figure 4 , the second embodiment of the present invention discloses a method for manufacturing a thin film transistor, for example, including:

[0046] Step S11: Form a first metal layer on a substrate, wherein the first metal layer includes a gate electrode;

[0047] Step S12: Form a first insulating layer on the substrate, wherein the first insulating layer covers the first metal layer;

[0048] Step S13: Form a semiconductor layer on the first insulating layer;

[0049] Step S14: Sequentially stack and form a transparent conductive layer and a second metal layer on the semiconductor layer;

[0050] Step S15: Pattern the second metal layer to form a first metal electrode and a second metal electrode;

[0051] Step S16: Pattern the transparent conductive layer to form a first transparent electrode and a second transparent electrode corresponding to the first metal electrode and the second metal electrode respectively;

[0052] Step S17: Pattern the semiconductor layer to form a groove between the first transparent electrode and the second transparent electrode;

[0053] Step S18: Form a second insulating layer on the second metal layer, wherein the second insulating layer fills the groove;

[0054] Step S19: Pattern the second insulating layer to form a through hole penetrating the second insulating layer; and

[0055] Step S20: Form a pixel electrode on the second metal layer, wherein the pixel electrode extends into the through hole to connect with the second metal layer;

[0056] Wherein, the first transparent electrode and the first metal electrode form a source electrode, the second transparent electrode and the second metal electrode form a drain electrode, and the distance between the first transparent electrode and the second transparent electrode along the channel direction is less than the distance between the first metal electrode and the second metal electrode along the channel direction.

[0057] In an embodiment of the present invention, step S14, for example, includes: forming the transparent conductive layer on the semiconductor layer; and forming the second metal layer on the transparent conductive layer, and the second metal layer completely covers the transparent conductive layer. Step S16, for example, includes: patterning the transparent conductive layer to form a first transparent electrode completely covered by the first metal electrode and a second transparent electrode completely covered by the second metal electrode.

[0058] Further, steps S15 and S16, for example, include: using the same mask to etch the second metal layer and the transparent conductive layer respectively to form the source electrode and the drain electrode. Here, it can be understood that patterning the second metal layer and patterning the transparent conductive layer, for example, use the same mask, that is, applying a photoresist on the second metal layer, exposing and developing the photoresist to obtain a patterned photoresist layer, and then using the patterned photoresist layer as a mask to etch the second metal layer and the transparent conductive layer respectively to form the first metal electrode, the second metal electrode, the first transparent electrode and the second transparent electrode, that is, forming the source electrode and the drain electrode.

[0059] In other embodiments of the present invention, step S13, for example, includes: forming the first semiconductor layer on the first insulating layer; and forming the second semiconductor layer on the first semiconductor layer. Step S17, for example, includes: performing the patterning process on the first semiconductor layer and the second semiconductor layer to form the groove penetrating the second semiconductor layer and extending into the first semiconductor layer.

[0060] In other embodiments of the present invention, the drain electrode includes, for example: a drain main body portion and a first drain extension portion and a second drain extension portion that laterally extend from the drain main body portion; the source electrode includes, for example: a source main body portion and a source extension portion that laterally extends from the source main body portion, wherein the source extension portion is located between the first drain extension portion and the second drain extension portion. By arranging the source extension portion between the first drain extension portion and the second drain extension portion, the area of the source electrode is reduced, that is, the electrode with a smaller self-capacitance of the thin film transistor is used as the source electrode to connect to the data line, reducing the capacitance of the source electrode, thereby reducing the pixel load and further improving the charging efficiency.

[0061] For ease of understanding, the following combines Figures 5a to 5g to specifically illustrate the preparation method of the thin film transistor 100 disclosed in the first embodiment of the present invention.

[0062] In step S11, the material of the substrate 110 is, for example, glass, quartz, organic polymer, etc. The first metal layer is a conductive metal thin film layer, and its material can be, for example, molybdenum, aluminum, copper, titanium, tungsten, etc., that is, the material of the gate electrode 121 is, for example, molybdenum, aluminum, copper, titanium, tungsten, etc. It is worth mentioning here that in addition to including the gate electrode 121, the first metal layer also includes, for example, the scanning line of the array substrate and the common voltage line of the array substrate, and the scanning line is connected to the gate electrode 121. As Figure 5a shown, step S11 can specifically be: depositing the first metal layer on the substrate 110 and performing a patterning process on the first metal layer to obtain the gate electrode 121. The patterning process mentioned here includes, for example: etching the first metal layer through a mask plate to form the gate electrode 121.

[0063] In step S12, the material of the first insulating layer 130 is, for example, one of silicon nitride or silicon oxide. Of course, the present invention is not limited thereto. As Figure 5b shown, step S12 includes, for example: forming the first insulating layer 130 by chemical vapor deposition or sputtering method. The first insulating layer 130 completely covers the first metal layer, that is, completely covers the gate electrode 121.

[0064] In step S13, the semiconductor layer 140 includes, for example: two layers: the first semiconductor layer is, for example, an a-Si layer and the second semiconductor layer is, for example, an n + -a-Si layer. Of course, the present invention is not limited thereto. The first semiconductor layer, for example, the a-Si layer and the second semiconductor layer, for example, the n + -a-Si layer are sequentially stacked on the first insulating layer 130 by chemical vapor deposition method. As Figure 5cAs shown, step S13 includes, for example: forming a semiconductor layer that completely covers the first insulating layer 130 by chemical vapor deposition, and then wet-etching the semiconductor layer that completely covers the first insulating layer 130 to obtain the semiconductor layer 140.

[0065] In step S14, the material of the transparent conductive layer 150 is, for example, a transparent conductive oxide such as ITO or IZO. The material of the second metal layer 160 is, for example, molybdenum, aluminum, copper, titanium, tungsten, etc. As Figure 5d shown, step S14 includes, for example: sputtering to form the transparent conductive layer 150 on the semiconductor layer 140 and the first insulating layer 130, and sputtering to form the second metal layer 160 on the transparent conductive layer 150, where the second metal layer 160 completely covers the transparent conductive layer 150, for example.

[0066] As Figure 5e shown, steps S15 to S17 can be understood as: using the same mask to pattern the second metal layer 160, the transparent conductive layer 150, and the semiconductor layer 140 to form the first transparent electrode 151 and the second transparent electrode 152 on both sides of the groove 141 and the first metal electrode 161 and the second metal electrode 162 corresponding to the first transparent electrode 151 and the second transparent electrode 152 respectively, where the first metal electrode 161 completely covers the first transparent electrode 151, and the second metal electrode 162 completely covers the second transparent electrode 152. Specifically, a photoresist is coated on the second metal layer 160, and the photoresist is exposed and developed to obtain a patterned photoresist layer. Then, using the patterned photoresist layer as a mask, the second metal layer 160, the transparent conductive layer 150, and the semiconductor layer 140 are etched respectively to form the source electrode 191 and the drain electrode 192, and the groove 141. When etching the transparent conductive layer 150 and the second metal layer 160 based on the same mask, since the loss of etching of the second metal layer is much greater than that of the transparent conductive layer 150, the distance L1 between the first transparent electrode 151 and the second transparent electrode 152 in the channel direction can be made smaller than the distance L2 between the first metal electrode 161 and the second metal electrode 162 in the channel direction, thereby reducing the channel length and improving the charging efficiency.

[0067] In step S18, the material of the second insulating layer 170 is, for example, silicon nitride or silicon oxide. As Figure 5f shown, steps S18 and S19 can be understood as: forming the second insulating layer 170 by chemical vapor deposition, and coating a photoresist on the second insulating layer 170, exposing and developing the photoresist to obtain a patterned photoresist layer. Then, using the patterned photoresist layer as a mask to etch the second insulating layer 170 to form a through hole 171.

[0068] In step S20, the pixel electrode 180 includes, for example, a conductive metal oxide, such as ITO, etc. AsFigure 5g As shown, step S20 includes, for example: sputtering and forming a pixel electrode layer on the second insulating layer 170, and then patterning the pixel electrode layer to form a pixel electrode 180. The patterning process includes, for example: coating a photoresist on the pixel electrode layer, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the pixel electrode layer using the patterned photoresist layer as a mask to form the pixel electrode 180, thereby completing the preparation of the thin film transistor 100.

[0069] In summary, for the method for preparing a thin film transistor disclosed in the embodiments of the present invention, by providing a transparent conductive layer between the semiconductor layer and the second metal layer, the first transparent electrode of the transparent conductive layer and the first metal electrode of the second metal layer form a source electrode, and the second transparent electrode of the transparent conductive layer and the second metal electrode of the second metal layer form a drain electrode. Moreover, by setting the distance between the first transparent electrode and the second transparent electrode in the channel direction to be less than the distance between the first metal electrode and the second metal electrode in the channel direction, the channel length of the thin film transistor can be reduced, thereby improving the charging speed, and effectively avoiding the problem of abnormal image display caused by insufficient charging of the existing liquid crystal display; further, by arranging the source electrode extension portion between the first drain electrode extension portion and the second drain electrode extension portion, the area of the source electrode is reduced, that is, the electrode with a smaller self-capacitance of the thin film transistor is used as the source electrode to connect to the data line, reducing the capacitance of the source electrode, thereby reducing the pixel load and further improving the charging efficiency.

[0070] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A thin film transistor, characterized in that, Comprising: A substrate; A first metal layer disposed on the substrate and including a gate electrode; A first insulating layer disposed on the substrate and covering the first metal layer; A semiconductor layer disposed on a side of the first insulating layer away from the first metal layer and provided with a groove; A transparent conductive layer disposed on a side of the semiconductor layer away from the first insulating layer and including a first transparent electrode and a second transparent electrode located on both sides of the groove; A second metal layer disposed on a side of the transparent conductive layer away from the semiconductor layer and including: a first metal electrode and a second metal electrode respectively corresponding to the first transparent electrode and the second transparent electrode; A second insulating layer disposed on a side of the second metal layer away from the transparent conductive layer and filling the groove, wherein the second insulating layer is provided with a through hole; and A pixel electrode disposed on a side of the second insulating layer away from the second metal layer and connected to the second metal layer through the through hole; Wherein, the first transparent electrode and the first metal electrode form a source electrode, the second transparent electrode and the second metal electrode form a drain electrode, and a distance between the first transparent electrode and the second transparent electrode in a channel direction is less than a distance between the first metal electrode and the second metal electrode in the channel direction; The transparent conductive layer and the second metal layer are etched via the same mask to form the source electrode and the drain electrode.

2. The thin film transistor according to claim 1, wherein The first metal electrode does not completely cover the first transparent electrode, and the second metal electrode does not completely cover the second transparent electrode.

3. The thin film transistor according to claim 1, wherein The semiconductor layer includes: A first semiconductor layer disposed on a side of the first insulating layer away from the first metal layer; A second semiconductor layer disposed on a side of the first semiconductor layer away from the first insulating layer; Wherein, the groove penetrates through the second semiconductor layer and extends into the first semiconductor layer.

4. The thin film transistor according to claim 1, characterized in that The drain electrode includes: a drain main body portion and a first drain extension portion and a second drain extension portion laterally extending from the drain main body portion; the source electrode includes: a source main body portion and a source extension portion laterally extending from the source main body portion, wherein the source extension portion is located between the first drain extension portion and the second drain extension portion.

5. A method for preparing a thin film transistor, characterized in that, Comprising: Forming a first metal layer on a substrate, wherein the first metal layer includes a gate electrode; Forming a first insulating layer on the substrate, wherein the first insulating layer covers the first metal layer; Forming a semiconductor layer on the first insulating layer; Sequentially stacking and forming a transparent conductive layer and a second metal layer on the semiconductor layer; Performing a patterning process on the second metal layer to form a first metal electrode and a second metal electrode; Performing a patterning process on the transparent conductive layer to form a first transparent electrode and a second transparent electrode respectively corresponding to the first metal electrode and the second metal electrode; Performing a patterning process on the semiconductor layer to form a groove located between the first transparent electrode and the second transparent electrode; Forming a second insulating layer on the second metal layer, wherein the second insulating layer fills the groove; Patterning the second insulating layer to form a through hole penetrating the second insulating layer; And Forming a pixel electrode on the second metal layer, wherein the pixel electrode extends into the through hole to connect the second metal layer; Wherein, the first transparent electrode and the first metal electrode form a source electrode, the second transparent electrode and the second metal electrode form a drain electrode, and the distance between the first transparent electrode and the second transparent electrode in the channel direction is less than the distance between the first metal electrode and the second metal electrode in the channel direction; Wherein, patterning the second metal layer to form a first metal electrode and a second metal electrode, and patterning the transparent conductive layer to form a first transparent electrode and a second transparent electrode corresponding to the first metal electrode and the second metal electrode respectively, includes: using the same mask to etch the second metal layer and the transparent conductive layer respectively to form the source electrode and the drain electrode.

6. The preparation method according to claim 5, characterized in that, The sequentially stacking and forming a transparent conductive layer and a second metal layer on the semiconductor layer includes: Forming the transparent conductive layer on the semiconductor layer; Forming the second metal layer on the transparent conductive layer, and the second metal layer completely covers the transparent conductive layer; The patterning the transparent conductive layer to form a first transparent electrode and a second transparent electrode corresponding to the first metal electrode and the second metal electrode respectively, includes: Patterning the transparent conductive layer to form a first transparent electrode not completely covered by the first metal electrode and a second transparent electrode not completely covered by the second metal electrode.

7. The preparation method according to claim 5, characterized in that, The forming a semiconductor layer on the first insulating layer includes: Forming the first semiconductor layer on the first insulating layer; Forming the second semiconductor layer on the first semiconductor layer; The patterning the semiconductor layer to form a groove between the first transparent electrode and the second transparent electrode includes: Patterning the first semiconductor layer and the second semiconductor layer to form the groove penetrating the second semiconductor layer and extending into the first semiconductor layer.

8. The preparation method according to claim 5, characterized in that, The drain electrode includes: a drain main body portion and a first drain extension portion and a second drain extension portion laterally extending from the drain main body portion; the source electrode includes: a source main body portion and a source extension portion laterally extending from the source main body portion, wherein the source extension portion is located between the first drain extension portion and the second drain extension portion.

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