Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method of forming a semiconductor structure, the structure comprising: a substrate comprising an adjacent drift region and body region, the drift region having a first ion therein, the body region having a second ion therein, the second ion having a conductivity type opposite to that of the first ion; a recess in the drift region and an isolation structure in the recess, the isolation structure comprising a semiconductor material; a gate structure on part of the substrate, the gate structure extending from a surface of the body region to a surface of the drift region, the gate structure being on part or all of a surface of the isolation structure. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] Lateral double-diffused metal oxide semiconductors (LDMOS) are high-voltage power devices characterized by high operating voltage, relatively simple fabrication processes, and high switching frequencies. Furthermore, the fabrication technology based on bulk silicon is well-established, thus LDMOS devices have broad development prospects. The drain, source, and gate of LDMOS devices are all located on their surface, making them easy to integrate into chips. Therefore, they are particularly suitable as high-voltage power devices in high-voltage integrated circuits and power integrated circuits.

[0003] However, the performance of existing lateral double-diffused metal-oxide semiconductors needs to be improved. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of lateral double-diffused metal oxide semiconductors.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including adjacent drift regions and a body region, wherein the drift regions contain first ions and the body regions contain second ions, the conductivity type of the second ions being opposite to that of the first ions; a groove located within the drift regions and an isolation structure located within the grooves, the isolation structure being made of a semiconductor material; and a gate structure located on a portion of the substrate, the gate structure extending from the surface of the body region to the surface of the drift region, the gate structure being located on part or all of the surface of the isolation structure.

[0006] Optionally, the material of the isolation structure includes silicon carbide.

[0007] Optionally, the material of the isolation structure may further include silicon carbide doped with a third ion; the conductivity type of the third ion is the same as that of the first ion.

[0008] Optionally, the concentration of the third ion is less than the concentration of the first ion.

[0009] Optionally, the isolation structure includes: a first isolation layer located on the sidewall surface and bottom surface of the groove, and a second isolation layer located on the first isolation layer.

[0010] Optionally, the material of the first isolation layer includes silicon carbide; the material of the second isolation layer includes silicon germanium.

[0011] Optionally, the material of the first isolation layer may further include silicon carbide doped with a third ion; the conductivity type of the third ion is the same as that of the first ion, and the third ion may include phosphorus ions or boron ions.

[0012] Optionally, it may also include: a drain region located within the drift region, and a source region located within the body region, wherein the ionic conductivity type of the source region and the drain region is the same as the conductivity type of the first ion.

[0013] Optionally, the first ion includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion; the first ion includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion.

[0014] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an adjacent first region and a second region; implanting first ions into the first region and the second region using a first ion implantation process to form an initial drift region in the first region and the second region; after forming the initial drift region, forming a groove in the first region; forming an isolation structure in the groove, the material of the isolation structure comprising a semiconductor material; after forming the isolation structure, forming a gate structure on a portion of the initial drift region, the gate structure extending from the surface of the second region to the surface of the first region, the gate structure being located on part or all of the surface of the isolation structure.

[0015] Optionally, the method of forming the isolation structure includes: forming an isolation material layer in the groove and on the initial drift region; planarizing the isolation material layer until the surface of the initial drift region is exposed, thereby forming the isolation structure.

[0016] Optionally, the material of the isolation structure includes silicon carbide.

[0017] Optionally, the material of the isolation structure may further include silicon carbide doped with a third ion; the conductivity type of the third ion is the same as that of the first ion, and the third ion may include phosphorus ions or boron ions.

[0018] Optionally, the concentration of the third ion is less than the concentration of the first ion.

[0019] Optionally, the process for forming the isolation material layer includes an epitaxial growth process or a deposition process.

[0020] Optionally, when forming the isolation material layer using the epitaxial growth process or deposition process, the process for forming the isolation material layer further includes: in-situ doping process.

[0021] Optionally, the isolation structure includes a first isolation layer located on the sidewall surface and bottom surface of the groove, and a second isolation layer located on the first isolation layer; the isolation material layer includes a first isolation material layer and a second isolation material layer located on the first isolation material layer.

[0022] Optionally, the material of the first isolation layer includes silicon carbide; the material of the second isolation layer includes silicon germanium.

[0023] Optionally, the material of the first isolation layer may further include silicon carbide doped with a third ion; the conductivity type of the third ion is the same as that of the first ion, and the third ion may include phosphorus ions or boron ions.

[0024] Optionally, the process for forming the first isolation material layer includes an epitaxial growth process or a deposition process.

[0025] Optionally, when forming the first isolation material layer using the epitaxial growth process or deposition process, the process for forming the first isolation material layer further includes: in-situ doping process.

[0026] Optionally, the process for forming the second isolation material layer includes an epitaxial growth process or a deposition process.

[0027] Optionally, after forming the gate structure, the method further includes: forming a mask structure on the substrate, the mask structure exposing the surface of the second region and the surface of the gate structure located on the second region; using the mask structure as a mask, implanting second ions in the second region using a second ion implantation process to form a body region in the second region, and causing the initial drift region of the first region to form a drift region, wherein the conductivity type of the second ion is opposite to that of the first ion.

[0028] Optionally, after forming the body region, the method further includes: forming a drain region within the drift region and forming a source region within the body region, wherein the ionic conductivity type of the source region and the drain region is the same as that of the first ion.

[0029] Optionally, the first ion includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion; the first ion includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] The semiconductor structure of the present invention includes an isolation structure within the drift region, and the material of the isolation structure comprises a semiconductor material. The semiconductor material of the isolation structure serves two purposes: firstly, it blocks most of the current, thus preventing diffusion; secondly, when the bias voltage across the isolation structure reaches a certain range, the semiconductor material allows a portion of the current to flow through the isolation structure to the channel, shortening the current path and thus shunting the current, thereby improving the operating current of the semiconductor structure.

[0032] The method for forming the technical solution of the present invention involves first forming an initial drift region in a first region and a second region, then forming a groove in the first region, and finally forming an isolation structure in the groove. The material of the isolation structure includes a semiconductor material. In this method, the semiconductor material of the isolation structure serves two purposes: firstly, it blocks most of the current, thus preventing diffusion; secondly, when the bias voltage across the isolation structure reaches a certain range, the semiconductor material allows a portion of the current to flow through the isolation structure to the channel, shortening the path of some current and thus acting as a current shunting mechanism, thereby improving the operating current of the semiconductor structure.

[0033] Furthermore, the material of the isolation structure includes silicon carbide. The silicon carbide material possesses diffusion-blocking and conductivity properties, thereby improving the operating current of the semiconductor structure while providing isolation.

[0034] Furthermore, the material of the isolation structure includes silicon carbide doped with phosphorus or boron ions. The phosphorus or boron ions can fine-tune the conductivity of the silicon carbide material.

[0035] Furthermore, the isolation structure includes a first isolation layer and a second isolation layer located on the first isolation layer. The material of the first isolation layer includes silicon carbide; the material of the second isolation layer includes silicon germanium. The silicon germanium material has good conductivity, thereby increasing the conductivity of the isolation structure.

[0036] Furthermore, the material of the first insulating layer also includes silicon carbide doped with phosphorus or boron ions. The phosphorus or boron ions can fine-tune the conductivity of the silicon carbide material. Attached Figure Description

[0037] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment;

[0038] Figures 2 to 7 This is a cross-sectional structural schematic diagram of the semiconductor structure formation process in one embodiment of the present invention;

[0039] Figure 8 and Figure 9 This is a cross-sectional schematic diagram of the semiconductor structure formation process in another embodiment of the present invention. Detailed Implementation

[0040] As described in the background section, the performance of existing laterally double-diffused metal-oxide-semiconductor semiconductors needs improvement. This will now be analyzed and explained with reference to specific embodiments.

[0041] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment.

[0042] Please refer to Figure 1 The system includes: a substrate 100, which includes an adjacent first region I and a second region II; a drift region 101 located in the first region I and a body region 102 located in the second region II; an isolation structure 103 located in the drift region 101; a gate structure 104 located on a portion of the drift region 101 and a portion of the body region 102, the gate structure 104 extending from the surface of the drift region 101 to the surface of the body region 102, and a portion of the gate structure 104 located on the surface of the isolation structure 103; a drain region 105 located in the drift region 101 and a source region 106 located in the body region 102.

[0043] In the semiconductor structure, the isolation structure 103 is used to block ions in the drain region 105 from diffusing into the channel, thereby increasing the breakdown voltage of the semiconductor structure and improving its breakdown resistance. The material of the isolation structure 103 is usually silicon oxide, and in order to reduce the use of photomasks, all the isolation structures 103 on the substrate are usually formed in one process, so that the depth of the isolation structures 103 is uniform and cannot be adjusted.

[0044] For the semiconductor structure, the isolation structure 103 formed in one process is usually quite deep. Since the material of the isolation structure 103 is insulating, the operating current of the semiconductor structure needs to bypass the isolation structure. This increases the path of the operating current of the semiconductor structure, thereby increasing the resistance and reducing the operating current of the semiconductor structure, which affects the performance of the semiconductor structure.

[0045] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. An isolation structure is formed within the drift region, and the material of the isolation structure includes a semiconductor material. The semiconductor material of the isolation structure serves two purposes: firstly, it blocks most of the current, thus preventing diffusion; secondly, when the bias voltage across the isolation structure reaches a certain range, the semiconductor material allows a portion of the current to flow through the isolation structure to the channel, shortening the current path and thus acting as a current shunting mechanism, thereby improving the operating current of the semiconductor structure.

[0046] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Figures 2 to 7 This is a cross-sectional schematic diagram of the semiconductor structure formation process in one embodiment of the present invention.

[0048] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 including adjacent first region I and second region II.

[0049] The substrate 200 may be made of silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the substrate 200 is made of silicon.

[0050] In this embodiment, the substrate 200 has a well region (not shown).

[0051] Depending on the type of semiconductor device to be formed, the conductivity type of the well region includes: N-type or P-type.

[0052] The method for forming the well region includes: doping the substrate 200 with N-type ions or P-type ions by ion implantation process to form the well region.

[0053] The N-type ion is one or more of phosphorus ions, arsenic ions, and antimony ions; the P-type ion is one or more of boron ions, indium ions, and gallium ions.

[0054] In this embodiment, the substrate 200 is a planar substrate.

[0055] In other embodiments, the substrate includes a substrate and fins located on a portion of the surface of the substrate.

[0056] Please continue to refer to this. Figure 2The first ion is implanted in the first region I and the second region II using the first ion implantation process, forming the initial drift region 201 in the first region I and the second region II.

[0057] The initial drift region 201 is used to subsequently form the drift region and the volume region. Specifically, the initial drift region 201 is located within the trap region.

[0058] The first ion includes N-type ions or P-type ions.

[0059] The semiconductor structure to be formed is an N-type LDMOS, and the first ion is an N-type ion, including one or more of phosphorus ions, arsenic ions, and antimony ions.

[0060] The semiconductor structure to be formed is a P-type LDMOS, and the first ion can also be a P-type ion, including one or more of boron ions, indium ions, and gallium ions.

[0061] Please refer to Figure 3 After the initial drift region 201 is formed, a groove 203 is formed in the first region I.

[0062] The groove 203 is used to subsequently form an isolation structure within the groove 203, and the isolation structure is used to improve the breakdown voltage of the semiconductor structure.

[0063] The method for forming the groove 203 includes: forming a patterned mask structure 202 on a first region I and a second region II, wherein the patterned mask structure 202 exposes a portion of the surface of the first region I; etching the first region I using the patterned mask structure 202 as a mask to form a groove 203 in the first region I.

[0064] The etching process for the first region I includes a dry etching process, which can form a groove 203 with good sidewall morphology and high dimensional accuracy.

[0065] The depth of the groove 203 is adjustable, thereby adjusting the depth of the isolation structure and the breakdown voltage of the semiconductor structure.

[0066] After the groove 203 is formed, the mask structure 202 is removed.

[0067] Please refer to Figure 4 An isolation structure 204 is formed within the groove 203, and the material of the isolation structure 204 includes a semiconductor material.

[0068] The isolation structure 204 is made of semiconductor material. On the one hand, the isolation structure 204 can block most of the current, thus preventing diffusion. On the other hand, when the bias voltage on both sides of the isolation structure 204 reaches a certain range, the semiconductor material of the isolation structure 204 can allow some current to flow through the isolation structure 204 to the channel, thus shortening the path of some current and thus playing a role in current shunting, thereby improving the operating current of the semiconductor structure.

[0069] The method of forming the isolation structure 204 includes: forming an isolation material layer (not shown) in the groove 203 and on the initial drift region 201; planarizing the isolation material layer until the surface of the initial drift region 201 is exposed, thereby forming the isolation structure 204.

[0070] In this embodiment, the isolation structure 204 is made of silicon carbide. The silicon carbide material has diffusion-blocking and conductivity properties, thereby improving the operating current of the semiconductor structure while providing isolation.

[0071] The process for forming the isolation material layer includes epitaxial growth or deposition processes.

[0072] In other embodiments, the material of the isolation structure further includes silicon carbide doped with a third ion; the conductivity type of the third ion is the same as that of the first ion, and the third ion includes phosphorus ions or boron ions. The phosphorus ions or boron ions can fine-tune the conductivity of the silicon carbide material.

[0073] In other embodiments, the concentration of the third ion is less than the concentration of the first ion. If the concentration of the third ion is greater than the concentration of the first ion, the material of the isolation structure is doped with too many third ions, which can easily generate tensile stress in the channel, making the semiconductor structure prone to leakage current.

[0074] In other embodiments, when forming the isolation material layer using the epitaxial growth process or deposition process, the process for forming the isolation material layer further includes: an in-situ doping process.

[0075] In another embodiment, the isolation structure includes a first isolation layer and a second isolation layer located on the first isolation layer.

[0076] Please refer to Figure 5 After forming the isolation structure 204, a gate structure 205 is formed on a portion of the initial drift region 201. The gate structure 205 extends from the surface of the second region II to the surface of the first region I. The gate structure 205 is located on part or all of the surface of the isolation structure 204.

[0077] The method for forming the gate structure 205 includes: forming a gate structure material layer (not shown) on a substrate 200; forming a patterned layer (not shown) on the gate structure material layer, wherein the patterned layer exposes a portion of the surface of the gate structure material layer; etching the gate structure material layer using the patterned layer as a mask until a portion of the surface of the first region I and a portion of the surface of the second region II are exposed, thereby forming the gate structure 205.

[0078] The gate structure 205 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0079] In this embodiment, the gate structure 205 further includes a protective layer (not shown in the figure) located on the top surface of the gate layer. The protective layer is used to protect the top surface of the gate layer, reduce the impact of subsequent processes on the gate layer, and help improve the performance of the formed semiconductor structure.

[0080] Please continue to refer to this. Figure 5 It also includes: forming a sidewall (not shown) on the sidewall of the gate structure 205.

[0081] The sidewall serves two purposes: firstly, it protects the sidewall surface of the gate structure 205 from the influence of subsequent processes, thereby maintaining its morphology and improving the stability of its electrical performance; secondly, it positions the source and drain regions that are subsequently formed.

[0082] The method for forming the sidewall includes: forming a sidewall material layer (not shown in the figure) on the surface of the substrate 200, the top surface of the gate structure 205, and the sidewall surface; and etching back the sidewall material layer until the surface of the substrate 200 and the top surface of the gate layer are exposed to form the sidewall.

[0083] The sidewall material includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the sidewall material includes silicon nitride.

[0084] Please refer to Figure 6 After forming the gate structure 205, the method further includes: forming a mask structure 206 on the substrate 200, the mask structure 206 exposing the surface of the second region II and the surface of the gate structure 205 located on the second region II; using the mask structure 206 as a mask, implanting a second ion in the second region II using a second ion implantation process, forming a body region 207 in the second region II, and causing the initial drift region 201 of the first region I to form a drift region 208, wherein the conductivity type of the second ion is opposite to that of the first ion.

[0085] The drift region 208 is used to separate the subsequently formed drain region and channel region, thereby extending the current path of the semiconductor structure and improving the breakdown voltage. The body region 207 is used to separate the subsequently formed source region and channel region.

[0086] The second ion includes N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, borofluorine ions or indium ions.

[0087] The first ion includes an N-type ion or a P-type ion, wherein the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion; the first ion includes an N-type ion or a P-type ion, wherein the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion.

[0088] Please refer to Figure 7 After forming the body region 207, the method further includes: forming a drain region 209 in the drift region 208 and forming a source region 210 in the body region 207, wherein the ionic conductivity type of the source region 210 and the drain region 209 is the same as the conductivity type of the first ion.

[0089] The method of forming a drain region 209 in the drift region 208 and a source region 210 in the body region 207 includes: using the sidewall and gate structure 205 as a mask, performing ion implantation on the body region 207 and the drift region 208 to form the source region 210 and the drain region 209.

[0090] The ions in the source region 210 and the drain region 209 include N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

[0091] Accordingly, the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 7 ,include:

[0092] Substrate 200, the substrate includes adjacent drift region 208 and body region 207, the drift region 208 contains a first ion, the body region 207 contains a second ion, the conductivity type of the second ion is opposite to that of the first ion;

[0093] The groove located in the drift region 208 and the isolation structure 204 located in the groove, wherein the material of the isolation structure 204 includes a semiconductor material;

[0094] A gate structure 205 is located on a portion of the substrate 200, the gate structure 205 extends from the surface of the body region 207 to the surface of the drift region 208, and the gate structure 205 is located on part or all of the surface of the isolation structure 204.

[0095] In this embodiment, the material of the isolation structure 204 includes silicon carbide.

[0096] In other embodiments, the material of the isolation structure further includes silicon carbide doped with a third ion; the conductivity type of the third ion is the same as that of the first ion.

[0097] In other embodiments, the concentration of the third ion is less than the concentration of the first ion.

[0098] In this embodiment, it also includes: a drain region 209 located in the drift region 208, and a source region 210 located in the body region 207, wherein the ionic conductivity type of the source region 210 and the drain region 209 is the same as the conductivity type of the first ion.

[0099] In this embodiment, the first ion includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion; the first ion includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion.

[0100] The semiconductor structure includes an isolation structure 204 within the drift region 208. The isolation structure 204 is made of a semiconductor material. The semiconductor material in the isolation structure 204 serves two purposes: firstly, it blocks most of the current, thus preventing diffusion; secondly, when the bias voltage across the isolation structure 204 reaches a certain range, the semiconductor material allows some current to flow through the isolation structure 204 to the channel, shortening the current path and thus shunting the current, thereby improving the operating current of the semiconductor structure.

[0101] Figure 8 and Figure 9 This is a cross-sectional schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0102] Please refer to Figure 8 , Figure 8 In order to be in Figure 3 The schematic diagram shows that an isolation structure is formed within the groove 203, and the material of the isolation structure includes semiconductor materials.

[0103] The isolation structure is made of semiconductor material. On the one hand, the isolation structure can block most of the current, thus preventing diffusion. On the other hand, when the bias voltage on both sides of the isolation structure reaches a certain range, the semiconductor material of the electrical isolation structure allows some current to flow through the isolation structure to the channel, shortening the path of some current and thus shunting the current, thereby improving the operating current of the semiconductor structure.

[0104] In this embodiment, the isolation structure includes a first isolation layer 301 located on the sidewall surface and bottom surface of the groove 203, and a second isolation layer 302 located on the first isolation layer 301.

[0105] The method of forming the isolation structure includes: forming a first isolation material layer (not shown) on the sidewall surface, bottom surface and initial drift region 201 of the groove 203; forming a second isolation material layer (not shown) on the first isolation material layer; planarizing the second isolation material layer and the first isolation material layer until the surface of the initial drift region 201 is exposed, thereby forming the isolation structure.

[0106] In this embodiment, the first isolation layer 301 is made of silicon carbide; the second isolation layer 302 is made of silicon germanium. The silicon germanium material has good conductivity, thereby increasing the conductivity of the isolation structure.

[0107] The process for forming the first isolation material layer includes an epitaxial growth process or a deposition process. The process for forming the second isolation material layer includes an epitaxial growth process or a deposition process.

[0108] In other embodiments, the material of the first insulating layer further includes silicon carbide doped with a third ion; the conductivity type of the third ion is the same as that of the first ion, and the third ion includes phosphorus ions or boron ions. The phosphorus ions or boron ions can fine-tune the conductivity of the silicon carbide material.

[0109] In other embodiments, the concentration of the third ion is less than the concentration of the first ion. If the concentration of the third ion is greater than the concentration of the first ion, the material of the isolation structure is doped with too many third ions, which can easily generate tensile stress in the channel, making the semiconductor structure prone to leakage current.

[0110] In other embodiments, when the first isolation material layer is formed using the epitaxial growth process or deposition process, the process for forming the first isolation material layer further includes: an in-situ doping process.

[0111] Please refer to Figure 9 Next, a gate structure 205 is formed on a portion of the initial drift region; a drift region 308 is formed in the first region I, and a body region 307 is formed in the second region II; a drain region 309 is formed in the drift region 308, and a source region 310 is formed in the body region 307. For the methods, processes, and materials used in forming the gate structure 205, drift region 308, body region 307, source region 310, and drain region 309, please refer to [reference needed]. Figures 5 to 7 This will not be elaborated upon here.

[0112] Accordingly, the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 9 ,include:

[0113] The substrate 200 includes adjacent drift regions 308 and body regions 307. The drift regions 308 contain first ions, and the body regions 307 contain second ions. The conductivity type of the second ions is opposite to that of the first ions.

[0114] A groove located within the drift region 308 and an isolation structure located within the groove, wherein the material of the isolation structure includes a semiconductor material;

[0115] A gate structure 305 is located on a portion of the substrate 200, the gate structure 305 extends from the surface of the body region 307 to the surface of the drift region 308, and the gate structure 305 is located on part or all of the isolation structure surface.

[0116] In this embodiment, the isolation structure includes: a first isolation layer 301 located on the sidewall surface and bottom surface of the groove, and a second isolation layer 302 located on the first isolation layer 301.

[0117] In this embodiment, the material of the first isolation layer 301 includes silicon carbide; the material of the second isolation layer 302 includes silicon germanium.

[0118] In other embodiments, the material of the first isolation layer further includes silicon carbide doped with a third ion; the conductivity type of the third ion is the same as that of the first ion, and the third ion includes phosphorus ions or boron ions.

[0119] In this embodiment, it also includes: a drain region 309 located in the drift region 308, and a source region 310 located in the body region 307, wherein the ionic conductivity type of the source region 310 and the drain region 309 is the same as the conductivity type of the first ion.

[0120] In this embodiment, the first ion includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion; the first ion includes an N-type ion or a P-type ion, the N-type ion includes a phosphorus ion or an arsenic ion, and the second ion includes a boron ion.

[0121] The semiconductor structure includes an isolation structure within the drift region, and the isolation structure is made of a semiconductor material. The semiconductor material serves two purposes: firstly, it blocks most of the current, thus preventing diffusion; secondly, when the bias voltage across the isolation structure reaches a certain range, the semiconductor material allows some current to flow through the isolation structure to the channel, shortening the current path and thus shunting the current, thereby improving the operating current of the semiconductor structure.

[0122] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, comprising: a substrate comprising an adjacent drift region and body region, the drift region having first ions therein, the body region having second ions therein, the second ions being of opposite conductivity type to the first ions; a recess in the drift region and an isolation structure in the recess, the isolation structure comprising a semiconductor material, a top surface of the isolation structure being flush with a top surface of the drift region, the isolation structure comprising a first isolation layer on sidewall surfaces and a bottom surface of the recess and a second isolation layer on the first isolation layer, the second isolation layer filling a portion of the recess other than the first isolation layer, a top surface of the second isolation layer being flush with the top surface of the drift region, the first isolation layer comprising silicon carbide, the second isolation layer comprising silicon germanium; a gate structure on a portion of the substrate, the gate structure extending from a surface of the body region to a surface of the drift region, the gate structure being on a portion or all of a surface of the isolation structure.

2. The semiconductor structure of claim 1, wherein, the isolation structure comprising silicon carbide doped with third ions, the third ions being of the same conductivity type as the first ions.

3. The semiconductor structure of claim 2, wherein, the third ions being at a lower concentration than the first ions.

4. The semiconductor structure of claim 1, wherein, the first isolation layer comprising silicon carbide doped with third ions, the third ions being of the same conductivity type as the first ions, the third ions comprising phosphorus ions or boron ions.

5. The semiconductor structure of claim 1, wherein, further comprising: a drain region in the drift region and a source region in the body region, the source and drain regions being of the same conductivity type as the first ions.

6. The semiconductor structure of claim 5, wherein, the first ions comprising N-type ions or P-type ions, the N-type ions comprising phosphorus ions or arsenic ions, the second ions comprising boron ions.

7. A method of forming a semiconductor structure, comprising: comprising: providing a substrate comprising an adjacent first region and second region; implanting first ions into the first region and second region using a first ion implantation process to form an initial drift region in the first region and second region; forming a recess in the first region after forming the initial drift region; forming an isolation structure in the recess, the isolation structure comprising a semiconductor material, a top surface of the isolation structure being flush with a top surface of the drift region, the isolation structure comprising a first isolation layer on sidewall surfaces and a bottom surface of the recess and a second isolation layer on the first isolation layer, the second isolation layer filling a portion of the recess other than the first isolation layer, a top surface of the second isolation layer being flush with the top surface of the drift region, the first isolation layer comprising silicon carbide, the second isolation layer comprising silicon germanium; forming a gate structure on a portion of the initial drift region after forming the isolation structure, the gate structure extending from a surface of the second region to a surface of the first region, the gate structure being on a portion or all of a surface of the isolation structure.

8. The method of forming a semiconductor structure of claim 7, wherein, a method of forming the isolation structure comprising: forming a layer of isolation material in the recess and on the initial drift region; planarising the layer of isolation material until a surface of the initial drift region is exposed to form the isolation structure.

9. The method of forming a semiconductor structure of claim 8, wherein, The material of the isolation structure comprises silicon carbide doped with third ions, the third ions have the same conductive type as the first ions, and the third ions comprise phosphorus ions or boron ions.

10. The method of forming a semiconductor structure of claim 9, wherein, The concentration of the third ions is less than the concentration of the first ions.

11. The method of forming a semiconductor structure of claim 8, wherein, The process of forming the isolation material layer comprises an epitaxial growth process or a deposition process.

12. The method of forming a semiconductor structure of claim 11, wherein, When the isolation material layer is formed by using the epitaxial growth process or the deposition process, the process of forming the isolation material layer further comprises an in-situ doping process.

13. The method of forming a semiconductor structure of claim 8, wherein, The isolation material layer comprises a first isolation material layer and a second isolation material layer on the first isolation material layer.

14. The method of forming a semiconductor structure of claim 7, wherein, The material of the first isolation layer further comprises silicon carbide doped with third ions, the third ions have the same conductive type as the first ions, and the third ions comprise phosphorus ions or boron ions.

15. The method of forming a semiconductor structure of claim 13, wherein, The process of forming the first isolation material layer comprises an epitaxial growth process or a deposition process.

16. The method of forming a semiconductor structure of claim 15, wherein, When the first isolation material layer is formed by using the epitaxial growth process or the deposition process, the process of forming the first isolation material layer further comprises an in-situ doping process.

17. The method of forming a semiconductor structure of claim 13, wherein, The process of forming the second isolation material layer comprises an epitaxial growth process or a deposition process.

18. The method of forming a semiconductor structure of claim 7, wherein, After the gate structure is formed, the method further comprises: forming a mask structure on the substrate, the mask structure exposes the surface of the second region and the surface of the gate structure on the second region; using the mask structure as a mask, a second ion implantation process is used to implant second ions into the second region to form a body region in the second region, and to form a drift region from the initial drift region of the first region, the conductive type of the second ions is opposite to that of the first ions.

19. The method of forming a semiconductor structure of claim 18, wherein, After the body region is formed, the method further comprises: forming a drain region in the drift region and a source region in the body region, the ion conductive type of the source region and the drain region is the same as that of the first ions.

20. The method of forming a semiconductor structure of claim 18, wherein, The first ions comprise N-type ions or P-type ions, the N-type ions comprise phosphorus ions or arsenic ions, and the second ions comprise boron ions.

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