Reverse-polarity red light-emitting diode chip and its manufacturing method

Abstract

The present disclosure provides an anti-polarity red light emitting diode chip and a preparation method thereof, belonging to the technical field of optoelectronic manufacturing. The anti-polarity red light emitting diode chip includes a substrate, a first semiconductor layer, a light emitting layer, a second semiconductor layer, an ohmic contact layer, and a transparent conductive layer stacked in sequence. An ohmic contact is formed between the ohmic contact layer and the transparent conductive layer. The surface of the ohmic contact layer away from the second semiconductor layer is roughened, and the thickness of the transparent conductive layer is not less than the roughening depth of the ohmic contact layer. The embodiments of the present disclosure can improve the light extraction effect of the chip and reduce the manufacturing cost.

Description

Technical Field

[0001] The present disclosure relates to the technical field of optoelectronic manufacturing, and particularly to an inverted-polarity red light-emitting diode chip and a preparation method thereof. Background Art

[0002] As a highly influential new product in the optoelectronic industry, a light-emitting diode (LED for short) has the characteristics of small size, long service life, rich and colorful colors, low energy consumption, etc., and is widely used in the fields of lighting, display screens, signal lights, backlights, toys, etc. The core structure of an LED is a light-emitting diode chip, and the fabrication of the light-emitting diode chip has a great influence on the optoelectronic properties of the LED.

[0003] An inverted-polarity red light-emitting diode chip generally includes a Si substrate, an Omni-Directional Reflector (ODR) layer, a p-type layer, a light-emitting layer, and an n-type layer stacked in sequence. An ohmic contact layer is usually provided in a region where an n electrode is to be formed on the n-type layer, and the n electrode is formed on the ohmic contact layer so that the n electrode can be electrically connected to the n-type layer. And roughening treatment is performed on the region around the n electrode on the n-type layer to break the total reflection on the surface of the n-type layer and improve the light extraction efficiency.

[0004] However, roughening treatment is only performed on the region around the ohmic contact layer on the n-type layer, and the improvement effect of light extraction is limited; if the ohmic contact layer is also roughened, the electrical connection between the ohmic contact layer and the n electrode will be affected, and the ohmic contact layer needs to have a sufficient thickness to meet the roughening treatment, which will increase the manufacturing cost of the chip. Summary of the Invention

[0005] Embodiments of the present disclosure provide an inverted-polarity red light-emitting diode chip and a preparation method thereof, which can improve the light extraction effect of the chip, satisfy the electrical connection between the ohmic contact layer and the electrode, and reduce the materials used in fabricating the ohmic contact layer to reduce the manufacturing cost. The technical solutions are as follows:

[0006] On the one hand, embodiments of the present disclosure provide an inverted-polarity red light-emitting diode chip, which includes a substrate, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, an ohmic contact layer, and a transparent conductive layer stacked in sequence. An ohmic contact is formed between the ohmic contact layer and the transparent conductive layer, the surface of the ohmic contact layer away from the second semiconductor layer is roughened, and the thickness of the transparent conductive layer is not less than the roughening depth of the ohmic contact layer.

[0007] Optionally, the ohmic contact layer is an n-type AlGaInP layer, and the transparent conductive layer is an indium tin oxide film layer; in the ohmic contact layer, the content of Al component is 10% to 30%, and the Si doping concentration is not less than 8E18 / cm 3 .

[0008] Optionally, the thickness of the ohmic contact layer is 0.1 μm to 0.2 μm, and the roughening depth is 0.2 μm to 1 μm; the thickness of the transparent conductive layer is 200 nm to 300 nm.

[0009] Optionally, the second semiconductor layer includes an n-type AlGaInP current spreading layer and an n-type AlGaInP roughening layer that are sequentially stacked on the light-emitting layer; in the n-type AlGaInP current spreading layer, the content of Al component is 20% to 40%, and the Si doping concentration is not less than 5E18 / cm 3 ; in the n-type AlGaInP roughening layer, the content of Al component is 50% to 65%, and the Si doping concentration is not less than 5E18 / cm 3 .

[0010] Optionally, a total internal reflection mirror layer is further provided between the substrate and the first semiconductor layer. The total internal reflection mirror layer includes an AZO layer and a plurality of MgF2 blocks. The plurality of MgF2 blocks are arranged in an array on the surface of the first semiconductor layer away from the second semiconductor layer. The AZO layer is located on the surface of the first semiconductor layer and covers the plurality of MgF2 blocks. In the direction perpendicular to the substrate, the thickness of the AZO layer is not less than the thickness of the MgF2 blocks.

[0011] Optionally, the roughness Ra of the AZO layer < 0.7 nm.

[0012] Optionally, the film layer of the first semiconductor layer connected to the total internal reflection mirror layer is a p-type GaP ohmic contact layer. In the p-type GaP ohmic contact layer, the C doping concentration is not less than 6E19 / cm 3 .

[0013] Optionally, the reverse-polarity red light-emitting diode further includes a first bonding layer and a second bonding layer. The first bonding layer and the second bonding layer are sequentially stacked on the surface of the substrate; the first bonding layer includes a Ti layer, a Pt layer, an Au layer, and an In layer that are sequentially stacked on the surface of the substrate, and the second bonding layer includes an In layer, an Au layer, a Ti layer, a Pt layer, a Ti layer, and an Au layer that are sequentially stacked on the surface of the first bonding layer.

[0014] On the other hand, an embodiment of the present disclosure also provides a method for manufacturing an anti-polarity red light emitting diode chip, the manufacturing method comprising: providing a substrate; sequentially forming a first semiconductor layer, a light emitting layer, and a second semiconductor layer on the substrate; sequentially forming an ohmic contact layer and a transparent conductive layer on a surface of the second semiconductor layer away from the light emitting layer, an ohmic contact being formed between the ohmic contact layer and the transparent conductive layer, a surface of the ohmic contact layer away from the second semiconductor layer being roughened, and a thickness of the transparent conductive layer being not less than a roughening depth of the ohmic contact layer.

[0015] Optionally, sequentially forming the ohmic contact layer and the transparent conductive layer on the surface of the second semiconductor layer away from the light emitting layer includes: forming an n-type AlGaInP layer on the surface of the second semiconductor layer; roughening the n-type AlGaInP layer to form the ohmic contact layer; depositing an indium tin oxide film layer on the ohmic contact layer to form the transparent conductive layer.

[0016] The beneficial effects brought by the technical solution provided by the embodiment of the present disclosure at least include:

[0017] The anti-polarity red light emitting diode chip provided by the embodiment of the present disclosure includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer sequentially stacked on a substrate. Among them, an ohmic contact layer and a transparent conductive layer are further sequentially stacked on a surface of the second semiconductor layer, an ohmic contact is formed between the ohmic contact layer and the transparent conductive layer, a surface of the ohmic contact layer away from the second semiconductor layer is roughened, and a thickness of the transparent conductive layer is not less than a roughening depth of the ohmic contact layer to wrap the ohmic contact layer therein.

[0018] Compared with the related art, by covering the entire surface of the ohmic contact layer on the second semiconductor layer and directly roughening the entire surface of the ohmic contact layer, the surface energy of the roughened ohmic contact layer can destroy the total reflection at the ohmic contact layer, and the roughening depth exceeds the thickness of the ohmic contact layer, which is equivalent to roughening the entire surface of the second semiconductor layer, effectively improving the light extraction effect. A transparent conductive layer is covered on the ohmic contact layer to fill the pores between the ohmic contact layers to connect the respective ohmic contact layers to ensure that the ohmic contact layer has the function of ohmic contact. This not only satisfies the electrical connection between the ohmic contact layer and the electrode, but also can minimize the material used in manufacturing the ohmic contact layer to reduce the manufacturing cost of the chip. Description of the Drawings

[0019] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0020] Figure 1 is a schematic structural diagram of an anti-polarity red light-emitting diode chip provided by an embodiment of the present disclosure;

[0021] Figure 2 is a top view of the anti-polarity red light-emitting diode chip provided by an embodiment of the present disclosure;

[0022] Figure 3 is a flowchart of a preparation method of an anti-polarity red light-emitting diode chip provided by an embodiment of the present disclosure;

[0023] Figure 4 is a preparation state diagram of an anti-polarity red light-emitting diode chip provided by an embodiment of the present disclosure;

[0024] Figure 5 is a preparation state diagram of an anti-polarity red light-emitting diode chip provided by an embodiment of the present disclosure.

[0025] The descriptions of the marks in the figure are as follows:

[0026] 11. Substrate; 12. GaAs substrate

[0027] 21. First semiconductor layer; 211. p-type GaP ohmic contact layer; 212. p-type GaP current spreading layer; 213. p-type AlInP confinement layer; 22. Light-emitting layer; 23. Second semiconductor layer; 231. n-type AlGaInP current spreading layer; 232. n-type AlGaInP roughened layer; 233. n-type AlInP confinement layer; 24. Groove; 25. First AlGaInP waveguide layer; 26. Second AlGaInP waveguide layer;

[0028] 31. Transparent conductive layer; 32. Ohmic contact layer;

[0029] 41. AZO layer; 42. MgF 2 block; 43. First bonding layer; 44. Second bonding layer;

[0030] 51. First electrode; 52. Second electrode;

[0031] 61. Metal layer; 62. Protective layer. Detailed implementation manners

[0032] To make the objectives, technical solutions, and advantages of the present disclosure more clear, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0033] Figure 1 It is a schematic structural diagram of an anti-polarity red light-emitting diode chip provided by an embodiment of the present disclosure. As Figure 1 shown, the anti-polarity red light-emitting diode chip includes a substrate 11, a first semiconductor layer 21, a light-emitting layer 22, a second semiconductor layer 23, an ohmic contact layer 32, and a transparent conductive layer 31 that are stacked in sequence. An ohmic contact is formed between the ohmic contact layer 32 and the transparent conductive layer 31. The surface of the ohmic contact layer 32 away from the second semiconductor layer 23 is roughened, and the thickness of the transparent conductive layer 31 is not less than the roughening depth of the ohmic contact layer 32.

[0034] The anti-polarity red light-emitting diode chip provided by an embodiment of the present disclosure includes a first semiconductor layer 21, a light-emitting layer 22, and a second semiconductor layer 23 that are stacked in sequence on the substrate 11. Among them, an ohmic contact layer 32 and a transparent conductive layer 31 are further stacked in sequence on the surface of the second semiconductor layer 23. An ohmic contact is formed between the ohmic contact layer 32 and the transparent conductive layer 31. The surface of the ohmic contact layer 32 away from the second semiconductor layer 23 is roughened, and the thickness of the transparent conductive layer 31 is not less than the roughening depth of the ohmic contact layer 32 to wrap the ohmic contact layer 32 therein.

[0035] Compared with the related art, by covering the entire surface of the ohmic contact layer on the second semiconductor layer 23 and directly roughening the entire surface of the ohmic contact layer, the surface energy of the roughened ohmic contact layer 32 can destroy the total reflection at the ohmic contact layer, and the roughening depth exceeds the thickness of the ohmic contact layer 32, which is equivalent to roughening the entire surface of the second semiconductor layer 23, effectively improving the light extraction effect. A transparent conductive layer 31 is covered on the ohmic contact layer 32 to fill the pores between the ohmic contact layers 32 to connect the respective ohmic contact layers 32 to ensure that the ohmic contact layer 32 has the function of ohmic contact. This not only satisfies the electrical connection between the ohmic contact layer 32 and the electrode, but also can minimize the materials used in making the ohmic contact layer to reduce the manufacturing cost of the chip.

[0036] In the embodiments of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 may be an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0037] As an example, the first semiconductor layer 21 is a p-type layer, and the second semiconductor layer 23 is an n-type layer.

[0038] Optionally, the ohmic contact layer 32 is an n-type AlGaInP layer, and the transparent conductive layer 31 is an indium tin oxide (ITO) film layer.

[0039] Among them, in the ohmic contact layer 32, the content of the Al component is 10% to 30%, and the Si doping concentration is not less than 8E18 / cm 3 .

[0040] Among them, the indium tin oxide film layer has good transmittance and low resistivity, which is convenient for carrier conduction and improves the injection efficiency.

[0041] In the embodiment of the present disclosure, by setting the manufacturing material of the ohmic contact layer 32 as an n-type AlGaInP, setting the content of the Al component to a lower content, and setting the Si doping concentration to be greater than 8E18 / cm 3 concentration, it is beneficial to form a good ohmic contact between the indium tin oxide film layer and the ohmic contact layer 32.

[0042] As an example, in the ohmic contact layer 32, the content of the Al component is 20%, and the Si doping concentration is 8E18 / cm 3 .

[0043] Exemplarily, the thickness of the ohmic contact layer 32 is 0.1 μm to 0.2 μm, the roughening depth is 0.2 μm to 1 μm, and the thickness of the transparent conductive layer 31 is 200 nm to 300 nm.

[0044] If the thickness of the ohmic contact layer 32 is set too small, it is not conducive to forming a good ohmic contact between the transparent conductive layer 31 and the ohmic contact layer 32, and it affects the effect of the ohmic contact layer 32 destroying the total reflection at the ohmic contact, which is not conducive to improving the light extraction effect; if the thickness of the ohmic contact layer 32 is set too large, it will result in more materials being used during manufacturing, increasing the manufacturing cost of the chip.

[0045] If the thickness of the transparent conductive layer 31 is set too small, the margin is not enough to meet the requirement of polishing the transparent conductive layer 31 flat in subsequent steps; if the thickness of the transparent conductive layer 31 is set too large, it will result in more materials being used during manufacturing, increasing the manufacturing cost of the chip.

[0046] As an example, in the embodiment of the present disclosure, the thickness of the ohmic contact layer 32 is 0.15 μm, and the thickness of the transparent conductive layer 31 is 250 nm.

[0047] Among them, the roughening depth refers to the distance between the surface where roughening starts from the ohmic contact layer and the surface where roughening is completed. That is, when the roughening depth exceeds the thickness of the ohmic contact layer, the second semiconductor layer located below the ohmic contact layer will also be roughened.

[0048] In the embodiments of the present disclosure, the roughness Ra of the transparent conductive layer 31 is less than 3 nm. Polishing the transparent conductive layer 31 flat is beneficial to forming an electrode on the transparent conductive layer 31 in subsequent processes.

[0049] Optionally, as Figure 1 shown, the second semiconductor layer 23 includes an n-type AlGaInP current spreading layer 231 and an n-type AlGaInP roughening layer 232 that are sequentially stacked on the light-emitting layer 22.

[0050] Among them, in the n-type AlGaInP current spreading layer 231, the content of the Al component is 20% to 40%, and the Si doping concentration is not less than 5E18 / cm3.

[0051] By setting the content of the Al component in the n-type AlGaInP current spreading layer 231 to a lower content and setting the Si doping concentration to be greater than 5E18 / cm 3 concentration, it is beneficial to current spreading.

[0052] As an example, in the n-type AlGaInP current spreading layer 231, the content of the Al component is 30%, and the Si doping concentration is 5E18 / cm 3 .

[0053] Exemplarily, the thickness of the n-type AlGaInP current spreading layer 231 is 1 μm to 2 μm.

[0054] If the thickness of the n-type AlGaInP current spreading layer 231 is set too small, it is not conducive to improving the effect of current spreading; if the thickness of the n-type AlGaInP current spreading layer 231 is set too large, it will result in more materials being used in production, increasing the manufacturing cost of the chip.

[0055] Among them, in the n-type AlGaInP roughening layer 232, the content of the Al component is 50% to 65%. By setting the content of the Al component in the n-type AlGaInP roughening layer 232 to a higher content, in this way, in the direction from the n-type AlGaInP current spreading layer 231 to the ohmic contact layer 32, the content of the Al component first increases and then decreases, which can increase the change range of the Al component in the second semiconductor layer 23 to improve the light-emitting efficiency.

[0056] As an example, in the n-type AlGaInP roughening layer 232, the content of the Al component is 60%.

[0057] Exemplarily, the thickness of the n-type AlGaInP roughening layer 232 is 1 μm to 2 μm.

[0058] If the thickness of the n-type AlGaInP roughened layer 232 is set too small, it is not conducive to forming a large change range of the Al component in the second semiconductor layer 23; if the thickness of the n-type AlGaInP roughened layer 232 is set too large, it will result in the use of more materials during fabrication, increasing the chip fabrication cost.

[0059] Optionally, the second semiconductor layer 23 further includes an n-type AlInP confinement layer 233. The n-type AlInP confinement layer 233, the n-type AlGaInP current spreading layer 231, and the n-type AlGaInP roughened layer 232 are sequentially stacked on the surface of the light-emitting layer 22.

[0060] Exemplarily, the thickness of the n-type AlInP confinement layer 233 is 0.2 μm to 0.5 μm.

[0061] Optionally, the light-emitting layer 22 may include 3 to 8 Al x Ga 1-x N quantum well layers and Al y Ga 1-y N quantum barrier layers, where 0 < x < y < 1. That is, the light-emitting layer 22 includes 3 to 8 alternating periods of Al x Ga 1-x N quantum well layers and Al y Ga 1-y N quantum barrier layers.

[0062] As an example, in the embodiment of the present disclosure, the light-emitting layer 22 includes 5 alternating periods of Al x Ga 1-x N quantum well layers and Al y Ga 1-y N quantum barrier layers.

[0063] Optionally, the thickness of the light-emitting layer 22 can be 150 nm to 200 nm.

[0064] Waveguide layers are respectively provided on two opposite surfaces of the light-emitting layer 22. By providing the waveguide layers, the refractive index can be increased to improve the light extraction effect of the light-emitting diode.

[0065] Among them, the first AlGaInP waveguide layer 25 is located on the first semiconductor layer 21, and the second AlGaInP waveguide layer 26 is located on the light-emitting layer 22.

[0066] Exemplarily, the thickness of the first AlGaInP waveguide layer 25 can be 50 nm to 90 nm. The thickness of the second AlGaInP waveguide layer 26 can be 50 nm to 90 nm.

[0067] In an embodiment of the present disclosure, the first semiconductor layer 21 includes a p-type GaP ohmic contact layer 211, a p-type GaP current spreading layer 212, and a p-type AlInP confinement layer 213 that are sequentially stacked on the substrate 11.

[0068] Exemplarily, the thickness of the p-type AlInP confinement layer 213 can be 200 nm to 300 nm; the thickness of the p-type GaP ohmic contact layer 211 can be 200 nm to 400 nm; the thickness of the p-type GaP current spreading layer 212 is 1 μm to 2 μm.

[0069] Optionally, as Figure 1 shown, a total internal reflection mirror layer is further provided between the substrate 11 and the first semiconductor layer 21. The total internal reflection mirror layer includes an AZO layer 41 and a plurality of MgF 2 blocks 42. The plurality of MgF 2 blocks 42 are arranged in an array on the surface of the first semiconductor layer 21 away from the second semiconductor layer 23. The AZO layer 41 is located on the surface of the first semiconductor layer 21 and covers the plurality of MgF 2 blocks 42. In the direction perpendicular to the substrate 11, the thickness of the AZO layer 41 is not less than the thickness of the MgF 2 blocks 42.

[0070] By providing the AZO layer 41 and the plurality of MgF 2 blocks 42 on the surface of the first semiconductor layer 21 to form a total internal reflection mirror with a composite refractive index, a primary total reflection layer is formed, which can greatly improve the primary reflectivity, reflect the light emitted by the epitaxial layer to the side where the second semiconductor layer 23 is located, and improve the light extraction effect of the chip.

[0071] Optionally, the roughness Ra of the AZO layer 41 < 0.7 nm. In this way, the formed total internal reflection mirror has a high flatness and a good reflection effect.

[0072] Optionally, the film layer in the first semiconductor layer 21 connected to the total internal reflection mirror layer is the p-type GaP ohmic contact layer 211. In the p-type GaP ohmic contact layer 211, the C doping concentration is not less than 6E19 / cm 3 .

[0073] By setting the C doping concentration of the p-type GaP ohmic contact layer 211 to be greater than 6E19 / cm 3 a good ohmic contact can be formed between the first semiconductor layer 21 and the AZO layer.

[0074] Optionally, as Figure 1 shown, the reverse-polarity red light-emitting diode further includes a first bonding layer 43 and a second bonding layer 44. The first bonding layer 43 and the second bonding layer 44 are sequentially stacked on the surface of the substrate 11.

[0075] Among them, the first bonding layer 43 includes a Ti layer, a Pt layer, an Au layer, and an In layer stacked in sequence on the surface of the substrate 11, and the second bonding layer 44 includes an In layer, an Au layer, a Ti layer, a Pt layer, a Ti layer, and an Au layer stacked in sequence on the surface of the first bonding layer 43.

[0076] In the embodiment of the present disclosure, the In layer of the first bonding layer 43 and the In layer of the second bonding layer 44 are bonded together. By utilizing the good bonding performance of In, the bonding stability between the first bonding layer 43 and the second bonding layer 44 can be improved.

[0077] An Au layer and a Pt layer are also provided in the first bonding layer 43 and the second bonding layer 44, which can reflect a small amount of light passing through the omnidirectional reflector, so that most of the light is reflected back to the light-emitting surface, improving the light-emitting effect of the chip. Among them, the Ti layer in the first bonding layer 43 and the second bonding layer 44 can improve the strength of the bonding layer, enabling the substrate 11 and the epitaxial layer to be bonded together more stably.

[0078] Optionally, as Figure 1 shown, the reverse-polarity red light-emitting diode chip further includes a first electrode 51 and a second electrode 52.

[0079] As Figure 1 shown, a groove 24 exposing the p-type GaP ohmic contact layer 211 in the first semiconductor layer 21 is further provided on the surface of the transparent conductive layer 31. The first electrode 51 is located in the groove 24 and is connected to the p-type GaP ohmic contact layer 211, enabling electrical connection between the first electrode 51 and the first semiconductor layer 21.

[0080] As Figure 1 shown, the second electrode 52 is located on the surface of the transparent conductive layer 31, and the second electrode 52 is connected to the transparent conductive layer 31 of the transparent conductive layer 31 to achieve electrical connection with the second semiconductor layer 23 through the transparent conductive layer 31 and the ohmic contact layer 32.

[0081] Among them, the first electrode 51 is a p-type electrode, and the second electrode 52 is an n-type electrode.

[0082] Exemplarily, as Figure 1 shown, the first electrode 51 can be an electrode layer covering the entire substrate 11, increasing the area of the electrode and improving the current injection efficiency.

[0083] Figure 2 is a top view of the reverse-polarity red light-emitting diode chip provided by the embodiment of the present disclosure. As Figure 1 、 2 shown, the second electrode 52 is in a block shape, and the second electrode 52 is located in the middle of the transparent conductive layer 31. The second electrode 52 is circular, avoiding the second electrode 52 having an overly large size design that blocks the light emission and affecting the light output effect.

[0084] Optionally, both the first electrode and the second electrode 52 each include a Ti layer, an Al layer, a Ti layer, an Al layer, a Ti layer, a Pt layer, a Ni layer, a Sn layer, and an Au layer that are sequentially stacked.

[0085] Among them, the thickness of the Ti layer in the first electrode 51 and the second electrode 52 is 50 nm to 150 nm, the thickness of the Al layer is 200 nm to 500 nm, the thickness of the Ti layer is 50 nm to 150 nm, the thickness of the Al layer is 200 nm to 500 nm, the thickness of the Ti layer is 50 nm to 150 nm, the thickness of the Pt layer is 200 nm to 500 nm, the thickness of the Ni layer is 300 nm to 700 nm, the thickness of the Sn layer is 5 μm to 10 μm, and the thickness of the Au layer is 5 nm to 15 nm.

[0086] As an example, the thickness of the Ti layer in the first electrode 51 and the second electrode 52 is 100 nm, the thickness of the Al layer is 300 nm, the thickness of the Ti layer is 100 nm, the thickness of the Al layer is 300 nm, the thickness of the Ti layer is 100 nm, the thickness of the Pt layer is 300 nm, the thickness of the Ni layer is 500 nm, the thickness of the Sn layer is 8 μm, and the thickness of the Au layer is 10 nm.

[0087] Optionally, as Figure 1 shown, a metal layer 61 is further provided on the surface of the substrate 11 away from the first semiconductor layer 21. The metal layer 61 can be a Ti layer or an Au layer to further enhance the reflection effect.

[0088] Optionally, as Figure 1 shown, a protective layer 62 is further provided on the transparent conductive layer 31. The protective layer 62 has through holes exposing partial regions of the transparent conductive layer 31 and the second electrode 52, and the protective layer 62 extends into the groove 24 and covers the p-type GaP ohmic contact layer 211.

[0089] Exemplarily, the protective layer 62 can be a Si 3 N 4 layer.

[0090] Figure 3 is a flowchart of a method for manufacturing an inverted-polarity red light-emitting diode chip provided by an embodiment of the present disclosure. As Figure 3 shown, the manufacturing method includes:

[0091] Step 101: Provide a substrate 11.

[0092] Step 102: Sequentially form a first semiconductor layer 21, a light-emitting layer 22, and a second semiconductor layer 23 on the substrate 11.

[0093] Step 103: An ohmic contact layer 32 and a transparent conductive layer 31 are sequentially formed on the surface of the second semiconductor layer 23 away from the light-emitting layer 22.

[0094] An ohmic contact is formed between the ohmic contact layer 32 and the transparent conductive layer 31. The surface of the ohmic contact layer 32 away from the second semiconductor layer 23 is roughened, and the thickness of the transparent conductive layer 31 is not less than the roughening depth of the ohmic contact layer 32.

[0095] The chip prepared by the preparation method provided by the embodiment of the present disclosure includes a first semiconductor layer 21, a light-emitting layer 22, and a second semiconductor layer 23 sequentially stacked on a substrate 11. Among them, an ohmic contact layer 32 and a transparent conductive layer 31 are further sequentially stacked on the surface of the second semiconductor layer 23. An ohmic contact is formed between the ohmic contact layer 32 and the transparent conductive layer 31. The surface of the ohmic contact layer 32 away from the second semiconductor layer 23 is roughened, and the thickness of the transparent conductive layer 31 is not less than the roughening depth of the ohmic contact layer 32 to wrap the ohmic contact layer 32 therein.

[0096] Compared with the related art, by covering the entire surface of the second semiconductor layer 23 with the ohmic contact layer and directly roughening the entire surface of the ohmic contact layer, the surface energy of the roughened ohmic contact layer 32 can destroy the total reflection at the ohmic contact layer, and the roughening depth exceeds the thickness of the ohmic contact layer 32, which is equivalent to roughening the entire surface of the second semiconductor layer 23, effectively improving the light extraction effect. Covering the transparent conductive layer 31 on the ohmic contact layer 32 to fill the pores between the ohmic contact layers 32 to connect the ohmic contact layers 32 to ensure that the ohmic contact layer 32 has the function of ohmic contact. This not only satisfies the electrical connection between the ohmic contact layer 32 and the electrode, but also can minimize the materials used in making the ohmic contact layer to reduce the manufacturing cost of the chip.

[0097] In step 101, the substrate 11 can be a flat substrate 11 or a patterned substrate 11. Exemplarily, the substrate 11 is a GaAs substrate 12.

[0098] Figure 4 It is a preparation state diagram of an inverted-polarity red light-emitting diode chip provided by an embodiment of the present disclosure. As Figure 4As shown, in step 102, the process of forming the first semiconductor layer 21, the light-emitting layer 22, and the second semiconductor layer 23 includes: successively growing an etch stop layer, an n-type AlGaInP ohmic contact layer, an n-type AlGaInP roughening layer 232, an n-type AlGaInP current spreading layer 231, an n-type AlInP confinement layer 233, a second AlGaInP waveguide layer 26, the light-emitting layer 22, a first AlGaInP waveguide layer 25, a p-type AlInP confinement layer 213, a p-type GaP current spreading layer 212, and a p-type GaP ohmic contact layer 211 on the GaAs substrate 12.

[0099] Before step 103, it further includes forming an omnidirectional reflector layer on the surface of the p-type GaP ohmic contact layer 211.

[0100] As Figure 4 shown, specifically, it may include: coating a photoresist layer on the p-type GaP ohmic contact layer 211, etching the photoresist layer, forming a hole-like arrangement pattern on the photoresist layer, and depositing MgF 2 by electron beam evaporation to form an array-arranged MgF 2 block 42. After removing the photoresist layer, depositing an AZO layer 41 on the array-arranged MgF 2 block 42 to connect the AZO layer 41 with the p-type GaP ohmic contact layer 211 to form an ohmic contact.

[0101] Among them, after forming the AZO layer 41, chemical mechanical polishing can be used to polish the surface of the AZO layer 41 flat so that the surface roughness Ra value of the AZO layer 41 is < 0.7 nm.

[0102] In the embodiment of the present disclosure, after forming the omnidirectional reflector layer, it may further include bonding the epitaxial structure to the Si substrate 11.

[0103] As Figure 5 shown, specifically, it may include: successively depositing an Au layer, a Ti layer, a Pt layer, a Ti layer Au layer, and an In layer on the surface of the AZO layer 41 as the second bonding layer 44. Then, providing a Si substrate 11 and successively depositing a Ti layer, a Pt layer, an Au layer, and an In layer on the surface of the Si substrate 11 as the first bonding layer 43. During bonding, the In layers in the first bonding layer 43 and the second bonding layer 44 are bonded together, and the GaAs substrate 12 and the etch stop layer are removed by wet chemical etching.

[0104] As Figure 1 shown, forming the ohmic contact layer 32 and the transparent conductive layer 31 on the second semiconductor layer 23 in step 103 may include the following steps:

[0105] First step, forming an n-type AlGaInP layer on the surface of the second semiconductor layer 23.

[0106] Among them, the n-type AlGaInP layer entirely covers the surface of the second semiconductor layer 23, and the thickness of the n-type AlGaInP layer can be 0.1 μm to 0.2 μm.

[0107] In the second step, the n-type AlGaInP layer is roughened to form an ohmic contact layer.

[0108] Among them, the roughening depth is not less than the thickness of the n-type AlGaInP layer.

[0109] The n-type AlGaInP layer is roughened using a roughening solution to form pores on the n-type AlGaInP layer, and the roughening depth can be 0.2 μm to 1 μm to ensure complete roughening of the n-type AlGaInP layer.

[0110] In the third step, an indium tin oxide film layer is deposited on the ohmic contact layer 32 to form a transparent conductive layer.

[0111] Among them, the transparent conductive layer 31 extends to the surface of the second semiconductor layer 23.

[0112] An ITO layer is deposited by rapid plasma deposition (RPD) method, so that an ohmic contact is formed between the ohmic contact layer 32 and the ITO layer, and the surface of the ITO layer is polished flat by chemical mechanical polishing, and the surface roughness Ra value of the ITO layer < 3 nm.

[0113] As Figure 1 shown, after forming the transparent conductive layer, it may further include: forming a pattern of electrode bonding wires on the ITO layer by photolithography, evaporating Ti layer, Al layer, Ti layer, Al layer, Ti layer, Pt layer, Ni layer, Sn layer and Au layer as the second electrode 52; defining the light-emitting region by photolithography, etching away the ITO layer by wet etching, and then dry etching to the p-type GaP ohmic contact layer 211 by inductively coupled plasma (ICP); depositing a protective layer 62 on the surface of the transparent conductive layer 31, forming an electrode hole on the protective layer 62 by photolithography, and evaporating Ti layer, Al layer, Ti layer, Al layer, Ti layer, Pt layer, Ni layer, Sn layer and Au layer in the electrode hole as the first electrode 51; finally, thinning the chip, depositing a metal layer 61 on the surface of the Si substrate 11, and separating the chip by laser cutting to obtain a reverse-polarity red light-emitting diode chip with the designed size.

[0114] The above are only optional embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An anti-polarity red light emitting diode chip, characterized in that, the anti-polarity red light emitting diode chip includes a substrate (11), a first semiconductor layer (21), a light emitting layer (22), a second semiconductor layer (23), an ohmic contact layer (32) and a transparent conductive layer (31) stacked in sequence. An ohmic contact is formed between the ohmic contact layer (32) and the transparent conductive layer (31). The surface of the ohmic contact layer (32) away from the second semiconductor layer (23) is roughened. The thickness of the transparent conductive layer (31) is not less than the roughening depth of the ohmic contact layer (32); the ohmic contact layer (32) is an n-type AlGaInP layer. The second semiconductor layer (23) includes an n-type AlGaInP current spreading layer (231) and an n-type AlGaInP roughening layer (232) stacked in sequence on the light emitting layer (22). The Al component content of the n-type AlGaInP roughening layer (232) is greater than the Al component content of the n-type AlGaInP layer, and the Al component content of the n-type AlGaInP roughening layer (232) is greater than the Al component content of the n-type AlGaInP current spreading layer (231).

2. The anti-polarity red light emitting diode chip according to claim 1, characterized in that, the transparent conductive layer (31) is an indium tin oxide film layer; In the ohmic contact layer (32), the content of the Al component is 10% to 30%, and the Si doping concentration is not less than 8E18 / cm 3 .

3. The anti-polarity red light emitting diode chip according to claim 2, characterized in that, the thickness of the ohmic contact layer (32) is 0.1 μm to 0.2 μm, and the roughening depth is 0.2 μm to 1 μm; the thickness of the transparent conductive layer (31) is 200 nm to 300 nm.

4. The anti-polarity red light emitting diode chip according to any one of claims 1 to 3, characterized in that, In the n-type AlGaInP current spreading layer (231), the content of the Al component is 20% to 40%, and the Si doping concentration is not less than 5E18 / cm 3 ; In the n-type AlGaInP roughened layer (232), the content of the Al component is 50% to 65%, and the Si doping concentration is not less than 5E18 / cm 3 .

5. The anti-polarity red light emitting diode chip according to any one of claims 1 to 3, characterized in that, An omnidirectional reflector layer is further provided between the substrate (11) and the first semiconductor layer (21). The omnidirectional reflector layer includes an AZO layer (41) and a plurality of MgF 2 blocks (42). The plurality of MgF 2 blocks (42) are arranged in an array on the surface of the first semiconductor layer (21) away from the second semiconductor layer (23). The AZO layer (41) is located on the surface of the first semiconductor layer (21) and covers the plurality of MgF 2 blocks (42). In a direction perpendicular to the substrate (11), the thickness of the AZO layer (41) is not less than the thickness of the MgF 2 blocks (42).

6. For the anti-polarity red light emitting diode chip according to claim 5, the roughness Ra of the AZO layer (41) < 0.7 nm.

7. The anti-polarity red light emitting diode chip according to claim 5, characterized in that, The film layer in the first semiconductor layer (21) connected to the omnidirectional reflector layer is a p-type GaP ohmic contact layer (211). In the p-type GaP ohmic contact layer (211), the C doping concentration is not less than 6E19 / cm 3 .

8. The anti-polarity red light emitting diode chip according to any one of claims 1 to 3, characterized in that, the anti-polarity red light emitting diode further includes a first bonding layer (43) and a second bonding layer (44). The first bonding layer (43) and the second bonding layer (44) are stacked in sequence on the surface of the substrate (11); the first bonding layer (43) includes a Ti layer, a Pt layer, an Au layer and an In layer stacked in sequence on the surface of the substrate (11). The second bonding layer (44) includes an In layer, an Au layer, a Ti layer, a Pt layer, a Ti layer and an Au layer stacked in sequence on the surface of the first bonding layer (43).

9. A preparation method of an anti-polarity red light emitting diode chip, characterized in that, the preparation method includes: providing a substrate; forming a first semiconductor layer, a light emitting layer and a second semiconductor layer on the substrate in sequence; An ohmic contact layer and a transparent conductive layer are sequentially formed on the surface of the second semiconductor layer away from the light-emitting layer. An ohmic contact is formed between the ohmic contact layer and the transparent conductive layer. The surface of the ohmic contact layer away from the second semiconductor layer is roughened. The thickness of the transparent conductive layer is not less than the roughening depth of the ohmic contact layer. The ohmic contact layer is an n-type AlGaInP layer. The second semiconductor layer includes an n-type AlGaInP current spreading layer and an n-type AlGaInP roughening layer that are sequentially stacked on the light-emitting layer. The Al component content of the n-type AlGaInP current spreading layer is greater than that of the n-type AlGaInP layer, and the Al component content of the n-type AlGaInP current spreading layer is greater than that of the n-type AlGaInP roughening layer.

10. The manufacturing method according to claim 9, characterized in that the sequentially forming of the ohmic contact layer and the transparent conductive layer on the surface of the second semiconductor layer away from the light-emitting layer includes: forming an n-type AlGaInP layer on the surface of the second semiconductor layer; roughening the n-type AlGaInP layer to form the ohmic contact layer; depositing an indium tin oxide film layer on the ohmic contact layer to form the transparent conductive layer.

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