Single-cycle control method and related device for PFC circuit

Abstract

The present invention discloses a single-cycle control method for a PFC circuit and related devices. The PFC circuit includes a PFC main loop, a voltage loop controller, and a control loop. The method, executed by the control loop, includes: obtaining a first regulated voltage value output by the voltage loop controller, and output voltage sampled values, output current sampled values, input voltage value, and input current value of the PFC main loop; determining a feedforward control variable based on the output voltage sampled values, output current sampled values, and input voltage value; summing the first regulated voltage value and the feedforward control variable to obtain a second regulated voltage value; determining a duty cycle based on the input voltage value, input current value, output voltage sampled value, and second regulated voltage value; and generating a pulse width modulation signal based on the duty cycle, the pulse width modulation signal being used to regulate and control the PFC main loop. The present invention enables rapid regulation and control of the PFC circuit, improves control effectiveness, and facilitates miniaturization of the PFC circuit.

Description

Technical Field

[0001] The present application relates to the field of circuit control technology, and in particular to a single-cycle control method and related device for a PFC circuit. Background Art

[0002] Single-cycle control technology has been widely used in PFC (Power Factor Correction) circuits in recent years due to its fast response and high robustness. However, in practical applications, to reduce the size of the PFC circuit, the inductor is often reduced in size. This reduction in inductor size results in a smaller inductor, which can easily cause oscillation under light loads. Existing single-cycle control algorithms cannot quickly and effectively control PFC circuits, easily causing excessive current stress on the switching devices in the PFC circuit, leading to device failure. Summary of the Invention

[0003] The embodiments of the present application aim to provide a single-cycle control method and related devices for a PFC circuit, so as to improve the regulation and control capability of the PFC circuit.

[0004] In a first aspect, the present application provides a single-cycle control method for a PFC circuit, wherein the PFC circuit includes a PFC main loop, a voltage loop controller, and a control loop, wherein the control loop is connected to the PFC main loop and the voltage loop controller, and the voltage loop controller is connected to the PFC main loop. The method is performed by the control loop and includes:

[0005] Obtaining a first regulated voltage value output by the voltage loop controller; wherein the voltage loop controller may obtain a preset output voltage value and an output voltage sample value of the PFC main loop, and use a difference between the preset output voltage value and the output voltage sample value of the PFC main loop as input to output the first regulated voltage value;

[0006] Obtaining an output voltage sampling value, an output current sampling value, and an input voltage value of the PFC main loop, and determining a feedforward control amount according to the output voltage sampling value, the output current sampling value, and the input voltage value;

[0007] Summing the first regulating voltage value and the feedforward control variable to obtain a second regulating voltage value;

[0008] Obtaining an input current value of the PFC main loop;

[0009] determining a first sub-duty cycle according to the second regulated voltage value, the input voltage value, the input current value, and the output voltage sampling value;

[0010] determining a second sub-duty cycle according to the second regulated voltage value, the input voltage value, and the input current value;

[0011] Summing the first sub-duty cycle and the second sub-duty cycle to obtain the duty cycle;

[0012] A pulse width modulation signal is generated according to the duty cycle; the pulse width modulation signal is used to regulate and control the PFC main loop.

[0013] In combination with the first aspect, in a feasible embodiment, determining the first sub-duty cycle according to the second regulated voltage value, the input voltage value, the input current value, and the output voltage sampling value includes:

[0014] Obtaining the adjustment additional value of the previous control cycle and calculating a first intermediate value according to a first preset calculation formula; wherein the first preset calculation formula is: first intermediate value = (second adjustment voltage value + adjustment additional value of the previous control cycle) * output voltage sampling value;

[0015] comparing the first intermediate value with a preset minimum value of intermediate values, and determining a second intermediate value based on the comparison result; wherein, if the first intermediate value is less than the preset minimum value of the intermediate value, the second intermediate value is equal to the preset minimum value of the intermediate value; and if the first intermediate value is greater than the preset minimum value of the intermediate value, the second intermediate value is equal to the first intermediate value;

[0016] Determining an adjustment additional value for a next control cycle based on a comparison result between the first intermediate value and a preset minimum value of the intermediate value; wherein, if the first intermediate value is greater than the preset minimum value of the intermediate value, the adjustment additional value for the next control cycle is equal to the difference between the adjustment additional value for the previous control cycle and a preset compensation value for the adjustment additional value; and if the first intermediate value is less than the preset minimum value of the intermediate value, the adjustment additional value for the next control cycle is equal to the sum of the adjustment additional value for the previous control cycle and the preset compensation value for the adjustment additional value;

[0017] The first sub-duty cycle is calculated according to a second preset calculation formula; wherein the second preset calculation formula is: the first sub-duty cycle = (the input current value + the input voltage value * the adjustment additional value of the next control cycle) / the second intermediate value.

[0018] In combination with the first aspect, in a feasible embodiment, determining the first sub-duty cycle according to the second regulated voltage value, the input voltage value, the input current value, and the output voltage sampling value includes:

[0019] Obtaining the adjustment additional value of the previous control cycle and calculating a first intermediate value according to a first preset calculation formula; wherein the first preset calculation formula is: first intermediate value = (second adjustment voltage value + adjustment additional value of the previous control cycle) * output voltage sampling value;

[0020] comparing the first intermediate value with a preset minimum value of intermediate values, and determining a second intermediate value based on the comparison result; wherein, if the first intermediate value is less than the preset minimum value of the intermediate value, the second intermediate value is equal to the preset minimum value of the intermediate value; and if the first intermediate value is greater than the preset minimum value of the intermediate value, the second intermediate value is equal to the first intermediate value;

[0021] determining a feedback adjustment value according to the first intermediate value and the preset minimum value;

[0022] Summing the feedback adjustment value and the initial value of the adjustment additional value to obtain the adjustment additional value of the next control cycle;

[0023] The first sub-duty cycle is calculated according to a second preset calculation formula; wherein the second preset calculation formula is: the first sub-duty cycle = (the input current value + the input voltage value * the adjustment additional value of the next control cycle) / the second intermediate value.

[0024] In combination with the first aspect, in a feasible embodiment, a multi-resonance controller is provided in the control loop, and determining the second sub-duty cycle according to the second adjustment voltage value, the input voltage value, and the input current value includes:

[0025] The resonant input voltage value of the multi-resonant controller is calculated according to a third preset calculation formula; wherein the third preset calculation formula is: the resonant input voltage value = the input voltage value * the second adjustment voltage value - the input current value;

[0026] Obtaining a preset resonance gain of the multi-resonance controller, and determining a resonant output voltage value of the multi-resonance controller according to the resonant input voltage value and the preset resonance gain;

[0027] The second sub-duty cycle is calculated according to a fourth preset calculation formula; wherein the fourth preset calculation formula is: the second sub-duty cycle=the first preset constant*the resonant output voltage value.

[0028] In combination with the first aspect, in a feasible embodiment, obtaining the resonant preset gain of the multi-resonant controller and determining the resonant output voltage value of the multi-resonant controller according to the resonant input voltage value and the resonant preset gain includes:

[0029] Obtaining the number of resonant frequency points of the PFC main loop, the frequencies corresponding to each of the resonant frequency points, the resonant bandwidth, and a second preset constant;

[0030] Determining a first constant value and a second constant value corresponding to each of the resonant frequency points according to the frequency, the resonant bandwidth, and the second preset constant of each of the resonant frequency points;

[0031] The calculation formula of the first constant value is: the first constant value = 2*(the square of the frequency of the resonant frequency point - the square of the second preset constant) / (the square of the frequency of the resonant frequency point + 2*resonant bandwidth*the second preset constant + the square of the second preset constant);

[0032] The calculation formula of the second constant value is: the second constant value = (the square of the frequency of the resonant frequency point - 2*resonant bandwidth*the second preset constant + the square of the second preset constant) / (the square of the frequency of the resonant frequency point + 2*resonant bandwidth*the second preset constant + the square of the second preset constant);

[0033] Obtaining the resonant input voltage value of the previous control cycle of the multi-resonant controller, and the sub-resonant output voltage value of the previous control cycle and the sub-resonant output voltage value of the previous control cycle corresponding to each of the resonant frequency points, and calculating the sub-resonant output voltage value corresponding to each of the resonant frequency points according to a fifth preset calculation formula; wherein the fifth preset calculation formula is: the sub-resonant output voltage value = the preset gain * (the resonant input voltage value - the resonant input voltage value of the previous control cycle) - the first constant value * the sub-resonant output voltage value of the previous control cycle - the second constant value * the sub-resonant output voltage value of the previous control cycle;

[0034] The sub-resonance output voltage values ​​corresponding to the respective resonant frequency points are summed to obtain the resonant output voltage value of the multi-resonance controller.

[0035] In combination with the first aspect, in a feasible embodiment, obtaining the output current sampling value and the input voltage value of the PFC circuit, and determining the feedforward control amount according to the output voltage sampling value, the output current sampling value, and the input voltage value includes:

[0036] The feedforward control amount is calculated according to a sixth preset calculation formula; the sixth preset calculation formula is: feedforward control amount = (output voltage sampling value * output current sampling value) / (input voltage value * input voltage value); wherein the input voltage value, the output voltage sampling value, and the output current sampling value are filtered values.

[0037] In a second aspect, the present application provides a single-cycle control device for a PFC circuit, the device comprising:

[0038] an acquisition unit, the acquisition unit being configured to acquire a first regulated voltage value output by a voltage loop controller; wherein the voltage loop controller may acquire a preset output voltage value and an output voltage sample value of a PFC main loop, and use a difference between the preset output voltage value and the output voltage sample value of the PFC main loop as input to output the first regulated voltage value;

[0039] The acquisition unit is further configured to acquire a preset output voltage value, an output voltage sampling value, an output current sampling value, an input voltage value, and an input current value of the PFC main circuit;

[0040] a processing unit, configured to determine a feedforward control amount according to the output voltage sampling value, the output current sampling value, and the input voltage value;

[0041] The processing unit is configured to sum the first regulating voltage value and the feedforward control variable to obtain a second regulating voltage value;

[0042] The processing unit is configured to determine a first sub-duty cycle according to the second regulated voltage value, the input voltage value, the input current value, and the output voltage sample value; determine a second sub-duty cycle according to the second regulated voltage value, the input voltage value, and the input current value; and obtain the duty cycle by summing the first sub-duty cycle and the second sub-duty cycle;

[0043] a generating unit, configured to generate a pulse width modulation signal according to the duty cycle;

[0044] A control unit is used to adjust and control the PFC main loop according to the pulse width modulation signal.

[0045] In a third aspect, the present application provides an electronic device, comprising a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, the program comprising instructions for executing the steps in the method described above, or the program comprising instructions for the steps of the device described above.

[0046] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed, the method described in any one of the above-mentioned first aspects is implemented.

[0047] The single-cycle control method for a PFC circuit provided by the technical solution of the present invention features fast output dynamic response. This method allows for rapid and effective regulation and control of the PFC circuit, thereby improving the control effectiveness of the PFC circuit. Furthermore, the improved control capability of the PFC circuit allows for a reduction in the size of the PFC circuit, facilitating further miniaturization of the PFC circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0049] Figure 1 A schematic structural diagram of a PFC circuit provided by an embodiment of the present invention;

[0050] Figure 2 A schematic structural diagram of another PFC circuit provided by an embodiment of the present invention;

[0051] Figure 3 for Figure 2 A calculation block diagram of an embodiment of a K value calculation subunit;

[0052] Figure 4 A schematic flow chart of a single-cycle control method for a PFC circuit provided by an embodiment of the present invention;

[0053] Figure 5 A schematic structural diagram of a PFC circuit control device provided by an embodiment of the present invention;

[0054] Figure 6 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to facilitate the understanding of the present application, in order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application, and preferred embodiments of the present application are provided in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of the present application. The present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited to the specific embodiments disclosed below.

[0056] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0057] The power factor (PF) in power factor correction (PFC) refers to the relationship between active power and total power consumption (apparent power), specifically the ratio of active power divided by total power consumption (apparent power). The power factor measures how effectively electricity is used; a higher power factor indicates higher power utilization. The power factor is a parameter used to measure the efficiency of electrical equipment; a low power factor indicates low power efficiency. Technologies designed to improve the power factor of electrical equipment are called power factor correction (PFC). The principle of a PFC circuit can be understood as adjusting the closure of the relevant switching devices in the PFC circuit so that the PFC circuit outputs a stable voltage.

[0058] See Figure 1 , Figure 1 1 is a schematic diagram of a structure of a PFC circuit provided in an embodiment of the present application. The single-cycle control method of the PFC circuit provided in the present application can be applied to the PFC circuit, which can be a single-phase PFC circuit or a three-phase PFC circuit. Figure 1 As shown, the PFC circuit may include a PFC main loop 100, a voltage loop controller 300, and a control loop 200. The control loop 200 is connected to the PFC main loop 100 and the voltage loop controller 300, and the voltage loop controller 300 is connected to the PFC main loop 100. In actual use, the control loop 200 can determine a duty cycle (here, assumed to be d) based on the input voltage value (here, assumed to be Uac), the input current value (here, assumed to be Iac), the output voltage sample value (here, assumed to be Uo), the output current sample value (here, assumed to be Iload), and the first regulated voltage value (here, assumed to be Uc) output by the voltage loop controller 300. The control loop can then generate a corresponding pulse width modulation (PWM) signal based on the duty cycle d. The control loop in the PFC circuit can use the PWM signal to control the on / off state of the switching devices in the PFC main loop, thereby ensuring that the output voltage of the PFC circuit tends to a stable preset voltage level.

[0059] See further Figure 1 .like Figure 1 As shown, the control loop 200 may specifically include a calculation module and a PWM generation control module. Information such as the input voltage Uac, input current Iac, output voltage sampled value Uo, output current sampled value Iload of the PFC main loop 100, and the first regulated voltage value Uc output by the voltage loop controller 300 can be input into the calculation module, allowing it to calculate the duty cycle d. The PWM generation control module can generate a control signal based on the duty cycle d to control the opening and closing of switching devices in the PFC main loop 100, thereby regulating the output of the PFC main loop 100. The calculation module may include a sampling unit for collecting data such as the input voltage Uac, input current Iac, output voltage sampled value Uo, output current sampled value Iload of the PFC main loop, and the first regulated voltage value Uc output by the voltage loop controller 300, and input this data into other data processing units within the calculation module. The calculation module may also include a multi-resonance control calculation unit for calculating the duty cycle to regulate the harmonics of the PFC circuit.

[0060] See also Figure 1 and Figure 4 , Figure 1 A schematic diagram of the structure of a PFC circuit provided in an embodiment of the present application is shown in FIG. Figure 4 1 is a flow chart of a single-cycle control method for a PFC circuit provided by an embodiment of the present application. The single-cycle control method for the PFC circuit can be specifically executed by the control loop described above. Figure 4 As shown, the method includes:

[0061] In step S210 , the control loop obtains a first adjustment voltage value output by the voltage loop controller.

[0062] The voltage loop controller may obtain a preset output voltage value (here assumed to be Uoref) and an output voltage sampling value Uo of the PFC main loop, and take a difference (here assumed to be Uerr) between the preset output voltage value and the output voltage sampling value of the PFC main loop as input to output the first regulation voltage value Uc.

[0063] The output voltage sampling value is the currently acquired instantaneous value of the PFC circuit output voltage. The first regulated voltage value output by the voltage loop controller can be input into the control loop for calculation by the calculation module within the control loop. The preset output voltage value is a pre-set voltage value for the PFC circuit and can be set based on the required voltage. It is understood that the voltage loop controller can perform deviation control based on the input voltage difference to output the first regulated voltage value. The output first regulated voltage value can be used to adjust the output voltage of the PFC main loop so that the output voltage of the PFC main loop approaches the required output voltage value. In some feasible implementations, the voltage loop controller can be a PI controller, a PID controller, a P controller, or a combination of any of the above controllers with a limiter, etc., without further limitation herein.

[0064] Step S220 , obtaining an output voltage sampling value Uo, an output current sampling value Iload, and an input voltage value Uac of the PFC main loop, and determining a feedforward control value (here assumed to be Ucforward) based on the output voltage sampling value, the output current sampling value, and the input voltage value.

[0065] The output current sampling value is the current currently output by the PFC circuit, and the output voltage sampling value is the same as the output voltage sampling value obtained by the voltage controller described above.

[0066] Among them, the feedforward control amount is an estimated amount, which is used to supplement the control of the first regulated voltage value output by the voltage loop controller, thereby improving the regulation performance of the PFC circuit in dynamic conditions, so that the voltage output by the PFC main loop can reach the required stable voltage value more quickly. Adding the feedforward control amount on the basis of the first regulated voltage value of the voltage loop controller improves the dynamic response speed of the PFC circuit.

[0067] In a feasible implementation, the feedforward control amount may be set according to existing empirical parameters to perform supplementary control on the first regulating voltage value output by the voltage loop controller.

[0068] In another feasible implementation, the feedforward control amount can be calculated according to the sixth preset calculation formula, and the sixth preset calculation formula is: feedforward control amount Ucforward = (output voltage sampling value Uo*output current sampling value Iload) / (input voltage value Uac*input voltage value Uac).

[0069] The calculation method of the above feedforward control quantity can be obtained by Figure 2The sixth preset calculation formula is executed by the feedforward calculation unit in the PFC circuit. In this embodiment, the sixth preset calculation formula is a formula for calculating admittance under ideal conditions. The value of the feedforward control variable can be equivalent to the input admittance value. This improves the dynamic response speed of the PFC circuit, allowing the output voltage of the PFC main loop, after regulation and control by the control loop, to quickly reach the voltage value required by the load. This enables the control loop to respond and regulate the PFC main loop more quickly than the voltage loop controller. Furthermore, in this example, the feedforward control variable is a DC quantity, so the input voltage value used to calculate the feedforward control variable is the effective value of the grid voltage, thereby ensuring the accuracy of the calculated feedforward control variable.

[0070] Based on the above embodiment, the input voltage value, the output voltage sampled value, and the output current sampled value used in the sixth preset calculation formula can be filtered values. This can achieve noise reduction, making the data used for calculation more accurate, thereby further shortening the development cycle and improving response speed. To filter the acquired data, a filter can be set in the sampling unit of the control loop. This filter can be a bandstop filter (BSF) or a notch filter.

[0071] Step S230 : summing the first regulating voltage value and the feedforward control variable to obtain a second regulating voltage value (assuming it is Uc1 ).

[0072] As can be understood, the use of a feedforward control variable can improve the control loop's speed in regulating the PFC main loop during dynamic conditions. The first regulated voltage value can compensate for the feedforward control variable to ensure the control loop's accuracy in regulating the PFC main loop output during steady-state conditions. A PFC circuit controlled using this method not only achieves high control accuracy but also fast dynamic response.

[0073] Step S240 , obtaining the input current value of the PFC main loop, and determining a duty cycle according to the input voltage value, the input current value, the output voltage sampling value, and the second regulation voltage value.

[0074] In some feasible implementations, the duty cycle may include a first sub-duty cycle, where the first sub-duty cycle is calculated based on the second regulated voltage value, the input voltage value, the input current value, and the sampled output voltage value. In one feasible implementation, the input voltage value used to calculate the first sub-duty cycle may be the effective value of the grid voltage. Alternatively, in another feasible implementation, a phase-locked loop (PLL) may be provided between the grid voltage input to the PFC circuit and the PFC circuit. In this case, the input voltage value used to calculate the first sub-duty cycle is the product of the peak value of the grid voltage and the unit sine wave output by the PLL, and the input voltage value used to calculate the first sub-duty cycle is the instantaneous value of the sampled PFC circuit input voltage. This configuration can improve the PFC main circuit's ability to resist grid interference and enhance the output stability of the PFC main circuit.

[0075] Specifically, the step of obtaining the first sub-duty cycle includes:

[0076] Step S241, obtain the adjustment additional value of the previous control cycle (here assumed to be K), and calculate the first intermediate value (here assumed to be Uctrl) according to the first preset calculation formula; wherein, the first preset calculation formula is: the first intermediate value Uctrl = (the second adjustment voltage value Uc1 + the adjustment additional value K of the previous control cycle) * the output voltage sampling value Uo.

[0077] It will be appreciated that, in a specific implementation, the PFC circuit may execute the single-cycle control method sequentially according to the first cycle, the second cycle, the third cycle, ..., and the Nth cycle. The cycle of the currently executing single-cycle control method may be recorded as the next control cycle. In this case, the data output during the currently executing cycle of the single-cycle control method is the data for the next control cycle. If the currently executing cycle of the single-cycle control method is the Nth cycle, then the previous control cycle of the currently executing single-cycle control method is the N-1th cycle, and the previous control cycle of the currently executing single-cycle control method is the N-2th cycle.

[0078] Based on the above, it can be seen that the second regulated voltage value Uc1 can be equivalent to the compensated input admittance. This not only ensures that the control loop can quickly calculate the duty cycle to control and regulate the PFC circuit in dynamic conditions, but also ensures the accuracy of controlling the PFC circuit in steady state. In the process of calculating the first sub-duty cycle, the principle of adding the additional regulation value to the second regulated voltage value is as follows:

[0079] It is known that in order to achieve the purpose of the input current following the input voltage, the purpose of current control can usually be expressed by the formula: Iac = G*Uac, where G is the admittance (equivalent to the second adjustment voltage value Uc1 in this application), which is determined by the voltage loop controller. From the steady-state volt-second theorem, we get: Uac = Uo*d. It can be seen that the duty cycle can be converted to: d = Iac / (G*Uo), which means that when the duty cycle d = Iac / (G*Uo), the voltage stability can be guaranteed. The product of admittance and output voltage is defined as the first intermediate value, that is: Uctrl = G*Uo. From the above analysis, it can be seen that: d = Iac / Uctrl. It is known that within a control cycle, the switching device has the situation where the upper tube is turned on and the lower tube is turned on. The switching device is a MOS tube, see Figure 1 In an ideal circuit, the duty cycle can be calculated immediately after sampling is completed and the PFC main circuit can be updated and regulated. At this time, in a single control cycle, when the lower tube is turned on, the current rises. Here, the current in the rising section is recorded as Δ Iac1; when the upper tube is turned on, the current decreases. Here, the current in the decreasing section is recorded as Δ Iac2. According to the current in the rising section and the current in the falling section within a single control cycle, the differential equation of the inductor current is:

[0080] Iac n -Iac n-1 =ΔIac1+ΔIac2

[0081] The sum of the current in the rising section and the current in the falling section can be further written as:

[0082]

[0083] Furthermore, the above formula can be simplified as:

[0084]

[0085] Where L is the inductance, 1-d n-1 is the duty cycle of the lower tube, d n-1 is the duty cycle of the upper tube, T s is the control period. According to the duty cycle calculation formula

[0086] d=Iac / Uctrl,

[0087]

[0088] Therefore, the above formula can be converted into:

[0089]

[0090] It can be seen that the characteristic roots of the above characteristic equation are:

[0091]

[0092] Since the necessary and sufficient condition for system stability is that the modulus of the characteristic root is less than 1, the stability condition for a single cycle is:

[0093] and Right now,

[0094] and Therefore, in this case the first intermediate value U ctrl The minimum value of is:

[0095]

[0096] However, in the above case, if the input admittance is 0 during control, the first intermediate value U ctrl Then it is 0, and the first intermediate value U cannot be satisfied. ctrl Greater than the minimum value

[0097]

[0098] This stable condition, so using the above formula principle to calculate the duty cycle d will not be able to achieve single-cycle control of the PFC circuit.

[0099] To avoid the situation where the admittance is uncontrollable when it is 0, an additional adjustment value K can be added to the original admittance G (that is, an additional adjustment value K is added to the second adjustment voltage value). In this case, the adjusted admittance G'=G+K. At this time, the output current should remain unchanged, and in order to achieve the purpose of the input current following the input voltage, the current control formula is expressed as: Iac==G'*Uac-K*Uac. To ensure that the output remains consistent when the additional adjustment value K is increased, the duty cycle should also remain unchanged, that is, d=Uac / Uo=(Iac+K*Uac) / (G'*Uo).

[0100] Substituting d at this time into the differential equation of the inductor current, we can get:

[0101]

[0102] Right now

[0103] and That is to say

[0104] and

[0105] Therefore, the minimum value of the adjusted first intermediate value Uctrl′ is That is, the preset minimum value of the intermediate value can be changed according to the needs The parameters in can be set arbitrarily.

[0106] From the above analysis, it can be seen that when an adjustment additional value K is added on the basis of the original admittance G, not only can normal control be guaranteed through the duty cycle. Moreover, even if the input admittance is 0, the adjustment additional value can still be adjusted according to the adjustment setting to meet the necessary condition that the minimum value is greater than 0, which can avoid the occurrence of no-load oscillation. Since the second adjustment voltage value in this application is equivalent to the compensated admittance value, adding the additional adjustment value K to the second adjustment voltage value can also ensure normal control through the duty cycle, and can ensure stability when no-load, and avoid the occurrence of no-load oscillation. Therefore, in this embodiment, the first preset calculation formula for calculating the first intermediate value can be: the first intermediate value Uctrl = (the second adjustment voltage value Uc1 + the adjustment additional value K of the previous control cycle) * the output voltage sampling value Uo.

[0107] Step S242, compare the first intermediate value with the preset minimum value of the intermediate value, and determine the second intermediate value based on the comparison result; wherein, if the first intermediate value is smaller than the preset minimum value of the intermediate value, the second intermediate value is equal to the preset minimum value of the intermediate value; if the first intermediate value is larger than the preset minimum value of the intermediate value, the second intermediate value is equal to the first intermediate value.

[0108] The second intermediate value Uctrl 1 described above can be determined by Figure 2 The minimum value limiting unit in the control logic is executed. It will be appreciated that if the first intermediate value is less than the preset minimum value, the first intermediate value will definitely not meet the stability condition. To ensure that the stability condition is met, the second intermediate value Uctrl 1 can be directly set to the preset minimum value, thereby improving the efficiency of the adjustment calculation while meeting the stability condition. If the first intermediate value Uctrl is greater than or equal to the preset minimum value, the first intermediate value Uctrl can be directly used as the second intermediate value Uctrl 1 to calculate the first sub-duty cycle. Thus, the solution provided by the present application can control the calculation of the first sub-duty cycle by adjusting the preset minimum value of the intermediate value, thereby affecting the control debugging of the control loop on the PFC main loop. Therefore, the present application has the advantage of convenient debugging.

[0109] Step S243: determining the adjustment additional value for the next control cycle.

[0110] When calculating the first sub-duty cycle, the control loop may perform calculations based on the adjustment additional value of the next control cycle to control and adjust the output of the PFC main loop.

[0111] In one possible implementation, Figure 2 As shown, the calculation module includes a K value calculation unit, that is, an adjustment additional value calculation unit for the next cycle. The K value calculation unit can determine the adjustment additional value of the next control cycle based on the comparison result of the first intermediate value and the preset minimum value; wherein, if the first intermediate value is greater than the preset minimum value, the adjustment additional value of the next control cycle is equal to the difference between the adjustment additional value of the previous control cycle and the preset compensation value of the adjustment additional value; if the first intermediate value is less than the preset minimum value, the adjustment additional value of the next control cycle is equal to the sum of the adjustment additional value of the previous control cycle and the preset compensation value of the adjustment additional value.

[0112] The adjustment additional value for the next control cycle is used to control the output of the PFC main loop in the next cycle. The adjustment additional value for the previous control cycle is used to identify the PFC main loop's adjustment control status during the previous control cycle and calculate the adjustment additional value for the next cycle. In this embodiment, if the first intermediate value is greater than the preset minimum value, it indicates that the first intermediate value used for adjustment has been increased. An increase in the first intermediate value indicates that the second adjustment voltage value has also increased, and an increase in the second adjustment voltage value indicates that the first adjustment voltage value has been increased. It can be understood that when the output voltage is low, the difference between the preset output voltage value and the sampled output voltage value, which serves as the input to the voltage loop controller, is positive, and the first adjustment voltage value output by the voltage loop controller is increased. Therefore, an increase in the first intermediate value indicates that the output voltage is too low and that the output voltage needs to be increased, i.e., the duty cycle of the lower transistor of the switching device needs to be increased. Since the first sub-duty cycle represents the duty cycle of the upper tube, and the duty cycle of the lower tube is equal to 1 minus the duty cycle of the upper tube, if the duty cycle of the lower tube is to be increased, the duty cycle of the upper tube must be decreased, and the adjustment additional value must be reduced. Therefore, the adjustment additional value of the next control cycle is equal to the difference between the adjustment additional value of the previous control cycle and the preset compensation value of the adjustment additional value. Similarly, if the first intermediate value is less than the preset minimum value, it means that the output voltage is too large, and the output voltage needs to be reduced, that is, the duty cycle of the lower tube needs to be reduced. In this case, the duty cycle of the upper tube needs to be increased, and the adjustment additional value needs to be increased. Therefore, the adjustment additional value of the next control cycle is equal to the sum of the adjustment additional value of the previous control cycle and the preset compensation value of the adjustment additional value.

[0113] See also Figure 3 In a feasible implementation, a feedback adjustment value is determined based on the first intermediate value and the preset minimum value; and then the feedback adjustment value and the initial value of the adjustment additional value are summed to obtain the adjustment additional value of the next control cycle.

[0114] In this embodiment, the control loop further includes a PI controller. Figure 2 The K value calculation unit in Figure 3 As shown. The adjustment additional value of the next control cycle can be determined by a PI controller. Specifically, the PI controller can use the difference between the first intermediate value Uctrl and the preset minimum value UctrlMin as the input of the PI controller to output a feedback adjustment value. The feedback adjustment value is the basic value of the adjustment additional value output on the basis of the previous control cycle, which can improve the accuracy of the adjustment additional value confirmation. The summation of the feedback adjustment value and the initial value of the adjustment additional value is to further improve the accuracy of the control loop regulation control, shorten the operation cycle, and improve the control efficiency. Among them, the initial value of the adjustment additional value (here denoted as KInit, as shown in Figure 3 ) can be zero, or it can have a certain value based on empirical data, and is not further limited here.

[0115] Step S244, calculate the first sub-duty cycle according to a second preset calculation formula; wherein the second preset calculation formula is: the first sub-duty cycle = (the input current value + the input voltage value * the adjustment additional value of the next control cycle) / the second intermediate value.

[0116] In some feasible embodiments, the duty cycle may be the sum of the first sub-duty cycle and the second sub-duty cycle.

[0117] The first sub-duty cycle can be used to regulate the fundamental wave and most harmonics, and the first sub-duty cycle can be calculated according to the method described above. The second sub-duty cycle is used to enhance the control loop's ability to regulate and control harmonics. The second sub-duty cycle combined with the first sub-duty cycle can further enhance the control loop's ability to regulate and control the PFC loop, improve the power factor value across the full load range, and reduce current harmonic distortion across the full load range. Specifically, the steps for determining the second sub-duty cycle include:

[0118] Step S245 , calculating the resonant input voltage value according to a third preset calculation formula; wherein the third preset calculation formula is: the resonant input voltage value=the input voltage value*the second adjustment voltage value-the input current value.

[0119] To regulate harmonics, the calculation module may include a multi-resonance control calculation unit, which may be a multi-resonance controller including at least two quasi-resonance controllers. The resonant input voltage value calculated by the third formula may serve as an input to the multi-resonance controller.

[0120] Step S246 , obtaining a resonance preset gain, and determining a resonance output voltage value of the multi-resonance controller according to the resonance input voltage value and the resonance preset gain.

[0121] The resonant output voltage value is the output value of the multi-resonant controller, and the specific determination steps include:

[0122] Step S2461: Obtain the number of resonant frequency points of the PFC main circuit, the frequency corresponding to each resonant frequency point, and the resonant bandwidth (here, assuming w c ), and a second preset constant (here assumed to be C).

[0123] Among them, the second preset constant C is used to calculate the resonant output voltage value, which can be equal to twice the operating frequency. The multi-resonance controller can have multiple resonant points, and the resonant points can be determined according to the frequency of the actual power grid and the order of the current harmonics that need to be suppressed. For the convenience of description, the following specific description is given as having two resonant points in the multi-resonance controller, and the resonant frequencies of these two resonant frequency points are respectively recorded as w1 and w2. It can be understood that the second preset constant, the number of resonant frequency points, the frequencies corresponding to each of the resonant frequency points, and the resonant bandwidth in this embodiment can be calculated only once during initialization.

[0124] Step S2462 : determining a first constant value and a second constant value corresponding to each of the resonant frequency points according to the frequency, the resonant bandwidth, and the second preset constant of each of the resonant frequency points.

[0125] The calculation formula of the first constant value is: the first constant value = 2*(the square of the frequency of the resonant frequency point - the square of the second preset constant) / (the square of the frequency of the resonant frequency point + 2*resonant bandwidth*the second preset constant + the square of the second preset constant);

[0126] The calculation formula of the second constant value is: the second constant value = (the square of the frequency of the resonant frequency point - 2*resonant bandwidth*the second preset constant + the square of the second preset constant) / (the square of the frequency of the resonant frequency point + 2*resonant bandwidth*the second preset constant + the square of the second preset constant).

[0127] The first constant value and the second constant value are used to calculate the sub-resonant output voltage value at each resonant frequency point. The calculation formula for the first constant value and the second constant value is a general formula for obtaining the first constant value and the second constant value when calculating the sub-resonant output voltage value at each resonant frequency point. The general formula can quickly calculate the first constant value and the second constant value, thereby quickly calculating the resonant output voltage value of the multi-resonant controller, improving the calculation speed of the second sub-duty cycle, shortening the calculation cycle, and improving the control efficiency of the control loop over the PFC main loop.

[0128] Specifically, the multi-resonance controller may include a quasi-resonance controller 1 and a quasi-resonance controller 2, each of which is used to adjust and control a resonant frequency point. The Z-domain transfer function of the quasi-resonance controller is as follows:

[0129] The Z-domain transfer function of the quasi-resonant controller 1 is:

[0130]

[0131] Among them, U o1 (z) represents the output of the quasi-resonant controller 1, U i (z) represents the input of the quasi-resonant controller 1, that is, the input of the multi-resonant controller, K1 represents the amplification factor of the quasi-resonant controller, w1 represents the frequency of the resonant frequency point, and w c represents the resonant bandwidth, and c is a second preset constant. Thus, the output of the quasi-resonant controller 1 can be expressed as:

[0132]

[0133] Similarly, the output of quasi-resonant controller 2 can be expressed as:

[0134]

[0135] When setting, the gains Rk of each quasi-resonant controller can be set equal, that is,

[0136]

[0137] If the order

[0138] Rk(U i (z)-U i (z)z -2 )=P(U i (z))

[0139] The output calculation formula of the two quasi-resonant controllers can be simplified to:

[0140]

[0141] Due to the commonality of the output calculation formulas of the two quasi-resonant controllers, we can further make

[0142]

[0143]

[0144]

[0145]

[0146] At this time, the output calculation formula of the two quasi-resonant controllers can be further simplified as:

[0147] U o1(z)=P(U i (z))-B 11 U o1 (z)z -1 -B 12 U o1 (z)z -2

[0148] U o2 (z)=P(U i (z))-B 21 U o2 (z)z -1 -B 22 U o2 (z)z -2

[0149] Among them, B11 and B21 are the first constant values ​​corresponding to the two resonant frequency points, and B12 and B22 are the second constant values ​​corresponding to the two resonant frequency points. It can be understood that since the P(Ui(z)) components of the two quasi-resonant controllers are consistent after the transformation, P(Ui(z)) only needs to be calculated once in the entire process. At the same time, it can be seen that the amplification factor K2 of the quasi-resonant controller 2 is:

[0150]

[0151] Step S2463, obtaining the resonant input voltage value of the last control cycle of the multi-resonance controller (ie, the U i (z)z -2 ), and the sub-resonance output voltage value of the previous control cycle corresponding to each of the resonant frequency points (i.e., the U o1 (z)z -1 and U o2 (z)z -1 ) and the sub-resonant output voltage value of the previous control cycle (i.e. the U o1 (z)z -2 and U o2 (z)z -2 ), and calculate the sub-resonant output voltage value corresponding to each of the resonant frequency points according to the fifth preset calculation formula; wherein, the fifth preset calculation formula is: the sub-resonant output voltage value = the resonant preset gain * (the resonant input voltage value - the resonant input voltage value of the previous control cycle) - the first constant value * the sub-resonant output voltage value of the previous control cycle - the second constant value * the sub-resonant output voltage value of the previous control cycle.

[0152] As can be seen from the above content, the fifth preset calculation formula is a calculation formula for the sub-resonant output voltage value of each quasi-resonant controller that adjusts each resonant frequency point in the multi-resonant controller, which is converted according to the Z-domain transfer function of each resonant controller in the multi-resonant controller. Among them, when the method of the present application is used to calculate the sub-resonant output voltage value, since the gain of the multi-resonant controller is the same when obtaining each resonant frequency point, it is only necessary to calculate the resonant preset gain once when calculating each sub-resonant output voltage value. Compared to calculating the gain of the corresponding quasi-resonant controller once for each sub-resonant output voltage value, the method of the present application has higher calculation efficiency and a shorter calculation development cycle.

[0153] Step S2464: summing the sub-resonant output voltage values ​​corresponding to the respective resonant frequency points to obtain the resonant output voltage value of the multi-resonant controller.

[0154] It can be understood that by taking the sum of the sub-resonant output voltage values ​​of each resonant frequency point as the resonant output voltage value of the multi-resonant controller, multiple resonant frequency points can be adjusted to improve the accuracy of the harmonic control data and improve the harmonic control effect.

[0155] Step S247, calculating the second sub-duty cycle according to a fourth preset calculation formula; wherein the fourth preset calculation formula is: the second sub-duty cycle = the first preset constant (here set to Pk) * the resonant output voltage value.

[0156] The first preset constant can be set based on actual needs and is not further limited here. The first preset constant can amplify or reduce the resonant output voltage by a certain factor, so that the ultimately calculated second sub-duty cycle and first sub-duty cycle can more accurately control the output voltage of the PFC main circuit.

[0157] Step S250: Generate a corresponding pulse width modulation signal according to the duty cycle; the pulse width modulation signal is used to adjust and control the PFC main loop.

[0158] See also Figure 1 The calculated duty cycle can be input into the PWM generation module, which can generate a pulse-width modulation signal for regulating and controlling the PFC main circuit based on the input duty cycle. Specifically, this pulse-width modulation signal can be transmitted to the driver module, which can control the switching devices in the PFC main circuit to turn on or off based on the pulse-width modulation signal, thereby adjusting the output voltage of the PFC circuit. The PWM generation module in this embodiment can generate the pulse-width modulation signal using a unipolar generation method or a bipolar generation method, without further limitation.

[0159] Based on the same inventive concept, embodiments of the present application further provide a PFC circuit single-cycle control device 500 for implementing the aforementioned single-cycle control method for a PFC circuit. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more embodiments of the PFC circuit single-cycle control device 500 provided below can be found in the above-described limitations of the PFC circuit single-cycle control method and are not further elaborated here.

[0160] See Figure 6 , Figure 6 This is a schematic diagram of the structure of a single-cycle control device for a PFC circuit in an embodiment of the present application. Figure 6 As shown, the PFC circuit single-cycle control device 500 includes: an acquisition unit 510 , a processing unit 520 , a generation unit 530 , and a control unit 540 .

[0161] The acquisition unit 510 is configured to acquire a first regulated voltage value output by a voltage loop controller. The voltage loop controller may acquire a preset output voltage value and an output voltage sampling value of the PFC main loop, and use the difference between the preset output voltage value and the output voltage sampling value of the PFC main loop as input to output the first regulated voltage value. The acquisition unit is further configured to acquire a preset output voltage value, an output voltage sampling value, an output current sampling value, an input voltage value, and an input current value of the PFC main loop.

[0162] The processing unit 520 is used to determine a feedforward control quantity based on the output voltage sampling value, the output current sampling value, and the input voltage value; the processing unit is used to sum the first adjustment voltage value and the feedforward control quantity to obtain a second adjustment voltage value; the processing unit is used to calculate a duty cycle based on the input voltage value, the input current value, the output voltage sampling value, and the second adjustment voltage value.

[0163] The generating unit 530 is configured to generate a pulse width modulation signal according to the duty cycle.

[0164] The control unit 540 is configured to regulate and control the PFC main loop according to the pulse width modulation signal.

[0165] Specifically, the specific working process of the PFC circuit single-cycle control device may correspond to the corresponding process in the aforementioned single-cycle control method of the PFC circuit, and will not be repeated here.

[0166] Each unit in the above-described single-cycle control device for a PFC circuit may be implemented in whole or in part via software, hardware, or a combination thereof. Each of the above modules may be embedded in or independent of a processor in a computer device in hardware form, or may be stored in a memory in the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0167] The present application also provides an electronic device, which may include various devices or computers with data processing capabilities, such as desktop computers, servers, laptop computers, tablet computers, etc.

[0168] See Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device in an embodiment of the present application. Figure 5 As shown, the electronic device includes a communication interface, a processor, a memory, and at least one communication bus for connecting the communication interface, the processor, and the memory.

[0169] The memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM). The memory 803 is used for related instructions and data.

[0170] The communication interface is used to receive and send data.

[0171] The processor may be one or more central processing units (CPUs). In the case where the processor is a CPU, the CPU may be a single-core CPU or a multi-core CPU.

[0172] The processor in the electronic device is used to read one or more program codes stored in the memory and execute any one of the methods described in the above embodiments.

[0173] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. When the computer-readable storage medium is run on a terminal, the method flow shown in the above method embodiment is implemented.

[0174] An embodiment of the present application also provides a computer program product. When the computer program product is run on a terminal, the method flow shown in the above method embodiment is implemented.

[0175] It should be understood that the processor mentioned in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0176] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0177] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated into the processor.

[0178] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0179] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0180] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0181] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0182] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0183] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0184] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0185] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0186] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0187] The modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0188] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A single-cycle control method for a PFC circuit, characterized in that: The PFC circuit includes a PFC main loop, a voltage loop controller, and a control loop. The control loop is connected to the PFC main loop and the voltage loop controller. The voltage loop controller is connected to the PFC main loop. The method is performed by the control loop and includes: Obtaining a first regulated voltage value output by the voltage loop controller; wherein the voltage loop controller may obtain a preset output voltage value and an output voltage sample value of the PFC main loop, and use a difference between the preset output voltage value and the output voltage sample value of the PFC main loop as input to output the first regulated voltage value; Obtaining an output voltage sampling value, an output current sampling value, and an input voltage value of the PFC main loop, and determining a feedforward control amount according to the output voltage sampling value, the output current sampling value, and the input voltage value; Summing the first regulating voltage value and the feedforward control variable to obtain a second regulating voltage value; Obtaining an input current value of the PFC main loop; determining a first sub-duty cycle according to the second regulated voltage value, the input voltage value, the input current value, and the output voltage sampling value; determining a second sub-duty cycle according to the second regulated voltage value, the input voltage value, and the input current value; Summing the first sub-duty cycle and the second sub-duty cycle to obtain the duty cycle; A pulse width modulation signal is generated according to the duty cycle; the pulse width modulation signal is used to regulate and control the PFC main loop.

2. The method according to claim 1, characterized in that The determining a first sub-duty cycle according to the second regulated voltage value, the input voltage value, the input current value, and the output voltage sampling value includes: Obtaining the adjustment additional value of the previous control cycle and calculating a first intermediate value according to a first preset calculation formula; wherein the first preset calculation formula is: first intermediate value = (second adjustment voltage value + adjustment additional value of the previous control cycle) * output voltage sampling value; comparing the first intermediate value with a preset minimum value of intermediate values, and determining a second intermediate value based on the comparison result; wherein, if the first intermediate value is less than the preset minimum value of the intermediate value, the second intermediate value is equal to the preset minimum value of the intermediate value; and if the first intermediate value is greater than the preset minimum value of the intermediate value, the second intermediate value is equal to the first intermediate value; Determining an adjustment additional value for a next control cycle based on a comparison result between the first intermediate value and a preset minimum value of the intermediate value; wherein, if the first intermediate value is greater than the preset minimum value of the intermediate value, the adjustment additional value for the next control cycle is equal to the difference between the adjustment additional value for the previous control cycle and a preset compensation value for the adjustment additional value; and if the first intermediate value is less than the preset minimum value of the intermediate value, the adjustment additional value for the next control cycle is equal to the sum of the adjustment additional value for the previous control cycle and the preset compensation value for the adjustment additional value; The first sub-duty cycle is calculated according to a second preset calculation formula; wherein the second preset calculation formula is: the first sub-duty cycle = (the input current value + the input voltage value * the adjustment additional value of the next control cycle) / the second intermediate value.

3. The method according to claim 1, characterized in that The determining a first sub-duty cycle according to the second regulated voltage value, the input voltage value, the input current value, and the output voltage sampling value includes: Obtaining the adjustment additional value of the previous control cycle and calculating a first intermediate value according to a first preset calculation formula; wherein the first preset calculation formula is: first intermediate value = (second adjustment voltage value + adjustment additional value of the previous control cycle) * output voltage sampling value; comparing the first intermediate value with a preset minimum value of intermediate values, and determining a second intermediate value based on the comparison result; wherein, if the first intermediate value is less than the preset minimum value of the intermediate value, the second intermediate value is equal to the preset minimum value of the intermediate value; and if the first intermediate value is greater than the preset minimum value of the intermediate value, the second intermediate value is equal to the first intermediate value; determining a feedback adjustment value according to the first intermediate value and the preset minimum value; Summing the feedback adjustment value and the initial value of the adjustment additional value to obtain the adjustment additional value of the next control cycle; The first sub-duty cycle is calculated according to a second preset calculation formula; wherein the second preset calculation formula is: the first sub-duty cycle = (the input current value + the input voltage value * the adjustment additional value of the next control cycle) / the second intermediate value.

4. The method according to claim 1, wherein The determining a second sub-duty cycle according to the second regulated voltage value, the input voltage value, and the input current value includes: The resonant input voltage value is calculated according to a third preset calculation formula; wherein the third preset calculation formula is: the resonant input voltage value = the input voltage value * the second adjustment voltage value - the input current value; Obtaining a preset resonance gain, and determining a resonance output voltage value according to the resonance input voltage value and the preset resonance gain; The second sub-duty cycle is calculated according to a fourth preset calculation formula; wherein the fourth preset calculation formula is: the second sub-duty cycle=the first preset constant*the resonant output voltage value.

5. The method according to claim 4, characterized in that The obtaining of the preset resonance gain and determining the resonance output voltage value according to the resonance input voltage value and the preset resonance gain includes: Obtaining the number of resonant frequency points of the PFC main loop, the frequencies corresponding to each of the resonant frequency points, the resonant bandwidth, and a second preset constant; Determining a first constant value and a second constant value corresponding to each of the resonant frequency points according to the frequency, the resonant bandwidth, and the second preset constant of each of the resonant frequency points; The calculation formula of the first constant value is: the first constant value = 2*(the square of the frequency of the resonant frequency point - the square of the second preset constant) / (the square of the frequency of the resonant frequency point + 2*resonant bandwidth*the second preset constant + the square of the second preset constant); The calculation formula of the second constant value is: the second constant value = (the square of the frequency of the resonant frequency point - 2*resonant bandwidth*the second preset constant + the square of the second preset constant) / (the square of the frequency of the resonant frequency point + 2*resonant bandwidth*the second preset constant + the square of the second preset constant); Obtaining the resonant input voltage value of the previous control cycle, and the sub-resonant output voltage value of the previous control cycle and the sub-resonant output voltage value of the previous control cycle corresponding to each of the resonant frequency points, and calculating the sub-resonant output voltage value corresponding to each of the resonant frequency points according to a fifth preset calculation formula; wherein the fifth preset calculation formula is: the sub-resonant output voltage value = the preset gain * (the resonant input voltage value - the resonant input voltage value of the previous control cycle) - the first constant value * the sub-resonant output voltage value of the previous control cycle - the second constant value * the sub-resonant output voltage value of the previous control cycle; The sub-resonance output voltage values ​​corresponding to the respective resonant frequency points are summed to obtain the resonant output voltage value.

6. The method according to claim 1, characterized in that The obtaining of the output current sampling value and the input voltage value of the PFC circuit, and determining the feedforward control amount according to the output voltage sampling value, the output current sampling value, and the input voltage value, includes: The feedforward control amount is calculated according to a sixth preset calculation formula; the sixth preset calculation formula is: feedforward control amount = (output voltage sampling value * output current sampling value) / (input voltage value * input voltage value); wherein the input voltage value, the output voltage sampling value, and the output current sampling value are filtered values.

7. A single-cycle control device for a PFC circuit, characterized in that: The device further comprises: an acquisition unit, the acquisition unit being configured to acquire a first regulated voltage value output by a voltage loop controller; wherein the voltage loop controller may acquire a preset output voltage value and an output voltage sample value of a PFC main loop, and use a difference between the preset output voltage value and the output voltage sample value of the PFC main loop as input to output the first regulated voltage value; The acquisition unit is further configured to acquire a preset output voltage value, an output voltage sampling value, an output current sampling value, an input voltage value, and an input current value of the PFC main circuit; a processing unit, configured to determine a feedforward control amount according to the output voltage sampling value, the output current sampling value, and the input voltage value; The processing unit is configured to sum the first regulating voltage value and the feedforward control variable to obtain a second regulating voltage value; The processing unit is configured to determine a first sub-duty cycle according to the second regulated voltage value, the input voltage value, the input current value, and the output voltage sample value; determine a second sub-duty cycle according to the second regulated voltage value, the input voltage value, and the input current value; and obtain the duty cycle by summing the first sub-duty cycle and the second sub-duty cycle; a generating unit, configured to generate a pulse width modulation signal according to the duty cycle; A control unit is used to adjust and control the PFC main loop according to the pulse width modulation signal.

8. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, the programs including instructions for executing the steps in the method according to any one of claims 1 to 6, or the programs including instructions for the steps of the apparatus according to claim 7.

9. A computer-readable storage medium, characterized in that A computer program for electronic data exchange is stored, wherein the computer program causes a computer to execute the method according to any one of claims 1 to 6.

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