Abnormality detection circuit and abnormality detection method
By generating and verifying the key value in the CPU's exception detection circuit to ensure its uniqueness and logical consistency, the problem of insufficient monitoring function in the prior art is solved, and the effect of monitoring program sequences in time and logic is achieved.
Patent Information
- Application Number
- CN202080086862.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-02-27
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2040-02-27
AI Technical Summary
In the prior art, when the CPU's abnormality detection circuit monitors the program sequence, periodic repetition of the key value and the direct use of the count value as the key value leads to insufficient monitoring function, and when other bus masters such as the debugger intervene, the key value may change, resulting in the watchdog timer counter being unable to be reset.
An exception detection circuit is designed to ensure the uniqueness and logical consistency of the key value when the counter is not reset, thereby monitoring the program sequence time and logic. The circuit includes a seed value storage unit, an calculator, a key value storage unit and a comparator. It generates a key value by performing a calculation process on the seed value, and verifies it when the key value is written to ensure that the counter is reset in an abnormal situation.
The function of monitoring program sequences in time and logic is realized, improving the accuracy and stability of monitoring, and avoiding the problem of key value changes caused by interventions such as debuggers.
Smart Images
Figure CN114830093B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an abnormality detection circuit and an abnormality detection method for detecting abnormality of a CPU. Background Art
[0002] As an abnormality detection circuit for detecting abnormality of a CPU, a watchdog timer is known. The watchdog timer detects abnormality of the CPU when the count value reaches a set timeout value without being reset by the CPU.
[0003] A scheme for using a key value when resetting a counter by a CPU has been proposed (for example, see Patent Documents 1 and 2). In Patent Document 1, a value obtained by performing a calculation on the key value used in the reset is used as the key value to be used next. In Patent Document 2, the count value of the counter is used as the key value to be used next.
[0004] Prior art literature
[0005] Patent Literature
[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 01-147643
[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 11-306047 Summary of the invention
[0008] Problems to be solved by the invention
[0009] However, in Patent Document 1, as a function of monitoring the program sequence, the function of performing logical monitoring is satisfied, but the value used as the key is a repeated value with a certain period, and if the previous key is determined, the next key is uniquely determined. Therefore, there is a problem that the next key does not change according to the operation status of the program sequence, and the monitoring function of the program sequence is weak.
[0010] In addition, in Patent Document 2, the key value is different depending on the timing of reading the count value, so randomness is obtained according to the operation status of the program sequence, but since the read value is used as the key value, there is no logical process processing, and the monitoring function of performing logical monitoring of the program sequence is insufficient. In addition, since the read count value is directly set as the key value, if the debugger or other bus master reads the register before the count value read by the CPU is written as the key value, the key value will change and the counter of the watchdog timer will not be reset.
[0011] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an abnormality detection circuit and an abnormality detection method capable of monitoring a program sequence temporally and logically.
[0012] Means for solving problems
[0013] In order to achieve the above-mentioned object, the abnormality detection circuit and the abnormality detection method of the present invention are constructed as follows.
[0014] The abnormality detection circuit of the present invention has a counter that counts from an initial value to a timeout value, and detects an abnormality of the CPU when the counter is not reset and the count value reaches the timeout value. The abnormality detection circuit is characterized in that it comprises: a seed value storage unit, which stores the seed value in a manner that can be read by the CPU; an operator, which generates a verification key value by performing a prescribed operation on the seed value stored in the seed value storage unit; a key value storage unit, to which the key value is written by the CPU; and a comparator, which compares the key value written to the key value storage unit with the verification key value, and when the key value written to the key value storage unit is consistent with the verification key value, the counter is reset, and the seed value determined when the counter is reset is stored in the seed value storage unit.
[0015] In addition, the abnormality detection method of the present invention utilizes a counter to count from an initial value to a timeout value, and detects a CPU abnormality when the counter is not reset and the count value reaches the timeout value. The method is characterized in that a seed value is stored in a seed value storage unit in a manner that can be read by the CPU, a verification key value is generated by an operator performing a prescribed operation on the seed value stored in the seed value storage unit, and the CPU waits for the key value to be written to the key value storage unit. A comparator compares the key value written to the key value storage unit with the verification key value. When the key value written to the key value storage unit is consistent with the verification key value, the counter is reset, and the seed value determined when the counter is reset is stored in the seed value storage unit.
[0016] Effects of the Invention
[0017] According to the abnormality detection circuit and the abnormality detection method of the present invention, the CPU needs to read the seed value and perform a series of actions such as the prescribed operation processing for different seed values and the writing of the key value each time before the count value reaches the timeout value, thereby achieving the effect of being able to monitor the program sequence in time and logic. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 This is a block diagram showing the structure of a microcomputer in which an abnormality detection circuit according to an embodiment of the present invention is built-in.
[0019] Figure 2 Yes means Figure 1 The timing diagram of the operation of the abnormality detection circuit shown in the figure is when there is a match and when there is a mismatch.
[0020] Figure 3 Yes means Figure 1 The timing diagram of the operation of the abnormality detection circuit during timeout is shown.
[0021] Figure 4 Yes means Figure 1 A block diagram of another configuration example of an abnormality detection circuit shown in FIG.
[0022] Figure 5 Yes means Figure 4 The timing diagram of the counting action of the free counter is shown.
[0023] Figure 6 Yes means Figure 1 A block diagram of another configuration example of an abnormality detection circuit shown in FIG. DETAILED DESCRIPTION
[0024] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.
[0025] Reference Figure 1 The abnormality detection circuit 10 of this embodiment is built in a microcomputer 1 having a CPU 2 for executing a program, a ROM 3 for storing the program executed by the CPU 2, and a RAM 4 as a work area of the CPU 2, and is formed on, for example, one semiconductor chip.
[0026] The abnormality detection circuit 10 is a watchdog timer that detects an abnormality of the CPU 2 when the count reaches a set count value without being reset by the CPU 2 , and is connected to the CPU 2 via the internal bus (BUS) 5 .
[0027] The abnormality detection circuit 10 has a bus interface (BUS_I / F) 11, a counter (COUNTER) 12, a seed value register (SEED) 13, an operator (CALCULATOR) 14, a write key register (WKEY) 15, a comparator (COMPARE) 16, a buffer (WRITE_KEY_BUF) 17, a first AND circuit 18, a second AND circuit 19, a first OR circuit 20 and a second OR circuit 21.
[0028] The counter 12 counts from an initial value (INITIAL_VALUE) at a predetermined clock, and outputs a count timeout signal (COUNT_TIMEOUT) when the count value reaches a set timeout value (TIMEOUT_VALUE).
[0029] In addition, when the reset counter signal (RESET_COUNTER) is input, the counter 12 resets the count value to the initial value and starts a new count. In addition, the reset counter signal (RESET_COUNTER) is input to the seed value register 13 as a seed value read signal (LOAD_SEED), and the count value of the counter 12 before reset is stored in the seed value register 13 as a seed value (SEED).
[0030] The seed value register 13 is configured to be read-accessible via the bus interface 11. The CPU 2 reads the seed value stored in the seed value register 13 before the count value of the counter 12 reaches the timeout value.
[0031] Regarding the seed value, the count value when the counter 12 is reset is stored in the seed value register 13. Therefore, the seed value changes according to the operation status of the program sequence. In addition, in the read access to the seed value register 13, no reading from the counter 12 occurs, so even if there is a read access to the seed value register 13 by another bus master controller, the seed value does not change.
[0032] The operator 14 generates a key value (CKEY) by performing a predetermined operation process on the seed value stored in the seed value register 13. For the predetermined operation process performed by the operator 14, an operation process that cannot generate a key value generated according to the seed value according to other seed values is applied. That is, the predetermined operation process is an operation process that sets the mapping from the seed value set to the key value set as a bijection, as the relationship between the seed value set of values that the seed value can take and the key value set of values that the key value can take. As a result, there is no same key value for different seed values, so the key value generated according to different seed values will not be valid, and the effectiveness of the function of performing logical monitoring is improved.
[0033] In addition, in the prescribed operation process, since the seed value and the key value correspond one-to-one, the bit width of the key value is set to be larger than the bit width of the seed value. That is, when the bit width of the key value is smaller than the bit width of the seed value, the same key may be generated from different seeds. Furthermore, in the prescribed operation process, it is set so that all bits of the seed value are used in the operation, and there are no unused bits.
[0034] The prescribed operation process is set as a combination of multiple operations, and bijection can be maintained in each operation. When the count value of the counter 12 and the key value (CKEY) are set to 32 bits, for example, the following formula combining bit swap, addition of fixed values (deleting the carry exceeding the bit width of the key value) and bit inversion (logical exclusive OR of fixed values) is applied as the prescribed operation process.
[0035] CKEY[31:0]=({SEED[7:0],SEED[31:8]}+0x85C421FE)^0x3486A8D7
[0036] The write key register 15 is configured to be write-accessible via the bus interface 11. The CPU 2 generates a key value (WKEY) by performing the same predetermined operation processing as the operation unit 14 on the seed value read from the seed value register 13, and writes the generated key value (WKEY) to the write key register 15 by outputting a write signal (WRITE_KEY) to the write key register 15 before the count value of the counter 12 reaches the timeout value.
[0037] The comparator 16 compares the key value (CKEY) calculated by the operator 14 with the key value (WKEY) written to the write key register 15, and outputs a comparison signal (COMP_KEY) which becomes HIGH (high level) when the two are consistent, and becomes LOW (low level) when the two are inconsistent.
[0038] The write signal (WRITE_KEY) is input to one input terminal of the first AND circuit 18 as a write buffer signal (WRITE_KEY_BUF) delayed by one clock via the buffer 17, and the comparison signal (COMP_KEY) output from the comparator 16 is input to the other inverting input terminal of the first AND circuit 18. Thus, when the key value (WKEY) written to the write key register 15 accompanying the write signal (WRITE_KEY) is inconsistent with the key value (CKEY) calculated by the operator 14, an inconsistent signal (UNMATCH KEY) is output from the output terminal of the first AND circuit 18.
[0039] The write signal (WRITE_KEY) to the write key register 15 is input to one input terminal of the second AND circuit 19 as a write buffer signal (WRITE_KEY_BUF) delayed by one clock via the buffer 17, and the comparison signal (COMP_KEY) output from the comparator 16 is input to the other input terminal of the first AND circuit 18. Thus, when the key value (WKEY) written to the write key register 15 accompanying the write signal (WRITE_KEY) matches the key value (CKEY) calculated by the operator 14, a match signal (MATCH_KEY) is output from the output terminal of the second AND circuit 19.
[0040] The count timeout signal (COUNT_TIMEOUT) output from the counter 12 is input to one input terminal of the first OR circuit 20, and the mismatch signal (UNMATCH_KEY) output from the first AND circuit 18 is input to the other input terminal of the first OR circuit 20. Thus, when either or both of the count timeout signal (COUNT_TIMEOUT) and the mismatch signal (UNMATCH_KEY) are input to the first OR circuit 20, an error signal (ERROR) is output from the output terminal of the first OR circuit 20 as a detection of abnormality of the CPU 2.
[0041] An error signal (ERROR) output from the first OR circuit 20 is input to one input terminal of the second OR circuit 21, and a match signal (MATCH_KEY) output from the second AND circuit 19 is input to the other input terminal of the second OR circuit 21. Thus, when either or both of the error signal (ERROR) and the match signal (UNMATCH_KEY) are input to the second OR circuit 21, a reset counter signal (RESET_COUNTER) is output from an output terminal of the second OR circuit 21.
[0042] Next, refer to Figure 2 The operation of the abnormality detection circuit 10 when the two conditions are consistent will be described.
[0043] In response to the write signal (WRITE_KEY) from the CPU 2, a key value (WKEY: 0xB1428929) is written to the write key register 15 at time t1. Then, the comparator 16 compares the key value (CKEY: 0xB1428929) generated by the operator 14 performing a predetermined operation on the seed value (SEED: 0x00000000) stored in the seed value register 13 with the key value (WKEY: 0xB1428929) written to the write key register 15.
[0044] Then, the key value (CKEY: 0xB1428929) and the key value (WKEY: 0xB1428929) are consistent, and the comparison signal (COMP_KEY) from the comparator 16 becomes HIGH, so the write buffer signal (WRITE_KEY_BUF) is output as the consistency signal (MATCH_KEY) from the output terminal of the second AND circuit 19. And the consistency signal (MATCH_KEY) is output as the reset counter signal (RESET_COUNTER) and the seed value read signal (LOAD_SEED) from the output terminal of the second OR circuit 21. Thus, the counter 12 resets the count value to the initial value, starts a new count, and the count value (0x0000A38D) before the reset of the counter 12 is stored in the seed value register 13 as the seed value (SEED: 0x0000A38D).
[0045] In this case, the CPU 2 can read the seed value from the seed value register 13, and perform a series of operations such as the prescribed operation processing for different seed values and writing the key value to the write key register 15 each time before the count value of the counter 12 reaches the timeout value, and can normally perform the prescribed operation processing for the seed value. Therefore, it is verified in terms of time and logic that the program sequence in the CPU 2 functions normally.
[0046] Next, refer to Figure 2 The operation of the abnormality detection circuit 10 when there is a mismatch will be described.
[0047] In response to the write signal (WRITE_KEY) from the CPU 2, a key value (WKEY: 0x12345678) is written to the write key register 15 at time t2. Then, the comparator 16 compares the key value (CKEY: 0x26428A76) generated by the operator 14 performing a predetermined operation on the seed value (SEED: 0x0000A38D) stored in the seed value register 13 with the key value (WKEY: 0x12345678) written to the write key register 15.
[0048] Then, since the key value (CKEY: 0xB1428929) and the key value (WKEY: 0xB1428929) do not match, the comparison signal (COMP_KEY) from the comparator 16 becomes LOW, and therefore, the write buffer signal (WRITE_KEY_BUF) is output as the mismatch signal (UNMATCH_KEY) from the output terminal of the first AND circuit 18. Furthermore, the mismatch signal (UNMATCH_KEY) is output as the error signal (ERROR) from the output terminal of the first OR circuit 20, and is output as the reset counter signal (RESET_COUNTER) and the seed value read signal (LOAD_SEED) from the output terminal of the second OR circuit 21. Thus, the counter 12 resets the count value to the initial value, starts a new count, and the count value (0x000002E5) before the reset of the counter 12 is stored in the seed value register 13 as the seed value (SEED: 0x000002E5).
[0049] In this case, the CPU 2 can read the seed value from the seed value register 13 and perform a series of operations such as a predetermined operation process for a different seed value and writing a key value to the write key register 15 each time before the count value of the counter 12 reaches the timeout value, but the predetermined operation process for the seed value cannot be performed normally. Therefore, it is detected that a logical abnormality has occurred in the program sequence of the CPU 2.
[0050] Next, refer to Figure 3 The operation of the abnormality detection circuit 10 at the time of timeout will be described.
[0051] When the count value reaches the set timeout value (TIMEOUT_VALUE) at time t3 without inputting the write signal (WRITE_KEY) from the CPU 2, the counter 12 outputs a count timeout signal (COUNT_TIMEOUT).
[0052] The count timeout signal (COUNT_TIMEOUT) is output as an error signal (ERROR) from the output terminal of the first OR circuit 20, and is output as a reset counter signal (RESET_COUNTER) and a seed value read signal (LOAD_SEED) from the output terminal of the second OR circuit 21. Thus, the counter 12 resets the count value to the initial value, starts a new count, and the count value (0x02000000) before the reset of the counter 12 is stored in the seed value register 13 as a seed value (SEED: 0x02000000).
[0053] In this case, the CPU 2 cannot perform a series of operations such as reading the seed value from the seed value register 13, executing a predetermined operation process for a different seed value each time before the count value of the counter 12 reaches the timeout value, and writing the key value to the write key register 15. Therefore, it is detected that the program sequence in the CPU 2 is abnormal in terms of time.
[0054] Figure 4 The abnormality detection circuit 10a shown is configured to include a free counter (FREE_COUNTER) 22 different from the counter 12, and when a seed value read signal (LOAD_SEED) is input to the seed value register 13, the count value of the free counter 22 is stored as a seed value (SEED).
[0055] like Figure 5 As shown, the free counter 22 counts sequentially between the initial value (INITIAL_VALUE) and the target value (TARGET_VALUE) based on a predetermined clock signal, and is not reset according to the reset counter signal (RESET_COUNTER) that resets the counter 12. In this example, it is necessary to add a structure such as the free counter 22, but the seed value (SEED) of each program sequence can be reliably set to a different value. That is, the following situation is assumed: when the CPU 2 performs a series of actions at the same time, the count value of the counter 12 reset by the reset counter signal (RESET_COUNTER) before resetting becomes the same value. In contrast, the free counter 22 is not reset according to the reset counter signal (RESET_COUNTER), so even if the CPU 2 performs a series of actions at the same time, the count value at the time of reset becomes a different value. In the free counter 22 , the count value between the initial value (INITIAL_VALUE) and the target value (TARGET_VALUE) is preferably set to a sufficiently large value, and may be set to a value greater than or equal to the count value between the initial value (INITIAL_VALUE) and the timeout value (TIMEOUT_VALUE) in the counter 12 .
[0056] Alternatively, a random number generator may be provided in place of the free counter 22 , and when a seed value read signal (LOAD_SEED) is input to the seed value register 13 , a random number generated by the random number generator may be stored as a seed value (SEED).
[0057] Furthermore, when there is an external circuit that functions as the free counter 22 or a random number generator, when the seed value read signal (LOAD_SEED) is input to the seed value register 13, the count value or random number of the external circuit may be stored as the seed value (SEED).
[0058] Figure 6 The abnormality detection circuit 10b shown is configured to omit the first AND circuit 18 and the first OR circuit 20, and even if the key value (WKEY) and the key value (CKEY) do not match, the error signal (ERROR) and the reset counter signal (RESET_COUNTER) are not output. In this case, only when the count value of the counter 12 reaches the timeout value (TIMEOUT_VALUE), the count timeout signal (COUNT_TIMEOUT) is output, and the error signal (ERROR) is output.
[0059] As described above, the present embodiment is an abnormality detection circuit 10, which has a counter 12 that counts from an initial value to a timeout value, and detects an abnormality of the CPU 2 when the counter 12 is not reset and the count value reaches the timeout value. The abnormality detection circuit 10 includes: a seed value register 13 as a seed value storage unit, which stores a seed value (SEED) in a manner that can be read by the CPU 2; an operator 14, which generates a key value (CKEY) for verification by performing a prescribed operation on the seed value stored in the seed value register 13; a write key register 15 as a key value storage unit, which is written by the CPU 2 with a key value (WKEY); and a comparator 16, which compares the key value (WKEY) written to the write key register 15 with the key value (CKEY) for verification, and when the key value (WKEY) written to the write key register 15 and the key value (CKEY) for verification are consistent, the counter 12 is reset, and the seed value (SEED) determined when the counter 12 is reset is stored in the seed value register 13.
[0060] According to this structure, CPU 2 needs to read the seed value from the seed value register 13 and perform a series of actions such as the prescribed operation processing for different seed values and the writing of the key value to the write key register 15 each time before the count value of the counter 12 reaches the timeout value, thereby being able to monitor the program sequence in terms of time and logic.
[0061] Furthermore, in this embodiment, in the prescribed operation processing performed by the operator 14, the relationship between the seed value set of values that the seed value (SEED) can take and the key value set of values that the verification key value (CKEY) can take is that the mapping from the seed value set to the key value set is a bijection.
[0062] According to this configuration, since the key value (WKEY) and the key value for verification (CKEY) do not match each other through different operation processes, the logical monitoring of the program sequence can be performed accurately.
[0063] Furthermore, in the present embodiment, the predetermined calculation process executed by the calculation unit 14 includes bit swapping.
[0064] According to this configuration, since the processing in software is more complicated than that in hardware, it is possible to accurately perform logical monitoring of the program sequence.
[0065] Furthermore, in the present embodiment, the count value at the time of resetting the counter 12 is stored in the seed value register 13 as a seed value (SEED).
[0066] According to this configuration, the count value of the counter 12 at the time of reset can be used as the seed value (SEED) without providing a new circuit for determining the seed value.
[0067] Furthermore, the present embodiment has a free counter 22. Even if the key value (WKEY) written into the write key register 15 is consistent with the key value (CKEY) used for verification, the free counter 22 is not reset. The count value of the free counter 22 when the counter 12 is reset is saved in the seed value register 13 as a seed value (SEED).
[0068] According to this configuration, even if the CPU 2 executes a series of operations at the same timing, the count value at the time of reset becomes a different value, and the program sequence can be logically monitored accurately.
[0069] Furthermore, the present embodiment includes a random number generator, and a random number generated by the random number generator when the counter 12 is reset is stored in the seed value register 13 as a seed value (SEED).
[0070] According to this configuration, even if the CPU 2 executes a series of operations at the same timing, the count value at the time of reset becomes a different value, and the program sequence can be logically monitored accurately.
[0071] Furthermore, in the present embodiment, a value determined by an external circuit when the counter 12 is reset is stored in the seed value register 13 as a seed value (SEED).
[0072] According to this configuration, it is possible to use a value determined by an external circuit as a seed value (SEED) without providing a circuit for determining a seed value within the circuit.
[0073] Furthermore, in the present embodiment, when the key value (WKEY) written to the write key register 15 does not match the key value (CKEY) for verification, the counter 12 continues counting without being reset.
[0074] According to this configuration, only when the count value of the counter 12 reaches the timeout value (TIMEOUT_VALUE), the error signal (ERROR) is output, and the error detection logic can be unified.
[0075] In addition, the present invention is not limited to the above-mentioned embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical concept of the present invention. In addition, the number, position, shape, etc. of the above-mentioned components are not limited to the above-mentioned embodiments, and can be set to the number, position, shape, etc. suitable for implementing the present invention. In addition, in each figure, the same reference numerals are marked on the same components.
[0076] Description of symbols
[0077] 1: microcomputer; 2: CPU; 3: ROM; 4: RAM; 5: internal bus; 10: abnormality detection circuit; 11: bus interface; 12: counter; 13: seed value register; 14: operator; 15: write key register; 16: comparator; 17: buffer; 18: first AND circuit; 19: second AND circuit; 20: first OR circuit; 21: second OR circuit; 22: free counter.
Claims
1. An abnormality detection circuit, comprising a counter that counts from an initial value to a timeout value, and detects an abnormality of a CPU when the count value reaches the timeout value without the counter being reset, wherein the abnormality detection circuit comprises: a seed value storage unit for storing the seed value in a manner that can be read by the CPU; a computing unit that generates a verification key value by executing a predetermined computing process on the seed value stored in the seed value storage unit; A key value storage unit, into which the key value is written by the CPU; as well as a comparator for comparing the key value written into the key value storage unit with the verification key value, When the key value written to the key value storage unit is consistent with the verification key value, the counter is reset, and the seed value determined when the counter is reset is stored in the seed value storage unit, The count value of the counter when it is reset is stored in the seed value storage unit as the seed value.
2. An abnormality detection circuit, comprising a counter that counts from an initial value to a timeout value, and detects an abnormality of a CPU when the count value reaches the timeout value without the counter being reset, wherein the abnormality detection circuit comprises: a seed value storage unit for storing the seed value in a manner that can be read by the CPU; a computing unit that generates a verification key value by executing a predetermined computing process on the seed value stored in the seed value storage unit; A key value storage unit, into which the key value is written by the CPU; as well as a comparator for comparing the key value written into the key value storage unit with the verification key value, When the key value written to the key value storage unit is consistent with the verification key value, the counter is reset, and the seed value determined when the counter is reset is stored in the seed value storage unit, The abnormality detection circuit includes a free counter which is not reset even if the key value written to the key value storage unit matches the verification key value. The count value of the free counter when the counter is reset is stored in the seed value storage unit as the seed value.
3. An abnormality detection circuit, comprising a counter that counts from an initial value to a timeout value, and detects an abnormality of a CPU when the count value reaches the timeout value without the counter being reset, wherein the abnormality detection circuit comprises: a seed value storage unit for storing the seed value in a manner that can be read by the CPU; a computing unit that generates a verification key value by executing a predetermined computing process on the seed value stored in the seed value storage unit; A key value storage unit, into which the key value is written by the CPU; as well as a comparator for comparing the key value written into the key value storage unit with the verification key value, When the key value written to the key value storage unit is consistent with the verification key value, the counter is reset, and the seed value determined when the counter is reset is stored in the seed value storage unit, The abnormality detection circuit has a random number generator, The random number generated by the random number generator when the counter is reset is stored in the seed value storage unit as the seed value.
4. An abnormality detection circuit, comprising a counter that counts from an initial value to a timeout value, and detects an abnormality of a CPU when the count value reaches the timeout value without the counter being reset, wherein the abnormality detection circuit comprises: a seed value storage unit for storing the seed value in a manner that can be read by the CPU; a computing unit that generates a verification key value by executing a predetermined computing process on the seed value stored in the seed value storage unit; A key value storage unit, into which the key value is written by the CPU; as well as a comparator for comparing the key value written into the key value storage unit with the verification key value, When the key value written to the key value storage unit is consistent with the verification key value, the counter is reset, and the seed value determined when the counter is reset is stored in the seed value storage unit, A value determined by an external circuit when resetting the counter is stored in the seed value storage unit as the seed value.
5. The abnormality detection circuit according to any one of claims 1 to 4, characterized in that: In a predetermined operation process executed by the operator, a relationship between a seed value set of possible values for the seed value and a key value set of possible values for the verification key value is formed such that a mapping from the seed value set to the key value set is a bijection.
6. The abnormality detection circuit according to any one of claims 1 to 4, characterized in that: The predetermined calculation process executed by the calculation unit includes bit swapping.
7. The abnormality detection circuit according to any one of claims 1 to 4, characterized in that: When the key value written to the key value storage unit does not match the verification key value, the counter continues counting without being reset.
8. A microcomputer, characterized in that: The device comprises: the abnormality detection circuit according to any one of claims 1 to 7; and the CPU.
9. An abnormality detection method, comprising: using a counter to count from an initial value to a timeout value, and detecting a CPU abnormality when the counter is not reset and the count value reaches the timeout value, wherein: storing the seed value in the seed value storage unit in a manner that can be read by the CPU, The verification key value is generated by executing a predetermined calculation process on the seed value stored in the seed value storage unit by a calculation unit, Waiting for the CPU to write the key value into the key value storage unit, The key value written into the key value storage unit is compared with the verification key value by a comparator, When the key value written to the key value storage unit is consistent with the verification key value, the counter is reset, and the seed value determined when the counter is reset is stored in the seed value storage unit, The count value of the counter when it is reset is stored in the seed value storage unit as the seed value.
Citation Information
Patent Citations
Watchdog timer
JP1989147643A
Runaway detecting device
JP1999306047A
Method and apparatus for detecting a fault condition in a computer processor
US6654905B1