Method for fabricating resonant cavities and distributed Bragg reflector mirrors for vertical cavity surface emitting lasers on the wings of epitaxial lateral overgrowth regions

Abstract

A method for producing high-quality, manufacturable apertures for light-emitting elements such as vertical-cavity surface-emitting lasers (VCSELs) using epitaxial lateral overgrowth (ELO). Strips comprising island-shaped III-nitride semiconductor layers are grown on a substrate using a growth-limiting mask, and the island-shaped III-nitride semiconductor layers are fabricated into a light-emitting resonant cavity having a minimum length across the strip. The apertures of the resonant cavity are also fabricated along the minimum length of the strip on the wing regions of the ELO. Distributed Bragg reflectors (DBRs) are fabricated as reflectors of the resonant cavity on the bottom and top of the ELO wing regions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit pursuant to 35 USC § 119(e) of the following co-pending and commonly assigned applications:

[0003] U.S. Provisional Application Serial No. 62 / 924,756, filed October 23, 2019, by Srinivas Gandrothula, Takeshi Kamikawa, and Masahiro Araki, entitled “METHOD OF FABRICATING A RESONANT CAVITY AND DISTRIBUTED BRAGG REFLECTOR MIRRORS FOR A VERTICAL CAVITY SURFACEEMITTING LASER ON A WING OF AN EPITAXIAL LATERAL OVERGROWTH REGION,” attorney docket No. G&C 30794.0745USP1 (2020-071-1);

[0004] This application is incorporated herein by reference.

[0005] This application is related to the following co-pending and co-assigned applications:

[0006] U.S. Utility Patent Application Serial No. 16 / 608,071, filed October 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE,” attorney docket No. 30794.0653USWO (UC 2017-621-2), which claims patent under 35 U.S.C. § 365(c) to U.S. Utility Patent Application Serial No. 16 / 608,071, filed October 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled “METHOD OF REMOVING ASUBSTRATE,” attorney docket No. 30794.0653WOU1 (UC 2017-621-2), which claims patent under 35 U.S.C. § 365(c) to U.S. Utility Patent Application Serial No. 16 / 608,071, filed October 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled “METHOD OF REMOVING ASUBSTRATE,” attorney docket No. 30794.0653WOU1 (UC No. PCT / US18 / 31393, filed on May 5, 2017, and entitled “METHOD OF REMOVING ASUBSTRATE,” filed by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, and having attorney docket number 30794.0653USP1 (UC 2017-621-1), which claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Patent Application Serial No. 62 / 502,205, filed on May 5, 2017, and entitled “METHOD OF REMOVING ASUBSTRATE,” by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen;

[0007] U.S. Utility Patent Application Serial No. 16 / 642,298, filed February 26, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” attorney docket No. 30794.0659USWO (UC 2018-086-2), which claims patent rights under 35 U.S.C. § 365(c) to U.S. Utility Patent Application Serial No. 16 / 642,298, filed February 26, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” attorney docket No. 30794.0659WOU1 (UC 2018-086-2), filed September 17, 2018 No. PCT / US18 / 51375, filed on September 15, 2017, and entitled “METHOD OF REMOVING ASUBSTRATE WITH A CLEAVING TECHNIQUE,” filed by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, and having attorney docket number 30794.0659USP1 (UC 2018-086-1);

[0008] U.S. Utility Patent Application Serial No. 16 / 978,493, filed on September 4, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OFFABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERALOVERGROWTH,” attorney docket No. 30794.0680USWO (UC 2018-427-2), which claims patent rights under 35 U.S.C. § 365(c) to U.S. Utility Patent Application Serial No. 16 / 978,493, filed on September 4, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERALOVERGROWTH,” filed on April 1, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li No. PCT / US19 / 25187, attorney docket no. 30794.0680WOU1 (UC 2018-427-2), which claims the benefit of co-pending and commonly assigned PCT International Patent Application Serial No. PCT / US19 / 25187, filed on March 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH,” attorney docket no. G&C 30794.0680USP1 (UC 2018-427-1) and the benefit of co-pending and commonly assigned U.S. Provisional Patent Application Serial No. 62 / 650,487;

[0009] U.S. Utility Patent Application Serial No. 17 / 048,383, filed October 16, 2020, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE REDEVICES,” attorney docket No. 30794.0681USWO (UC 2018-605-2), which claims patent under 35 U.S.C. § 365(c) to U.S. Utility Patent Application Serial No. 17 / 048,383, filed October 16, 2020, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE REDEVICES,” attorney docket No. 30794.0681USWO (UC 2018-605-2), which claims patent under 35 U.S.C. § 365(c) to U.S. Utility Patent Application Serial No. 17 / 048,383, filed October 16, 2020, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE No. PCT / US19 / 32936, filed on May 17, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING ABAR OF ONE OR MORE DEVICES,” attorney docket No. G&C 30794.0681USP1 (UC 2018-605-1), and commonly assigned;

[0010] PCT International Patent Application Serial No. PCT / US19 / 34868, filed May 30, 2019, by Srinivas Gandrothula and Takeshi Kamikawa, entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE,” attorney docket No. G&C 30794.0682WOU1 (UC 2018-614-2), which claims unconditional right under 35 U.S.C. section 119(e) to an application filed May 30, 2018, by Srinivas Gandrothula and Takeshi Kamikawa, entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE,” attorney docket No. G&C 30794.0682USP1 (UC 2018-614-2). 2018-614-1) to the benefit of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 677,833;

[0011] PCT International Patent Application Serial No. PCT / US19 / 59086, filed on October 31, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH,” attorney docket No. G&C 30794.0693WOU1 (UC 2019-166-2), which claims patent under 35 U.S.C. Section 119(e) to PCT International Patent Application Serial No. PCT / US19 / 59086, filed on October 31, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH,” attorney docket No. G&C benefit of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 753,225, which is 30794.0693USP1 (UC 2019-166-1);

[0012] PCT International Patent Application Serial No. PCT / US20 / 13934, filed January 16, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH,” attorney docket No. G&C 30794.0713WOU1 (UC 2019-398-2), which claims patent under 35 U.S.C. section 119(e) to PCT International Patent Application Serial No. PCT / US20 / 13934, filed January 16, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH,” attorney docket No. G&C 30794.0713USP1 (UC 2019-398-2), which claims patent under 35 U.S.C. section 119(e) to PCT International Patent Application Serial No. PCT / US20 / 13934, filed January 16, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH,” attorney docket No. G&C 30794.0713USP1 (UC 2019-398-1) and the benefit of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 793,253;

[0013] PCT International Patent Application Serial No. PCT / US20 / 20647, filed March 2, 2020, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR FLATTENING A SURFACE ON AN Epitaxial Lateral Growth Layer,” attorney docket No. G&C 30794.0720WOU1 (UC 2019-409-2), which claims unconditional right under 35 U.S.C. section 119(e) to an application filed March 1, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER,” attorney docket No. G&C benefit of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 812,453, which is 30794.0720USP1 (UC 2019-409-1);

[0014] PCT International Patent Application Serial No. PCT / US20 / 22735, filed March 13, 2020, by Takeshi Kamikawa, Masahiro Araki, and Srinivas Gandrothula, entitled “SUBSTRATE FOR REMOVAL OF DEVICES USING VOID PORTIONS,” attorney docket No. G&C 30794.0722WOU1 (UC 2019-412-2), which claims patent rights under 35 U.S.C. § 119(e) to PCT International Patent Application Serial No. PCT / US20 / 22735, filed March 13, 2020, by Takeshi Kamikawa, Masahiro Araki, and Srinivas Gandrothula, entitled “SUBSTRATE FOR REMOVAL OF DEVICES USING VOID PORTIONS,” attorney docket No. G&C the benefit of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 817,757, which is 30794.0722USP1 (UC 2019-412-1); and

[0015] PCT International Patent Application Serial No. PCT / US20 / 22430, filed on March 12, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “SUBSTRATE FOR REMOVAL OF DEVICES USING VOID PORTIONS,” attorney docket No. G&C 30794.0724WOU1 (UC 2019-416-1), which claims patent under 35 U.S.C. § 119(e) to an application filed on March 12, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “SUBSTRATE FOR REMOVAL OF DEVICES USING VOID PORTIONS,” attorney docket No. G&C benefit of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 817,216, which is 30794.0724USP1 (UC 2019-416-1);

[0016] All of these applications are incorporated herein by reference. Technical Field

[0017] The present invention relates to a method for fabricating a good quality light emitting aperture of a vertical cavity surface emitting laser (VCSEL) on the wing of an epitaxial lateral overgrowth (ELO) region. Background Art

[0018] There is a lot of interest in making VCSELs that meet the requirements of manufacturability, good quality, non-critical tolerances, optimal characteristics, and better yields. The work done by Kuramoto et al. (APEX, 11, 112101 (2018)) in developing epitaxial distributed Bragg reflectors (DBRs) and the work done by Hamaguchi et al. (APEX, 12, 044004 (2019)) in developing a curved mirror approach on the substrate side are some examples of the industry's interest in higher quality VCSEL devices.

[0019] In the case of visible region luminescent materials, group III nitride materials, i.e., materials having the chemical formula B w Al x Ga y In z N-based (B, Al, Ga, In)N semiconductors, where 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1, and w + x + y + z = 1, such as GaN, are essential for fabricating high-quality VCSELs. Alternatively, some approaches have used III-nitride templates on foreign substrates such as Si and sapphire. However, particularly for devices involving stimulated emission and smaller dimensional light-emitting regions, uniform epitaxy is recommended over heterogeneous epitaxy or heteroepitaxial growth to tolerate micron-scale defects.

[0020] In U.S. Patent No. 9,407,067 and U.S. Patent Application Publication No. 2019 / 0173263, as well as in the publication Phys. Status Solidi A 2016, 213, 1170-1176, Hamaguchi et al. mention fabricating light-emitting element holes on the ELO region; however, undesirable crystal quality between mass production and the length of the resonant cavity may affect the final characteristics of the device.

[0021] Furthermore, Hamaguchi et al. used a curved mirror approach, which still requires thinning the substrate to reduce absorption losses in the cavity, a process that can be difficult to control on an industrial scale. Furthermore, removing or thinning the substrate by chemical or mechanical polishing would be tedious and affect yield.

[0022] A robust method for removing a substrate after fabricating a light-emitting element on a substrate is presented in Takeshi et al. (APEX, Vol. 27, No. 17, pp. 24717-24723 (2019)) and in PCT International Patent Application No. PCT / US18 / 31293, filed May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, cross-referenced above, and entitled “METHOD OF REMOVING A SUBSTRATE.” The method is used as an example of removing a substrate after fabricating a light-emitting element on the substrate.

[0023] Nevertheless, there remains a need in the art for improved methods of manufacturing VCSELs (including resonant cavities and reflective mirrors of the resonant cavities). The present invention satisfies this need. Summary of the Invention

[0024] To overcome the limitations of the prior art discussed above, and to overcome other limitations that will become apparent upon reading and understanding this specification, the present invention discloses a method for making good quality holes for a device, such as a VCSEL, that emits light perpendicular to a substrate from which the device is epitaxially fabricated.

[0025] Specifically, the present invention proposes a method for producing high-quality VCSEL device designs using a combination of epitaxial lateral overgrowth and mechanical exfoliation. Furthermore, the present invention provides a method for addressing yield and bad pixel issues associated with display applications, where improved VCSEL quality and faster communication are required. The present invention also proposes a processing method for integrating or mass-producing VCSELs by assembling or packaging them in pre-assembled strips.

[0026] Key aspects of the present invention include:

[0027] The device’s light-emitting aperture is fabricated on the wing region of the ELO III-nitride layer; therefore, the device is designed to have better crystal quality in terms of defects and stacking faults than device apertures fabricated directly on the native substrate.

[0028] The VCSEL's cavity length can be controlled epitaxially, rather than using complex thinning techniques or chemical methods on the native substrate.

[0029] • At least one DBR mirror of the cavity is placed on a wing of the ELO III-nitride layer, and after separating the ELO III-nitride layer from its native substrate, the at least one DBR mirror may be placed on the back side of the ELO III-nitride layer.

[0030] The substrate can be recycled for the next batch of device manufacturing.

[0031] • This method is independent of the crystal orientation of the native substrate.

[0032] In the present invention, the surface of the DBR mirror for resonant cavity VCSEL is prepared using only a growth confinement mask.

[0033] When a long resonant cavity of a VCSEL is required, the present invention can be used to make a curved reflector.

[0034] • The present invention includes a method for achieving stress relaxation of an ELO III-nitride layer by placing a DBR mirror after removing the ELO III-nitride layer from its host substrate to produce a crack-free and long-life device 111.

[0035] Some possible designs using this approach are described in the following description.When combined with the above cross-referenced inventions relating to removing semiconductor devices from semiconductor substrates, the present invention has a number of advantages over conventionally manufacturable device elements.

[0036] In one embodiment, the present invention performs the following steps: growing an island-shaped III-nitride semiconductor layer on a substrate using a growth confinement mask and an ELO method; wherein the growth confinement mask occupies at least 50% or more of a single device. The ELO region represents an area with reduced dislocation density compared to areas not covered by the ELO. The light-emitting aperture of the VCSEL is confined to the wings of the ELO region, thereby forming an aperture of good crystal quality. The resonant cavity and DBR reflector of the VCSEL device are fabricated on the wings of the ELO region, as well as on the top and bottom of the ELO region wings, respectively.

[0037] The interface between the growth confinement mask surface and the ELO region is smooth enough to fabricate a light-reflecting DBR mirror without requiring harsh chemical treatments. The island-shaped III-nitride semiconductor layer is removed from the substrate, and another DBR mirror is placed on the backside of the ELO III-nitride layer, which is the interface between the growth confinement mask and the ELO III-nitride layer.

[0038] The ELO method for forming an island-shaped III-nitride semiconductor layer can include growth by metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), etc. To precisely control the thickness, thereby precisely controlling the cavity length of the VCSEL device. The dimensions of the III-nitride semiconductor layer are such that one or more of the island-shaped III-nitride semiconductor layers form a strip (referred to as a semiconductor strip or device strip). By doing so, nearly identical devices can be manufactured adjacent to each other in a self-assembled array, so that they can be more easily scaled up through integration. Alternatively, the ELO III-nitride layers can be initially agglomerated so that they can be separated into device strips or individual chips later.

[0039] By designing an appropriate manufacturing process, each device in such a strip can be addressed individually or in combination with other devices. For example, a common cathode or anode can be fabricated for a monolithically integrated strip of such devices, or individual devices can be addressed for full-color display applications. Consequently, high yields can be achieved.

[0040] In addition, the present invention can use a foreign substrate to grow the island-shaped III-nitride semiconductor layer forming the strip. For example, the present invention can use a GaN template grown on a foreign substrate such as sapphire, Si, GaAs, SiC, etc.

[0041] In addition, the ELO method can significantly reduce the dislocation density and stacking fault density, which are critical issues when using heterogeneous substrates.

[0042] Therefore, the present invention can simultaneously solve multiple problems caused by using a foreign substrate.For example, in a laser device, the interface between the growth confinement mask and the ELO III-nitride layer can be used as a facet of the resonator. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Referring now to the drawings, wherein like reference numerals designate corresponding parts throughout:

[0044] FIG1(a) is a schematic diagram of a substrate, a growth restriction mask, and an epitaxial layer according to an embodiment of the present invention.

[0045] FIG1(b) shows an enlarged view of the device layer on the island-shaped III-nitride semiconductor layer, and

[0046] FIG1(c) is a top view of a strip of a device fabricated on an island-shaped Group III nitride semiconductor layer.

[0047] Figure 2(a) 、 2(b) , 2(c), 2(d), 2(e), and 2(f) are schematic diagrams of when the ELO III-nitride layer coalesces with the adjacent ELO III-nitride layer from each adjacent open region.

[0048] Figure 3(a) 、 3(b) , 3(c), 3(d), 3(e), and 3(f) show a new device design when a light-reflecting DBR mirror of the VCSEL cavity is embedded between two ELO III-nitride layers.

[0049] Figure 3(g) 、 3(h) , 3(i), 3(j), and 3(k) are potential designs of embedded DBR reflectors, and

[0050] Figure 3(l) and 3(m) They are Figure 3(j) and 3(k) A magnified version of .

[0051] Figure 4(a) 、 4(b) 4(c), 4(d), and 4(e) are cross-sectional views of a process for obtaining a concave patch on a III-nitride substrate, wherein the patch can be used to form a curved light-reflecting mirror on the n-side by allowing the III-nitride ELO III-nitride layer to flow from an opening region into a designed shape,

[0052] FIG4(f) is a cross-sectional view of an island-shaped III-nitride semiconductor layer formed on a processed substrate, and

[0053] FIG4( g ) shows a VCSEL device fabricated using this substrate.

[0054] Figure 5(a) 、 5(b) 5(c) and 5(d) are cross-sectional views of a process for obtaining an irregular (rectangular, pyramidal, etc.) shaped patch on a III-nitride substrate, wherein the patch can be used to form a light-reflecting mirror of a designed shape on the n-side by allowing the III-nitride ELO III-nitride layer to flow from an open area into the designed shape,

[0055] FIG5(e) is a cross-sectional view of an island-shaped group III nitride semiconductor layer formed on a processed substrate.

[0056] FIG5(f) is a VCSEL device manufactured using the substrate prepared in step FIG5(d).

[0057] FIG5( g ) is a patterned master substrate having a two-period growth confinement mask structure in the form of stripes, wherein the recesses near the opening regions contribute to the formation of a patterned-shaped ELO III-nitride layer.

[0058] Figure 5(h) is a patterned master substrate in patch form, and

[0059] FIG5(i) is a graphical representation of when the device layer is formed on a pre-patterned master substrate.

[0060] FIG6(a) shows how partitioned regions are formed with periodic lengths along the strips of the device according to one embodiment of the present invention.

[0061] Figure 6(b) 、 6(c) and 6(d) show how the support plate is attached to the strip of the device, and

[0062] FIG6(e) is a cross-sectional view of a support plate having a finger-like structure for attaching and gripping an island-shaped Group III nitride semiconductor layer.

[0063] FIG7( a ) shows a possible method of removing the ELO III-nitride layer using the hook technique.

[0064] FIG7( b ) shows a coalesced or non-coalesced structure for hook technology.

[0065] FIG7( c ) shows a selective etching mask arrangement, wherein two types of etching masks are shown,

[0066] Figure 7(d) shows a type-1 etch to separate the III-nitride layer chip, where the hook comes from the open ELO window.

[0067] Figure 7(e) shows a type-2 etch, where an optical microscope image shows a III-nitride layer chip sandwiched between a growth confinement mask and an etch mask.

[0068] Figure 7(f) shows the III-nitride layer sandwiched between the growth limit mask and the etch mask in step 2, and the placement of the fixed chip layer in step 3,

[0069] FIG7( g) shows a fixed chip layer that is selectively etched to obtain hook pattern 1, hook pattern 2, and hook pattern 3,

[0070] FIG7(h) shows optical and scanning electron microscope images of a pattern 3 hook-type III-nitride layered chip.

[0071] Figure 7(i) shows the unique curved mirror VCSEL structure process on the n-side epitaxial layer, and

[0072] FIG7( j ) shows a double-clad FP laser structure using the hook process.

[0073] Figure 8(a) shows the image of the c-plane ELO III-nitride layer growth and interface surface morphology measurement after removal,

[0074] Figure 8(b) shows images of the semi-polar 20-21 plane ELO III-nitride layer growth and interface surface morphology measurement after removal, and

[0075] Figure 8(c) and 8(d) Shown are images of non-polar 10-10 planar ELO III-nitride layer growth and interface surface morphology measurements after removal of two different growth-limiting mask patterns.

[0076] Figure 9(a) 、 9(b) , 9(c), 9(d) and 9(e) show the interface of controlling the bottom of the ELO III-nitride layer for fabricating a DBR mirror of a resonant cavity VCSEL.

[0077] 9( f ​​) is an optical microscope image of a 20-2-1ELO III-nitride layer grown on various masks, FIG. 9( g ) is an optical microscope image of a 20-2-1ELO III-nitride layer removed on an adhesive film, and FIG. 9( h ) is an atomic force microscope (AFM) scan of the interface at the ELO wing of the removed 20-2-1ELO III-nitride layer.

[0078] FIG. 9( i ) is a graph of surface roughness at the interface of an ELO III-nitride layer with various types of masks.

[0079] Figure 10(a) 、 10(b) , 10(c), 10(d), 10(e) and 10(f) are different possible designs of VCSEL devices.

[0080] FIG10( g ) is a cross-sectional view of a single-hole VCSEL device having opposite side electrodes formed of island-shaped group III nitride semiconductor layers,

[0081] FIG10( h) is a cross-sectional view of a single-hole VCSEL device having the same side electrode formed of an island-shaped group III nitride semiconductor layer,

[0082] FIG10( i ) is a cross-sectional view of a single-hole VCSEL device having opposite side electrodes and an n-side curved reflector formed of an island-shaped group III nitride semiconductor layer.

[0083] FIG10( j) is a cross-sectional view of a single-hole VCSEL device having the same side electrode and an n-side curved reflector formed by an island-shaped group III nitride semiconductor layer.

[0084] FIG10( k ) is a cross-sectional view of a single-hole VCSEL device having opposite side electrodes and a p-side curved reflector formed of an island-shaped III-nitride semiconductor layer, and

[0085] FIG10( l ) is a cross-sectional view of a single-hole VCSEL device having the same side electrode and a p-side curved reflector formed of an island-shaped Group III nitride semiconductor layer.

[0086] Figure 11(a) 、 11(b) , 11(c), 11(d), 11(e), 11(f), 11(g) and 11(h) show a VCSEL manufacturing process on a non-agglomerated island-shaped III-nitride semiconductor layer according to one embodiment of the present invention, and

[0087] Figure 11(i) 、 11(j) and 11(k) show possible solutions when the aspect ratio of the non-coalesced ELO structure does not allow enough space to fabricate a VCSEL device.

[0088] Figure 12(a) 、 12(b) , 12(c), 12(d), 12(e), 12(f), 12(g), 12(h), 12(i), 12(j) and 12(k) illustrate a process for removing a strip of a device according to an embodiment of the present invention.

[0089] Figure 13(a) 、 13(b) and 13(c) are schematic diagrams of the effect of the growth confinement mask on the interface.

[0090] Figures 14(a), 14(b), 14(c), 14(d), 14(e), 14(f) and 14(g) illustrate a process flow for defining an n-side light reflecting layer after removing the strips of the device using a support plate, and also illustrate possible device designs when VCSEL devices fabricated on the wings and opening regions of the ELO III-nitride layer are included in the device design.

[0091] Figure 15(a) and 15(b) The process of dividing the device after the n-electrode formation is shown.

[0092] Figure 16(a) 、 16(b) , 16(c), 16(d), 16(e) and 16(f) show that the removed island-shaped Group III nitride semiconductor layer is placed on a heat sink.

[0093] Figure 17(a) 、 17(b) , 17(c) and 17(d) illustrate how wire bonds are attached to a device according to one embodiment of the present invention.

[0094] Figure 18(a) and 18(b)A moonlight integration or multi-color integration with a heat dissipation plate according to one embodiment of the present invention is shown.

[0095] Figure 19 A flow chart for integrating a VCSEL device into a display backplane or maximizing flux.

[0096] Figure 20(a) 、 20(b) , 20(c), 20(d) and 20(e) show the processes dedicated to integrating the various devices.

[0097] Figure 21(a) 、 21(b) , 21(c) and 21(d) show the process specifically for integrating the strips of devices.

[0098] Figure 22 One possible mass transfer technique using an ultraviolet (UV) sensitive carrier and a UV laser is shown.

[0099] Figure 23(a) 、 23(b) , 23(c), 23(d), 23(e) and 23(f) represent the processes used to fabricate the embedded DBR resonator VCSEL and scaled-up versions of possible designs.

[0100] FIG24(a) shows a growth confinement mask embedded by an ELO III-nitride layer, and

[0101] FIG. 24( b ) shows visible cracks in the surface of the ELO III-nitride layer.

[0102] Figure 25 is a flow chart illustrating a method of removing a strip including one or more devices from a substrate by bonding a support plate to the strip. DETAILED DESCRIPTION

[0103] In the following description of the preferred embodiments, reference is made to specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0104] Overview

[0105] The present invention describes a method for fabricating a light-emitting hole on or above the interface of an ELO III-nitride layer and fabricating a light-emitting element according to the following steps.

[0106] Specifically, the present invention discloses a method for manufacturing VCSELs that is intended to allow designs for mass production and better thermal characteristics. In addition to conventional planar DBR designs, the present invention can incorporate curved DBR reflectors on the p-side or n-side, or even embed DBR designs.

[0107] The present invention encompasses the following methods:

[0108] 1. Short cavity VCSEL with planar DBR mirror, where a better wing area can be obtained in case of short cavity VCSEL without unwanted crystal quality for hole placement.

[0109] 2. Long-cavity VCSELs with curved DBR mirrors, where the curved mirrors have the advantage of reducing diffraction losses by focusing the reflected light back into the aperture. Long cavities can be used for better thermal management, increasing lifetime, output power, and efficiency.

[0110] 3. Short or long cavity embedded light reflective DBR reflector design, better thermal performance. This approach avoids unwanted crystal quality due to agglomeration.

[0111] 4. A method for making good crystal quality, self-grown, curved or non-planar mirrors based on the ELO method for longer cavity VCSELs is simple and can be manufactured on an industrial level.

[0112] In the following example, a process for realizing a VCSEL is described.

[0113] Figure 1(a) 、 1(b) and 1(c) show a method comprising providing a III-nitride-based substrate 101, such as a bulk GaN substrate 101, wherein FIG1(a) is a schematic diagram of the substrate, the growth confinement mask, and the epitaxial layer, FIG1(b) shows an enlarged view of the device layer on the island-shaped III-nitride semiconductor layer, and FIG1(c) is a top view of a strip of a device fabricated on the island-shaped III-nitride semiconductor layer.

[0114] Growth restriction mask 102 is formed on or over GaN-based substrate 101. Specifically, growth restriction mask 102 is provided in direct contact with substrate 101, or is provided indirectly via an intermediate layer grown by MOCVD or the like, the intermediate layer being made of a Group III nitride-based semiconductor deposited on substrate 101.

[0115] The growth limiting mask 102 can be formed of an insulating film, such as a SiO2 film deposited on the base substrate 101 by chemical vapor deposition (CVD), sputtering, ion beam deposition (IBD), etc., wherein the SiO2 film is then patterned by photolithography and etching using a predetermined photomask to include an opening region 103 and a non-growth region 104 (which may be patterned or not).

[0116] An epitaxial III-nitride layer 105, such as a GaN-based layer 105, is grown on a GaN substrate 101 and a growth confinement mask 102 by ELO. Growth of the ELO III-nitride layer 105 occurs first in the opening regions 103 on the GaN-based substrate 101 and then laterally from the opening regions 103 on the growth confinement mask 102. The growth of the ELO III-nitride layer 105 at adjacent opening regions 103 may be stopped or interrupted before coalescing on top of the growth confinement mask 102. This interrupted growth results in a non-grown region 104 between adjacent ELO III-nitride layers 105.

[0117] Additional III-nitride semiconductor device layers 106 are deposited on or over ELO III-nitride layer 105 and may include active region 106a, p-type layer 106b, electron blocking layer (EBL) 106c, and cladding layer 106d, among other layers.

[0118] ELO III-nitride layer 105 includes one or more flat surface regions 107 and layer bending regions 108 at the edges of its adjacent non-growth regions 104. The width of flat surface regions 107 is preferably at least 5 μm, and most preferably 30 μm or greater.

[0119] ELO III-nitride layer 105 and additional III-nitride-based semiconductor device layer 106 separated by non-growth region 104 are referred to as island-shaped III-nitride semiconductor layers 109, which take the shape of stripes 110. The distance between island-shaped III-nitride semiconductor layers 109, that is, the width of non-growth region 104, is typically 20 μm or less, and preferably 5 μm or less, but is not limited to these values.

[0120] The growth of the island-shaped III-nitride semiconductor layer 109 is terminated before coalescence with its next adjacent layer, and by doing so, the ELO region of the island-shaped III-nitride semiconductor layer 109 is free from unwanted crystal defects caused by coalescence between the next adjacent layers because most of the defects originate from the opening region 103 and do not propagate to the top surface of the island-shaped III-nitride semiconductor layer 109.

[0121] As shown in FIG1( c ), the light-emitting apertures of the VCSEL devices 111 are processed on either side of the opening region 103 (preferably between the opening region 103 and the layer bending region 108). By doing so, each strip 110 can include one or more devices 111. For example, the strip 110 of FIG1( c ) includes an array of nearly identical light-emitting apertures for multiple devices 111 formed on either side of the opening region 103 along the length of the strip 110.

[0122] There are many methods for removing the strip 110 including the device 111 from the substrate 101. For example, the present invention can utilize an ELO method to remove the strip 110 of the device 111. Typically, the ELO method is utilized to reduce the defect density in the island-shaped III-nitride semiconductor layer 109.

[0123] In the ELO method for removing the strips 110 of the device 111, the bonding strength between the substrate 101 and the ELO III-nitride layer 105 is weakened by the growth restriction mask 102. In this case, the bonding region between the substrate 101 and the ELO III-nitride layer 105 is the opening region 103, wherein the width of the opening region 103 is narrower than that of the ELO III-nitride layer 105. Therefore, the growth restriction mask 102 reduces the bonding region, making this method preferable for removing the epitaxial layers 105, 106, 109.

[0124] In another embodiment, Figures 2(a)-2(f) As shown, the ELO III-nitride layers 105 are allowed to coalesce with each other. Specifically, Figure 2(a) 、 2(b) , 2(c), 2(d), 2(e), and 2(f) are diagrams when the ELO III-nitride layer 105 is coalesced with the adjacent ELO III-nitride layer 105 from each adjacent opening region 103.

[0125] After the ELO III-nitride layer 105 coalesces at region 201 in FIG. 2( a ), Figure 2(b) 、 2(c) , 2(d) and 2(e), and a subsequent III-nitride semiconductor device layer 106 is deposited. A light-emitting device 111 having holes is fabricated on the wing region of the ELO III-nitride layer 105 away from the coalescence region 201 and the opening region 103. The III-nitride semiconductor layers 105, 106, 109 can then be divided at 202 and 203, as shown in FIG. 2(f), for example, using dry etching or laser scribing.

[0126] Figure 3(a) 、 3(b), 3(c), 3(d), 3(e), and 3(f) show new device designs when one or more light-reflecting DBR mirrors of the resonant cavity of the VCSEL device 111 are embedded between two ELO III-nitride layers, Figure 3(g) 、 3(h) , 3(i), 3(j), and 3(k) are potential designs of embedded DBR reflectors, and Figure 3(l) and 3(m) They are Figure 3(j) and 3(k) A magnified version of .

[0127] In one embodiment, Figure 3(a)-3(m) As shown, a light-reflecting DBR mirror 301 is fabricated on substrate 101. The DBR mirror placement 301 is selected to reside on the wing region of the previously grown ELO III-nitride layer 105. A second epitaxial lateral overgrowth layer 302 is formed from a single open region between the two DBR mirrors 301 on either wing of the previously embedded ELO III-nitride layer 105. The later-grown ELO III-nitride layer 302 is again allowed to coalesce 303 and form the subsequent III-nitride device layer 106. As a result, an embedded DBR mirror 301 can be formed between the first ELO III-nitride layer 105 and the second ELO III-nitride layer 302. In addition, there is a current confinement region 304, a p-pad 305, a bonding layer 306, a carrier 307, a current confinement layer 308, a current spreading layer 309, an n-GaN layer 310, an n-pad 311 deposited to contact the n-GaN layer 310 on the opposite side of the interface 312, and a second DBR mirror 313.

[0128] Figure 4(a) 、 4(b) 4(c), 4(d), and 4(e) are cross-sectional views of a process for obtaining a concave patch on a III-nitride substrate 101, wherein the patch can be used to form a curved light-reflecting mirror on the n-side by allowing the III-nitride ELO III-nitride layer 105 to flow from the opening region 103 into a designed shape, FIG4(f) is a cross-sectional view of an island-shaped III-nitride semiconductor layer 109 formed on the processed substrate 101, and FIG4(g) is a VCSEL device 111 manufactured using the substrate 101. These figures will be described in more detail below.

[0129] Figure 5(a) 、 5(b), 5(c) and 5(d) are cross-sectional views of a process for obtaining an irregular (rectangular, conical, etc.) shaped patch on a III-nitride substrate 101, wherein the patch can be used to form a light-reflecting mirror of a designed shape on the n-side by allowing the ELO III-nitride layer 105 to flow from the opening region 103 into the designed shape, FIG5(e) is a cross-sectional view of an island-shaped III-nitride semiconductor layer 109 formed on the processed substrate 101, FIG5(f) is a VCSEL device 111 manufactured using the substrate 101 prepared in FIG5(d), FIG5(g) is a patterned master substrate 101 having a two-period growth restriction mask 102 structure in the form of a strip, wherein the recess near the opening region 103 helps to form the patterned shape of the ELO III-nitride layer 105, FIG5(h) is a patterned master substrate 101 in the form of a patch, and FIG5(i) is a graphical representation when the device layer 106 is formed on the pre-patterned master substrate 101. These figures are described in more detail below.

[0130] In one embodiment, Figures 4(a)-4(g) As shown in Figures 5(a)-5(i), the III-nitride substrate 101 is pre-processed to form a curved or irregularly shaped patch. Then, as previously described, an ELO III-nitride-based layer 105 is allowed to grow from the opening region 103. In this case, the grown ELO III-nitride layer 105 takes the shape of the mask 102 region, thereby forming a self-formed curved or irregular reflector for the resonant cavity of the long cavity VCSEL device 111.

[0131] The typical manufacturing steps of the present invention are described in more detail below:

[0132] Step 1: directly or indirectly forming a growth restriction mask 102 having a plurality of strip-shaped opening regions 103 on a substrate 101 , wherein the substrate 101 is a III-nitride-based semiconductor, or the substrate 101 is a heterogeneous substrate.

[0133] Step 2: Growing a plurality of epitaxial layers 105 , 106 and 109 on substrate 101 using growth restriction mask 102 such that the growth extends in a direction parallel to stripe-shaped opening regions 103 of growth restriction mask 102 , wherein ELO III-nitride layer 105 is not coalesced.

[0134] Step 3: A device 111 is fabricated by conventional methods at the ELO window region, which is mostly covered by the flat surface region 107 , wherein a light reflecting element structure (DBR), p-electrode, n-electrode, pads, etc. are deposited at predetermined locations.

[0135] Step 4: Forming a structure for separating the devices 111 .

[0136] Step 5: Remove the ELO III-nitride layer 105 from the substrate 101 using process #1 or #2.

[0137] In process #1, the open area of ​​the ELO III-nitride layer 105 is referred to as Region 1, and the area where adjacent ELO III-nitride layer 105 wings meet or may not meet is referred to as Region 2:

[0138] 1. Region 1 202 and Region 2 203 are etched to expose at least the growth limit mask 102 and the ELO III-nitride layer 105. Individual devices 111 are as follows: Figure 6(a)-6(e) 1. As shown divided, these figures illustrate how divided regions 202, 203 are formed at periodic lengths along the strips 110 of devices 111, and how a support plate 601 is attached to the strips 110 of devices 111. The support plate 601 may have finger-like structures 602 for supporting the strips 110 of devices 111 or individual devices 111 themselves.

[0139] 2. Place a hook layer or auxiliary layer on the device 111 to prevent the ELO III-nitride layer 105 from floating. Preferably, a dielectric layer such as SiO2 can be placed between the devices 111 so that the newly placed dielectric stays on the exposed growth limit mask 102 via the anchored divided device 111. The strength of the anchor can be controlled by the thickness of the newly placed dielectric layer. This is Figures 7(a)-7(j)7( a) shows a possible method of removing layer 109 from substrate 101 using a mask 701 for etching, placed hooks or anchors 702 and attached receptors 703, followed by an optional step of dissolving the growth limiting mask 102; FIG7( b) shows non-agglomerated and agglomerated structures 704, 705 for the hook process; FIG7( c) shows a set selective etching mask 701, wherein two types of etching masks 701 are shown; FIG7( d) shows a type-1 etching for separating III-nitride layer 109, wherein hooks 702 come from an open ELO window; FIG7( e) shows a type-2 etching, wherein an optical microscope image shows device 111 sandwiched between growth limiting mask 102 and etching mask 701; FIG7( f) shows a device 111 sandwiched between growth limiting mask 102 and etching mask 701 in step 2. 7( g ) shows the fixed chip layer 702, which is selectively etched to obtain various hook patterns; FIG7( h ) shows optical and scanning electron microscope images of the hook device 111; FIG7( i ) shows a process for fabricating a curved reflector 706 on the n-side epitaxial layer of the VCSEL device 111; and FIG7( j ) shows a double-clad Fabry-Perot (FP) laser device 111 fabricated using a hook process, wherein the FP laser device 111 is sandwiched between two carriers 703 and consists of a cladding layer 707, an n-GaN and waveguide layer 708, a single or multiple quantum wells 709, an electron blocking layer, a p-GaN and waveguide layer 710 and a cladding layer 711 and a ridge structure 712.

[0140] 3. As described above, the device 111 is bonded to one or more carriers 703, which can be a substrate, or a polymer film with some adhesive or with some vacuum holes to hold the device 111, or a temporary transport location before transfer to a substrate containing functional electrodes, or a highly glued UV transparent substrate that is sensitive to UV laser.

[0141] 4. Skip to step 6, or the device 111 can be separated mechanically by using ultrasonic treatment or by gentle peeling.

[0142] In process #2, the removal method follows step 4 and the etching is performed accordingly. The second process leaves open areas 202 of the ELO III-nitride layer 105 unetched. A carrier, support plate, susceptor, or receptor is attached to the divided devices 111. Alternatively, as described below in step 7, the divided ELO III-nitride layer 105 can be removed through a polymer film with an adhesive attachment layer.

[0143] In process #2, step 6 can be performed before or after step 4 because the open region, which serves as a weak connection area between the ELO III-nitride layer 105 and its growth substrate 101, prevents the layer 105 from floating away or falling off.

[0144] Step 6: Dissolve the growth restriction mask 102 by wet etching.

[0145] Step 7: Remove the device 111 from the substrate 101 .

[0146] Step 7.1: Attaching a polymer film to the device 111. More preferably, as Figure 6(a)-6(e) As shown, the device 111 is first attached to a support plate, and a polymer film is placed over the device 111 and the support plate.

[0147] Step 7.2: Apply pressure to the polymer film so that the polymer film wraps at least the top surface and part of the adjacent surface of the device 111, and more preferably, the polymer film wraps the top surface of the support plate and partially covers its side surfaces.

[0148] Step 7.3: Lower the temperature of the membrane and substrate 101 while applying pressure.

[0149] Step 7.4: The thermal stress between the device 111 and the polymer film separates the device 111 from its host substrate 101.

[0150] After separation by process #1 or #2, the ELO III-nitride layer 105 or device 111 is attached directly or indirectly to a polymer film facing the exposed interface between the ELO III-nitride layer 105 and the growth confinement mask 102. This interface is smooth enough to place a second DBR mirror to complete the resonant cavity of the VCSEL device 111. Figures 8(a)-8(d) As shown in Figures 8(a)-8(d) The growth of the ELO III-nitride layer 105 and the interface surface morphology measurement are shown, wherein FIG8(a) shows an image of the growth of the c-plane ELO III-nitride layer 105 and the interface surface morphology measurement after removal, and FIG8(b) shows an image of the growth of the semi-polar 20-21 plane ELO III-nitride layer 105 and the interface surface morphology measurement after removal, and Figure 8(c) and 8(d) Images of non-polar 10-10 plane ELO Group III-nitride layer 105 growth and interface surface morphology measurements after removal of two different growth confinement mask 102 patterns are shown.

[0151] Step 8: A second light reflecting element (i.e., a DBR mirror) is fabricated on the interface between the ELO wing region and the growth limiting mask 102, and more preferably, on the wing region of the ELO III-nitride layer 105 slightly away from the opening region 103. For example, a space slightly larger than 1 μm or 2 μm may be left from the opening region 103 to place the second DBR on the ELO wing region.

[0152] Besides placing a second DBR reflector at the ELO wing interface, there are other options:

[0153] (1) For example, an externally fabricated DBR reflector substrate can be attached to the back surface of the removed III-nitride epitaxial layers 105, 106, 109 by surface activated bonding or diffusion pressure bonding or by some other means, so that the top and bottom DBR reflectors of the removed III-nitride epitaxial layers 105, 106, 109 at the wing region of the ELO III-nitride layer 105 can be used as the resonant cavity of the VCSEL device 111; alternatively, the external DBR can be replaced with an epitaxial light reflecting layer, such as AlInN / GaN, to improve the thermal performance of the VCSEL device 111.

[0154] (2) Deposition of a DBR mirror layer on the interface of the removed III-nitride ELO wing region.

[0155] Step 9: Fabricate n-electrodes at separate areas of the device 111 (n-electrodeposition is required for top and bottom electrode configurations after placement of the second DBR layer).

[0156] Step 10: Disassemble the strip 110 into individual devices 111 (may be performed after step 3).

[0157] Step 11: Mount each device 111 on a heat sink, such as SiC, AlN, etc.

[0158] Step 12: Divide the heat sink to separate the components 111 .

[0159] These steps are explained in more detail below.

[0160] Process steps

[0161] Step 1: Forming a Growth Limiting Mask

[0162] In one embodiment, the III-nitride layer 105 is grown by ELO on a III-nitride substrate 101 (such as an m-plane GaN substrate 101) patterned with a growth limit mask 102 composed of SiO2, wherein the ELO III-nitride layer 105 does not coalesce on top of the SiO2.

[0163] The growth restriction mask 102 consists of stripe-shaped opening regions 103, wherein the SiO2 stripes of the growth restriction mask 102 have a width of 1 μm-20 μm and a spacing of 30 μm-150 μm between the opening regions 103. If a non-polar substrate 101 is used, the opening regions 103 are arranged along the <0001> Axis orientation. If a semipolar (20-21) or (20-2-1) plane is used, the opening region 103 is oriented parallel to the [-1014] or [10-14] directions, respectively. Other planes can also be used, in which the opening region 103 is oriented in other directions.

[0164] When using a III-nitride substrate 101, the present invention can obtain high-quality III-nitride semiconductor layers 105, 106, and 109 while avoiding protrusions or curvature of the substrate 101 during epitaxial growth due to homogeneous epitaxial growth. As a result, the present invention can also easily obtain a device 111 with reduced defect density, such as reduced dislocations and stacking faults.

[0165] Furthermore, these techniques can be used with a foreign substrate 101 such as sapphire, SiC, LiAlO 2 , Si, etc., as long as it is possible to grow the ELO III-nitride layer 105 through the growth confinement mask 102 .

[0166] Step 2: Grow multiple epitaxial layers on the substrate using a growth-limiting mask

[0167] In step 2, a III-nitride semiconductor device layer 106 is grown on the ELO III-nitride layer 105 in the flat region 107 by conventional methods. In one embodiment, MOCVD is used for epitaxial growth of the island-shaped III-nitride semiconductor layer 109 (including the ELO III-nitride layer 105 and the III-nitride semiconductor device layer 106). In one embodiment, the island-shaped III-nitride semiconductor layers 109 are separated from each other because the MOCVD growth is stopped before the ELO III-nitride layer 105 coalesces. In another embodiment, the island-shaped III-nitride semiconductor layers 109 are coalesced, and then etching is performed to remove unwanted areas.

[0168] Trimethylgallium (TMGa), trimethylindium (TMIn), and triethylaluminum (TMAl) are used as Group III element sources. Ammonia (NH3) is used as a feed gas to supply nitrogen. Hydrogen (H2) and nitrogen (N2) are used as carrier gases for the Group III element sources. It is important to include hydrogen in the carrier gas to achieve a smooth surface epitaxial layer.

[0169] Salt water and bis(cyclopentadienyl)magnesium (Cp2Mg) are used as n-type and p-type dopants. The pressure setting is typically 50 to 760 Torr. The III-nitride-based semiconductor layer is typically grown at a temperature range of 700 to 1250°C.

[0170] For example, growth parameters include the following: TMG at 12 sccm, NH 3 at 8 slm, carrier gas at 3 slm, SiH 4 at 1.0 sccm, and a V / III ratio of approximately 7700.

[0171] ELO of Group III Nitride Layers by Confined Area Epitaxy (LAE)

[0172] In the prior art, numerous pyramidal hillocks have been observed on the surface of grown m-plane III-nitride films. See, for example, U.S. Patent Application Publication No. 2017 / 0092810. Furthermore, wavy surfaces and concave portions appear on the growth surface, which degrade surface roughness. This is a significant problem when fabricating VCSEL structures on such surfaces. Therefore, it is preferable to grow epitaxial layers 105, 106, and 109 on non-polar or semi-polar substrates 101, which is known to be difficult.

[0173] For example, according to some papers, a smooth surface can be obtained by controlling the bevel angle (>1 degree) of the growth surface of the substrate 101 and by using N2 carrier gas conditions. However, due to high production costs, these are very limiting conditions for mass production. In addition, the bevel angle of the GaN substrate 101 fluctuates greatly from its manufacturing method to the origin. For example, if the substrate 101 has a large in-plane bevel angle distribution, it has different surface morphologies at these points in the wafer. In this case, the large in-plane bevel angle distribution reduces the yield. Therefore, the technology must not depend on the in-plane bevel angle distribution.

[0174] The present invention solves these problems as set forth below.

[0175] 1. The growth region is limited by the region of the growth limit mask 102 starting from the edge of the substrate 101 .

[0176] 2. Substrate 101 is a non-polar or semi-polar III-nitride substrate 101 having an off-angle orientation ranging from -16 degrees to +30 degrees from the m-plane toward the c-plane. Alternatively, a heterogeneous substrate 101 having a III-nitride-based semiconductor layer deposited thereon may be used, wherein the layer has an off-angle orientation ranging from +16 degrees to -30 degrees from the m-plane toward the c-plane.

[0177] 3. The island-shaped Group III nitride semiconductor layer 109 has a long side perpendicular to the a-axis of the Group III nitride-based semiconductor crystal.

[0178] 4. During the MOCVD growth process, a hydrogen atmosphere can be used.

[0179] 5. The island-shaped group III nitride semiconductor layers 109 are not aggregated with each other.

[0180] 6. In other embodiments, the growth restriction mask 102 or the light reflecting mirror element is placed on the wing region of the island-shaped III-nitride-based semiconductor layer where the main growth occurs, such as Figure 9(a)-9(e) As shown, Figure 9(a) 、 9(b) 9(c), 9(d) and 9(e) show the interface of the bottom of the ELO III-nitride layer used to make one of the DBR mirrors of a resonant cavity VCSEL. These figures are described in more detail below.

[0181] 7. Perform MOCVD growth to embed the second placed growth restriction mask 102 or light reflecting mirror

[0182] Using at least the above steps #1, #2 and #3, a strip 110 of devices 111 having a smooth surface is obtained. Preferably, each of the above steps #1, #2, #3, #4, #5, #6 and #7 is performed.

[0183] These results were obtained using the following growth conditions.

[0184] In one embodiment, the growth pressure ranges from 60 to 760 Torr, although the growth pressure is preferably in the range of 100 to 300 Torr to obtain a wide width of the island-shaped III-nitride semiconductor layer 109; the growth temperature ranges from 900 to 1200°C; the V / III ratio ranges from 1000 to 30,000, and more preferably from 3000 to 10,000; TMG is 2 to 20 sccm; NH3 ranges from 3 to 10 slm; and the carrier gas is hydrogen alone, or both hydrogen and nitrogen. To obtain a smooth surface, it is necessary to optimize the growth conditions for each plane by conventional methods.

[0185] After growing for about 2-8 hours, the ELO III-nitride layer 105 has a thickness of about 8-50 μm and a stripe 110 width of about 20-150 μm, where the stripe 110 width includes the width of the island III-nitride semiconductor layer 109 .

[0186] Step 3: Fabricate the device

[0187] In step 3, a device 111 is fabricated on the flat surface area 107 by conventional methods, wherein various device 111 designs are possible, such as Figures 10(a)-10(l) As shown, Figure 10(a) 、 10(b), 10(c), 10(d), 10(e) and 10(f) are different possible designs of the VCSEL device 111.

[0188] FIG10( g) is a cross-sectional view of a single-hole VCSEL device 111, showing a current confinement region 304, a p-pad 305, a bonding layer 306, a carrier 307, a current confinement layer 308, a current spreading layer 309, an n-GaN layer 310, an n-pad 311 deposited to contact the n-GaN layer 310 on the opposite side of the interface 312, and a second DBR mirror 313.

[0189] 10( h ) is a cross-sectional view of a single-hole VCSEL device 111 having the same side electrode formed of an island-shaped III-nitride semiconductor layer 109 , FIG. 10( i ) is a cross-sectional view of a single-hole VCSEL device 111 having opposite side electrodes and an n-side curved reflector 313 formed of an island-shaped III-nitride semiconductor layer 109 , FIG. 10( j ) is a cross-sectional view of a single-hole VCSEL device 111 having the same side electrode and an n-side curved reflector 313 formed of an island-shaped III-nitride semiconductor layer 109 , FIG. 10( k ) is a cross-sectional view of a single-hole VCSEL device 111 having opposite side electrodes and a p-side curved reflector 301 formed of an island-shaped III-nitride semiconductor layer 109 , and FIG. 10( l ) is a cross-sectional view of a single-hole VCSEL device 111 having the same side electrode and a p-side curved reflector 301 formed of an island-shaped III-nitride semiconductor layer.

[0190] The design shown can also be used in Figures 2(a)-2(f) , 3(a)-3(m), 4(a)-4(g) and 5(a)-5(i) and Figures 11(a)-11(k) The various methods mentioned are used to grow the III-nitride layer. Figure 11(a) 、 11(b) , 11(c), 11(d), 11(e), 11(f), 11(g) and 11(h) show a VCSEL manufacturing process on a non-agglomerated island-shaped III-nitride semiconductor layer 109 according to one embodiment of the present invention, and Figure 11(i) 、 11(j) and 11( k ) show possible solutions when the aspect ratio of the non-coalesced ELO structure does not allow enough room to fabricate the VCSEL device 111 .

[0191] In these designs, a first light-reflecting mirror is designed at a designated portion of the wing region of the ELO III-nitride layer 105 by defining a current-confining region 308 on the p-GaN side. Subsequently, a current-spreading layer 309, such as a contact layer of ITO, is deposited over the region containing the current-confining aperture. The light-reflecting DBR mirror 301 is a combination of dielectric layers with different refractive indices placed over the current-confining aperture, such that the contact layer is located between the p-GaN and the DBR. A p-pad 305 is photolithographically defined.

[0192] Step 4: Forming the structure for separating the devices

[0193] The purpose of this step is to prepare the ELO III-nitride layer 105 including current confinement, current diffusion, DBR, p-electrode and n-electrode into the form of strips 110 or individual units of the device 111, i.e. VCSEL. By etching the regions 202 and 203, the strips 110 of the device 111 can be realized, e.g. Figure 6(a)-6(e) shown.

[0194] like Figure 6(a)-6(e) As shown, partition support region 202 is a region that horizontally separates ELO III-nitride layer 105 into individual VCSEL devices 111 or a group of VCSEL devices 111 formed with periodic lengths, where each period is determined by the length of device 111. For example, in the case of VCSEL device 111, one period is set to 25-200 μm and is vertically along strip 110. When implementing process #1 for removing ELO III-nitride layer 105, etching regions 202 and 203 are necessary. However, when implementing process #2 for removal, opening region 202 may not necessarily be etched.

[0195] The dividing support areas 202, 203 are lines scribed by a diamond tip scriber or a laser scriber, such as Figure 6(a)-6(e) As shown; or trenches formed by dry etching such as RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma); but not limited to these methods. Divided support regions 202, 203 may be formed only on the side surfaces of stripe 110 or on one side of stripe 110. The depth of divided support regions 202, 203 is preferably 1 μm or more.

[0196] In both cases, the strip 110 can be divided into individual devices 111 at the dividing support regions 202, 203 because the dividing support regions 202, 203 are weaker than any other portion. The dividing support region 202 avoids breaking the strip 110 at an unintentional location, making it possible to accurately determine the length of the device 111.

[0197] The vertically divided support region 202 is created at the surface of the opening region 103 in a manner avoiding the current injection region and the p-electrode in the light emitting structure, but it may cover at least a portion of the current confinement layer.

[0198] like Figure 6(a)-6(e) As shown, divided support areas 202 and 203 are formed according to the number of devices 111 to be removed. For example, individual VCSEL devices 111 or VCSEL devices 111 placed side by side in the opening area can be lifted together during the subsequent removal process #2.

[0199] In addition, if Figure 6(a)-6(e) As shown, the entire strip 110 containing an array of VCSEL devices 111 or VCSEL devices 111 placed side by side in the open area can be lifted. Optionally, the support plate 601 can have finger structures 602, where the plate 601 is thin enough to provide space and flexibility for the finger structures 602. The finger structures 602 can be attached to the removed strip 110 of devices 111.

[0200] Boosting of the entire bar 110 is helpful when integrating single-color illumination or scaling up power from individual devices 111. Alternatively, bar 110 type boosting can also be performed when multi-color integration is required for a display or any such demanding application.

[0201] Step 5: Remove the ELO III-nitride layer from the substrate

[0202] After process #1 for removing the ELO III-nitride layer 105, the semiconductor layers including the current confinement layer, current spreading layer, DBR mirrors, and electrodes are divided together into individual devices 111 or a group of devices 111. Anchors or hooks may be placed on the individual devices 111 or a group of devices 111.

[0203] The divided semiconductor layer is then attached to a receiver or support plate via a bonding layer. The device 111 is then removed from the III-nitride native substrate 101 by gently peeling. Here, the anchor material can be the same as the growth confinement mask 102, or any material that is strong enough to hold the divided devices 111 and weak enough to break when the peeling is performed. Alternatively, the attached device 111 can self-detach from the substrate 101 when the growth confinement layer 102 and the anchor dissolve (e.g., using hydrofluoric acid (HF) or buffered HF (BHF) to dissolve the growth confinement mask 102 and the anchor layer).

[0204] At the interface between the growth confinement mask 102 and the ELO III-nitride layer 105, on the n-GaN side, a second light-reflecting DBR mirror is placed on the backside of the removed ELO III-nitride layer 105 in the wing region. Then, an n-pad is deposited to contact the n-GaN layer. In some designs, the n-pad is placed on the other side of the interface.

[0205] During process #2 for removing the ELO III-nitride layer 105, in step 4, when performing process #2, etching region 1 202 may be avoided, and then skipping to step 5.

[0206] Step 6: Dissolve the growth limit mask by wet etching

[0207] The method may further comprise the step of removing at least a portion, or preferably substantially all, or most preferably all, of the growth limit mask 102 by dissolving it using a wet etchant.

[0208] The growth limit mask 102 is removed using a chemical solution such as HF or BHF. This allows the device 111 to be easily removed from the substrate 101. This process is preferably performed before removing the III-nitride layers 105, 106, 109 from the substrate 101. This step can also be performed before processing the device 111 in step 3 or during step 3.

[0209] Step 7: Remove the device from the substrate

[0210] From here on, the process for removing the strip 110 of the device 111 is explained. Specifically, according to one embodiment of the present invention, Figure 12(a) 、 12(b) , 12(c), 12(d), 12(e), 12(f), 12(g), 12(h), 12(i), 12(j) and 12(k) illustrate a process for removing strip 110 of device 111.

[0211] Step 7.1 involves attaching a polymer film 1201 to the strip 110 of devices 111. In this embodiment, the polymer film 1201 is composed of a base film, an adhesive, and a backing film. Preferably, the adhesive-attached polymer film 1201 is sensitive to UV energy so that subsequent separation of the devices 111 from the film 1201 can be achieved in a UV-controlled environment.

[0212] Step 7.2 involves applying pressure to the polymer film 1201 and the substrate 101. The purpose of applying pressure is to position the polymer film 1201 between the strips 110 of the device 111 or between the carrier (support) board 1202. The polymer film 1201 is softer than the strips 110 of the device 111, so the polymer layer 1201 can easily wrap around the strips 110 of the device 111 and / or the carrier 1202. Preferably, the polymer film 1201 is heated to soften it, which makes it easier for the polymer film 1201 to cover the strips 110 of the device 111 and / or the carrier 1202.

[0213] Step 7.3 comprises reducing the temperature of the polymer film 1201 and the substrate 101 while maintaining the applied pressure. It is not necessary to apply pressure during the temperature change.

[0214] Step 7.4 involves removing strips 110 of device 111 by utilizing the difference in thermal coefficients between polymer film 1201 and substrate 101. Polymer film 1201 shrinks as the temperature decreases. As a result, the bottom of polymer film 1201 is lower than the top of carrier 1202 or strips 110 of device 111.

[0215] Polymer film 1201 can apply horizontal pressure to the side surfaces of strips 110 of device 111, exposing cleavage points 1203 and causing strips 110 of device 111 to tilt diagonally downward. This pressure applied from the side surfaces allows strips 110 of device 111 to be effectively removed from substrate 101. During low temperatures, polymer film 1201 maintains the pressure applied to strips 110 of device 111 from the top of polymer film 1201.

[0216] Various methods can be used to reduce the temperature. For example, the substrate 101 and polymer film 1201 can be placed in liquid N2 (e.g., at 77°K) while applying pressure. The temperature of the substrate 101 and polymer film 1201 can also be controlled using a piezoelectric transducer.

[0217] When the temperature is lowered, the substrate 101 and the polymer film 1201 may be wetted by atmospheric moisture. In this case, the temperature reduction may be performed in a dry air atmosphere or a dry N2 atmosphere, which prevents the substrate 101 and the polymer film 1201 from getting wet.

[0218] Thereafter, the temperature is raised to, for example, room temperature, and pressure is no longer applied to the polymer film 1201. At this point, the strips 110 of the device 111 have been removed from the substrate 101, and the polymer film 1201 is then separated from the substrate 101. When the polymer film 1201, especially the polymer film 1201 having an adhesive, is used, the strips 110 of the device 111 can be easily and quickly removed using the polymer film 1201.

[0219] Depending on the growth conditions, there may be situations where there are different heights between the strips 110 of the device 111. In this case, the removal method using polymer films 1201 is good at removing strips 110 of different heights of the device 111 because these films 1201 are flexible and soft.

[0220] Optionally, the above process can be implemented when the carrier or support plate 1202 has a finger-shaped structure.

[0221] Step 8: Make the Second Light Reflecting DBR Mirror

[0222] The removed strips 110 of the device 111 have a back surface that is the interface between the ELO III-nitride layer 105 and the growth confinement mask 102. The interface is formed by allowing the epitaxial layer to grow laterally from the opening region 103 of the substrate 101. The surface morphology at the ELO interface between the ELO III-nitride layer 105 and the growth confinement mask 102 can be controlled by the parameters of the growth confinement mask 102 and the growth parameters of the ELO III-nitride layer 105.

[0223] Figure 9(a)-9(e) The dependence of the surface topography on the growth confinement mask 102 is shown.

[0224] Case 1: A thinner growth limit mask 102 (e.g., 10 nm to 50 nm thick) may degrade at higher MOCVD growth temperatures when performing epitaxial lateral overgrowth. Consequently, uncontrolled open regions 901 are generated in the growth limit mask 102. During the epitaxial lateral overgrowth, these uncontrolled open regions 901 may be refilled along with the intended open regions 103, resulting in a connection path between the substrate 101 and the ELO III-nitride layer 105. When the strips 110 of the device 111 are removed, the diffused epitaxial layer at these uncontrolled open regions 901 may include a rough region interface 902 at the backside of the device 111. In this case, the yield of a smooth interface at the removed ELO III-nitride layer 105 may be reduced.

[0225] Case 2: A thicker growth limit mask 102 (e.g., 100 nm to 1000 nm, or more typically 1000 nm thick) can confine degraded regions, such as damaged regions 903, to the growth limit mask 102 at higher MOCVD growth temperatures while performing epitaxial lateral overgrowth. Thus, the uncontrolled open regions 901 can be eliminated by increasing the height of the growth limit mask 102, which translates into a better interface 904 between the ELO III-nitride layer 105 and the growth limit mask 102. The increased aspect ratio (thickness / width) at the break point due to the thicker growth limit mask 102 facilitates removal of the strips 110 of the device 111, which is an additional advantage.

[0226] Case 3: Alternatively, instead of a thicker growth limit mask 102, a combination of growth limit masks 905 will also function as in Case 2. One growth limit mask 102 for easy stripping (e.g., SiO2) and another growth limit mask 102 for stability at higher temperatures (e.g., SiN) can be deposited as a combined growth limit mask 102. A combined thickness of 100 nm to 1000 nm or greater is preferred, and is typically 1000 nm. By selecting a thermally stable growth limit mask 102 at the interface with the ELO III-nitride layer 105, a better surface 906 can be obtained for removing the strips 110 of the device 111.

[0227] To obtain a smooth interface and higher yield at the back surface of the removed ELO III-nitride layer 105 , a thicker growth limit mask 102 or multiple layers of growth limit mask 102 is preferred over a thinner growth limit mask 102 .

[0228] exist Figure 9(f) 、 9(g) Proof-of-concept studies of the results for the above scenarios are presented in Figures 9(h), 9(i). Specifically, two types of growth-limiting masks 102 are reported: (a) single-layer masks 102 and (b) multilayer masks 102. In each type, PECVD or sputtering deposition was selected to deposit the SiO2 and / or SiN films. In addition, a single-layer SiN growth-limiting mask 102 was also added for investigation. Semipolar 20-2-1 planar and nonpolar 10-10 substrates 101 were selected for investigation; however, the results were the same for substrates with c-plane or other crystal orientations.

[0229] As shown in FIG9(f), an ELO III-nitride layer 105 is grown on a substrate 101 patterned with a mask 102 by MOCVD, wherein the mask 102 is deposited by PECVD and / or sputtering, and the thickness varies from 100 nm to 300 nm for a single-layer mask 102, and a 60 nm SiN layer is added to the single-layer mask 102 to make a multi-layer mask 102. FIG9(g) shows the ELO III-nitride layer 105 removed for various masks 102, wherein the dotted line represents the opening area 103, and the area on both sides of the dotted line is the ELO wing, and the surface shown is the interface of interest for the DBR mirror. The interface on the ELO wing is scanned using AFM, and the results are shown in FIG9(h). As can be seen from the AFM scan results, when thinner single-layer masks 102 (100 nm and 200 nm) are used to grow the ELO III-nitride layer 105, the interface becomes rough, reaching over 2 nm for both PECVD and sputter-deposited films; however, the interface of the ELO III-nitride layer 105 grown on the 300 nm thick sputter-deposited single-layer mask 102 is smoother than its PECVD counterpart, by approximately 0.4 nm. Scans of the PECVD and sputter-deposited masks 102 before they were introduced into the MOCVD environment showed that the PECVD film had larger grain sizes and increased surface roughness than the sputter-deposited film. A thin 60 nm SiN film was placed on the single-layer mask 102 to make them multilayer as in Case 3 above, and the interfaces of the ELO III-nitride layers removed from these masks 102 showed a significant improvement in interface smoothness, as can be seen in the AFM scans. Even with the addition of a thinner single-layer mask 102 with a 60nm thick SiN layer, a minimum surface roughness as low as 0.25nm was achieved, indicating that the nitride termination must remain stable at higher temperatures and epitaxial growth conditions. The single-layer SiN film also resulted in a smoother surface, supporting this conclusion. It is believed that high-quality single-layer films deposited using sputtering, IBD, or ECR deposition will produce high-quality films, or by using a nitride termination mask 102, a smooth interface can be achieved.

[0230] Figure 9(i) is a graph of the surface roughness of the interface versus the type and thickness of various masks 102. This graph is augmented with an AFM scan measured from a non-polar 10-10 plane.

[0231] like Figure 13(a) 、 13(b)13( c ), after removing the strips 110 of the device 111, the mesas are etched and second light-reflecting mirrors 313 are defined by alignment with the first light-reflecting layer. These figures are schematic diagrams illustrating the effect of the growth limit mask 102 on the interface. The second reflective layer is a combination of one or more dielectric layers. For example, pairs of SiO 2 / Nb 2 O 5 layers can be deposited, typically 10 pairs.

[0232] Preferably, the DBR reflector layer for the resonant cavity of the VCSEL device 111 is far away from the opening region, for example, more than 1-2 μm away, so as to reduce the influence of the unwanted crystal quality near the ELO III-nitride layer 105 on the VCSEL performance from the bending shape of the opening region.

[0233] Alternatively, a prefabricated DBR mirror can be attached to the removed ELO strip 110 of the device 111 by surface activated bonding or some other diffusion bonding mechanism. The attached external DBR mirror can be epitaxial in nature to improve the thermal performance of the device 111.

[0234] Figures 8(a)-8(d) is an image of the sample interface surface between the ELO III-nitride layer 105 and the growth confinement mask 102. Specifically, Figures 8(a)-8(d) The experimental results for three different crystal orientations, namely polar c-plane (1000), semi-polar (20-21) and non-polar (10-10), as well as thinner growth restriction mask 102, thicker growth restriction mask 102 and multi-layer growth restriction mask 102 are shown.

[0235] FIG8( a ) shows the results obtained by implementing the process #1 removal method to remove a grown ELO III-nitride layer 105 from a polar c-plane substrate 101. The c-plane III-nitride ELO III-nitride layer 105 was transferred to a polymer film using process #1. In this case, the growth limit mask 102 was 1 μm thick SiO2. The image shows the back surface of the ELO III-nitride layer 105 on the polymer film.

[0236] The surface shown in the image is an N-polar surface. In principle, this surface will become rough when exposed to chemicals such as potassium hydroxide (KOH). For example, when using photoelectrochemical etching to remove Ga-polar semiconductor layers, the surface exposed to these chemicals cannot be used to make DBR mirrors. In this method, the native ELO III-nitride layer 105 on the growth confinement mask 102 is used to make the DBR mirror.

[0237] The images shown include a magnified image of the back (interface) surface observed by laser microscopy, a scanning electron microscope (SEM) image, and an atomic force microscope (AFM) image performed on one back surface. The surface roughness was found to be from sub-nanometer to 1 or 2 nanometers, which is optimal for placing the second DBR mirror to complete the resonant cavity of the VCSEL device 111.

[0238] FIG8( b ) shows the results obtained by implementing the process #2 removal method to remove native ELO III-nitride layers 105 from semipolar 20-21 and nonpolar 10-10 substrates 101. These are images of ELO III-nitride layers 105 of semipolar 20-21 planar III-nitride transferred onto polymer films using process #2. In this case, the growth limit mask 102 was 0.2 μm thick SiO2.

[0239] The image shown includes the back surface of an ELO III-nitride layer 105 on a polymer film. The surface shown in the image is the back surface of the 20-21 surface, which, in principle, can become roughened when exposed to chemicals such as KOH. For example, when using a photoelectrochemical etching method to remove a Ga-polar semiconductor layer, the surface exposed to the chemicals used in the method will support poorer interfaces. The roughness increases with the nitrogen polarity of the exposed surface. These interfaces are useful for fabricating DBR mirrors. In this method, a native ELO III-nitride layer 105 on a growth confinement mask 102 is used to fabricate a DBR mirror.

[0240] The images include a magnified image of the back (interface) surface observed by laser microscopy, a SEM image taken on one back surface (particularly on the wing area), and an AFM image. The surface roughness was found to be from sub-nanometer to several nanometers, which is optimal for placing the second DBR mirror to complete the resonant cavity of the VCSEL device 111.

[0241] Similarly, Figure 8(c) shows an ELO III-nitride layer 105 of non-polar 10-10 planar III-nitride transferred onto a polymer film using process #2. In this case, the growth-limiting mask 102 is 1 μm thick SiO2. The image includes the back surface of the ELO III-nitride layer 105 on the polymer film. The surface shown in the image is the back surface of the 10-10 surface. In this method, the native ELO III-nitride layer 105 on the growth-limiting mask 102 will be used to fabricate a DBR mirror.

[0242] These images include magnified images of the back (interface) surface observed by laser microscopy, SEM images, and AFM images taken on one back surface (particularly on the wing area). The surface roughness was found to be from sub-nanometer to several nanometers, which is optimal for placing the second DBR mirror to complete the resonant cavity of the VCSEL device 111.

[0243] Figure 8(d) shows an ELO III-nitride layer 105 of non-polar 10-10 planar III-nitride transferred onto a polymer film using process #2. In this case, the growth confinement mask 102 is a multilayer of 50 nm SiN and 1 μm thick SiO2, with the SiN facing the interface of the ELO surface. These images are of the back surface of the ELO III-nitride layer 105 on the polymer film. The surface shown in the images is the back surface of the 10-10 surface. In this method, the native ELO III-nitride layer 105 on the growth confinement mask 102 is used to fabricate a DBR mirror.

[0244] The images include a magnified image of the back (interface) surface observed by laser microscopy and an AFM image taken on one back surface, specifically the wing region. The AFM results show the surface roughness of the ELO wing when located on SiO2 and SiN, respectively. On the SiN surface, the ELO III-nitride layer 105 has a finer grain structure than the ELO III-nitride layer 105 on the SiO2 surface. Surface roughness was found to range from sub-nanometer to several nanometers, which is optimal for placement of the second DBR mirror to complete the resonant cavity of the VCSEL device 111.

[0245] As mentioned above, the growth restriction mask 102 may have an impact on the back surface. However, when no chemicals are involved, controlling the interface is a much simpler method than chemical or mechanical polishing or photoelectrochemical etching. Preferably, using a thicker growth restriction mask 102 and / or multiple growth restriction masks 102 can improve the yield at the interface.

[0246] Optionally, placing a metal layer on top of the growth confinement mask 102 (which can withstand the temperatures used to form the ELO III-nitride layer 105) can produce a mirror-like finish at the interface of the removed ELO III-nitride layer 105. The backside interface of the removed ELO III-nitride layer 105 at the wing region can later be used to place a second DBR mirror for the resonant cavity of the VCSEL.

[0247] The present invention helps to obtain better crystal quality and smoother surface for the DBR reflector of the resonant cavity of the VCSEL device 111. In addition, this method does not rely on crystal orientation, while other techniques are either cumbersome, chemically sensitive to crystal orientation, or have low tolerance for mass production.

[0248] The essence of the present invention is not only to use the ELO technique to obtain a better quality crystalline device layer 106 and a smooth interface of the DBR mirror of the resonant cavity, but also to control the cavity thickness and recycle the expensive host substrate 101 , such as a III-nitride substrate 101 .

[0249] Step 9: Fabricate n-electrodes at separate regions of the device

[0250] After removing the strip 110 or device 111 from the substrate 101, the strip 110 remains attached to the carrier, such as Figures 14(a)-14(g) As shown, the strip 110 is shown positioned in an inverted manner. Specifically, Figure 14(a) 、 14(b) , 14(c), 14(d), 14(e), 14(f) and 14(g) show a process flow for defining the n-side light reflecting layer after removing the strip 110 of the device 111 using a support plate, and also show possible device designs when the VCSEL device 111 fabricated on the two wings and the opening region 103 of the ELO III-nitride layer 105 is included in the device 111 design.

[0251] FIG14( a) shows the backside of strip 110 or device 111 having an n-electrode 1401 and a step-like feature 1402 at the opening region 103 between two side-by-side light-reflecting mirrors 1403. Step-like feature 1402 directly contacts substrate 101 or underlying layers, but is not on growth-limiting mask 102. Step-like feature 1402 is the only connection to substrate 101 that houses ELO III-nitride layer 105. In this view, step-like feature 1402 is separated from its host substrate 101 and may contain substantially no material from host substrate 101.

[0252] Then, after strip 110 is removed from substrate 101, an n-electrode 1401 is deposited on the backside of device 111. N-electrode 1401 preferably includes a stepped feature 1402. During process #2, stepped feature 1402 is not exposed to a robust environment and remains intact with host substrate 101 prior to separation, providing n-electrode 1401 with favorable surface conditions for low contact resistivity. Region 1402 is not exposed in process #2 until strip 110 or device 111 is removed from its host substrate 101. Secondary light-reflecting DBR mirror 313 is preferably positioned away from the edge of stepped feature 1402, for example, at least 1-2 μm away, to promote better crystal quality of VCSEL device 111. Therefore, using stepped feature 1402 can increase the yield of VCSEL device 111 because n-electrode 1401 of device 111 can occupy space that would otherwise be unused for resonant cavity structure.

[0253] Alternatively, n-electrode 1401 may also be provided on the top surface of strip 110 or device 111 , which is the surface prepared for p-electrode 305 .

[0254] Typically, n-electrode 1401 is composed of the following materials: Ti, Hf, Cr, Al, Mo, W, and Au. For example, the n-electrode can be composed of Ti-Al-Pt-Au (thickness of 30-100-30-500 nm), but is not limited to these materials. Deposition of these materials can be performed by electron beam evaporation, sputtering, thermal evaporation, etc.

[0255] When process #2 is used to remove the ELO III-nitride layer 105 from the host substrate 101, the strip 110 of the device 111 with ELO wings having the stepped features 1402 therebetween can be lifted onto a carrier or polymer film. In this case, the possible device 111 configuration spans the Figures 10(a)-10(f) The same ranges as depicted in the case of single wing removal. Figures 14(a)-14(g) A possible device 111 design is shown having two ELO wings including open areas.

[0256] Step 10: Break the Strips Into Individual Devices

[0257] like Figure 15(a) and 15(b) As shown, after the n-electrode is provided, each strip 110 is divided into a plurality of devices 111. Specifically, Figure 15(a) and 15(b) The process of dividing the device 111 after the n-electrode formation is shown.

[0258] As shown in Figure 15(b), dividing the support region 1501 helps to divide the strip 110 into individual devices 111. Fracture methods and other conventional methods can be used, but are not limited to these methods.

[0259] Step 11: Mount Each Component on a Heatsink

[0260] Figure 16(a) 、 16(b) , 16 ( c ), 16 ( d ), 16 ( e ) and 16 ( f ) show the removed strip 110 of the device 111 being placed on a heat sink 1601 .

[0261] After step 8, the divided strips 110 are lifted using one of three methods: (1) as shown in FIG16(a), the polymer film 1201 is attached to the strips 110 of the device 111, and then the strips 110 of the device 111 are bonded to the carrier 1601 using solder 1602 as shown in FIG16(d); (2) as shown in FIG16(b), the polymer film 1201 is attached to the connecting plate 1603, where the connecting plate 1603 is directly connected to the device 111. 11, and then bonding the connecting plate 1603 to the carrier 1601 using solder 1602 as shown in Figure 16(e); and (3) attaching the polymer film 1201 to the connecting plate 1603 as shown in Figure 16(c), wherein the connecting plate 1603 has a finger-like structure 1604 directly connected to the strip 110 of the device 111, and then bonding the connecting plate 1603 to the carrier 1601 using solder 1602 as shown in Figure 16(f).

[0262] In one embodiment, the polymer film 1201 is a UV sensitive dicing tape that is exposed to UV light, which reduces the adhesive strength of the film 1201. This makes it easier to remove the device 111 from the film 1201.

[0263] In this step, a heat sink 1601 made of AlN is prepared. Au-Sn solder 1602 is placed on the heat sink 1601, the heat sink 1601 is heated above the melting temperature of the solder 1602, and the device 111 on the polymer film 1201 is bonded to the heat sink 1601 using the Au-Sn solder 1602. The device 111 can be mounted on the heat sink 1601 in two ways: (1) with the n-electrode 1401 side facing down or (2) with the p-electrode 305 side facing down, depending on which side is exposed as the light-emitting side. Figures 16(d)-16(f) Device 111 is shown mounted to heat sink 1601 using solder 1602. Alternatively, the carrier is a heat sink structure.

[0264] Step 12: Divide the Heat Sink

[0265] Figure 17(a) 、 17(b) , 17(c) and 17(d) illustrate how wire bonds are attached to device 111 according to one embodiment of the present invention.

[0266] like Figures 17(a)-17(d) As shown, wire bonds 1701 and 1702 are attached to the device 111, and then the heat sink 1601 is divided, for example, between one or more devices 111. Figure 17(a) is an example device 111 with two VCSEL apertures separated by a stepped feature, and Figure 17(b) is an example device with a single VCSEL aperture. Figure 17(c) and 17(d)It is shown how the bonds 1701 , 1702 are prepared for the entire strip 110 of devices 111 of their respective design.

[0267] Figures 17(a)-17(d) It is shown how VCSEL devices 111 in the form of a bar 110 can be integrated for applications requiring greater power or light emission. However, even in applications requiring a large amount of light flux (monochromatic or multi-color), several bars 110 can be integrated together.

[0268] According to an embodiment of the present invention, FIG. 18( a ) shows single-color integration, and FIG. 18( b ) shows multi-color integration, in which a plurality of devices 111 are located on a heat sink 1601 .

[0269] Mass transfer for display applications transfer)

[0270] Method 1

[0271] When the target size is below 50 μm, the present invention provides a solution to the problem of quantity transfer for smaller light-emitting apertures (or so-called emissive inorganic pixels).

[0272] As described above, the VCSEL devices 111 fabricated on the ELO III-nitride layer 105 can be removed. In particular, these devices 111 preferably have a large ELO wing area and a small opening area 103, i.e., the ratio between the wing area and the opening area 103 should be greater than 1, more preferably 5-10, and in particular, the opening area 103 should be approximately 1-5 μm. Therefore, the devices 111 can be more easily removed from the III-nitride substrate 101 and can be transferred to an external carrier or processed in a further step in an easy manner.

[0273] Figure 19 FIG. 1 is a flow chart for integrating a VCSEL device 111 into a display backplane or to maximize flux. The steps are described as follows:

[0274] Step A: Removing the device 111 (strip 110 ) from the substrate 101 .

[0275] Step B: Further process device 111 to complete fabrication, or skip to step c if no further fabrication is required

[0276] Step C: Transfer the device 111 to a donor wafer.

[0277] Step D: Electrical characterization of the stamp using a Juggling Needle Handler (JNH).

[0278] Step E: Feedback the qualified graph to JNH.

[0279] Step F: Pick up qualified devices 111 using the vacuum control needle of JNH.

[0280] Step G: Feedback display panel is mapped to JNH.

[0281] Step H: Rearrange the qualified devices 111 on the JNH according to the display panel mapping.

[0282] Step I: Release the device 111 (strip 110) at the desired location.

[0283] Step J: Bonding the qualified device 111 to the display panel.

[0284] Step K: Define wire bonds or ribbon bonds.

[0285] Step L: Completed.

[0286] Device 111 Figures 10(a)-10(l) and 16(a)-16(f), the bare device 111 or the device 111 combined with the heat sink 1601 is transferred to the donor wafer 2001 as shown in Figure 20(a), which shows a process specifically for integrating the strips 110 of devices 111 into a whole.

[0287] The device 111 of interest may be a strip 110 of devices 111 having VCSEL devices 111 on either side of the opening region 103 or a single VCSEL device 111 on one of the ELO wings. For example, Figure 20(a)-20(e) The transfer process of the VCSEL device 111 on either side of the opening area 103 is shown. Figures 21(a)-21(d) The transfer flow is shown when an individual device 111 is addressed.

[0288] Individual devices 111 as shown in FIG20( a) or strips 110 of devices 111 as shown in FIG21( a) can be transferred to a donor wafer 2001 after step G, or can be determined after step H. As shown in FIG20( b), a juggling needle handler (JNH) stamp 2002 can be used, where the JNH stamp 2002 consists of an array of one or more JNH needles 2003 and functions 2004 such as electrical, vacuum, heating, logic control, etc., as shown in FIG20( a). For example, the size of the JNH stamp 2002 can be 20 mm × 20 mm to electrically characterize and pick up devices 111 from the donor wafer 2001.

[0289] The JNH stamp 2002 can transfer adjacent devices 111 (eg, every x devices 111), such as Figure 20(c) and 21(b) As shown, or devices 111 separated by a certain interval (for example, every 3x devices 111) can be transferred, as shown Figure 20(d)and 21(c) shown.

[0290] For example, in a simple rough estimate, when considering a typical device 111 dimension of 40 μm x 40 μm with a pitch of 20 μm, the stamp 2002 can accommodate 333 vertical devices 111 and 333 horizontal devices. Therefore, at least 100,000 devices 111 can be transferred in one minute (this can be done even faster with advanced equipment).

[0291] In addition, if Figure 20(e) and 21(d) As shown, a micro-LED display transfer process can be readily used for this transfer process. Display 2005 can be composed of a plurality of devices 111 , where a JNH stamp 2002 can pick and place an array 2006 of devices 111 .

[0292] When both the VCSEL device 111 and the micro LED device 111 employ removal processes and manufacturing techniques, both process #1 and process #2 are likely to meet industry standards.

[0293] Advantages of this approach include:

[0294] • The device 111 or the strip 110 of the device 111 may be fabricated homoepitaxially.

[0295] Compared to the homoepitaxial device 111, the device 111 is fabricated on an ELO wing region with low defects.

[0296] • When the size of the device 111 becomes <50 μm, defects will play a significant role in determining the brightness; however, this approach will tolerate this.

[0297] • If each individual device 111 separated by the stair-like feature is addressed individually, then the bad pixel problem in display applications can be solved by backing up each pixel with another pixel during display panel integration.

[0298] It is possible to overcome conventional size integration limitations and add spare pixels in a given space.

[0299] • The strip 110 transfer method with devices 111 has a greater throughput compared to picking up each individual device 111 .

[0300] Full color integration or monolithic integration can be achieved through programmable JNH.

[0301] Method 2

[0302] Figure 22A second method is shown that can be used to remove a device 111 (e.g., a VCSEL, micro-LED, or edge-emitting laser manufactured using the methods described herein). Figure 22 One possible volume transfer technique using an ultraviolet (UV) sensitive carrier (eg a polymer film) 2201 and a UV laser 2201 is shown, wherein strips 110 of devices 111 are glued 2203 to the carrier 2201 .

[0303] The strips 110 of devices 111 are removed onto a UV-sensitive polymer film 2201 and then integrated onto a functional backplane 2204 (e.g., a thin film transistor, integrated backplane, or CMOS circuit backplane) having electrical pads 2205 or other components. The strips 110 of devices 111 on the UV-sensitive polymer film 2201 are bombarded with a pulsed UV laser 2202 from the back side of the polymer film 2201 while the functional backplane 2204 is brought into proximity with them.

[0304] Definition of terms

[0305] III-nitride-based substrates

[0306] The III-nitride-based substrate 101 may include any type of III-nitride-based substrate, as long as the III-nitride-based substrate is capable of growing the III-nitride-based semiconductor layers 105, 106, 109 through the growth confinement mask 102, and any GaN substrate 101 sliced ​​from a bulk GaN and AlN crystal substrate on a {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} plane, etc., or other planes.

[0307] Heterogeneous substrate

[0308] Furthermore, the present invention may also utilize a foreign substrate 101. For example, a GaN template or other III-nitride-based semiconductor layer may be grown on the foreign substrate 101 (such as sapphire, Si, GaAs, SiC, etc.) before the growth restriction mask 102 is formed. The GaN template or other III-nitride-based semiconductor layer is typically grown on the foreign substrate 101 to a thickness of approximately 2-6 μm, and then the growth restriction mask 102 is disposed on the GaN template or other III-nitride-based semiconductor layer.

[0309] Growth-limiting mask

[0310] Growth restriction mask 102 includes a dielectric layer (such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, ZrO2, etc.), or a refractory metal or noble metal (such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc.). Growth restriction mask 102 may be a stacked structure of the above materials. Alternatively, it may be a structure of multiple stacked layers of the above materials.

[0311] In one embodiment, the thickness of growth restriction mask 102 is approximately 0.05-3 μm. The width of the mask is preferably greater than 20 μm, and more preferably, greater than 40 μm. Growth restriction mask 102 is deposited by, but not limited to, sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), or the like.

[0312] On an m-plane free-standing GaN substrate 101, a growth restriction mask 102 includes a plurality of opening regions 103 periodically arranged in a first direction parallel to the 11-20 direction of substrate 101 and in a second direction parallel to the 0001 direction of substrate 101, at intervals extending along the second direction. The length of opening regions 103 is, for example, 200 to 35,000 μm; the width is, for example, 2 to 180 μm; and the intervals between opening regions 102 are, for example, 20 to 180 μm. The width of opening regions 103 is typically constant in the second direction, but may vary in the second direction as desired.

[0313] On the c-plane free-standing GaN substrate 101 , the opening regions 103 are arranged in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 1-100 direction of the substrate 101 .

[0314] On a semipolar (20-21) or (20-2-1) GaN substrate 101, the opening regions 103 are arranged in directions parallel to [-1014] and [10-14], respectively.

[0315] Alternatively, a foreign substrate 101 can be used. When a c-plane GaN template is grown on a c-plane sapphire substrate 101, the opening region 103 is oriented in the same direction as the c-plane free-standing GaN substrate 101; when an m-plane GaN template is grown on an m-plane sapphire substrate 101, the opening region 103 is oriented in the same direction as the m-plane free-standing GaN substrate 101. This allows the m-plane cleavage plane to be used to divide the strips 110 of the device 110 using the c-plane GaN template, and the c-plane cleavage plane to be used to divide the strips 110 of the device 111 using the m-plane GaN template, which is more preferred.

[0316] Group III nitride-based semiconductor layer

[0317] The ELO III-nitride layer 105 , the III-nitride semiconductor device layer 106 , and the island III-nitride semiconductor layer 109 may include In, Al, and / or B, as well as other impurities such as Mg, Si, Zn, O, C, H, and the like.

[0318] The III-nitride-based semiconductor device layer 106 typically includes more than two layers, the more than two layers including at least one of an n-type layer, an undoped layer, and a p-type layer. The III-nitride-based semiconductor device layer 106 specifically includes a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, and the like. In the case where the device 111 has a plurality of III-nitride-based semiconductor layers, the distance between adjacent island-shaped III-nitride semiconductor layers 109 is typically 30 μm or less, and preferably 10 μm or less, but is not limited to these numbers. In the semiconductor device 111, a plurality of electrodes according to the type of the semiconductor device 111 are set at predetermined positions.

[0319] Epitaxial lateral overgrowth

[0320] The crystallinity of the island-shaped group III nitride semiconductor layer 109 grown on the growth restriction mask 102 from the stripe-shaped opening region 103 of the growth restriction mask 102 using ELO is very high.

[0321] Furthermore, two advantages can be obtained by using the group III nitride-based substrate 101. One advantage is that, compared with using the sapphire substrate 101, a high-quality island-shaped group III nitride semiconductor layer 109 can be obtained, such as one with a very low defect density.

[0322] Another advantage of using similar or identical materials for both epitaxial layer 109 and substrate 101 is that it can reduce strain in epitaxial layer 109. Furthermore, due to similar or identical thermal expansion, this method can reduce the amount of bending of substrate 101 during epitaxial growth. As described above, the effect is that production yield can be high due to improved temperature uniformity.

[0323] The use of foreign substrates 101 (such as sapphire (m-plane, c-plane), LiAlO2, SiC, Si, etc.) for the growth of epitaxial layers 105, 106, 109 is that these substrates are low-cost substrates, which is an important advantage for mass production.

[0324] When it comes to the quality of the device 111, for the reasons described above, it is more preferable to use a free-standing III-nitride-based substrate 101. On the other hand, the use of a foreign substrate 101 makes it easy to remove the III-nitride-based semiconductor layers 105, 106, and 109 due to the weaker bonding strength at the cleavage point.

[0325] Moreover, when multiple island-shaped III-nitride semiconductor layers 109 are grown, these layers are separated from each other (i.e., formed in isolation), so the tensile stress or compressive stress generated in each island-shaped III-nitride semiconductor layer 109 is confined within layer 109, and the effect of the tensile stress or compressive stress does not affect other III-nitride-based semiconductor layers.

[0326] Furthermore, since the growth limiting mask 102 and the ELO III-nitride layer 105 are not chemically bonded, stress in the ELO III-nitride layer 105 may be relaxed by slippage induced at the interface between the growth limiting mask 102 and the ELO III-nitride layer 105 .

[0327] Moreover, as shown in the non-growth region 104 in FIG1(a), there is a gap between each island-shaped III-nitride semiconductor layer 109, resulting in the substrate 101 having a plurality of rows of island-shaped III-nitride semiconductor layers 109, which provides flexibility and the substrate 101 can be easily deformed and bent when an external force is applied.

[0328] Therefore, even if slight warping, curvature or deformation occurs in the substrate 101, this can be easily corrected by a small external force, thereby avoiding cracks. Therefore, the substrate 101 can be handled by a vacuum chuck, which makes the manufacturing process of the semiconductor device 111 easier to perform.

[0329] As described above, an island-shaped III-nitride semiconductor layer 109 made of high-quality semiconductor crystals can be grown by suppressing the curvature of the substrate 101. In addition, even when the III-nitride-based semiconductor layers 105, 106, and 109 are very thick, the occurrence of cracks, etc. can be suppressed, so that a large-area semiconductor device 111 can be easily realized.

[0330] Flat surface area

[0331] The flat surface area 107 is between the layer bending areas 108. Furthermore, the flat surface area 107 is in the area of ​​the growth limit mask 102.

[0332] The semiconductor device 111 is manufactured mainly on the flat surface area 107. The width of the flat surface area 107 is preferably at least 5 μm, and more preferably 10 μm or more. The flat surface area 107 has high thickness uniformity for each semiconductor layer 105, 106, 109 in the flat surface area 107.

[0333] Layer bending area

[0334] FIG1( b) shows a layer bending region 108. If the layer bending region 108 including the active layer 106a remains in the device 111, part of the light emitted from the active layer 106a is reabsorbed. Therefore, it is preferred to remove at least part of the active layer 106a in the layer bending region 108 by etching.

[0335] If the layer bending region 108 including the active layer 106a remains in the VCSEL device 111, the laser mode may be affected by the layer bending region 108 due to the low refractive index (e.g., InGaN layer). Therefore, it is preferred to remove at least a portion of the active layer 106a in the layer bending region 108 by etching.

[0336] The emission region formed by the active layer 106a is a current injection region. In the case of the VCSEL 111, the emission region is a resonant cavity hole structure located vertically above the p-side or below the n-side, or vice versa.

[0337] For a VCSEL, the edge of the light emitting region should be at least 1 μm or more away from the edge of the layer bending region 108 , and more preferably 5 μm.

[0338] From another perspective, the epitaxial layer of the flat surface region 107 excluding the opening region 103 has a smaller defect density than the epitaxial layer of the opening region 103. Therefore, it is more preferred that the hole structure should be formed in the flat surface region 107 including the wing region.

[0339] semiconductor devices

[0340] The semiconductor device 111 is, for example, a Schottky diode, a light-emitting diode, a semiconductor laser, a photodiode, a transistor, etc., but is not limited to these devices 111. The present invention is particularly useful for VCSELs and semiconductor lasers that require a smooth region to form a cavity.

[0341] polymer film

[0342] A polymer film 1201 is used to remove an island-shaped III-nitride semiconductor layer 109 from a III-nitride-based substrate 101 or a GaN template used with a foreign substrate 101. In the present invention, a dicing tape including a commercially available UV-sensitive dicing tape can be used as the polymer film 1201. For example, the structure of the polymer film 1201 may include three layers or two layers, but is not limited to these examples. The base film material (e.g., having a thickness of approximately 80 μm) may be made of polyvinyl chloride (PVC). The back film material (e.g., having a thickness of approximately 30 μm) may be made of polyethylene terephthalate (PET). The adhesive layer (e.g., having a thickness of approximately 15 μm) may be made of an acrylic UV-sensitive adhesive.

[0343] When the polymer film 1201 is a UV-sensitive dicing tape and is exposed to UV light, the viscosity of the film 1201 is drastically reduced. After removing the island-shaped Group III nitride semiconductor layer 109 from the substrate 101, the polymer film 1201 is exposed to UV light, which makes it easy to remove.

[0344] heat sink

[0345] As described above, the removed strips 110 can be transferred to the heat sink 1701, which can be made of AlN, SiC, Si, Cu, CuW, etc. Figures 17(a)-17(d) As shown in FIG, solder 1702 for bonding is provided on a heat sink 1701. Solder 1702 may be Au-Sn, Su-Ag-Cu, Ag paste, etc. Then, the n-electrode 311 or the p-electrode 305 is bonded to the solder 1702. The device 111 may also be flip-chip bonded to the heat sink 1701.

[0346] In the case where the device 111 is bonded to the heat sink 1701, the size of the heat sink 1701 is not important and can be designed as desired.

[0347] Light reflecting DBR mirror

[0348] The light reflecting layer mentioned in the present invention is also referred to as a dielectric DBR reflector. The DBR reflector is composed of, for example, a semiconductor multilayer film or a dielectric multilayer film. Examples of dielectric materials include, but are not limited to, Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, etc., or nitrides of these elements, such as SiN, AlN, AlGaN, GaN, BN, etc., or oxides of these elements, such as SiOx, TiOx, NbOx, ZrOx, TaOx, ZnOx, AlOx, HfOx, SiNx, AlNx, etc. The light reflecting layer can be obtained by alternately stacking one or more dielectric materials with different refractive indices. Materials with different refractive indices, different thicknesses, and different numbers of material layers are selected to obtain the desired light reflectivity. The thickness of each dielectric layer can be adjusted according to the material and the oscillation wavelength of the light emitted from the resonant cavity.

[0349] Preferably, the thickness of these layers is an odd multiple of one-quarter the oscillation wavelength. The reflectivities of the two light-reflecting elements (one at the top and one at the bottom) are different. These two light-reflecting elements, including the active layer, the n-GaN layer, and a portion of the p-GaN layer, are collectively referred to as the resonant cavity. Generally, the reflectivity of the light-emitting side of the device's light-reflecting layer is lower than that of the other side.

[0350] Current limited area

[0351] The resonant cavity can be created by shaping the current flowing through the VCSEL device 111 to be narrow enough to be confined within the diameter of the resonant cavity of the aperture. This can be achieved by making the layers surrounding the aperture where the current injection occurs more conductive than its adjacent layers. For example, using reactive ion etching or plasma etching or a dielectric mask, the area adjacent to the aperture can be made resistive.

[0352] Alternative Embodiments

[0353] First embodiment

[0354] A Group III nitride-based semiconductor device 111 and a method of manufacturing the same according to the first embodiment are explained.

[0355] In the first embodiment, as Figures 1(a)-1(c) As shown, a base substrate 101 or a main substrate 101 is first provided, and a growth restriction mask 102 having a plurality of stripe-shaped opening regions 103 is formed on the substrate 101 .

[0356] In this embodiment, the island-shaped III-nitride semiconductor layer 109 is substantially uniform and has a very smooth surface. Figures 4(a)-4(g) As shown in Figures 5(a)-5(i) and 10(a)-10(l), a light-emitting aperture is defined on the ELO wing region by designing a current confinement region. One of the DBR reflectors of the VCSEL is placed on the current confinement region. The VCSEL requires a light-reflecting reflector (such as a DBR) located on top of the current aperture to filter the selected wavelength.

[0357] The strips 110 of the device 111 containing the island-shaped III-nitride semiconductor layer 109 are removed using process #1 or process #2. A second light reflecting mirror is placed on the back region at the interface between the growth confinement mask 102 and the ELO III-nitride layer 105 interface, and then Figures 10(a)-10(l) The n-electrode is defined by the design of the device 111 explained in [1]. The island-shaped III-nitride semiconductor layer 109 is divided into devices 111 using a fracture method. This method can be applied before removing the ELO III-nitride layer 105 from the main substrate 101. There are many reasons why these methods are believed to achieve better results.

[0358] First, the island-shaped III-nitride semiconductor layer 109 is removed from the freestanding GaN substrate 101. The freestanding GaN substrate 101 has many defects, such as dislocations and stacking faults. However, by exposing only a small area for epitaxial growth and allowing the epitaxial layer to relax on the wing region, which is not in direct contact with the III-nitride substrate 101 in the vertical direction, a light-emitting hole with fewer defects can be achieved. Furthermore, the island-shaped III-nitride semiconductor layer 109 is produced by MOCVD, so it has extremely high crystal quality.

[0359] Second, the width of the opening region and the height of the fracture region are very narrow and short, which makes it easy to remove the epitaxial layer. The width is about 1-5 μm, and the height is about 5-180 μm. The island-shaped semiconductor layer 109 is processed through steps 1-13 of the above method to obtain a VCSEL.

[0360] When a non-agglomerated stripe patterning method is selected to fabricate the VCSEL device 111, as discussed for the semi-polar and non-polar ELO III-nitride layers 105, unlike the polar ELO III-nitride layers 105, the non-polar and semi-polar ELO III-nitride layers 105 tend to form aspect ratios that do not leave much room to fabricate the entire VCSEL cavity and its electrode pads, e.g., Figure 11(i) 、 11(j) and 11(k). In this case, Figure 11(i) and 11(j) As shown, the complex aspect ratio non-agglomerated ELO III-nitride layer 105 formed on the host substrate 101 is etched or polished back to an aspect ratio such as that shown in FIG. 11( k ), which accommodates the Figures 10(a)-10(f) The complete device 111 structure is shown.

[0361] This method facilitates obtaining a smooth interface for the DBR mirror used to fabricate the VCSEL device 111. Conventional methods for fabricating DBR mirrors, such as thinning the substrate 101 or removing semiconductor layers by photolithography, are cumbersome and dependent on crystal orientation. However, this method is robust and independent of the crystal plane. The substrate 101 used to produce the device layer 106 can be recycled several times for similar fabrication. The method of the present invention not only provides a smooth crystal interface for the DBR mirror, but also provides a device 111 of good crystal quality because the present invention proposes fabricating the resonant cavity entirely on the wings of the ELO III-nitride layer 105. Preferably, this excludes the open region of the substrate 101 from which the device layer 106 is grown.

[0362] Second embodiment

[0363] In a second embodiment, the ELO III-nitride layer 105 on the III-nitride substrate 101 is coalesced, as shown in FIG. Figures 2(a)-2(f) As shown. The manufacturing of the device 111 is similar to that of the first embodiment, except that an additional etching must be performed at the coalescence region 203 to remove the ELO III-nitride layer 105 from the host substrate 101. After removing the ELO III-nitride layer 105 from the host substrate 101, similar manufacturing steps as those mentioned in the first embodiment are followed to realize the second DBR mirror of the resonant cavity.

[0364] Third embodiment

[0365] The third embodiment is similar to the first and second embodiments for designing a VCSEL device 111, except that the surface of the III-nitride substrate 101, which in the previous embodiments is covered by a planar growth restriction mask 102, is shaped. The growth restriction mask 102 (whose shape subsequently serves as an interface for placing the second DBR) can be shaped as a finite radius curve with a center of curvature away from the surface of the main substrate 101 or as Figures 4(a)-4(g) and rectangular / conical container surfaces as shown in 5(a)-5(i). Later, the shaped surface is covered with a growth limiting mask 102, leaving an exposed open area for the growth of the ELO III-nitride layer 105. Dry etching (such as RIE) can also be used to form a slightly rectangular or conical container shape, and the two periodic mask patterns are in Figures 4(a)-4(g) and 5(a)-5(i).

[0366] FIG5(g) shows a patterned master substrate 101. In order to remove the ELO III-nitride layer 105 whose interface is modified to a finite radius curved surface, the master substrate 101 needs to be patterned using a two-period growth confinement mask 102. For example, dry etching as described in FIG5(a), or an electrochemical etching process as described in FIG4(a), or alternatively, nanoimprinting the desired structure of the growth confinement mask 102 on the master substrate 101, are some possible techniques.

[0367] Throughout this disclosure, the designs of devices 111 are shown using cross-sectional views, even though their actual representation would be best presented using the illustrated top view stripe structure. An example of this is shown in FIG5(g) along with the cross-sectional views of FIG4(g) and FIG5(d). Alternatively, a patch structure of growth restriction mask 102 as shown in FIG5(h) can be followed to realize individual devices 111 as described in FIG4(g) and FIG5(f). In this case, the division of stripe 110 of devices 111 into individual devices 111 can be avoided, as compared to the stripe-like pattern used to fabricate devices 111.

[0368] Alternatively, this embodiment may also be practiced on a III-nitride substrate 101 having a highly doped III-nitride semiconductor layer 301 .

[0369] Once the host substrate 101 is patterned as desired, the ELO III-nitride layer 105 formed by the open regions adopts the shape of the growth confinement mask 102 by leaving a smooth interface between the growth confinement mask 102 and the ELO III-nitride layer 105. In particular, the patterned shapes on the host substrate 101 serve as wings for the ELO III-nitride layer 105.

[0370] Once the desired ELO III-nitride layer 105 and semiconductor device layer 106 are formed, the processing of the VCSEL device 111 is performed similarly to the above process. The ELO III-nitride layer 105 is removed from the host substrate 101 by process #1 or process #2. The second DBR mirror of the VCSEL resonator is placed at the interface.

[0371] Fourth embodiment

[0372] The fourth embodiment uses process #2 and pairs of elevated devices 111. For example, the devices 111 are partitioned so that each cell contains two devices 111, one on each wing of the ELO III-nitride layer 105 separated by an open region. Figures 14(a)-14(g) is an enlarged view of a possible device 111 design.

[0373] Fifth embodiment

[0374] In the fifth embodiment, ELO can be performed at least twice, such as Figure 3(a)-3(m) As shown in Figures 23(a)-23(f). For the second ELO growth, the growth restriction mask 102 can be selected as one of the light-reflecting DBR mirrors, preferably, an n-GaN side light-reflecting mirror. Specifically, Figure 23(a) 、 23(b) , 23(c), 23(d), 23I, and 23(f) represent processes for fabricating embedded DBR resonant cavity VCSELs and scaled-up versions of possible designs.

[0375] For example, in Figures 23(a)-23(f) In the design shown, the unwanted crystal quality obtained during the embedding process of the light reflective layer is separated from the resonant cavity path. The main ELO III-nitride semiconductor layer 105 of this process can be used to extract heat generated from the operation of the device 111 using the open area path 2301 at the main substrate 101 area.

[0376] This design can be modified in many ways, such as using the III-nitride semiconductor layers 105 for heat dissipation, or making them thinner to avoid interference with the light cone, or opening the p-side electrode pattern to allow light to be emitted by closing the n-side electrode structure, etc.

[0377] like Figures 23(a)-23(f) As shown, when following process #2, the device 111 removed from the main substrate 101 can be carefully designed to have two resonant cavities, one on each side of the open area.

[0378] Sixth embodiment

[0379] In the sixth embodiment, an AlGaN layer is used as the island-shaped III-nitride semiconductor layer 109. The AlGaN layer can be grown as an ELO III-nitride layer 105 on various off-angle substrates 101, with the Al composition set to 0.03-0.05. Using the present invention, the AlGaN layer 109 can have a very smooth surface. Using the present invention, the AlGaN layer 109 can be removed from various off-angle substrates 101 as an island-shaped III-nitride semiconductor layer 109.

[0380] Seventh embodiment

[0381] In a seventh embodiment, an ELO III-nitride layer 105 is grown on various bevel-angled substrates 101. The bevel angle orientation ranges from 0 to +15 degrees from the m-plane toward the c-plane, and the bevel angle orientation ranges from 0 to -28 degrees. The present invention allows strips 110 to be removed from various bevel-angled substrates 101 without breaking them. When using various crystalline planar substrates 101, mechanically removing the strips 110 may result in a stepped, cleaved surface at the opening region of the strips 110, making the opening region unsuitable for fabricating a DBR mirror for a VCSEL device 111. However, regardless of the crystal orientation, the surface on the removed wing region of the strips is sufficiently smooth to fabricate such precision DBR mirrors for VCSEL devices 111. For example, when a semipolar strip 110 is removed from its primary semipolar plane 20-2-1 or 20-21, the open region of the removed portion of strip 110 may contain a split nonpolar plane 10-10, etc., which is angled at 75 or 15 degrees with respect to the primary semipolar plane and may appear as a staircase pattern in the open region, as shown in FIG8(k). However, the wing region of strip 110 shown in FIG8(i) contains a smoother surface than the open region. Therefore, the proposed method of fabricating a DBR reflector for a VCSEL device 111 on the wing region of the ELO region is an optimal solution independent of the crystal plane. This is an advantage of this technique because various oblique angle orientations of the semiconductor planar device 111 can be achieved without changing the manufacturing process.

[0382] Eighth embodiment

[0383] In the eighth embodiment, an ELO III-nitride compound layer 105 is grown on a c-plane substrate 101 having two different off-cut orientations. After processing a desired device 111, the island-shaped III-nitride compound semiconductor layer 109 is removed.

[0384] Ninth embodiment

[0385] In the ninth embodiment, a sapphire substrate 101 is used as a heterogeneous substrate. Except for the use of the sapphire substrate 101 and the buffer layer, the structure is almost the same as that of the first embodiment. In this embodiment, the buffer layer may also include an additional n-GaN layer or an undoped GaN layer. The buffer layer is grown at a low temperature of about 500-700°C. The n-GaN layer or the undoped GaN layer is grown at a higher temperature of about 900-1200°C. The total thickness is about 1–3μm. Then, a growth restriction mask 102 is set on the buffer layer and the n-GaN layer or the undoped GaN layer. The remaining processes for completing the device 111 are the same as those of the first to fourth embodiments.

[0386] On the other hand, a buffer layer is not required. For example, the growth restriction mask 102 can be directly placed on the foreign substrate 101. Thereafter, the ELO III-nitride layer 105 and / or the III-nitride-based semiconductor device layer 106 can be grown. In this case, the interface between the surface of the foreign substrate 101 and the bottom surface of the ELO III-nitride layer 105 is easily divided due to the heterojunction interface, which includes many defects.

[0387] With the present invention, a smooth interface of the ELO III-nitride layer 105 can be obtained for the resonant cavity even when a foreign substrate 101 is used, because the wing regions of the ELO III-nitride layer 105 and the interface between the growth confinement mask 102 and the ELO III-nitride layer 105 are used as resonant cavity mirrors in the device 111.

[0388] The use of a foreign substrate 101 also has a significant impact on mass production. For example, compared to a freestanding GaN substrate 101, the foreign substrate 101 used can be a low-cost and large-sized substrate 101 such as sapphire, GaAs, and Si. This results in a low-cost device 111. In addition, sapphire and GaAs substrates are well-known as low-thermal conductivity materials, so devices 111 using these substrates have thermal issues. However, using the present invention, since the device 111 is removed from the foreign substrate 101, these thermal issues can be avoided.

[0389] Furthermore, in the case of using the ELO growth method to remove the strips 110 of the device 111 , the method can significantly reduce the dislocation density and stacking fault density, which have been critical issues in the case of using the foreign substrate 101 .

[0390] Therefore, the present invention can solve many problems caused by using a foreign substrate 101.

[0391] Tenth embodiment

[0392] The tenth embodiment removes the ELO III-nitride layer 105 using a fixed precision hook that temporarily holds the ELO III-nitride layer 105 and releases it onto a temporary carrier substrate or permanently bonds it to a substrate, CMOS panel, or TFT backplane. Using ELO technology, larger wings can be created, on which several devices 111, such as VCSELs, LEDs, and power electronics, can be fabricated. This allows these devices 111 to exhibit unique characteristics, resulting in reduced defects, compared to devices 111 fabricated from conventional substrates.

[0393] This is Figures 7(a)-7(j) As described in

[15] , in the first part of the hook process, as shown in FIG7(b), either agglomerated or discrete III-nitride layers are used; in both cases, the desired optical device 111 can be placed on top of the ELO III-nitride layer 105. For example, the ELO III-nitride layer 105 is masked 701 with a SiO2 layer deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering. By placing two different types of hooks 702, the mask 701 can be patterned to extract the useful chip from the ELO III-nitride layer 105 of the ELO wing. For example, in a type-1 etch, as shown in FIG7(c), an open ELO window is included in the mask 701 pattern; thus, the open ELO window acts as a hook 702 to hold the device 111. Similarly, in a type-2 etch, as shown in FIG7(g), an open ELO window is not included, resulting in several other types of hooks 702.

[0394] This process can be performed after all front-end processes are completed for the agglomerated or discrete ELO III-nitride layer 105. For example, in the case of a small-sized LED, the operating device 111 designed on the ELO wing includes a p-electrode and an n-electrode on the top side of the III-nitride semiconductor layer 109. The mask 701 used to etch the III-nitride layer 109 on the main substrate 101 can also be used as a passivation layer to prevent leakage or improve the efficiency of the small-sized LED.

[0395] Using a mask 701, typically SiO2, the desired chip dimensions are etched to at least expose the growth restriction mask 102. Then, in the type-2 etch, a hook layer 702 is placed to contact the exposed growth restriction mask 102. Optionally, the hook layer 702 can contact the main substrate 101 at the opened ELO window. In addition, the process of etching down the III-nitride semiconductor layer 109 to expose the underlying growth restriction mask 102 can be completed in two steps. For example, in the case of a thicker (>10μm) III-nitride semiconductor layer 109, a hard mask 701 is first used to etch slightly above the growth restriction mask 102 so that the underlying growth restriction mask 102 is not exposed at this time; then, in the second step, a soft mask 701 (such as photoresist) is used to expose at least the underlying growth restriction mask 102. This configuration results in one of the hook 702 designs, pattern 1, which is named in the type-2 etch. Alternatively, only the hard mask 701 and / or the soft mask 701 may be used, and the underlying growth limiting mask 102 may be exposed without a two-step etching process.

[0396] In the Type 2 etch, after exposing the underlying growth confinement mask 102, as shown in FIG7(f), the etch layer has no support from the host substrate 101, except that it is sandwiched between the growth confinement mask 102 and the etch mask 701. At this stage, the III-nitride layered device 111 has not detached from the host substrate 101. The inventors have experimentally observed that after exposing the growth confinement mask 102, 100% of the III-nitride layered device 111 remains on the growth confinement mask 102, as shown, for example, in the optical microscope image in FIG7(h). At this point, the III-nitride layered device 111 is sandwiched between the growth confinement mask 102 and the mask 701 used to expose the growth confinement mask 102. This is a unique configuration that can only be achieved using the method of the present invention. Although the growth confinement layer for the ELO process is initially prepared at a low temperature of approximately 300° C., during the formation of the III-nitride layer 109 in the MOCVD reactor chamber, the growth confinement mask 102 is exposed to a higher temperature of approximately 1200° C., which promotes weaker bonding, such as van der Waals forces, between the growth confinement mask 102 and the back side of the III-nitride layer 109.

[0397] Optionally, as shown in FIG7(f), a further fixing process is possible by placing a thin layer, a chip fixing layer 702, preferably a dielectric SiO2 with a thickness of 10 nm to 300 nm on top of the etching mask 701. Figure 7(g) and 7(h)Several hook designs are shown, including Pattern 1, Pattern 2, and Pattern 3, which are made possible by selectively opening the etching mask 701 and the chip-mounting layer 702. In FIG7(h), the inventors present an experimentally demonstrated Pattern 3 hook design, in which the chip-mounting layer 702 protects the device 111 with a strip that spans the width of the device 111.

[0398] Now, the carrier wafer can be temporary or permanent and can be attached to the Ill-nitride layered device 111. Applying ultrasonic or mechanical or thermal treatment, the only supporting hook layer 702 can be broken and the device 111 can be transferred to the carrier wafer.

[0399] This unique process not only helps solve the current volume transfer problem of micro-LEDs, but also helps achieve unique patterns for VCSELs and double-clad edge-emitting Fabry-Perot lasers, as described below.

[0400] VCSEL: n-side curved mirror on the epitaxial layer without substrate

[0401] As shown in Figure 7(i), after placing the fixed chip layer 702, the device 111 can be transferred to a temporary carrier 703 using crystal bonding, electronic wax, or a temporary attachment layer. After being transferred to the temporary carrier 703, the back side of the device 111 is patterned into a concave surface by reflowing the resist, and a curved reflector is fabricated on the back side of the device 111. The device 111 is then transferred back to the permanently bonded wafer 706 for packaging, where light is extracted from the p-side of the device 111. Using this process and removing the substrate 101, it is possible for the VCSEL device 111 to emit light from the p-side, whereas other processes, such as photoelectrochemical etching or electrochemical etching, may not be able to form an n-side curved reflector on the removed epitaxial layer.

[0402] Double-clad Fabry-Perot (FP) laser

[0403] FIG7( j) shows a double-clad Fabry-Perot (FP) laser fabricated according to one embodiment of the present invention, wherein the FP laser is composed of a carrier 703, a cladding layer 707, an n-GaN and waveguide layer 708, a single or multiple quantum wells 709, a p-GaN and waveguide layer 710, and an ITO cladding layer 711. Unlike dividing the III-nitride layer device 111 into small-sized LEDs or VCSELs, an FP laser can be designed on the ELO wing by placing a ridge structure 712 and confinement layers 707, 708, 710, 711 on the ELO wing region. For example, before removing the laser bar 110 by any of the above-mentioned hook techniques, an ITO layer 711 is placed on the outside as a cladding layer, and after removal, another cladding layer 707, such as aluminum nitride (AlN), is placed on the outside. This process is easier to control for achieving double-clad FP lasers because the thickness of the ELO wings in the n-GaN and waveguide layers 708 can be epitaxially controlled, which is very critical for the design of long-wavelength lasers, and the precisely designed laser epilayers can be removed from the surface of the growth confinement mask 102. The two cladding layers 707 and 711 are placed externally using, for example, sputtering, electron beam, ECR, CVD, etc. Optionally, in the case where the back surface of the FP laser of the ELO wings in the n-GaN and waveguide layers 708 is not necessarily flat, even if the thickness on the n-GaN base layer exceeds the desired dimension, it can be etched back to the desired value after transferring the FP laser bar 110 to the carrier 703 before placing the second cladding layer 711. In this configuration, for better thermal management, junction-down or interlayer cooling techniques can be applied to the final device 111.

[0404] mass production

[0405] One design attempts to embed a DBR-like reflector structure, for example, a growth restriction mask 102 having an ELO III-nitride layer 105 as shown in FIG24(a). However, as shown in FIG24(b), cracks are generated on the surface of the ELO III-nitride layer 105. Specifically, FIG24(a) shows the growth restriction mask 102 embedded in the ELO III-nitride layer 105, and FIG24(b) shows visible cracks in the surface of the ELO III-nitride layer 105.

[0406] The thermal expansion coefficients of the embedded DBR mirror material (primarily the dielectric layer of the growth confinement mask 102) and the semiconductor ELO III-nitride layer 105 differ significantly. Consequently, significant stress is generated between these layers 102 and 105 when the ambient temperature changes. Typically, the ELO III-nitride layer 105 is fabricated in an MOCVD environment at approximately 700°C to 1200°C and must be cooled to room temperature in order to fabricate the device 111. This is the most common scenario when implementing embedded DBR mirror patterns.

[0407] The internal stress accumulated between the ELO III-nitride layer 105 and the DBR reflector material 102 may gradually lead to cracks in the layers of the device 111. This also makes the contact between the embedded DBR reflector 102 and the ELO III-nitride layer 105 located on top of it unreliable. The cracks in the layers of the device 111 absorb moisture and make the DBR susceptible to environmental influences, and in the worst case, the device layer 106 can self-lift. This will affect the reflectivity of the DBR reflector and the lifetime of the device 111. Experimentally, as shown in Figures 24(a)-24(b) As shown, when a growth restriction mask 102 including a dielectric layer comprising SiO2 is embedded by forming an ELO III-nitride layer 105 on top of the growth restriction mask 102, cracks are observed in the ELO III-nitride layer 105. These cracks not only reduce yield but also degrade the characteristics of the device 111.

[0408] In summary, several reliability issues arise when placing a DBR mirror without first removing the ELO III-nitride layer 105:

[0409] • Built-in internal stress and ELO III-nitride layer 105 weakly bonded to the DBR mirror can lead to delamination and cracks in the device layer 106, causing reliability and yield issues.

[0410] The difference in thermal expansion coefficients of the dielectric material 102 and the semiconductor host substrate 101 induces internal stress between the device layer 106 and the DBR mirror, leading to cracks in the device layer 106 .

[0411] • Unreliable contact is established at the interface between the DBR mirror and the device layer 106 , which will affect the yield, reliability and efficiency of the device 111 .

[0412] DBR reflectors can absorb moisture from cracks, degrading their original design characteristics.

[0413] In order to form the ELO III-nitride layer 105 on the surface of the DBR mirror, the top surface of the DBR mirror must be selected to accommodate a good crystalline ELO layer. If the appropriate DBR material is not selected, then debris from the ELO material will randomly settle on the surface of the DBR mirror, affecting yield and reliability.

[0414] • If the device 111 includes the main substrate 101, the device 111 will be expensive.

[0415] • Light emitted from the device 111 may be absorbed in the included host substrate 101, so thinning must be introduced, which brings additional costs, and the byproducts of the thinning are useless.

[0416] Polishing and etching methods are difficult to achieve uniform and planar thinning distribution.

[0417] • In this case, non-planar DBR mirror shapes are not possible.

[0418] • Careful design must be followed to avoid unwanted crystal mass at the agglomeration area.

[0419] A weak bond between the ELO III-nitride layer 105 and the DBR mirror can have detrimental effects, but can also be advantageous in some respects:

[0420] 1. The ELO III-nitride layer 105 is weakly bonded to the DBR reflector, maintaining a smooth interface at the back surface of the ELO III-nitride layer 105 .

[0421] 2. The ELO III-nitride layer 105, which is weakly bonded to the DBR mirror, can facilitate the above removal process to improve yield.

[0422] 3. Flexibility in choosing a single or double layer growth confinement mask 102 instead of the complex dielectric layer pairs of typical DBR designs.

[0423] 4. Whether the DBR reflector material is degraded when exposed to extreme temperature conditions.

[0424] The present invention alleviates these problems by exploiting the weak bonding interface between the DBR mirror and the ELO III-nitride layer 105:

[0425] 1. After removing the ELO III-nitride layer 105, we place the desired DBR mirror design externally on the smooth interface remaining due to weak bonding on the back surface of the ELO III-nitride layer 105. For example, we can use surface activated bonding with an externally prepared DBR mirror, or sputter or deposit the DBR layer to achieve better bonding and higher reliability.

[0426] 2. Weak Bond Assisted Removal of ELO The III-nitride layered device 111 achieves better yield.

[0427] Furthermore, after removing the ELO III-nitride layer 105 or device layer 106 from the host substrate 101, the DBR mirror can be deposited externally. By doing so, the device layer 106 becomes stress-free due to its standalone nature. Next, the DBR mirror can be deposited or placed at the interface of the ELO wing region, which ensures reliable bonding with the wing interface, thereby enabling the desired functionality of the DBR to be achieved.

[0428] Preferably, the DBR should be placed at least 1 μm away from the edge of the etched portion, to avoid etching damage. Experimental observations show that the interface of the removed ELO wing has a roughness of less than 2 nm, and can reach sub-nanometer levels at best. Furthermore, improvements to reduce interface roughness using a multilayer approach, a thermally stable growth confinement mask 102, or material parameter development have been proposed.

[0429] Finally, the method of the present invention is cost-effective because the device 111 is removed from the host substrate 101 and the host substrate 101 can be recycled several times.

[0430] Alternative designs

[0431] Design 1

[0432] The above sections of this application describe one type of design, referred to as Design 1, as shown in Figure 10(g). As described below, alternative designs may also be used.

[0433] Design 2

[0434] Figure 10(h) and 14(c) Another type of design, referred to as Design 2, is shown.

[0435] In this design, a first light reflecting mirror 301 is designed at a designated portion of the wing region of the ELO III-nitride layer 105 by defining a current confining region 308 on the p-GaN side.

[0436] Subsequently, a current spreading layer 309 and a contact layer (eg, ITO) are deposited over the region including the current confining hole. The light reflecting DBR mirror 301 is a combination of dielectric layers with different refractive indices placed over the current confining hole such that the contact layer is between the p-GaN and the DBR.

[0437] At this stage, a single-aperture device 111, as shown in FIG10(h), or a dual-aperture device 111, as shown in FIG14(c), can be fabricated by patterning the p-pad 305 accordingly. In the case of a single-aperture design, the p-pad 305 is photolithographically defined to aid aperture demarcation. These designs define the p-pad 305 and the n-pad 311 on the same side. To define the n-pad 311, the III-nitride semiconductor layers 105, 106, and 109 are etched from top to bottom down to the n-GaN layer, and then the n-pad 305 is deposited.

[0438] Subsequently, the single or dual hole bar 110 is attached to a carrier 307 via a bonding layer 306. The device 111 is then removed from the substrate 101 using an adhesive film.

[0439] At one side of the interface 312 between the growth confinement mask 102 and the ELO III-nitride layer 105, a second light reflecting mirror 313 is blanket deposited on the back side of the device 111, which is n-GaN.

[0440] Design 3

[0441] Figure 10(i) and 14(d) Another type of design, referred to as Design 3, is shown.

[0442] In this design, a first light reflecting mirror is designed at a designated portion of the wing region of the stripe 110 by defining a current confining region 308 on the p-GaN side.

[0443] Subsequently, a current spreading layer 309 and a contact layer (e.g., ITO) are deposited over the region including the current confining hole. A light reflecting DBR mirror 301 (which is a combination of dielectric layers with different refractive indices) is placed over the current confining hole with the contact layer between the p-GaN and the DBR.

[0444] At this stage, a single-aperture device 111 as shown in Figure 10(i) or a dual-aperture device 111 as shown in Figure 14(d) can be fabricated by accordingly patterning the p-pad 305. In the case of a single-aperture design, the p-pad is photolithographically defined to aid aperture demarcation.

[0445] The device 111 is attached to the carrier 307 via the bonding layer 306. The device 111 is then removed from the substrate 101 using an adhesive film. The raised shape 1010 is then transferred by photolithography onto the n-GaN side at the interface between the growth restriction mask 102 and the ELO region.

[0446] A second light reflecting DBR mirror 313 is deposited on the raised shape. An n-pad is blanket deposited for electrical connection.

[0447] Finally, the device 111 is transferred to a carrier 307a via the bonding layer 306a. Alternatively, by selecting a carrier 307 and a bonding layer 306 that are transparent to the emission light of the device 111, the transfer process to the second carrier 307a can be avoided.

[0448] Design 4

[0449] Figure 10(j) and 14(e) Another type of design, referred to as Design 4, is shown.

[0450] In this design, a first light reflecting mirror is designed at a designated portion of the wing region of the stripe 110 by defining a current confining region 308 on the p-GaN side.

[0451] Subsequently, a current spreading layer 309 and a contact layer (e.g., ITO) are deposited over the region including the current confining hole. A light reflecting DBR mirror 301 (which is a combination of dielectric layers with different refractive indices) is placed over the current confining hole with the contact layer between the p-GaN and the DBR.

[0452] At this stage, a single-aperture device 111 as shown in FIG10(j) or a dual-aperture device 111 as shown in FIG14(e) can be manufactured by patterning the p-pad 305 accordingly. In the case of a single-aperture design, the p-pad 305 is photolithographically defined to aid aperture demarcation. This design defines the n-pad 305 and the p-pad 311 on the same side.

[0453] The III-nitride semiconductor layers 105, 106, and 109 are etched from top to bottom to expose the n-GaN layer in order to define the n-pad 311. The n-pad 311 is deposited at a designated portion.

[0454] Device 111 is attached to carrier 307 via bonding layer 307. Device 111 is then removed from substrate 101 using an adhesive film. Then, at the interface between growth restriction mask 102 and ELO III-nitride layer 105, a raised shape is transferred to the n-GaN side by photolithography.

[0455] The second light reflecting DBR mirror 313 is deposited on the convex shape.

[0456] Finally, the device 111 is transferred to the carrier 307 a via the bonding layer 306 a .

[0457] Alternatively, by selecting a carrier 307 and a bonding layer 306 that are transparent to the emitted light of the device 111 , a transfer process to the second carrier 307 a may be avoided.

[0458] Design 5

[0459] Figure 10(k) and14(f) Another type of design, referred to as Design 5, is shown.

[0460] This design can be fabricated on a III-nitride layer grown by the methods mentioned in Figures 1(c) and 11(b).

[0461] In this design, a convex shape is patterned on the p-side of device 111. Specifically, the III-nitride-based epitaxial layer 106 of device 111 is terminated with a p-type layer. To create a curved surface, a thick n-GaN layer 310 is deposited on the p-GaN layer after defining a current confinement region 308 in the p-layer.

[0462] A raised shape is then patterned on the thicker n-GaN layer on either side of the open area coinciding with the wing area of ​​the ELO. A current spreading layer 309 (eg, ITO) is deposited on the raised area, followed by a light reflecting element 313 and then a p-pad 305.

[0463] At this stage, a single-aperture device 111 as shown in Figure 10(k) or a dual-aperture device 111 as shown in Figure 14(f) can be distinguished by correspondingly patterning the p-pad 305. In the case of a single-aperture design, the p-pad 305 is photolithographically defined to aid aperture demarcation.

[0464] The device 111 is then attached to the carrier 307 via the bonding layer 306. The device 111 is then removed from the substrate 101 using an adhesive film.

[0465] On the backside of the n-GaN device 111 , at the interface 312 between the growth limit mask 102 and the ELO III-nitride layer 105 , a second light reflecting mirror 313 is photolithographically defined, and an n-pad 311 is deposited to contact the n-GaN layer.

[0466] Design 6

[0467] Figure 10(l) and 14(g) Another type of design, referred to as Design 6, is shown.

[0468] In this design, a convex shape is patterned on the p-side of device 111. Specifically, the III-nitride-based epitaxial layer 106 of device 111 is terminated with a p-type layer. To create a curved surface, a thick n-GaN layer 310 is deposited on the p-GaN layer after defining a current confinement region 308 in the p-layer.

[0469] Raised shapes are patterned on the thicker n-GaN layer 310 on either side of the opening area, coinciding with the wing regions of the ELO III-nitride layer 105. A current spreading layer 309 (e.g., ITO) is deposited on the raised areas, and then a light reflecting element 301 is deposited on the raised shapes, followed by the p-pad layer 305.

[0470] In this design, n-pad 311 and p-pad 305 are on the same side of device 111 , where the III-nitride semiconductor layers 105 , 106 , 109 are etched from top to bottom and n-pad 311 is deposited at the designated area.

[0471] At this stage, the single-aperture device 111 as shown in FIG. 10( l ) or the dual-aperture device 111 as shown in FIG. 14( g ) can be distinguished by patterning the p-pad 305 and the n-pad 311 accordingly.

[0472] The device 111 is attached to the carrier 307 via the bonding layer 306. The device 111 is then removed from the substrate 101 using an adhesive film.

[0473] On the back side of the device 111 , which is n-GaN, at the interface 312 between the growth limit mask 102 and the ELO III-nitride layer 105 , a second light reflecting mirror 313 is photolithographically defined or blank deposited to complete the device 111 .

[0474] Design 7

[0475] Figure 3(l) 、 3(m) , 23(a)-23(f) show another type of design, referred to as Design 7.

[0476] In this design, a light-reflecting mirror DBR 301 is placed on the initially grown coalesced III-nitride semiconductor layer 105. The DBR 301 is embedded in the second stage of MOCVD growth, so that coalescence lines appear above the newly established growth confinement mask 303. Once the DBR 301 is embedded, the III-nitride semiconductor layer 106, including the active layer and the p-GaN layer, is grown, as shown in FIG3(c).

[0477] The design of Figure 3(1) includes a p-pad 305 and an n-pad 311 on the same side of the device 111. A current confinement layer 308 is designed at a specified location on the p-GaN layer using photolithography. Thereafter, a current spreading layer 309 is placed on the p-GaN layer containing the current confinement hole. A light reflecting DBR mirror 313 is placed on the current confinement hole. The p-pad 305 is then defined on the light reflecting DBR mirror, and the n-pad 311 is deposited on the n-GaN layer by etching the device 111 from top to bottom until the n-GaN layer is exposed. The device 111 is attached to a carrier 307 via a bonding layer 306. The device 111 is then removed from the substrate 101 using an adhesive film.

[0478] exist Figures 23(a)-23(d) In the example, light-reflecting DBR mirror 301 can be placed on the initially grown island-shaped III-nitride semiconductor layer 109. DBR mirror 301 will be embedded in the second stage of MOCVD growth as a result of coalescence lines appearing above growth restriction mask 102. The position of these lines can be adjusted by exposing regions 2301 and 2302. For example, by making the width of opening region 2301 between the width of growth restriction mask 102 and the exposed region including layer bending region 108, and by making region 2302 wider than region 2301, DBR mirror 310 can be embedded so that coalescence line 2303 resides at the edge of DBR mirror 301. Thus, the distance between the two coalescence lines 2303 can be manipulated to obtain a high-quality epitaxial region of DBR mirror 301. Once the DBR 301 is embedded as shown in FIG23(b), a Group III nitride semiconductor layer 106 including an active layer and a p-GaN layer is grown as shown in FIG23(c), and a p-pad 305 is deposited as shown in FIG23(d).

[0479] The p-pad 305 and n-pad 311 are located on opposite sides of the device 111. A current confinement layer 308 is designed at a designated location on the p-GaN layer using photolithography. A current spreading layer 309 is then placed on the p-GaN layer containing the current confinement hole. A light-reflecting DBR mirror 301 is placed over the current confinement hole. This design is only for a single hole. The hole on the p-side essentially overlaps between the two wing regions obtained during the two ELO growths, and more specifically, overlaps between the two coalescence lines generated by the secondary ELO growth. The p-pad 305 is defined on the light-reflecting mirror 301. The device 111 is attached to a carrier 307 via a bonding layer 306. The device 111 is then removed from the substrate 101 using an adhesive film. The n-pad 311 is then deposited on the backside at the designated area in a manner that does not obstruct light emission.

[0480] exist Figure 23(e) and 23(f)In the figure, p-pad 305 and n-pad 311 are on opposite sides of device 111. A current confinement layer 308 is designed at a designated location on the p-GaN layer using photolithography. A current spreading layer 309 is then placed on the p-GaN layer containing the current confinement hole. A light-reflecting DBR mirror 301 is placed over the current confinement hole. This design is only for a single hole. The hole on the p-side essentially overlaps between the two wing regions obtained during the two ELO growths, and more specifically, overlaps between the two merged lines generated by the secondary ELO growth. P-pad 305 is defined on light-reflecting mirror 301. Device 111 is attached to carrier 307 via bonding layer 306. Device 111 is then removed from substrate 101 using an adhesive film. An n-pad 311 is then deposited on the backside at the designated area in a manner that does not obstruct light emission.

[0481] Pattern 1

[0482] Pattern 1 Figures 4(a)-4(g) As shown in , this is a set of designs that require preprocessing before performing actual ELO. Figures 4(a)-4(g) The shape shown can be obtained in several ways,

[0483] For example, Figures 4(a)-4(g) The pattern 1 can be obtained by the following steps:

[0484] i. Depositing a highly doped III-nitride layer 401 on the III-nitride substrate 101 .

[0485] ii. Depositing a mask 402 in the form of stripes on the highly doped III-nitride layer 401, the mask 402 having two different widths x, y separated by a distance z.

[0486] iii. For example, the highly doped Group III nitride layer 401 is selectively etched using electrochemical etching.

[0487] iv. The resulting concavity 403 may appear in the selectively etched areas.

[0488] v. The resulting concave shape 403 is covered by a growth limiting mark 404, while a region 405 with a width of 1 μm to 10 μm is selectively opened between two concave shapes 403. The opened region 405 is preferably smaller than 5 μm.

[0489] Pattern 2

[0490] Pattern 2 Figures 5(a)-5(g) As shown in , this is a set of designs that need to be pre-processed before performing the actual ELO. Figures 5(a)-5(g) The shape shown can be obtained in several ways.

[0491] For example, Figures 5(a)-5(g)Pattern 2 in can be obtained by following the steps below:

[0492] i. Depositing a highly doped III-nitride layer 501 on the III-nitride substrate 101. Alternatively, the pattern may utilize the III-nitride substrate 101 without a highly doped layer.

[0493] ii. Depositing a mask 502 in the form of stripes on the highly doped III-nitride layer 501, the mask 502 having two different widths x, y separated by a distance z.

[0494] iii. The highly doped Group III nitride layer 501 is then selectively dry etched, for example using reactive ion etching, resulting in a recessed shape 503 that may appear at the selectively etched areas.

[0495] iv. Then, the substrate 101 including the recessed area is covered with a growth limiting mark 504, while a region 505 with a width of 1 μm to 10 μm is selectively opened between two consecutive recessed shapes 503. The opening region 505 is preferably less than 5 μm.

[0496] Design 8: Device on Pattern 1

[0497] In this design, referred to as Design 8 with Pattern 1, the epitaxial layer is grown laterally on Figures 4(a)-4(g) on a patterned mask.

[0498] The III-nitride epitaxial layer 105 exhibits a concave shape 403 at the windows on either side of the opening region 405. Later, a III-nitride based layer 106 including an active layer and a p-GaN layer is grown on 405. The device 111 can be separated into single-hole devices 111, or can be integrated as a whole containing two holes as a single device 111 as needed.

[0499] The configuration of device 111 is best suited for a long cavity resonator 412 between two light reflecting mirrors 408, 413. By having a long light reflecting cavity, better thermal management and less tolerance on the placement of active layers in the cavity 412 can be achieved, thus foreseeing more feasible manufacturability.

[0500] After growing the active layer and p-GaN layer on top of the base III-nitride semiconductor layer, photolithography is used to design a current confinement layer 406 at a desired location on the p-GaN layer. A current spreading layer 407 is then placed on the p-GaN layer containing the current confinement aperture. A light-reflecting mirror 408, such as a DBR mirror, is placed over the current confinement aperture. Both single and dual apertures are possible designs. The aperture on the p-side is placed vertically above the concave region. A p-pad 409 is defined on the light-reflecting mirror.

[0501] Device 111 is then attached to carrier 410 via bonding layer 411. Device 111 is then removed from substrate 101 using an adhesive film. After transferring device 111 to the carrier, a light-reflecting mirror is deposited on the raised shape area (when viewing the back side of device 111), which then defines an n-pad.

[0502] If only devices 111 with a single hole are required, the separation of the dual-hole devices 111 can be performed along line YY' as shown in FIG. 5( f ).

[0503] If the carrier and bonding layer are transparent for the emitted light from the aperture, no further transfer is required; however, if an opaque carrier and / or bonding layer is chosen, the device 111 must be transferred to the carrier 410 using the bonding layer 411 after fabrication of the n-side light reflecting mirror and the n-pad.

[0504] Design 9: Device on Pattern 2

[0505] In this design, referred to as design with pattern 2, the epitaxial layer is grown laterally on Figures 5(a)-5(g) 3(a) . The dry etch can create penetrations into the III-nitride semiconductor ELO layer 105 anywhere between sharp edges or tapered edges.

[0506] The III-nitride epitaxial layer 105 has a designed shape (sharp or tapered) 510 at the windows on either side of the opening region 505. Later, a III-nitride-based layer 106 including an active layer and a p-Gan layer is grown on 105. The device 111 can be a single-hole device 111 alone, or can be integrated into a whole containing two holes as a single device 111 as needed.

[0507] The configuration of device 111 is best suited for a long cavity resonator 512 between two light reflecting mirrors. By having a long light reflecting cavity, better thermal management and less tolerance on the placement of active layers in the cavity can be achieved, thus foreseeing feasible manufacturability.

[0508] After growing the active layer and p-GaN layer on top of the base III-nitride semiconductor layer, photolithography is used to design a current confinement layer 506 at a desired location on the p-GaN layer. A current spreading layer 507 is then placed on the p-GaN layer containing the current confinement hole. A light-reflecting mirror 508 is placed over the current confinement hole. Both single and dual hole designs are possible. The hole on the p-side is placed vertically above the concave region. A p-pad 509 is defined on the light-reflecting mirror.

[0509] Device 111 is then attached to carrier 510 via bonding layer 511. Device 111 is then removed from substrate 101 using an adhesive film. After transferring device 111 to carrier 510, a light-reflecting mirror is deposited on design shape 504 (when viewing the backside of device 111) and defines an n-pad.

[0510] If only devices 111 with a single aperture are required, separation of the dual-aperture devices 111 is performed along line YY' as shown in FIG. 5( f ).

[0511] If the carrier and bonding layer are transparent for the emitted light from the hole, no further transfer is required; however, if an opaque carrier and / or bonding layer is chosen, the device 111 must be transferred to the carrier 510 using the bonding layer 511 after manufacturing the n-side light reflecting mirror and the n-pad.

[0512] The device 111 described above consists of the following III-nitride semiconductor device layers 106 placed one on top of the other in the order described, grown on an ELO III-nitride layer 105 deposited on a growth limit mask 102: n-Al 0.06 GaN cladding layer, n-GaN guiding layer, InGaN / GaN multiple quantum well (MQW) active layer, AlGaN EBL layer, p-GaN waveguide layer, ITO cladding layer, SiO2 current confinement layer (or reactive ion etching can be used to confine the current to the hole), and p-electrode.

[0513] The optical resonator consists of a cavity structure with cavities formed at the top and bottom of device 111. Dielectric DBRs, also known as optical reflective mirrors, consist of multiple dielectric layers with different refractive indices. The optical resonator provides optical confinement in the vertical direction. The length between the two DBRs in the optical resonator structure is on the order of 5 to 50 μm, and is typically 10 μm. Indium tin oxide (ITO) serves as a current spreading layer.

[0514] Conventional methods such as photolithography and dry etching or reactive ion etching can be used to fabricate the hole structure. The depth of the current confinement region (from the top to the bottom surface) is within the p-GaN waveguide layer. Based on simulations or previous experimental data, the region of interest for current blocking is pre-determined before etching is performed.

[0515] In one embodiment, the p-electrode 509 can be composed of one or more of the following materials: Pd, Ni, Ti, Pt, Mo, W, Ag, Au, etc. For example, the p-electrode 509 can include Pd-Ni-Au (thickness of 3-30-300 nm). These materials can be deposited by electron beam evaporation, sputtering, thermal evaporation, etc. In addition, the p-electrode 509 is typically deposited on the ITO current spreading layer 507.

[0516] Process steps

[0517] Figure 25 The present invention is a flow chart illustrating a method for fabricating a high-quality light-emitting aperture for a VCSEL device 111 on an ELO wing region of an ELO III-nitride layer 105, wherein one or more strips 110 of the device 111 comprised of III-nitride semiconductor layers 105, 106, 109 are formed on a substrate 101. The steps of the method are described in more detail below.

[0518] Block 2501 represents the step of providing a host substrate 101. In one embodiment, substrate 101 is a semiconductor substrate, regardless of crystal orientation, such as a Group III nitride-based substrate 101 (e.g., a GaN-based substrate 101) or a foreign substrate 101 (e.g., a sapphire substrate 101). This step may also include an optional step of depositing a template layer on or above substrate 101, wherein the template layer may include a buffer layer or an intermediate layer, such as a GaN bottom layer.

[0519] Box 2502 represents the step of depositing a growth restriction mask 102 on or over substrate 101 (ie, on substrate 101 itself or on a template layer). Growth restriction mask 102 is patterned to include a plurality of stripe-shaped opening regions 103. Growth restriction mask 102 may include a multi-layer structure.

[0520] Block 2503 represents the step of forming one or more III-nitride layers 105 on or over growth limit mask 102 using epitaxial lateral overgrowth (ELO). This step may or may not include stopping the growth of ELO III-nitride layers 105 before adjacent ones of the ELO III-nitride layers 105 coalesce with each other.

[0521] Block 2504 represents the step of growing one or more III-nitride device layers 106 on or over ELO III-nitride layer 105, thereby fabricating strips 110 that form one or more devices 111 on substrate 101. Fabrication of additional devices 111 may occur before and / or after strips 110 are removed from substrate 101.

[0522] Box 2505 represents the step of fabricating strip 110 into device 111 .

[0523] Block 2506 represents the step of removing strip 110 comprised of ELO III-nitride layer 105 and III-nitride device layer 106 from substrate 101. The removed ELO III-nitride layer 105 comprises at least a partially processed portion of VCSEL device 111. The thickness of the removed ELO III-nitride layer 105 is epitaxially controlled to achieve a functional version of VCSEL device 111. At least one of the removed ELO III-nitride layers 105 is used to extract heat from VCSEL device 111 during operation of device 111.

[0524] Block 2507 represents the step of placing one or more dielectric distributed Bragg reflector (DBR) mirrors for the resonant cavity of the VCSEL device 111 on the back side of the removed ELO III-nitride layer 105, wherein the back side of the removed ELO III-nitride layer 105 has a non-planar shape, and the dielectric DBR mirrors are placed on the back side of the removed ELO III-nitride layer 105 at the wing region of the removed ELO III-nitride layer 105. The host substrate is pre-patterned to achieve the non-planar shape, and the non-planar shape includes a curvature, the back side of the removed ELO III-nitride layer 105 has a finite radius of curvature, and the center of the curvature is on one side of the surface of the host substrate 101. The at least one dielectric DBR mirror is sandwiched between the removed ELO III-nitride layers 105. A dielectric DBR mirror is placed on the back side of the removed ELO III-nitride layer 105 at a distance of at least 1 μm from the edges of the coalescing and opening regions 103. The resonant cavity of the VCSEL device 111 formed by the DBR mirror does not contain a substantial portion of the host substrate 101.

[0525] Block 2508 represents the optional step of dividing the strip 110 into one or more devices 111 at dividing support regions formed along the strip 110 .

[0526] Block 2509 represents the step of mounting the device 111 in the module, wherein the device 111 is mounted to the poles and platforms of the module.

[0527] Box 2510 represents the resulting products of the method, namely, one or more III-nitride-based semiconductor devices 111 (such as VCSEL devices 111) fabricated according to the method, and the substrate 101 that has been removed from the devices 111 and is available for recycling and reuse.

[0528] Device 111 may include one or more ELO III-nitride layers 105 grown on or over growth limit mask 102 on substrate 101, wherein growth of ELO III-nitride layers 105 is stopped before adjacent ones of ELO III-nitride layers 105 coalesce with each other. Device 111 may also include one or more additional III-nitride device layers 106 grown on or over ELO III-nitride layers 105 and substrate 101.

[0529] Advantages and Benefits

[0530] The present invention provides many advantages and benefits:

[0531] The expensive III-nitride based substrate 101 can be reused after the substrate 101 is removed from the device layer 106 .

[0532] • High quality layers 105, 106, 109 can be obtained using a substrate 101 of the same or similar material with a very low defect density.

[0533] • Using the same or similar materials for both the substrate 101 and the layers 105 , 106 , 109 may reduce strain in the layers 105 , 106 , 109 .

[0534] • Using materials with the same or similar thermal expansion for both the substrate 101 and the layers 105, 106, 109 can reduce bowing of the substrate 101 during epitaxial growth.

[0535] • The layer 105 grown by ELO has good crystal quality.

[0536] When the ELO III-nitride layers 105 are not coalesced, the internal strain is relieved, which helps to avoid any cracks. This is very useful for the device layer 106 being an AlGaN layer, especially in the case of a high Al content layer.

[0537] The resonant cavity of the VCSEL device 111 is fabricated on the ELO wing region.

[0538] The ELO wing region is a low-defect region, which improves the characteristics of the device 111 .

[0539] • No tedious substrate thinning process is required to fabricate the second DBR mirror of the cavity. Conventional fabrication requires thinning to avoid significant absorption of the emission wavelength of the device 111.

[0540] Alternative processes for removing semiconductor layers, such as photochemical etching, are dependent on the crystal plane and are extremely slow. However, the method described herein is not crystal plane dependent. By controlling the growth restriction mask 102 and the growth parameters, any plane of the crystal can achieve a smooth interface at the growth restriction mask 102.

[0541] • On the other hand, the removal method of the present invention is inexpensive, stable, and can be used for mass transfer.

[0542] • After removal of the ELO III-nitride layers 105, they can be simply surface bonded to externally prepared DBR mirrors by surface activation or diffusion bonding, as the interface of the removed layers is smooth enough to facilitate such bonding techniques.

[0543] Embedded DBR reflector design can better manage heat.

[0544] Long cavity curved mirror structures can be fabricated without involving complex steps and using only epitaxially grown layers, which allows recycling of the substrate.

[0545] The island-shaped group III nitride semiconductor layer 109 is isolated and formed, thereby reducing tensile stress or compressive stress.

[0546] Furthermore, the growth limit mask 102 and the ELO III-nitride layer 105 are not chemically bonded, so stress in the ELO III-nitride layer 105 and the additional device layer 106 can be relaxed by slip induced at the interface between the growth limit mask 102 and the ELO III-nitride layer 105 .

[0547] The presence of non-growth regions 104 between each island-shaped III-nitride semiconductor layer 109 provides flexibility, allowing substrate 101 to easily deform and potentially bend when an external force is applied. Therefore, even if slight warping, curvature, or deformation occurs in substrate 101, this can be easily corrected with a small external force, preventing the occurrence of cracks. As a result, handling substrate 101 using a vacuum chuck is possible, facilitating the manufacturing process of semiconductor device 111.

[0548] • The non-growth region 104 makes it easy to dissolve the growth limit mask 102 over a large area.

[0549] By suppressing the curvature of the substrate 101, high-quality semiconductor crystal layers 105, 106, 109 can be grown. Furthermore, even when the layers 105, 106, 109 are very thick, the occurrence of cracks can be suppressed, thereby easily realizing a large-area semiconductor device 111.

[0550] • This manufacturing method can also be easily applied to large wafer sizes (>2 inches).

[0551] • Light emitting apertures made on either side of the opening area 103 will improve the size of the light output.

[0552] By conventional means, it is difficult to place similar light emitting devices 111 close enough to solve the problem of insufficient light.

[0553] in conclusion

[0554] This concludes the description of the preferred embodiments of the present invention. The foregoing description of one or more embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the present invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. A method comprising: forming one or more epitaxial lateral overgrowth (ELO) III-nitride layers on the growth confinement mask using the master substrate; removing the ELO III-nitride layer from the host substrate; as well as One or more dielectric distributed Bragg reflector (DBR) mirrors for a resonant cavity of a vertical cavity surface emitting laser (VCSEL) are placed on the back side of the removed ELO III-nitride layer at the wing regions of the removed ELO III-nitride layer.

2. The method of claim 1 , further comprising placing at least one of the dielectric DBR mirrors on the ELO III-nitride layer and forming an additional ELO III-nitride layer on at least one of the dielectric DBR mirrors.

3. The method according to claim 1, wherein The wing region has a roughness value of less than 2 nm.

4. The method according to claim 2, wherein: At least one of the dielectric DBR mirrors is sandwiched between the removed ELO Group III-nitride layer and the additional ELO Group III-nitride layer.

5. The method according to claim 1, wherein The dielectric DBR mirror is placed on the back side of the removed ELO III-nitride layer at a distance of at least 1 μm from the coalescence region of the ELO III-nitride layer and the edge of the opening region of the growth limit mask.

6. The method according to claim 1, wherein The removed ELO Group III-nitride layer comprises at least a partially processed portion of the VCSEL.

7. The method according to claim 1, wherein Epitaxy controls the thickness of the removed ELO III-nitride layer to achieve a functional version of the VCSEL.

8. The method according to claim 1, wherein At least one of the removed ELO Group III-nitride layers is used to extract heat from the VCSEL during device operation.

9. The method according to claim 1, wherein: The resonant cavity of the VCSEL does not include a portion of the main substrate that is larger than a threshold value.

10. The method according to claim 1, wherein The back side of the removed ELO Group III-nitride layer has a non-planar shape.

11. The method according to claim 10, wherein: The non-planar shape includes a curvature, the back side of the removed ELO III-nitride layer has a finite radius of curvature, and the center of the curvature is located on one side of the surface of the host substrate.

12. The method according to claim 10, wherein: The master substrate is pre-patterned to achieve the non-planar shape.

13. The method according to claim 1, wherein The growth restriction mask includes a multi-layer structure.

14. The method according to claim 1, wherein The growth limiting mask is placed using a sputtering-type deposition system.

15. The method according to claim 1, wherein The main substrate is a semiconductor substrate.

16. The method according to claim 15, wherein The semiconductor substrate is a Group III nitride substrate.

17. The method according to claim 15, wherein: The semiconductor substrate is independent of crystal orientation.

18. A device comprising: forming one or more epitaxially laterally overgrown (ELO) III-nitride layers on a growth confinement mask using a master substrate, wherein the ELO III-nitride layers are removed from the master substrate after formation to expose a backside of the ELO III-nitride layers; as well as One or more dielectric distributed Bragg reflector (DBR) mirrors for a resonant cavity of a vertical cavity surface emitting laser (VCSEL) are placed on the exposed back side of the ELO III-nitride layer at the wing regions of the removed ELO III-nitride layer.

19. A method for producing high-quality and manufacturable holes for light-emitting elements, comprising: forming a Group III nitride semiconductor layer on a substrate using a growth limit mask and epitaxial lateral overgrowth (ELO), wherein the Group III nitride semiconductor layer is formed into strips of one or more devices; and One or more light emitting resonant cavities are fabricated on the strips, wherein the light emitting resonant cavities are defined by distributed Bragg reflectors formed on the epitaxial laterally overgrown wing regions.

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