Three-Dimensional Memory Device Comprising an Antioxidant Contact Structure and Method for Manufacturing the Same

Abstract

The present invention relates to a semiconductor structure, which includes: semiconductor devices located on the top surface of a substrate semiconductor layer, a lower-level metal interconnect structure, a source-level material layer, and a three-dimensional memory array. The three-dimensional memory array includes: an alternating stack of insulating layers and conductive layers, and memory stack structures that vertically extend through the alternating stack and include corresponding vertical semiconductor channels and corresponding memory membranes. A vertical alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. Through-memory-level interconnect via structures vertically extend through each plate within the vertical alternating sequence and contact a central portion of the top surface of one of the lower-level metal interconnect structures. At least one silicon nitride liner prevents or reduces oxidation of the lower-level metal interconnect structure below the through-memory-level interconnect via structures.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non - Provisional Application No. 16 / 952,526, filed on November 19, 2020, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly, to a three - dimensional memory device including an antioxidant contact structure and a method of manufacturing the same. Background Art

[0004] A three - dimensional memory device may include a memory stack structure. The memory stack structure is disposed over a substrate and extends through an alternating stack of insulating layers and conductive layers. The memory stack structure includes a vertical stack of memory elements disposed at levels of the conductive layers. Peripheral devices may be disposed on the substrate below the alternating stack and the memory stack structure. Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a semiconductor structure including: a semiconductor device on a top surface of a substrate semiconductor layer; a lower - level metal interconnect structure embedded in a lower - level dielectric material layer, electrically connected to the semiconductor device, and disposed over the substrate semiconductor layer; a source - level material layer disposed over the lower - level dielectric material layer and including an opening therethrough; an alternating stack of insulating layers and conductive layers disposed over the source - level material layer; a memory stack structure vertically extending through the alternating stack and including corresponding vertical semiconductor channels and corresponding memory membranes; a vertical alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack; a first through - memory - level interconnect via structure vertically extending through each plate within the vertical alternating sequence and contacting a central portion of a top surface of one of the lower - level metal interconnect structures; and at least one silicon nitride liner contacting a peripheral portion of a top surface of one of the lower - level metal interconnect structures and contacting a cylindrical bottom end portion of a sidewall of the first through - memory - level interconnect via structure.

[0006] According to one aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes: forming a semiconductor device on a top surface of a substrate semiconductor layer; forming a lower-level metal interconnect structure that is embedded in a lower-level dielectric material layer and electrically connected to the semiconductor device above the substrate semiconductor layer; forming a three-dimensional array of memory elements above the lower-level dielectric material layer, wherein the three-dimensional array of memory elements includes: an alternating stack of insulating layers and conductive layers that covers a source-level material layer; a memory stack structure that extends vertically through the alternating stack and includes corresponding vertical semiconductor channels and corresponding memory membranes; and a vertical alternating sequence of insulating plates and dielectric material plates that is laterally surrounded by the alternating stack; forming a first through-memory-level via cavity through each plate within the vertical alternating sequence; and forming a first through-memory-level interconnect via structure in the first through-memory-level via cavity, wherein: the first through-memory-level interconnect via structure contacts a central portion of a top surface of one of the lower-level metal interconnect structures; and at least one silicon nitride liner contacts a peripheral portion of the top surface of one of the lower-level metal interconnect structures and contacts a cylindrical bottom end portion of a sidewall of the first through-memory-level interconnect via structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a vertical cross-sectional view of an exemplary structure after forming a semiconductor device, a lower-level dielectric layer, a lower metal interconnect structure, and a source-level material layer in a process according to a first embodiment of the present disclosure.

[0008] Figure 1B is Figure 1A an enlarged view of the source-level material layer in the process of

[0009] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a first alternating stack of an insulating layer and a first spacer material layer according to an embodiment of the present disclosure.

[0010] Figure 3 is a vertical cross-sectional view of an exemplary structure after patterning a first stepped region, a first backward stepped dielectric material portion, and an interlayer dielectric layer according to an embodiment of the present disclosure.

[0011] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a first memory opening, a first support opening, and various sacrificial fill structures according to an embodiment of the present disclosure.

[0012] Figure 5is a vertical cross-section of an exemplary structure after forming a second insulating layer and a second spacer material layer of an alternating stack, a second stepped surface, and a second backward stepped dielectric material portion according to an embodiment of the present disclosure.

[0013] Figure 6 is a vertical cross-section of an exemplary structure after forming an interlayer memory opening and an interlayer support opening according to an embodiment of the present disclosure.

[0014] Figures 7A to 7D Shows sequential vertical cross-sections of a memory opening during formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0015] Figure 8A is a vertical cross-section of an exemplary structure after forming a memory opening fill structure and a support pillar structure according to an embodiment of the present disclosure.

[0016] Figure 8B is Figure 8A another vertical cross-section of the exemplary structure.

[0017] Figure 8C is Figure 8A and Figure 8B yet another vertical cross-section of the exemplary structure.

[0018] Figure 8D is a horizontal cross-section along the Figure 8B horizontal plane D-D’. The vertical cross-section plane B-B’ is the plane of the vertical cross-section of Figure 8B The vertical cross-section plane C-C’ is the plane of the vertical cross-section of Figure 8C

[0019] Figure 9A is a vertical cross-section of an exemplary structure after forming a dielectric trench structure according to an embodiment of the present disclosure.

[0020] Figure 9B is Figure 9A another vertical cross-section of the exemplary structure.

[0021] Figure 9C is Figure 9A and Figure 9B yet another vertical cross-section of the exemplary structure.

[0022] Figure 9D is a horizontal cross-section along the Figure 9B horizontal plane D-D’. The vertical cross-section plane B-B’ is the plane of the vertical cross-section of Figure 9B The vertical cross-section plane C-C’ is the plane of the vertical cross-section of Figure 9C

[0023] Figure 10A is a vertical cross - sectional view of an exemplary structure after forming a dorsal trench and a through - memory - tier via cavity in accordance with an embodiment of the present disclosure.

[0024] Figure 10B is Figure 10A another vertical cross - sectional view of an exemplary structure.

[0025] Figure 10C is Figure 10A and Figure 10B yet another vertical cross - sectional view of an exemplary structure.

[0026] Figure 10D is a horizontal cross - sectional view along the Figure 10B horizontal plane D - D'. The vertical cross - sectional plane B - B' is the plane of the vertical cross - section of Figure 10B The vertical cross - sectional plane C - C' is the plane of the vertical cross - section of Figure 10C

[0027] Figures 11A to 11C Shows a sequential vertical cross - sectional view of a memory opening fill structure and a dorsal trench during the formation of a source - tier material layer in accordance with an embodiment of the present disclosure.

[0028] Figure 12A is a vertical cross - sectional view of an exemplary structure after depositing a conformal silicon nitride liner in accordance with an embodiment of the present disclosure.

[0029] Figure 12B is Figure 12A another vertical cross - sectional view of an exemplary structure.

[0030] Figure 12C is Figure 12A and Figure 12B yet another vertical cross - sectional view of an exemplary structure.

[0031] Figure 13A is a vertical cross - sectional view of an exemplary structure after forming a conformal silicon oxide liner in accordance with an embodiment of the present disclosure.

[0032] Figure 13B is Figure 13A another vertical cross - sectional view of an exemplary structure.

[0033] Figure 13C is Figure 13A and Figure 13B yet another vertical cross - sectional view of an exemplary structure.

[0034] Figure 14A is a vertical cross - sectional view of an exemplary structure after patterning a conformal silicon oxide liner and a conformal silicon nitride liner in accordance with an embodiment of the present disclosure.

[0035] Figure 14B is Figure 14A Another vertical cross-sectional view of an exemplary structure of

[0036] Figure 14C is Figure 14A and Figure 14B Another vertical cross-sectional view of an exemplary structure of

[0037] Figure 14D is a horizontal cross-sectional view along the Figure 14B horizontal plane D-D'. The vertical cross-sectional plane B-B' is Figure 14B the plane of the vertical cross-section of Figure 14C The vertical cross-sectional plane C-C' is

[0038] Figure 15A A vertical cross-sectional view of an exemplary structure after an oxidation process for forming a dielectric semiconductor oxide material portion according to an embodiment of the present disclosure.

[0039] Figure 15B is Figure 15A Another vertical cross-sectional view of an exemplary structure of

[0040] Figure 15C is Figure 15A and Figure 15B Another vertical cross-sectional view of an exemplary structure of

[0041] Figure 15D is a horizontal cross-sectional view along the Figure 15B horizontal plane D-D'. The vertical cross-sectional plane B-B' is Figure 15B the plane of the vertical cross-section of Figure 15C The vertical cross-sectional plane C-C' is

[0042] Figure 16A A vertical cross-sectional view of an exemplary structure after forming a backside recess according to an embodiment of the present disclosure.

[0043] Figure 16B is Figure 16A Another vertical cross-sectional view of an exemplary structure of

[0044] Figure 16C is Figure 16A and Figure 16B Another vertical cross-sectional view of an exemplary structure of

[0045] Figure 16D is a horizontal cross-sectional view along the Figure 16B horizontal plane D-D'. The vertical cross-sectional plane B-B' is Figure 16B the plane of the vertical cross-section of Figure 16C The vertical cross-sectional plane C-C' is

[0046] Figure 17A is a vertical cross - sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0047] Figure 17B is Figure 17A another vertical cross - sectional view of the exemplary structure.

[0048] Figure 17C is Figure 17A and Figure 17B yet another vertical cross - sectional view of the exemplary structure.

[0049] Figure 18A is a vertical cross - sectional view of an exemplary structure after forming an insulating spacer according to an embodiment of the present disclosure.

[0050] Figure 18B is Figure 18A another vertical cross - sectional view of the exemplary structure.

[0051] Figure 18C is Figure 18A and Figure 18B yet another vertical cross - sectional view of the exemplary structure.

[0052] Figure 19A is a vertical cross - sectional view of an exemplary structure after forming various contact via structures and higher - level metal interconnect structures according to an embodiment of the present disclosure.

[0053] Figure 19B is Figure 19A another vertical cross - sectional view of the exemplary structure.

[0054] Figure 19C is Figure 19A and Figure 19B yet another vertical cross - sectional view of the exemplary structure.

[0055] Figure 19D is a horizontal cross - sectional view along the Figure 19B horizontal plane D - D'. The vertical cross - sectional plane B - B' is the plane of the vertical cross - section of Figure 19B and the vertical cross - sectional plane C - C' is the plane of the vertical cross - section of Figure 19C .

[0056] Figure 20A is a vertical cross - sectional view of a first alternative configuration of an exemplary structure after forming various contact via structures and higher - level metal interconnect structures according to an embodiment of the present disclosure.

[0057] Figure 20B is Figure 20A another vertical cross - sectional view of the exemplary structure.

[0058] Figure 21A is a vertical cross - sectional view of a second alternative configuration of an exemplary structure after forming various contact via structures and higher - level metal interconnect structures according to an embodiment of the present disclosure.

[0059] Figure 21B is Figure 21A another vertical cross - sectional view of the exemplary structure.

[0060] Figure 22A is a vertical cross - sectional view of a third alternative configuration of an exemplary structure after forming various contact via structures and higher - level metal interconnect structures according to an embodiment of the present disclosure.

[0061] Figure 22B is Figure 22A another vertical cross - sectional view of the exemplary structure.

[0062] Figure 22C is Figure 22A and Figure 22B yet another vertical cross - sectional view of the exemplary structure.

[0063] Figure 22D is a horizontal cross - sectional view along the horizontal plane D - D’ of Figure 22B The vertical cross - sectional plane B - B’ is the plane of the vertical cross - section of Figure 22B The vertical cross - sectional plane C - C’ is the plane of the vertical cross - section of Figure 22C

[0064] Figure 23A is a vertical cross - sectional view of a third alternative configuration of an exemplary structure after forming various contact via structures and higher - level metal interconnect structures according to an embodiment of the present disclosure.

[0065] Figure 23B is Figure 23A another vertical cross - sectional view of the exemplary structure. Detailed Description

[0066] Embodiments of the present disclosure provide a three - dimensional memory device including an antioxidant contact structure and a method of manufacturing the same, and various embodiments are described in detail herein.

[0067] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of the element is shown, unless explicitly described or otherwise clearly indicated as not having a repetition of the element. Serial numbers such as “first,” “second,” and “third” are used solely to identify similar elements and different serial numbers may be used throughout the specification and claims of the present disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0068] Like reference numerals designate like or similar elements. Unless otherwise specified, elements having the same reference numerals are assumed to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between elements providing shared edges or surfaces. If two or more elements do not contact each other directly or do not contact each other directly, the two elements are "separated" from each other or are "separated" from each other. As used herein, a first element positioned "on" a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is an electrical conduction path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component.

[0069] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entirety of an underlying or overlying structure, or may have a scope less than the scope of the underlying or overlying structure. Additionally, a layer may be a region of a continuous structure that is uniform or non-uniform and has a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above it, and / or below it.

[0070] As used herein, if a second surface is above or below a first surface and if there is a vertical or substantially vertical plane including the first surface and the second surface, the first surface and the second surface are "vertically coincident" with each other. A substantially vertical plane is a plane that extends linearly in a direction at an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may include or may not include curvature in a direction perpendicular to the vertical or substantially vertical direction.

[0071] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate such as a semiconductor wafer without an intervening substrate. The term "monolithic" means that the layers of each level of the array are directly deposited on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, titled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned before bonding or removed from the memory levels, but since the memory levels were initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein.

[0072] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package can include one or more semiconductor chips (or "chips") that are bonded therein, for example, by flip-chip bonding or another chip-to-chip bonding. A package or chip can include a single semiconductor die (or "die") or multiple semiconductor dice. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip having multiple dice is capable of simultaneously executing as many external commands as the total number of planes therein. Each die includes one or more planes. The same concurrent operations can be executed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be executed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0073] Reference Figure 1A and Figure 1B, showing an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a semiconductor substrate 8 and semiconductor devices 710 formed thereon. The semiconductor substrate 8 may include a substrate semiconductor layer 9 at least in its upper portion. A shallow trench isolation structure 720 may be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation between the semiconductor devices 710. The semiconductor devices 710 may include, for example, field effect transistors, which include respective transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, dielectric gate spacers 756, and a gate capping dielectric 758. The semiconductor devices 710 may include any semiconductor circuit to support the operation of a memory structure to be formed subsequently, which semiconductor circuit is generally referred to as a driver circuit, and which driver circuit is also referred to as a peripheral circuit. As used herein, a peripheral circuit refers to any one, each, or all of a word line decoder circuit, a word line switching circuit, a bit line decoder circuit, a bit line sensing and / or switching circuit, a power supply / distribution circuit, a data buffer and / or latch, or may be any other semiconductor circuit that can be implemented external to the memory array structure of a memory device. For example, the semiconductor device may include a word line switching device for electrically biasing the word lines of a three-dimensional memory structure to be formed subsequently.

[0074] A dielectric material layer may be formed over the semiconductor device, which dielectric material layer is referred to herein as a lower level dielectric material layer 760. The lower level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks the diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric material layer 764 covering the dielectric liner 762, an optional planar silicon nitride liner 766 covering the first dielectric material layer 764, and at least one second dielectric layer 768. The planar silicon nitride liner 766 preferably has a thickness greater than 2 nm, such as a thickness in the range of 4 nm to 40 nm (such as 6 nm to 20 nm). The dielectric layer stack (which includes the lower level dielectric material layer 760) may be used as a matrix for lower level metal interconnect structures 780, which lower level metal interconnect structures provide electrical wiring to and from the respective nodes of the landing pads for the through-memory level interconnect vias structures to be formed in the semiconductor device and subsequently. The lower level metal interconnect structures 780 may be formed within the dielectric layer stack of the lower level dielectric material layer 760 and cover the field effect transistors. The lower level metal interconnect structures 780 may include lower level metal line structures positioned below and optionally contacting the bottom surface of the planar silicon nitride liner 766.

[0075] For example, the lower-level metal interconnect structure 780 may be formed within the first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers, in which various elements of the lower-level metal interconnect structure 780 are sequentially formed. Each dielectric material layer selected from the first dielectric material layer 764 may include any one of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as alumina). In one embodiment, the first dielectric material layer 764 may comprise or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9, the dielectric constant of undoped silicate glass (silicon oxide). The lower-level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting corresponding source and drain nodes or gate electrode contacts of the device), intermediate lower-level metal line structures 784, lower-level metal via structures 786, and metal pad structures 788 configured to serve as landing pads for through-memory-level interconnect vias to be formed subsequently.

[0076] The metal pad structure 788 may be formed within the topmost dielectric material layer of the first dielectric material layer 764, which may be a plurality of dielectric material layers. Each of the lower-level metal interconnect structures 780 may include a metal nitride liner 788L and a metal fill structure 788F. The top surface of the metal pad structure 788 and the topmost surface of the first dielectric material layer 764 may be planarized by a planarization process such as chemical mechanical planarization. A planar silicon nitride liner 766 (if present) may be formed directly on the top surface of the metal pad structure 788 and the topmost surface of the first dielectric material layer 764.

[0077] The planar silicon nitride liner 766 may be a silicon nitride liner and may have a uniform thickness between the planar bottom surface and the planar top surface. According to one aspect of the present disclosure, the thickness of the planar silicon nitride liner 766 may be selected such that the planar silicon nitride liner 766 effectively serves as a diffusion barrier layer during a subsequent oxidation process performed after forming a three-dimensional array of memory elements and before forming through-memory-level contact via structures thereon. In one embodiment, the planar silicon nitride liner 766 may have a thickness in the range of 4 nm to 100 nm (such as 8 nm to 50 nm), but smaller and larger thicknesses may also be employed. The planar silicon nitride liner 766 may be deposited by a chemical vapor deposition process.

[0078] At least one second dielectric material layer 768 may include a single dielectric material layer or multiple dielectric material layers. Each dielectric material layer selected from the at least one second dielectric material layer 768 may include any one of doped silicate glass, undoped silicate glass, and organosilicate glass. In one embodiment, the at least one second dielectric material layer 768 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9, the dielectric constant of undoped silicate glass (silicon oxide).

[0079] Generally, the semiconductor device 710 may be formed on the top surface of the substrate semiconductor layer 9, and a lower-level metal interconnect structure 780 embedded in the lower-level dielectric material layer 760 and electrically connected to the semiconductor device 710 may be formed above the substrate semiconductor layer 9. The planar silicon nitride liner 766 may be directly formed on the top surface of a subset of the lower-level metal interconnect structures 780. The entire top surface of each lower-level metal interconnect structure 780 within the subset of the lower-level metal interconnect structures 780 may be contacted by the planar silicon nitride liner 766.

[0080] The in-process source-level material layer 10' may include various layers that are subsequently modified to form the source-level material layer. The source-level material layer, when formed, includes a source contact layer that serves as a common source region for the vertical field-effect transistors of the three-dimensional memory device. In one embodiment, the in-process source-level material layer 10' may include, from bottom to top, a lower source-level material layer 112, a lower sacrificial liner 103, a source-level sacrificial layer 104, a higher sacrificial liner 105, a higher source-level semiconductor layer 116, a source-level insulating layer 117, and an optional source-select level conductive layer 118.

[0081] The lower source-level material layer 112 and the higher source-level semiconductor layer 116 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source-level material layer 112 and the higher source-level semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the lower source-level material layer 112 and the higher source-level semiconductor layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source-level material layer 112 and the higher source-level semiconductor layer 116 may be in the range of 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses may also be used.

[0082] The source-level sacrificial layer 104 includes a sacrificial material that can be selectively removed with respect to the lower sacrificial liner 103 and the higher sacrificial liner 105. In one embodiment, the source-level sacrificial layer 104 may include a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source-level sacrificial layer 104 may be in the range of 30 nm to 400 nm, such as 60 nm to 200 nm, but smaller and larger thicknesses may also be used.

[0083] The lower sacrificial liner 103 and the higher sacrificial liner 105 include materials that can be used as an etch stop material during the removal of the source-level sacrificial layer 104. For example, the lower sacrificial liner 103 and the higher sacrificial liner 105 may include silicon oxide, silicon nitride, and / or a dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the higher sacrificial liner 105 may include a silicon oxide layer with a thickness in the range of 2 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0084] The source-level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source-level insulating layer 117 may be in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, but smaller and larger thicknesses may also be used. The optional source-select level conductive layer 118 may include a conductive material that can be used as a source-select level gate electrode. For example, the optional source-select level conductive layer 118 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon, which can subsequently be converted to doped polysilicon through an annealing process. The thickness of the optional source-select level conductive layer 118 may be in the range of 30 nm to 200 nm, such as 60 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0085] The in-process source-level material layer 10' may be formed directly above a subset of semiconductor devices on a semiconductor substrate 8 (e.g., a silicon wafer). As used herein, a first element is located "directly above" a second element if the first element is positioned above a horizontal plane that includes the top surface of the second element and the area of the first element, and the area of the second element has an area overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the semiconductor substrate 8). In one embodiment, the in-process source-level material layer 10' may have openings in each area where a via structure for direct memory level interconnection is to be subsequently formed. For example, the in-process source-level material layer 10' may have openings in the memory array region 100.

[0086] The source level material layer 10' in the process can be patterned to provide openings in regions where the direct access memory level interconnect via structure and the direct access dielectric contact via structure are to be subsequently formed therein. The patterned portions of the source level material layer 10' in the process are present in each memory array region 100, in which a three-dimensional memory stack structure will be subsequently formed.

[0087] In one embodiment, the staircase region 200 can be laterally spaced from the memory array region 100 along a first horizontal direction hd1. The horizontal direction perpendicular to the first horizontal direction hd1 is referred to herein as a second horizontal direction hd2. In one embodiment, additional openings can be formed in the source level material layer 10' within the region of the memory array region 100, in which a three-dimensional memory array including a memory stack structure will be subsequently formed. The peripheral device region 400 filled with a portion of the field dielectric material can be provided adjacent to the staircase region 200.

[0088] The region of the combination of the semiconductor device 710 and the lower level dielectric material layer 760 and the lower level metal interconnect structure 780 is referred to herein as the underlying peripheral device region 700, which is positioned below the memory level component to be subsequently formed and includes the peripheral devices for the memory level component. The lower level metal interconnect structure 780 can be formed in the lower level dielectric material layer 760.

[0089] The lower level metal interconnect structure 780 can be electrically connected to the active nodes (e.g., the transistor active region 742 or the gate electrode 754) of the semiconductor device 710 (e.g., a CMOS device), and can be positioned at the level of the lower level dielectric material layer 760. The direct access memory level interconnect via structure can be directly formed on the lower level metal interconnect structure 780 subsequently to provide an electrical connection to the memory device to be also formed subsequently. In one embodiment, the pattern of the lower level metal interconnect structure 780 can be selected such that the metal pad structure 788 (which is a subset of the lower level metal interconnect structure 780 positioned at the topmost portion of the lower level metal interconnect structure 780) can provide a landing pad structure for the direct access memory level interconnect via structure to be subsequently formed.

[0090] See Figure 2, an alternating stack of a first material layer and a second material layer can be formed. Each first material layer can include a first material, and each second material layer can include a second material different from the first material. In an embodiment where at least another alternating stack of material layers is subsequently formed over the alternating stack of the first material layer and the second material layer, the alternating stack is referred to herein as the first layer alternating stack. The levels of the first layer alternating stack are referred to herein as the first layer levels, and the levels of the alternating stack to be subsequently formed directly above the first layer levels are referred to herein as the second layer levels and so on.

[0091] The first layer alternating stack can include a first insulating layer 132 as the first material layer and a first spacer material layer as the second material layer. In one embodiment, the first spacer material layer can be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer can be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using embodiments in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are explicitly contemplated herein.

[0092] In one embodiment, the first material layer and the second material layer can be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 can include a first insulating material, and each first sacrificial material layer 142 can include a first sacrificial material. A plurality of alternating first insulating layers 132 and first sacrificial material layers 142 are formed over the source level material layer 10' during the process. As used herein, a "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0093] As used herein, an alternating stack of a first element and a second element refers to a structure in which instances of the first element and instances of the second element alternate. Each instance of the first element that is not an end element of a plurality of non-alternating elements is adjacent to two instances of the second element on both sides, and each instance of the second element that is not an end element of a plurality of non-alternating elements is adjacent to two instances of the first element at both ends. The first element can always have the same thickness, or can have different thicknesses. The second element can always have the same thickness, or can have different thicknesses.

[0094] The alternating plurality of first material layers and second material layers can start with an instance of the first material layer or an instance of the second material layer, and can end with an instance of the first material layer or an instance of the second material layer. In one embodiment, instances of the first element and instances of the second element can form a unit that repeats periodically within the alternating plurality of elements.

[0095] The first alternating stack (132, 142) may include a first insulating layer 132 made of a first material and a first sacrificial material layer 142 made of a second material different from the first material. The first material of the first insulating layer 132 may be at least one insulating material.

[0096] Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal nitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0097] The second material of the first sacrificial material layer 142 may be a sacrificial material that can be selectively removed with respect to the first material of the first insulating layer 132. As used herein, if the removal process removes the first material at a rate that is at least twice the removal rate of the second material, the removal of the first material is "selective" with respect to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material with respect to the second material.

[0098] Subsequently, the second material of the first sacrificial material layer 142 can be replaced with a conductive electrode, which can be used as, for example, a control gate electrode of a vertical NAND device. According to one aspect of the present disclosure, the first sacrificial material layer 142 includes a dielectric material. In one embodiment, the first sacrificial material layer 142 may be a material layer containing silicon nitride.

[0099] In one embodiment, the first insulating layer 132 may contain silicon oxide, and the sacrificial material layer may contain a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) can be used as the precursor material for the CVD process. The second material of the first sacrificial material layer 142 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0100] The thicknesses of the first insulating layer 132 and the first sacrificial material layer 142 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the pair of the first insulating layer 132 and the first sacrificial material layer 142 can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each first sacrificial material layer 142 in the first layer alternating stack (132, 142) can have a uniform thickness that is substantially constant within each corresponding first sacrificial material layer 142.

[0101] The first insulating capping layer 170 can then be formed over the first layer alternating stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating capping layer 170 can be in the range of 20 nm to 300 nm, but smaller and larger thicknesses can also be used.

[0102] Reference Figure 3 , the first insulating capping layer 170 and the first layer alternating stack (132, 142) can be patterned to form a first stepped surface in the stepped region 200. The staircase region 200 can include a corresponding first stepped region and a second stepped region. In the first stepped region, the first stepped surface is formed. In the second stepped region, additional stepped surfaces are subsequently formed in the second layer structure (which is subsequently formed over the first layer structure) and / or additional layer structures.

[0103] The first stepped surface can be formed, for example, by forming a mask layer having openings therein, etching cavities within the level of the first insulating capping layer 170 and iteratively expanding the etching region, and vertically recessing the cavities by etching each pair of the first insulating layer 132 and the first sacrificial material layer 142 positioned directly below the bottom surface of the etching cavities within the etching region. In one embodiment, the top surface of the first sacrificial material layer 142 can be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as the first stepped cavity.

[0104] A depositable dielectric fill material, such as undoped silicate glass or doped silicate glass, can be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material can be removed above a horizontal plane including the top surface of the first insulating capping layer 170. The remaining portion of the dielectric fill material that fills the regions on the first stepped surface constitutes the first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to the vertical distance from the substrate to the top surface on which the element is present. The first layer alternating stack (132, 142) and the first backward stepped dielectric material portion 165 together constitute the first layer structure, which is the structure in a process that is subsequently modified.

[0105] An interlayer dielectric layer 180 can optionally be deposited over the first layer structure (132, 142, 170, 165). The interlayer dielectric layer 180 comprises a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 can comprise a doped silicate glass having an etch rate greater than that of the material of the first insulating layer 132, which may comprise undoped silicate glass. For example, the interlayer dielectric layer 180 can comprise phosphosilicate glass. The thickness of the interlayer dielectric layer 180 can be in the range of 30 nm to 300 nm, although smaller and larger thicknesses can also be used.

[0106] See Figure 4 , various first layer openings can be formed through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the in-process source level material layer 10'. A photoresist layer (not shown) can be applied over the interlayer dielectric layer 180 and can be lithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer can be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the in-process source level material layer 10' by a first anisotropic etching process to simultaneously (i.e., during the first isotropic etching process) form various first layer openings. The various first layer openings can include first layer memory openings and first layer support openings.

[0107] The first layer memory openings are openings formed through each layer within the first alternating stack (132, 142) in the memory array region 100 and are subsequently used to form memory stack structures therein. The first layer memory openings can be formed in clusters of first layer memory openings. Each cluster of first layer memory openings can be formed as a two-dimensional array of first layer memory openings.

[0108] The first layer support opening is an opening formed in the stepped region 200 and is subsequently used to form a support pillar structure. A subset of the first layer support openings formed through the first backward stepped dielectric material portion 165 can be formed through the corresponding horizontal surfaces of the first stepped surface.

[0109] In one embodiment, the first anisotropic etching process can include an initial step in which the materials of the first alternating stack (132, 142) and the material of the first backward stepped dielectric material portion 165 are etched simultaneously. The chemistry of the initial etching step can be alternated to optimize the etching of the first and second materials in the first alternating stack (132, 142) while providing an average etching rate comparable to the material of the first backward stepped dielectric material portion 165. The first anisotropic etching process can use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various first layer openings can be substantially vertical or can be tapered.

[0110] After etching through the alternating stack (132, 142) and the first backward stepped dielectric material portion 165, the chemistry of the terminal portion of the first anisotropic etching process can be selected to etch through one or more dielectric materials of at least one second dielectric layer 768 at an etching rate higher than the average etching rate of the source level material layer 10' during the process. For example, the terminal portion of the anisotropic etching process can include a step of etching one or more dielectric materials of at least one second dielectric layer 768, which is selective to the semiconductor material within the component layer in the source level material layer 10' during the process. In one embodiment, the terminal portion of the first anisotropic etching process can etch through the source select level conductive layer 118, the source level insulating layer 117, the higher source level semiconductor layer 116, the higher sacrificial liner 105, the source level sacrificial layer 104, and the lower sacrificial liner 103, and at least partially into the lower source level semiconductor layer 112. The terminal portion of the first anisotropic etching process can contain at least one etching chemical for etching the various semiconductor materials of the source level material layer 10' in the process. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0111] Optionally, portions of the first layer memory openings and the first layer support openings at the level of the interlayer dielectric layer 180 may be laterally extended by isotropic etching. In such a case, the interlayer dielectric layer 180 may comprise a dielectric material (such as borosilicate glass) that has a greater etching rate in dilute hydrofluoric acid than the first insulating layer 132, which may comprise undoped silicate glass. Isotropic etching (such as wet etching using HF) may be used to extend the lateral dimension of the first layer memory openings at the level of the interlayer dielectric layer 180. Optionally, portions of the first layer memory openings located at the level of the interlayer dielectric layer 180 may be widened to provide a larger landing pad for second layer memory openings that will subsequently pass through the second layer alternating stack (formed subsequently prior to forming the second layer memory openings).

[0112] Sacrificial first layer opening fill portions (148, 128) may be formed in the various first layer openings. For example, a sacrificial first layer fill material is deposited simultaneously in each of the first layer openings. The sacrificial first layer fill material comprises a material that can be selectively removed subsequently with respect to the materials of the first insulating layer 132 and the first sacrificial material layer 142.

[0113] In one embodiment, the sacrificial first layer fill material may comprise a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0114] In another embodiment, the sacrificial first layer fill material may comprise a silicon oxide material that has a higher etching rate than the materials of the first insulating layer 132, the first insulating capping layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may comprise borosilicate glass or porous or non-porous organosilicate glass that has an etching rate at least 100 times higher than that of a dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In such a case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0115] In yet another embodiment, the sacrificial first layer fill material may include amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon) that can subsequently be removed by ashing, or a silicon-based polymer that can subsequently be selectively removed for the materials of the first alternating stack (132, 142).

[0116] Portions of the deposited sacrificial material can be removed from above the topmost layer of the first layer alternating stack (132, 142), such as from above the interlayer dielectric layer 180. For example, the sacrificial first layer fill material can be recessed into the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process can include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 can be used as an etch stop layer or a planarization stop layer.

[0117] The remaining portions of the sacrificial first layer fill material include sacrificial first layer opening fill portions (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory opening constitutes a sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support opening constitutes a sacrificial first layer support opening fill portion 128. The various sacrificial first layer opening fill portions (148, 128) are formed simultaneously, i.e., during the same set of processes, including a deposition process that deposits the sacrificial first layer fill material and a planarization process that removes the first layer deposition process from above the first alternating stack (132, 142) (such as from above the top surface of the interlayer dielectric layer 180). The top surfaces of the sacrificial first layer opening fill portions (148, 128) can be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening fill portions (148, 128) may or may not include a cavity therein.

[0118] See Figure 5 , a second layer structure can be formed above the first layer structure (132, 142, 170, 148). The second layer structure can include an additional alternating stack of an insulating layer and a spacer material layer, and these spacer material layers can be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers can subsequently be formed on the top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) includes a plurality of alternating third material layers and fourth material layers. Each third material layer can contain a third material, and each fourth material layer can contain a fourth material different from the third material. In one embodiment, the third material can be the same as the first material of the first insulating layer 132, and the fourth material can be the same as the second material of the first sacrificial material layer 142.

[0119] In one embodiment, the third material layer can be the second insulating layer 232, and the fourth material layer can be the second spacer material layer that provides a vertical spacing between each pair of vertically adjacent second insulating layers 232. In one embodiment, the third material layer and the fourth material layer can be the second insulating layer 232 and the second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 can be at least one insulating material. The fourth material of the second sacrificial material layer 242 can be a sacrificial material that can be selectively removed with respect to the third material of the second insulating layer 232. The second sacrificial material layer 242 can include an insulating material, a semiconductor material, or a conductive material. Subsequently, the fourth material of the second sacrificial material layer 242 can be replaced with a conductive electrode, which can be used as, for example, a control gate electrode of a vertical NAND device.

[0120] In one embodiment, each second insulating layer 232 can include a second insulating material, and each second sacrificial material layer 242 can include a second sacrificial material. In this case, the second alternating stack (232, 242) can include a plurality of alternating second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 can be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0121] The third material of the second insulating layer 232 can be at least one insulating material. The insulating material that can be used for the second insulating layer 232 can be any material that can be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that can be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that can be used for the second sacrificial material layer 242 can be any material that can be used for the first sacrificial material layer 142. In one embodiment, the second insulating material can be the same as the first insulating material, and the second sacrificial material can be the same as the first sacrificial material.

[0122] The thicknesses of the second insulating layer 232 and the second sacrificial material layer 242 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and second sacrificial material layer 242 pairs can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stack (232, 242) can have a uniform thickness that is substantially constant within each respective second sacrificial material layer 242.

[0123] The second stepped surface in the second stepped region can be formed in the stepped region 200 using the same set of processing steps as those used to form the first stepped surface in the first stepped region, where the pattern of at least one mask layer is appropriately adjusted. A second back-stepped dielectric material portion 265 can be formed over the second stepped surface in the stepped region 200.

[0124] Subsequently, a second insulating capping layer 270 can be formed over the second alternating stack (232, 242). The second insulating capping layer 270 comprises a dielectric material different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 can comprise silicon oxide. In one embodiment, the first sacrificial material layer and the second sacrificial material layer (142, 242) can comprise silicon nitride.

[0125] Generally, at least one alternating stack of an insulating layer (132, 232) and a spacer material layer (such as a sacrificial material layer (142, 242)) can be formed over the source level material layer 10' in the process, and at least one back-stepped dielectric material portion (165, 265) can be formed over the stepped region on the at least one alternating stack (132, 142, 232, 242).

[0126] See Figure 6 that various second layer openings can be formed through the second layer structure (232, 242, 265, 270). A photoresist layer (not shown) can be applied over the second insulating capping layer 270 and can be lithographically patterned to form various openings therethrough. The pattern of the openings can be the same as the pattern of the various first layer openings, which is the same as the sacrificial first layer opening fill portions (148, 128). Thus, the photoresist layer can be patterned using the lithographic mask used to pattern the first layer openings.

[0127] The pattern of the openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270) by a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form various second layer openings. The various second layer openings can include second layer memory openings 249 and second layer support openings 229.

[0128] The second layer memory opening 249 is formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening fill portions 148. The second layer support opening 229 is formed directly on the top surface of a corresponding one of the sacrificial first layer support opening fill portions 128. Additionally, each second layer support opening 229 may be formed to pass through a horizontal surface within the second stepped surface, which second stepped surfaces include the interface surface between the second alternating stack (232, 242) and the second backward stepped dielectric material portion 265.

[0129] The second anisotropic etching process may include an etching step in which the material of the second layer alternating stack (232, 242) and the material of the second backward stepped dielectric material portion 265 are etched simultaneously. The chemistry of the etching step may be alternated to optimize the etching of the material in the second layer alternating stack (232, 242) while providing an average etch rate comparable to that of the material of the second backward stepped dielectric material portion 265. The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etch process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various second layer openings may be substantially vertical or may be tapered. The bottom perimeter of each second layer opening may be laterally offset and / or may be fully positioned within the perimeter of the top surface of the underlying sacrificial first layer opening fill portions (148, 128). The photoresist layer may then be removed, for example, by ashing.

[0130] An etching process may be used to remove the sacrificial first layer fill material of the sacrificial first layer opening fill portions (148, 128), which etching process selectively etches the sacrificial first layer fill material with respect to the materials of the first insulating layer and the second insulating layer (132, 232), the first sacrificial material layer and the second sacrificial material layer (142, 242), the first insulating capping layer and the second insulating capping layer (170, 270), and the interlayer dielectric layer 180. A memory opening 49 (also referred to as an interlayer memory opening 49) is formed in each combination of the second layer memory opening 249 and the volume from which the sacrificial first layer memory opening fill portion 148 is removed. A support opening 19 (also referred to as an interlayer support opening 19) is formed in each combination of the second layer support opening 229 and the volume from which the sacrificial first layer support opening fill portion 128 is removed.

[0131] Figures 7A to 7D Sequential cross-sectional views of the memory opening 49 during the formation of the memory opening fill structure are provided. The same structural changes occur in each of the memory opening 49 and the support opening 19.

[0132] See Figure 7A which shows Figure 6The memory opening 49 in the first exemplary device structure. The memory opening 49 extends through the first layer structure and the second layer structure.

[0133] Referring Figure 7B , a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L can be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer that consists essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide can consist essentially of at least one metal element and oxygen, or can consist essentially of at least one metal element, oxygen, and at least one non-metal element such as nitrogen. In one embodiment, the blocking dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer can be in the range of 1 nm to 20 nm, but smaller and larger thicknesses can also be used. Subsequently, the dielectric metal oxide layer can be used as a dielectric material portion that blocks the leakage of stored charge to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or in addition, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0134] Subsequently, the charge storage layer 54 can be formed. In one embodiment, the charge storage layer 54 can be a continuous layer or a patterned discrete portion of a charge trapping material that includes a dielectric charge trapping material (e.g., which can be silicon nitride). Alternatively, the charge storage layer 54 can include a continuous layer or a patterned discrete portion of a conductive material (such as doped polysilicon or a metal material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates) by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) can have vertically coincident sidewalls, and the charge storage layer 54 can be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242) can be laterally recessed with respect to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and an anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced-apart memory material portions. The thickness of the charge storage layer 54 can be in the range of 2 nm to 20 nm, but smaller and larger thicknesses can also be used.

[0135] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under appropriate electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, their alloys, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can include a silicon oxide layer substantially free of carbon or a silicon oxynitride layer substantially free of carbon. The thickness of the tunneling dielectric layer 56 can be in the range of 2 nm to 20 nm, but smaller and larger thicknesses can also be used. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes the memory film 50 that stores a memory bit.

[0136] The semiconductor channel material layer 60L comprises a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one group III-V compound semiconductor material, at least one group II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L can have uniform doping. In one embodiment, the semiconductor channel material layer 60L has p-type doping, where the p-type dopant (such as boron atoms) is present at an atomic concentration in the range of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polycrystalline silicon and / or consists essentially of boron-doped amorphous silicon or boron-doped polycrystalline silicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, where the n-type dopant (such as phosphorus atoms or arsenic atoms) is present at an atomic concentration in the range of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3An atomic concentration within a range exists. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2 nm to 10 nm, but smaller and larger thicknesses can also be used. A cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 60L).

[0137] See Figure 7C , in the case where the cavity 49' in each memory opening is not completely filled by the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low-pressure chemical vapor deposition (LPCVD)) or by a self-planarizing deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second insulating capping layer 270 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the second insulating capping layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0138] See Figure 7D , a doped semiconductor material having a second conductivity type can be deposited in the cavity covering the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The deposited doped semiconductor material, the semiconductor channel material layer 60L, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 covering the horizontal plane (which includes the top surface of the second insulating capping layer 270) can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0139] Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. The dopant concentration in the drain region 63 can be in the range of 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 , but smaller and larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0140] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be formed subsequently after forming the backside recess. As used herein, macroscopic retention time refers to the retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0141] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunneling dielectric layer 56, multiple memory elements including portions of the charge storage layer 54, and optionally the blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. During the process, the source level material layer 10', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265), the interlayer dielectric layer 180, and the memory opening fill structure 58 together constitute a memory level component.

[0142] See Figures 8A to 8D , which shows an exemplary structure after forming the memory opening fill structure 58. A support pillar structure 20 is formed in the support opening 19 while forming the memory opening fill structure 58. Each support pillar structure 20 may have the same set of components as the memory opening fill structure 58. In one embodiment, a cluster of memory opening fill structures 58 may extend laterally along a first horizontal direction (e.g., the word line direction) hd1 and may be laterally spaced apart along a second horizontal direction (e.g., the bit line direction) hd2 perpendicular to the first horizontal direction hd1. A group of clusters of memory opening fill structures 58 may be laterally spaced apart along the second horizontal direction hd2. Regions without the memory opening fill structure 58 and the support pillar structure 20 may be provided between a pair of laterally spaced groups of memory opening fill structures 58. In one embodiment, the unit pattern UP may repeat periodically along the second horizontal direction hd2.

[0143] See Figures 9A to 9D, a contact-level dielectric layer 280 can be formed over the second-layer structures (232, 242, 270, 265). The contact-level dielectric layer 280 includes a dielectric material such as silicon oxide and can be formed by a conformal or non-conformal deposition process. For example, the contact-level dielectric layer 280 can include undoped silicate glass and can have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses can also be used.

[0144] A photoresist layer (not shown) can be applied over the contact-level dielectric layer 280 and can be lithographically patterned to form a trench shape in the region of the memory array region 100 where there is no memory opening fill structure 58. Anisotropic etching can be performed to form trench grooves having substantially vertical sidewalls that extend through the contact-level dielectric layer 280, the second-layer structures (232, 242, 270, 265) below the trench-shaped opening in the photoresist layer, and the first-layer structures (132, 142, 170, 165). Each trench groove can vertically extend into the in-process source-level material layer 10' and laterally surround the perimeter of a corresponding opening through the in-process source-level material layer 10'. The photoresist layer can be removed, for example, by ashing. Each set of continuous material portions of the first-layer alternating stack (132, 142) and the second-layer alternating stack (232, 242) surrounded by the trench grooves includes a vertical alternating sequence of a first insulating plate 132', a first dielectric material plate 142', a second insulating plate 232', and a second dielectric material plate 142'. The patterned portion of the first insulating layer 132 surrounded laterally by the trench grooves includes the first insulating plate 132'. The patterned portion of the first sacrificial material layer 142 surrounded laterally by the trench grooves includes the first dielectric material plate 142'. The patterned portion of the first insulating capping layer 170 surrounded laterally by the first-layer trench grooves includes the first insulating capping plate 170'. The patterned portion of the interlayer dielectric layer 180 surrounded laterally by the trench grooves includes the interlayer dielectric plate 180'. The patterned portions of the first insulating layer 132 and the first sacrificial material layer 142 within each first-layer trench groove include a first vertical alternating sequence of the first insulating plate 132' and the first dielectric material plate 142'. The first sacrificial material layer 142, the first dielectric material plate 142' includes a first dielectric material such as silicon nitride.

[0145] The patterned portion of the second insulating layer 232 that is laterally surrounded by the trench includes a second insulating plate 232'. The patterned portion of the second sacrificial material layer 242 that is laterally surrounded by the trench includes a second dielectric material plate 242'. The patterned portion of the second insulating capping layer 270 that is laterally surrounded by the second layer of trenches includes a second insulating capping plate 270'. The patterned portions of the second insulating layer 232 and the second sacrificial material layer 242 within each second layer of trenches include a second vertical alternating sequence of the second insulating plate 232' and the second dielectric material plate 242'. The second sacrificial material layer 242 and the second dielectric material plate 242' include a second dielectric material, such as silicon nitride. Each vertical alternating sequence of the insulating plates (132', 232') and the dielectric material plates (142', 242') is laterally surrounded by an alternating stack of the insulating layers (132, 232) and the sacrificial material layers (142, 242).

[0146] A dielectric material, such as silicon oxide, can be deposited in the trenches by a conformal deposition process, such as low-pressure chemical vapor deposition, or a self-planarizing deposition process, such as spin coating. The excess portion of the deposited dielectric material can be removed from above the top surface of the contact-level dielectric layer 280 by a planarization process. The remaining portion of the dielectric material in the trenches constitutes the dielectric trench structure 176.

[0147] In one embodiment, each dielectric trench structure 176 can have a horizontal cross-sectional shape of a rectangular frame. In this case, the outer sidewalls of each dielectric trench structure 176 can include a pair of longitudinal sidewalls that extend laterally along a first horizontal direction hd1 and a pair of transverse sidewalls that extend laterally along a second horizontal direction hd2. The inner sidewalls of each dielectric trench structure 176 can include a pair of longitudinal sidewalls that extend laterally along the first horizontal direction hd1 and a pair of transverse sidewalls that extend laterally along the second horizontal direction hd2.

[0148] Each of the first insulating plates 132' may be vertically spaced apart from the top surface of the in-process source-level material layer 10' by the same vertical distance as the corresponding first insulating layer 132 in the first alternating stack is from the top surface of the in-process source-level material layer 10'. Each of the first dielectric material plates 142' may be vertically spaced apart from the top surface of the in-process source-level material layer 10' by the same vertical distance as the corresponding first dielectric material layer 142 in the first alternating stack is from the top surface of the in-process source-level material layer 10'. Each of the second insulating plates 232' may be vertically spaced apart from the top surface of the in-process source-level material layer 10' by the same vertical distance as the corresponding second insulating layer 232 in the second alternating stack is from the top surface of the in-process source-level material layer 10'. Each of the second dielectric material plates 242' may be vertically spaced apart from the top surface of the in-process source-level material layer 10' by the same vertical distance as the corresponding second dielectric material layer 242 in the second alternating stack is from the top surface of the in-process source-level material layer 10'.

[0149] See Figures 10A to 10D , a photoresist layer (not shown) may be applied over the contact-level dielectric layer 280 and may be lithographically patterned to form linear openings and discrete openings. The linear openings extend laterally along a first horizontal direction hd1 with a corresponding uniform width and may be periodically repeated along a second horizontal direction hd2 with a width equal to the width of the cell pattern UP along the second horizontal direction hd2. A first subset of the discrete openings in the photoresist layer may be formed over the respective vertical alternating sequences of the insulating plates (132', 232') and the dielectric material plates (142', 242'). A second subset of the discrete openings in the photoresist layer may be formed over the back stepped dielectric material portions (165, 265). Each of the discrete openings in the photoresist layer may be formed entirely within the area of a respective one of the metal pad structures 788.

[0150] An anisotropic etching process may be performed to etch the contact-level dielectric layer 280, the alternating stacks {(132, 142), (232, 242)} and the intermediate material layers (170, 180) therebetween, and the unmasked portions of the higher regions of the in-process source-level material layer 10'. The terminal step of the anisotropic etching process may be selective to the metal material of the metal pad structure 788 and / or to the semiconductor material of the source-level sacrificial layer 104.

[0151] The dorsal trench 79 can be formed under the linear opening in the photoresist layer through the contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), and the first layer structure (132, 142, 170, 165) and into the in-process source-level material layer 10'. The portions of the contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), the first layer structure (132, 142, 170, 165), and the in-process source-level material layer 10' that are under the linear opening in the photoresist layer can be removed to form the dorsal trench 79. In one embodiment, the dorsal trench 79 can be formed between groups of memory opening fill structures 58 that are laterally spaced apart along the second horizontal direction hd2. The top surface of the source-level sacrificial layer 104 can be physically exposed at the bottom of each dorsal trench 79. The dorsal trench 79 is laterally spaced apart from the dielectric trench structure 176.

[0152] The first through-memory-level via cavity 779 can be formed through a respective one of the vertical alternating sequences of insulating plates (132’, 232’) and dielectric material plates (142’, 242’). Each first through-memory-level via cavity 779 can vertically extend through each plate within the respective vertical alternating sequence of insulating plates (132’, 232’) and dielectric material plates (142’, 242’). The top surface of the metal pad structure 788 can be physically exposed at the bottom of each first through-memory-level via cavity 779.

[0153] The second through-memory-level via cavity 579 can be formed through the back-step dielectric material portions (165, 265). Each second through-memory-level via cavity 579 can vertically extend through each of the back-step dielectric material portions (165, 265). The top surface of the metal pad structure 788 can be physically exposed at the bottom of each second through-memory-level via cavity 579.

[0154] Generally speaking, the dorsal trench 79 can be formed simultaneously with the formation of the first through-memory-level via cavity 779 and the second through-memory-level via cavity 579 by performing an anisotropic etching process. The portion of the planar silicon nitride liner 766 that is under the through-memory-level via cavities (779, 579) is removed by the anisotropic etching process. The central portion of the top surface of a respective one of the lower-level metal interconnect structures 760 can be physically exposed through the opening in the planar silicon nitride liner 766 when the through-memory-level via cavities (779, 579) are formed.

[0155] See Figure 11A, an etchant that selectively etches the material of the source-level sacrificial layer 104 with respect to the materials of the first alternating stack (132, 142), the second alternating stack (232, 242), the first and second insulating capping layers (170, 270), the contact-level dielectric layer 280, the higher sacrificial liner 105, and the lower sacrificial liner 103 can be introduced into the backside trench in an isotropic etching process. For example, if the source-level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon germanium alloy, and if the higher and lower sacrificial liners (105, 103) comprise silicon oxide, a wet etching process (which uses hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH)) can be used to selectively remove the source-level sacrificial layer 104 with respect to the higher and lower sacrificial liners (105, 103). A source cavity 109 can be formed in the volume from which the source-level sacrificial layer 104 is removed.

[0156] Wet etching chemistries such as hot TMY and TMAH are selective for the doped semiconductor materials of the higher source-level semiconductor layer 116 and the lower source-level semiconductor layer 112. Thus, using selective wet etching chemistries such as hot TMY and TMAH in the wet etching process for forming the source cavity 109 provides a larger process window against etching depth variations during the formation of the backside trench 79. Specifically, when forming the source cavity 109, in embodiments where the sidewalls of the higher source-level semiconductor layer 116 are physically exposed or in embodiments where the surface of the lower source-level semiconductor layer 112 is physically exposed, the collateral etching of the higher source-level semiconductor layer 116 and / or the lower source-level semiconductor layer 112 is minimal, and structural variations of exemplary structures caused by accidental physical exposure of the surface of the higher source-level semiconductor layer 116 and / or the lower source-level semiconductor layer 112 during the manufacturing steps do not result in device failure. Each of the memory opening fill structures 58 can be physically exposed to the source cavity 109. Specifically, each of the memory opening fill structures 58 can include sidewalls and bottom surfaces that are physically exposed to the source cavity 109.

[0157] Reference Figure 11B, a sequence of isotropic etchants (such as wet etchants) can be applied to the physically exposed portion of the memory film 50 to etch various component layers of the memory film 50 in an external-to-internal order, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper and lower sacrificial pads (105, 103) can be incidentally etched during the removal of the portion of the memory film 50 located at the level of the source cavity 109. The volume of the source cavity 109 can be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower sacrificial pads (105, 103). The top surface of the lower source-level semiconductor layer 112 and the bottom surface of the upper source-level semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 can be formed by selectively isotropically etching the source-level sacrificial layer 104 and the bottom portion of each memory film 50 for at least one source-level semiconductor layer (such as the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116) and the vertical semiconductor channel 60.

[0158] Reference Figure 11C , a doped semiconductor material doped with a second conductivity type can be deposited on the physically exposed semiconductor surface around the source cavity 109. The second conductivity type is opposite to the first conductivity type, which is the doped conductivity type of the vertical semiconductor channel 60. The physically exposed semiconductor surface includes the bottom portion of the outer sidewall of the vertical semiconductor channel 60 and the horizontal surfaces of at least one source-level semiconductor layer (112, 116). For example, the physically exposed semiconductor surface can include the bottom portion of the outer sidewall of the vertical semiconductor channel 60, the top horizontal surface of the lower source-level semiconductor layer 112, and the bottom surface of the upper source-level semiconductor layer 116.

[0159] In one embodiment, a doped semiconductor material of the second conductivity type can be deposited on the physically exposed semiconductor surface around the source cavity 109 by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and an n-type dopant precursor gas can flow into the processing chamber including the exemplary structure simultaneously. For example, the semiconductor precursor gas can include silane, disilane, or dichlorosilane, the etchant gas can include gaseous hydrogen chloride, and the n-type dopant precursor gas such as phosphine, arsine, or stibine. In this case, the selective semiconductor deposition process grows an in-situ doped semiconductor material from the physically exposed semiconductor surface around the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114, which can contact the sidewall of the vertical semiconductor channel 60. The atomic concentration of the dopants of the second conductivity type in the deposited semiconductor material can be at 1.0×10 20 / cm 3to 2.0×10 21 / cm 3 within the range of, such as 2.0×10 20 / cm 3 to 8.0×10 20 / cm 3 The initially formed source contact layer 114 may consist essentially of semiconductor atoms and dopant atoms of a second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch-back processes may be used in combination with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0160] The duration of the selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 may be formed by selectively depositing a doped semiconductor material from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Thus, the source level sacrificial layer 104 may be replaced by the source contact layer 114.

[0161] A layer stack including a lower source level semiconductor layer 112, a source contact layer 114, and a higher source level semiconductor layer 116 constitutes a source layer (112, 114, 116). The source layer (112, 114, 116) is electrically connected to the first end (such as the bottom end) of each of the vertical semiconductor channels 60. A set of layers including the source layer (112, 114, 116), the source level insulating layer 117, and the source select level conductive layer 118 constitutes a source level material layer 10, which replaces the source level material layer 10' during the replacement process. Generally speaking, the source level material layer 10 includes a source contact layer 114, which includes a doped semiconductor material and contacts each of the vertical semiconductor channels 60.

[0162] See Figures 12A to 12C, the silicon nitride liner can be deposited by a conformal deposition process, such as a chemical vapor deposition process. The silicon nitride liner is referred to herein as the conformal silicon nitride liner 771 or the first conformal silicon nitride liner. The conformal silicon nitride liner 771 can be formed by conformally depositing silicon nitride directly on the sidewalls of each through-memory-level via cavity (779, 579) and each backside trench 79. In one embodiment, the conformal silicon nitride liner 771 contacts each plate within each vertical alternating sequence of insulating plates (132’, 232’) and dielectric material plates (142’, 242’). The conformal silicon nitride liner 771 can consist essentially of silicon nitride and can have a thickness greater than 2 nm, such as a thickness in the range of 4 nm to 40 nm (such as 6 nm to 20 nm), but smaller and larger thicknesses can also be employed. The conformal silicon nitride liner 771 can be a conformal layer that extends continuously across the entire lateral extent of the exemplary structure.

[0163] See Figures 13A to 13C , an oxidation process can be performed to convert at least the surface portion of the conformal silicon nitride liner 771 into a silicon oxide liner, which is referred to herein as the conformal silicon oxide liner 772 or the first conformal silicon oxide liner. The oxidation process can be a thermal oxidation process or a plasma oxidation process. In the case of performing a thermal oxidation process, a wet oxidation process, a dry oxidation process, or a radical oxidation process (such as an in-situ steam generation oxidation process) can be employed. If a planar silicon nitride liner 766 is present, the oxidation process can optionally be performed for a sufficient time to convert the entire conformal silicon nitride liner 771 into the conformal silicon oxide liner 772. If the planar silicon nitride liner 766 is omitted, then the oxidation process is terminated after only converting the surface portion of the conformal silicon nitride liner 771 into the conformal silicon oxide liner 772, but at least a portion of the conformal silicon nitride liner 771 remains below the conformal silicon oxide liner 772. For example, at least 2 nm thick, such as 3 nm to 10 nm thick, portion of the conformal silicon nitride liner 771 remains below the conformal silicon oxide liner 772. The planar silicon nitride liner 766 and / or the bottom portion of the conformal silicon nitride liner 771 below the through-memory-level via cavity (779 579) can prevent or reduce the oxidation of the metal pad structure 788 during the formation of the conformal silicon oxide liner 772.

[0164] In one embodiment, a conformal silicon oxide liner 772 can be formed by oxidizing a surface portion of the conformal silicon nitride liner 771 without oxidizing portions of the sidewalls of the conformal silicon nitride liner 771 adjacent to the through-memory-level via cavities (779, 579) or adjacent to the sidewalls of the backside trench 79. For example, the duration of the oxidation process can be selected such that a portion of the conformal silicon nitride liner 771 is not oxidized by the oxidation process. In one embodiment, the thickness of the remaining portion of the conformal silicon nitride liner 771 after the oxidation process can be in the range of 10% to 90% of the initial thickness of the deposited conformal silicon nitride liner 771, such as 20% to 80%. The conformal silicon oxide liner 772 can contact the conformal silicon nitride liner 771. In one embodiment, residual nitrogen atoms can be present within the interfacial portion of the conformal silicon oxide liner 772 that is close to the conformal silicon nitride liner 771. In such a case, the interfacial portion of the conformal silicon oxide liner 772 can include a nitrogen-doped surface region having a variable atomic concentration of nitrogen atoms that decreases with distance from the conformal silicon nitride liner 771.

[0165] See Figures 14A to 14D , a photoresist layer 69 can be applied over the exemplary structure and can be lithographically patterned to cover the through-memory-level via cavities (779, 579) without covering the backside trench 79. A series of isotropic etching processes can be employed to isotropically etch the unmasked portions of the conformal silicon oxide liner 772 and the conformal silicon nitride liner 771. For example, a first wet etching process using hydrofluoric acid can be performed to etch the unmasked portion of the conformal silicon oxide liner 772, and a second wet etching process using a combination of hot phosphoric acid can be employed to etch the unmasked portion of the conformal silicon nitride liner 771. Subsequently, the photoresist layer 69 can be removed, for example, by ashing.

[0166] See Figures 15A to 15D, an oxidation process can be performed to convert physically exposed surface portions of a semiconductor material into dielectric semiconductor oxide portions. For example, surface portions of the source contact layer 114 and the higher source level semiconductor layer 116 can be converted into dielectric semiconductor oxide plates 122, and surface portions of the source select level conductive layer 118 can be converted into annular dielectric semiconductor oxide spacers 124. The bottom portions of the planar silicon nitride liner 766 and / or conformal silicon nitride liner 771 below the through memory level via cavity (779 579) can prevent or reduce the oxidation of the metal pad structure 788 during the formation of the conformal silicon oxide liner 772, dielectric semiconductor oxide plates 122, and annular dielectric semiconductor oxide spacers 124. For example, if the metal pad structure 788 includes a titanium nitride metal nitride liner 788L, then the oxidation of titanium nitride during the oxidation step forms titanium oxide with a higher resistivity. The planar silicon nitride liner 766 covers the exposed top portion of the titanium nitride metal nitride liner 788L, while the bottom portion of the conformal silicon nitride liner 771 prevents the titanium nitride metal nitride liner 788L from being exposed in the through memory level via cavity 779, and thus reduces or prevents the formation of titanium oxide with a higher resistivity in the metal pad structure 788 during one or more oxidation steps.

[0167] See Figures 16A to 16D , the sacrificial material layers (142, 242) can be selectively removed with respect to the insulating layers (132, 232), the first and second insulating capping layers (170, 270), the contact level dielectric layer 280, and the source contact layer 114, dielectric semiconductor oxide plates 122, and annular dielectric semiconductor oxide spacers 124. For example, an isotropic etching process can be used to introduce an isotropic etchant that selectively etches the material of the sacrificial material layers (142, 242) with respect to the materials of the insulating layers (132, 232), the first and second insulating capping layers (170, 270), the back stepped dielectric material portions (165, 265), and the outermost layer of the memory film 50 into the backside trench 79.

[0168] The isotropic etching process can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in a gaseous phase. For example, if the sacrificial material layers (142, 242) comprise silicon nitride, the etching process can be a wet etching process in which an exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials used in the art. The duration of the isotropic etching process can be selected such that the entire sacrificial material layer (142, 242) is removed by the isotropic etching process.

[0169] A dorsal recess (143, 243) can be formed in the volume from which the sacrificial material layer (142, 242) is removed. The dorsal recess (143, 243) includes a first dorsal recess 143 that can be formed in the volume from which the first sacrificial material layer 142 is removed and a second dorsal recess 243 that can be formed in the volume from which the second sacrificial material layer 242 is removed. Each dorsal recess in the dorsal recess (143, 243) can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each dorsal recess in the dorsal recess (143, 243) can be greater than the height of the corresponding dorsal recess (143, 243). A plurality of dorsal recesses (143, 243) can be formed in the volume of the material from which the sacrificial material layer (142, 242) is removed. Each of the dorsal recesses (143, 243) can extend substantially parallel to the top surface of the substrate semiconductor layer 9. The dorsal recess (143, 243) can be vertically defined by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each dorsal recess in the dorsal recess (143, 243) can have a uniform height throughout.

[0170] The first lateral recess 143 can be laterally defined by the outer sidewalls of the corresponding dielectric trench structure 176. Thus, the outer sidewalls of the dielectric trench structure 176 are physically exposed to the first lateral recess 143. The second lateral recess 243 can be laterally defined by the outer sidewalls of the corresponding dielectric trench structure 176. Thus, the outer sidewalls of the dielectric trench structure 176 are physically exposed to the second lateral recess 243.

[0171] See Figures 17A to 17C , A dorsal blocking dielectric layer (not shown) can optionally be deposited in the dorsal recesses (143, 243) and the dorsal trench 79 and above the first contact level dielectric layer 280. The dorsal blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the dorsal blocking dielectric layer can comprise aluminum oxide. The dorsal blocking dielectric layer can be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the dorsal blocking dielectric layer can be in the range of 1 nm to 20 nm, such as 2 nm to 10 nm, but smaller and larger thicknesses can also be used.

[0172] At least one conductive material can be deposited in the plurality of dorsal recesses (243, 243), on the sidewalls of the dorsal trench 79, and above the contact-level dielectric layer 280. The at least one conductive material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material can include elemental metals, intermetallic alloys of at least two elemental metals, conductive nitrides of at least one elemental metal, conductive metal oxides, conductive doped semiconductor materials, conductive metal-semiconductor alloys such as metal silicides, their alloys, and combinations or stacks thereof.

[0173] In one embodiment, the at least one conductive material can include at least one metal material, i.e., a conductive material containing at least one metal element. Non-limiting exemplary metal materials that can be deposited in the dorsal recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material can include a conductive metal nitride liner that includes a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive fill material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material for filling the dorsal recesses (143, 243) can be a combination of a titanium nitride layer and a tungsten fill material.

[0174] A conductive layer (146, 246) can be formed in the dorsal recesses (143, 243) by depositing at least one conductive material. A plurality of first conductive layers 146 can be formed in the plurality of first dorsal recesses 143, a plurality of second conductive layers 246 can be formed in the plurality of second dorsal recesses 243, and a continuous metal material layer (not shown) can be formed on the sidewalls of each dorsal trench 79 and above the contact-level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 can include a respective conductive metal nitride liner and a respective conductive fill material. Thus, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced with the first conductive layer and the second conductive layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with an optional portion of the dorsal barrier dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced with an optional portion of the dorsal barrier dielectric layer and the second conductive layer 246. A dorsal cavity exists within the portion of each dorsal trench 79 that is not filled with the continuous metal material layer.

[0175] Residual conductive material can be removed from within the dorsal trenches 79. Specifically, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each dorsal trench 79 and from above the contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first dorsal recess forms the first conductive layer 146. Each remaining portion of the deposited metal material in the second dorsal recess forms the second conductive layer 246. The sidewalls of the first conductive layer 146 and the second conductive layer can be physically exposed to the respective dorsal trenches 79.

[0176] Generally speaking, the remaining portions of the first sacrificial material layer 142 that are located outside the dielectric trench structure 176 are replaced by the first conductive layer 146, and the remaining portions of the second sacrificial material layer 242 that are outside the dielectric trench structure 176 are replaced by the second conductive layer 246. Each conductive layer (146, 246) can be a conductive sheet that includes openings. A first subset of the openings through each conductive layer (146, 246) can be filled with a memory opening fill structure 58. A second subset of the openings through each conductive layer (146, 246) can be filled with a support pillar structure 20. Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) can include word lines for the memory elements. The semiconductor devices in the underlying peripheral device region 700 can include word line switching devices that are configured to control the bias voltage to the respective word lines. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory level assembly includes an alternating stack {(132, 146), (232, 246)} and the memory stack structures 55 that vertically extend through the alternating stack (132, 146, 232, 246).

[0177] A three-dimensional array of memory elements can be formed above the lower level dielectric material layer 760. The three-dimensional array of memory elements includes: an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) that covers a semiconductor material layer within the source level material layer 10; memory stack structures 55 that vertically extend through the alternating stack and include respective vertical semiconductor channels 60 and respective memory membranes 50; and a vertical alternating sequence of insulating plates (132’, 232’) and dielectric material plates (142’, 242’) that is laterally surrounded by the alternating stack {(132, 146), (232, 246)}.

[0178] See Figures 18A to 18C, A dielectric material such as silicon oxide can be conformally deposited in the backside trenches 79 and the through-memory-level via cavities (779, 579), and can be anisotropically etched. The remaining patterned vertical extensions of the dielectric material in the backside trenches 79 include the backside insulating spacers 74. The remaining patterned vertical extensions of the dielectric material in the first through-memory-level via cavity 779 include the first insulating spacers 774. The remaining patterned vertical extensions of the dielectric material in the second through-memory-level via cavity 579 include the second insulating spacers 574. The lateral thicknesses of the backside insulating spacers 74, the first insulating spacers 774, and the second insulating spacers 574 can have a thickness in the range of 6 nm to 100 nm (such as 12 nm to 50 nm), but smaller and larger thicknesses can also be employed.

[0179] See Figures 19A to 19D , A photoresist layer (not shown) can be applied to the exemplary structure and can be lithographically patterned to form openings in the regions covering the memory opening fill structure 58 and in the regions covering the stepped surfaces of the alternating stack {(132, 146), (232, 246)}. A drain contact via cavity is formed above the drain region 63 of the memory opening fill structure 58. A layer contact via cavity is formed above the stepped surface of the alternating stack {(132, 146), (232, 246)}.

[0180] At least one metal material (such as a combination of a metal nitride liner (e.g., TiN, TaN, or WN) and a metal fill material (e.g., W, Cu, Mo, Ru, Co, etc.)) can be deposited in the unfilled volumes of the backside trenches 79, the through-memory-level via cavities (779, 579), the drain contact via cavities, and the layer contact via cavities. The excess portions of at least one metal material can be removed from above the horizontal plane including the contact-level dielectric layer 280 by a planarization process. The horizontal extensions of the conformal silicon oxide liner 772 and the conformal silicon nitride liner 771 (if present) can be removed from above the horizontal plane including the contact-level dielectric layer 280 by a planarization process. This embodiment can reduce or prevent the oxidation of conductive layers such as tungsten and / or TiN.

[0181] A backside contact via structure 76 can be formed in each backside trench 79. A first through-memory-level interconnect via structure 776 can be formed in each first through-memory-level via cavity 779. A second through-memory-level interconnect via structure 576 can be formed in each second through-memory-level via cavity 579. A drain contact via structure 88 can be formed on the top surface of a corresponding one in the drain region 63. A layer contact via structure 86 can be formed on the top surface of a corresponding one in the conductive layers (146, 246).

[0182] In one embodiment, each first direct memory level through - via structure 776 contacts a central portion of the top surface of a respective one of the lower - level metal interconnect structures 680 (such as the metal pad structure 788). At least one silicon nitride liner (766, 771) contacts a peripheral portion of the top surface of a respective one of the lower - level metal interconnect structures 680 and contacts a cylindrical bottom - end portion of the sidewall of the first direct memory level through - via structure 776. Each first direct memory level through - via structure 776 extends vertically through each plate within the respective vertical alternating sequence of insulating plates (132’, 232’) and dielectric material plates (142’, 242’), and contacts a central portion of the top surface of a respective one of the lower - level metal interconnect structures 680. The planar silicon nitride liner 771 extends laterally over the plurality of lower - level metal interconnect structures 780 and contacts their top surfaces.

[0183] Each conformal silicon nitride liner 771 formed within the first direct memory level via cavity 779 is referred to herein as a first conformal silicon nitride liner, and each conformal silicon nitride liner 771 formed within the second direct memory level via cavity 579 is referred to herein as a second conformal silicon nitride liner. Each conformal silicon oxide liner 772 formed within the first direct memory level via cavity 779 is referred to herein as a first conformal silicon oxide liner, and each conformal silicon oxide liner 772 formed within the second direct memory level via cavity 579 is referred to herein as a second conformal silicon oxide liner. Each of the conformal silicon nitride liner 771 and the conformal silicon oxide liner 772 may have a top surface in a horizontal plane that includes the direct memory level through - via structures (776, 576) and the back - side contact via structure 76.

[0184] In one embodiment, each back - side contact via structure 76 extends vertically through the alternating stack of insulating layers {(132, 146), (232, 246)}, contacts one of the source - level material layers 10, and includes the same material as the direct memory level through - via structures (776, 576). The back - side insulating spacer 74 laterally surrounds each back - side contact via structure 76 and contacts each layer within the alternating stack {(132, 146), (232, 246)}.

[0185] Subsequently, a line - level dielectric material layer 290 and higher - level metal interconnect structures (98, 96) may be formed. The higher - level metal interconnect structures (98, 96) may include bit lines 98 and connecting metal lines (e.g., word - line interconnects) 96. Additional higher - level dielectric material layers (not shown) and additional higher - level metal interconnect structures (not shown) may be formed as needed.

[0186] SeeFigure 20A and Figure 20B , by omitting the formation of the planar silicon nitride liner 766, a first alternative configuration of the exemplary structure can be derived from the exemplary structure of Figures 19A to 19D . In this case, the first conformal silicon nitride liner and the second conformal silicon nitride liner 771 act as oxidation barriers during the oxidation process and prevent or reduce the oxidation of the underlying lower-level metal interconnect structure 780 (such as the metal pad structure 788).

[0187] See Figure 21A and Figure 21B , by patterning the continuous planar silicon nitride liner 766 into a plurality of discrete planar silicon nitride liners 766 that are not interconnected with each other, a second alternative configuration of the exemplary structure can be derived from the exemplary structure of Figures 19A to 19D . In one embodiment, each planar silicon nitride liner does not contact any other lower-level metal interconnect structures in the lower-level metal interconnect structure. The planar silicon nitride liner 766 and the first and second conformal silicon nitride liners 771 act as oxidation barriers during the oxidation process. The planar silicon nitride liner 766 preferably has a thickness greater than 2 nm, such as a thickness in the range of 4 nm to 40 nm (such as 6 nm to 20 nm). Preferably, the planar silicon nitride liner 766 extends at least 300 nm from the edge of the through-memory-level via cavity (779, 579), such as 400 nm to 1 micron.

[0188] See Figures 22A to 22D , by omitting the formation of the conformal silicon nitride liner 771 at the processing step of Figures 12A to 12C , and by forming a conformal silicon oxide liner 772 by oxidizing the entire thickness of the silicon nitride liner 771 at the processing step of Figures 13A to 13C , a third alternative configuration of the exemplary structure can be derived from the exemplary structure of Figures 19A to 19D . Each patterned portion of the conformal silicon oxide liner 772 includes a first conformal silicon oxide liner after the planarization process at the processing step of Figures 19A to 19D in the first through-memory-level via cavity, and each patterned portion of the conformal silicon oxide liner 772 includes a second conformal silicon oxide liner after the planarization process at the processing step of Figures 19A to 19D in the second through-memory-level via cavity. In this case, each first conformal silicon oxide liner 772 can contact each plate within the corresponding vertical alternating sequence of the insulating plates (132’, 232’) and the dielectric material plates (142’, 242’), and laterally surround the first through-memory-level interconnect via structure 776.

[0189] See Figure 23A and Figure 23B, by patterning the planar silicon nitride liner 766 into a plurality of discrete planar silicon nitride liners 766, a fourth alternative configuration of the exemplary structure can be derived from a third alternative configuration of the exemplary structures of Figure 22A and Figure 22B . Each silicon nitride liner 766 can contact the entire perimeter of the top surface of a corresponding lower-level metal interconnect structure 780 (such as a metal pad structure 788).

[0190] In one embodiment, each planar silicon nitride liner 766 can be entirely below a horizontal plane including the bottom surface of the source-level material layer 10. Each planar silicon nitride liner 766 can contact the entire perimeter of the top surface of at least one of the lower-level metal interconnect structures 780.

[0191] Referring to all the figures and in accordance with various embodiments of the present disclosure, a semiconductor structure is provided that includes: a semiconductor device 710 on the top surface of a substrate semiconductor layer 9; a lower-level metal interconnect structure 780 embedded in a lower-level dielectric material layer 760 and electrically connected to the semiconductor device 710 and covering the substrate semiconductor layer 9; a source-level material layer 10 covering the lower-level dielectric material layer 760 and including an opening therethrough; an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) covering the source-level material layer 10; a memory stack structure 55 extending vertically through the alternating stack {(132, 146), (232, 246)}, and including corresponding vertical semiconductor channels 60 and corresponding memory films 50; a vertical alternating sequence of insulating plates (132’, 232’) and dielectric material plates (142’, 242’) laterally surrounded by the alternating stack {(132, 146), (232, 246)}; a first through-memory-level interconnect via structure 776 extending vertically through each plate within the vertical alternating sequence {(132’, 142’), (232’, 242’)} and contacting a central portion of the top surface of one of the lower-level metal interconnect structures 780; and at least one silicon nitride liner (766, 771) contacting a peripheral portion of the top surface of one of the lower-level metal interconnect structures 680 and contacting a cylindrical bottom end portion of the sidewall of the first through-memory-level interconnect via structure 776.

[0192] In one embodiment, at least one silicon nitride liner (766, 771) includes a first conformal silicon nitride liner 771 that contacts each plate within the vertically alternating sequence {(132’, 142’), (232’, 242’)}. In one embodiment, the semiconductor structure includes a first conformal silicon oxide liner 772 that contacts the inner cylindrical sidewall of the conformal silicon nitride liner 771 and laterally surrounds the first through-memory-level interconnect via structure 776. In one embodiment, the interfacial portion of the first conformal silicon oxide liner 772 includes a nitrogen-doped surface region having a variable atomic concentration of nitrogen atoms that decreases with distance from the first conformal silicon nitride liner 771.

[0193] In one embodiment, the semiconductor structure includes a first insulating spacer 774 that contacts and laterally surrounds the first through-memory-level interconnect via structure 776 and is laterally surrounded by the first conformal silicon oxide liner 772. In one embodiment, the first conformal silicon nitride liner 771 has a top surface in a horizontal plane that includes the top surface of the first through-memory-level interconnect via structure 776, and the at least one silicon nitride liner 771 has a thickness greater than 2 nm.

[0194] In one embodiment, the semiconductor structure includes: a backside contact via structure 76 that vertically extends through the alternating stack {(132, 146), (232, 246)}, contacts one of the source-level material layers 10, and includes the same material as the first through-memory-level interconnect via structure 776; and a backside insulating spacer 74 that laterally surrounds the backside contact via structure 76 and contacts each layer within the alternating stack {(132, 146), (232, 246)}. In one embodiment, the source-level material layer 10 includes a source contact layer 114 that includes a doped semiconductor material and contacts each of the vertical semiconductor channels 60.

[0195] In one embodiment, at least one silicon nitride liner (771, 766) includes a planar silicon nitride liner 766 that is entirely below the horizontal plane that includes the bottom surface of the source-level material layer 10.

[0196] In one embodiment, the planar silicon nitride liner 766 contacts the entire perimeter of the top surface of one of the lower-level metal interconnect structures 780. In one embodiment, the planar silicon nitride liner 766 laterally extends over and contacts the top surface of at least another one of the lower-level metal interconnect structures 780.

[0197] In one embodiment, the planar silicon nitride liner 766 does not contact any other lower-level metal interconnect structure in the lower-level metal interconnect structure 780. In one embodiment, the semiconductor structure further includes a conformal silicon nitride liner 771 that contacts each plate within the vertically alternating sequence; and a first conformal silicon oxide liner 772 that contacts each plate within the vertically alternating sequence {(132’,142’), (232’,242’)} and laterally surrounds the conformal silicon nitride liner 771 and contacts the first direct memory level interconnect via structure 776.

[0198] In one embodiment, the semiconductor structure includes: at least one backward stepped dielectric material portion (165, 265) that contacts the stepped surface of the alternating stack {(132, 146), (232, 246)}; and a second direct memory level interconnect via structure 576 that vertically extends through the at least one backward stepped dielectric material portion (165, 265) and contacts a central portion of the top surface of another one of the lower-level metal interconnect structures 780; wherein a portion of the at least one silicon nitride liner (766, 771) contacts a peripheral portion of the top surface of another one of the lower-level metal interconnect structures 780 and contacts a cylindrical bottom end portion of the sidewall of the second direct memory level interconnect via structure 576. In one embodiment, the at least one silicon nitride liner includes a plurality of silicon nitride liners (766, 771).

[0199] Various embodiments of the present disclosure can be used to prevent oxidation of a subset of the lower-level metal interconnect structures 780, such as the metal pad structure 788, during the formation of the dielectric semiconductor oxide plate 122, the annular dielectric semiconductor oxide spacer 124, and the conformal silicon oxide spacer 772. Specifically, the flow of oxygen atoms to the metal nitride liner 788L of each metal pad structure 788 can be blocked by the at least one silicon nitride liner (766, 771), and the degradation of the contact resistance between the metal pad structure 788 and the various direct memory level interconnect via structures (776, 576) can be reduced.

[0200] Although specific embodiments have been mentioned previously, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will envision that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise explicitly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". In embodiments where specific structures and / or configurations are shown to be used in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A semiconductor structure, comprising: a semiconductor device located on a top surface of a substrate semiconductor layer; a lower-level metal interconnect structure embedded in a lower-level dielectric material layer and electrically connected to the semiconductor device and covering the substrate semiconductor layer; a source-level material layer covering the lower-level dielectric material layer and including an opening therethrough; an alternating stack of an insulating layer and a conductive layer covering the source-level material layer; a memory stack structure vertically extending through the alternating stack and including respective vertical semiconductor channels and respective memory films; a vertical alternating sequence of an insulating plate and a dielectric material plate laterally surrounded by the alternating stack; a first through-memory-level interconnect via structure vertically extending through each plate within the vertical alternating sequence and contacting a central portion of a top surface of one of the lower-level metal interconnect structures; at least one silicon nitride liner contacting a peripheral portion of the top surface of the one of the lower-level metal interconnect structures and contacting a cylindrical bottom end portion of a sidewall of the first through-memory-level interconnect via structure, wherein the at least one silicon nitride liner includes a first conformal silicon nitride liner contacting each plate within the vertical alternating sequence; and a first conformal silicon oxide liner contacting an inner cylindrical sidewall of the conformal silicon nitride liner and laterally surrounding the first through-memory-level interconnect via structure.

2. The semiconductor structure according to claim 1, wherein an interface portion of the first conformal silicon oxide liner includes a nitrogen-doped surface region having a variable atomic concentration of nitrogen atoms decreasing with distance from the first conformal silicon nitride liner.

3. The semiconductor structure according to claim 1, further comprising a first insulating spacer contacting and laterally surrounding the first through-memory-level interconnect via structure and laterally surrounded by the first conformal silicon oxide liner.

4. A semiconductor structure, comprising: a semiconductor device located on a top surface of a substrate semiconductor layer; a lower-level metal interconnect structure embedded in a lower-level dielectric material layer and electrically connected to the semiconductor device and covering the substrate semiconductor layer; a source-level material layer covering the lower-level dielectric material layer and including an opening therethrough; an alternating stack of an insulating layer and a conductive layer covering the source-level material layer; a memory stack structure vertically extending through the alternating stack and including respective vertical semiconductor channels and respective memory films; a vertical alternating sequence of an insulating plate and a dielectric material plate laterally surrounded by the alternating stack; A first direct memory level through - via structure that vertically extends through each plate within the vertical alternating sequence and contacts a central portion of the top surface of one of the lower - level metal interconnect structures; and at least one silicon nitride liner that contacts a peripheral portion of the top surface of the one of the lower - level metal interconnect structures and contacts a cylindrical bottom end portion of the sidewall of the first direct memory level through - via structure, wherein the at least one silicon nitride liner includes a planar silicon nitride liner that is entirely located below a horizontal plane including the bottom surface of the source - level material layer, wherein the planar silicon nitride liner contacts the entire periphery of the top surface of the one of the lower - level metal interconnect structures, and wherein the planar silicon nitride liner laterally extends at least 300 nm from the edge of the first direct memory level through - hole structure.

5. The semiconductor structure according to claim 4, wherein the at least one silicon nitride liner has a thickness in the range of 4 nm to 40 nm.

6. A semiconductor structure, comprising: a semiconductor device located on a top surface of a substrate semiconductor layer; a lower - level metal interconnect structure embedded in a lower - level dielectric material layer, electrically connected to the semiconductor device, and covering the substrate semiconductor layer; a source - level material layer covering the lower - level dielectric material layer and including an opening therethrough; an alternating stack of an insulating layer and a conductive layer covering the source - level material layer; a memory stack structure vertically extending through the alternating stack and including corresponding vertical semiconductor channels and corresponding memory membranes; a vertical alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack; a first direct memory level through - via structure that vertically extends through each plate within the vertical alternating sequence and contacts a central portion of the top surface of one of the lower - level metal interconnect structures; at least one silicon nitride liner that contacts a peripheral portion of the top surface of the one of the lower - level metal interconnect structures and contacts a cylindrical bottom end portion of the sidewall of the first direct memory level through - via structure, wherein the at least one silicon nitride liner includes a planar silicon nitride liner that is entirely located below a horizontal plane including the bottom surface of the source - level material layer; a conformal silicon nitride liner that contacts each plate within the vertical alternating sequence; and a first conformal silicon oxide liner that contacts each plate within the vertical alternating sequence and laterally surrounds the conformal silicon nitride liner and the first direct memory level through - via structure.

7. A method of forming a semiconductor structure, comprising: forming a semiconductor device on a top surface of a substrate semiconductor layer; Form a lower-level metal interconnect structure that is embedded in a lower-level dielectric material layer and electrically connected to the semiconductor device above the substrate semiconductor layer; Form a three-dimensional array of memory elements above the lower-level dielectric material layer, wherein the three-dimensional array of memory elements includes: an alternating stack of insulating layers and conductive layers that covers a source-level material layer; a memory stack structure that extends vertically through the alternating stack and includes corresponding vertical semiconductor channels and corresponding memory membranes; and a vertical alternating sequence of insulating plates and dielectric material plates that is laterally surrounded by the alternating stack; Form a first through-memory-level via cavity through each plate within the vertical alternating sequence; and Form a first through-memory-level interconnect via structure within the first through-memory-level via cavity; Wherein: The first through-memory-level interconnect via structure contacts a central portion of the top surface of one of the lower-level metal interconnect structures; At least one silicon nitride liner contacts a peripheral portion of the top surface of the one of the lower-level metal interconnect structures and contacts a cylindrical bottom end portion of the sidewall of the first through-memory-level interconnect via structure; and The at least one silicon nitride liner includes a first conformal silicon nitride liner that is formed by conformally depositing silicon nitride directly on the sidewalls of the first through-memory-level via cavity, and Wherein the method further includes forming a first conformal silicon oxide liner by oxidizing a surface portion of the first conformal silicon nitride liner without oxidizing a portion of the first conformal silicon nitride liner adjacent to the sidewalls of the first through-memory-level via cavity.

8. A method of forming a semiconductor structure, comprising: Form a semiconductor device on a top surface of a substrate semiconductor layer; Form a lower-level metal interconnect structure that is embedded in a lower-level dielectric material layer and electrically connected to the semiconductor device above the substrate semiconductor layer; Form a three-dimensional array of memory elements above the lower-level dielectric material layer, wherein the three-dimensional array of memory elements includes: an alternating stack of insulating layers and conductive layers that covers a source-level material layer; a memory stack structure that extends vertically through the alternating stack and includes corresponding vertical semiconductor channels and corresponding memory membranes; and a vertical alternating sequence of insulating plates and dielectric material plates that is laterally surrounded by the alternating stack; Form a first through-memory-level via cavity through each plate within the vertical alternating sequence; and Form a first through-memory-level interconnect via structure within the first through-memory-level via cavity; Wherein: The first through-memory-level interconnect via structure contacts a central portion of the top surface of one of the lower-level metal interconnect structures; At least one silicon nitride liner contacts a peripheral portion of the top surface of one of the lower level metal interconnect structures and contacts a cylindrical bottom end portion of a sidewall of the first direct memory level through via structure; and the at least one silicon nitride liner includes a first conformal silicon nitride liner formed by conformally depositing silicon nitride directly on a sidewall of the first direct memory level via cavity, and wherein the method further includes: forming a backside trench simultaneously with the formation of the first direct memory level via cavity by performing an anisotropic etching process, wherein the first conformal silicon nitride liner is formed on a sidewall of the backside trench; and removing a portion of the first conformal silicon nitride liner from inside the backside trench.

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