Composite waveguide structure and preparation method thereof

Abstract

The present application provides a composite waveguide structure and a preparation method thereof, belonging to the technical field of electro-optical modulators, comprising a first waveguide wafer, including a substrate, a SiO2 film, a first metal electrode, a first waveguide structure, a second metal electrode and a groove; the second metal electrode is connected to the first metal electrode through a metal interconnection through-hole, the second metal electrode is also connected to a thermal adjustment structure, a pad hole is provided above the second metal electrode, and the bottom of the groove is located above the first waveguide structure in the area to be bonded; the electro-optical film comprises a SiO2 film, a waveguide boss and a second waveguide structure, the waveguide boss and the second waveguide structure are located in the groove, the second waveguide structure is bonded to the bottom of the groove, a bonding reserved hole is provided on the SiO2 film, the position of which corresponds to the position of the pad hole, and the material of the second waveguide structure is an electro-optical material. The present application scheme improves the process structure compatibility between the bonding area and the non-bonding area, and the CMOS process compatibility of W2W in heterogeneous integration applications.

Description

Technical Field

[0001] The present application relates to the technical field of electro-optic modulators, and in particular to a composite waveguide structure and a preparation method thereof. Background Art

[0002] Optical communications, radio frequency photonic systems, millimeter wave measuring instruments and other devices using optical devices have increasingly higher bandwidth requirements. In semiconductor photonic modulators, the limitation of electron carrier transmission time fundamentally affects the high-frequency operating characteristics of diode-based electro-optical modulators (EOMs), which has aroused great interest in the research of materials with high-frequency electro-optical modulation properties. Lithium niobate (LN) has attracted widespread attention in integrated optics due to its superior electro-optical and nonlinear optical properties. Mach-Zehnder modulators (MZMs) heterojunctionally integrated with silicon or silicon nitride waveguides have been proven to achieve very high modulation bandwidths, supporting high-frequency modulation far exceeding 100 GHz.

[0003] Ideally, the fabrication of this electro-optic modulator should be compatible with conventional CMOS processes used in silicon photonics, resulting in higher performance, lower cost, and improved manufacturing scalability. Electro-optic modulator (composite waveguide) structures composed of thin-film lithium niobate and silicon nitride are typically fabricated using die-to-wafer (D2W) or wafer-to-wafer (W2W) bonding.

[0004] Prior art fabrication of LN-SiNx composite waveguides via W2W bonding typically involves front-end processes such as LN and metal electrode photolithography and thin film fabrication, making them incompatible with CMOS processes. Furthermore, the LN process relies on the processing of the SiNx waveguide chip, limiting LN process flexibility and reducing process efficiency. While fabricating a buried electrode structure by placing a metal electrode (Al) beneath the SiNx, and then bonding the LN-cut single chip to a SiNx waveguide wafer or a single SiNx waveguide chip via D2W or D2D bonding can address the CMOS incompatibility issue, this approach presents significant risks and challenges in the LN Si substrate removal process. For example, the D2W method presents the following: ① the risk of LN chip detachment during Si grinding; ② the risk of etchant damage to the SiNx waveguide device during wet etching of residual Si after grinding. The D2D method typically uses dry etching to remove the Si substrate, which is also incompatible with CMOS processes and unsuitable for mass production. Summary of the Invention

[0005] In view of this, the embodiments of the present application provide a method for preparing an LN-SiN composite waveguide structure and a composite waveguide structure, which at least partially solve the problems of incompatibility with CMOS processes and low process efficiency in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a composite waveguide structure, comprising a first waveguide wafer and an electro-optical thin film bonded to the first waveguide wafer.

[0007] The first waveguide wafer includes a first substrate, a first SiO2 film disposed on the first substrate, and a first metal electrode, a first waveguide structure, a second metal electrode and a groove disposed in the first SiO2 film;

[0008] The first metal electrode, the first waveguide structure, and the second metal electrode are located in the first SiO2 film from low to high. The first metal electrode is located on both sides of the first waveguide structure. The second metal electrode is connected to the first metal electrode via a metal interconnection through-hole. The second metal electrode is also connected to a thermal adjustment structure. A pad hole is provided above the second metal electrode. The groove is located in the area to be bonded, and the bottom of the groove is located above the first waveguide structure in the area to be bonded.

[0009] The electro-optical film includes a second SiO2 film, a waveguide boss and a second waveguide structure arranged in sequence. The waveguide boss and the second waveguide structure are located in the groove. The second waveguide structure is bonded to the bottom of the groove. A bonding pre-hole is provided on the second SiO2 film. The position of the bonding pre-hole corresponds to the position of the pad hole. The material of the second waveguide structure is an electro-optical material.

[0010] According to a specific implementation of the embodiment of the present application, the deviation between the sum of the heights of the waveguide boss and the second waveguide structure and the depth of the groove is less than 50 nm.

[0011] According to a specific implementation of the embodiment of the present application, the waveguide boss and the second waveguide structure are both spaced apart from the sidewall of the groove by a preset distance.

[0012] In a second aspect, an embodiment of the present application further provides a method for preparing a composite waveguide structure, for preparing the composite waveguide structure according to any embodiment of the first aspect, the method comprising:

[0013] forming the first SiO2 film on the first substrate, and sequentially forming the first metal electrode and the first waveguide structure in the first SiO2 film;

[0014] preparing the metal interconnection through-hole above at least one of the first metal electrodes, and filling the metal interconnection through-hole with metal;

[0015] preparing the second metal electrode and the thermal adjustment structure above the metal interconnection through hole;

[0016] forming the groove above the first waveguide structure in the area to be bonded of the first SiO2 film;

[0017] preparing the pad hole above the second metal electrode to complete the preparation of the first waveguide wafer;

[0018] preparing a second waveguide wafer, wherein the second waveguide wafer includes a second substrate and the electro-optical thin film disposed on the second substrate;

[0019] Bonding the second waveguide wafer to the first waveguide wafer, with the second waveguide structure bonded to the bottom of the groove, and the bonding reserved hole and the pad hole being arranged opposite to each other;

[0020] The second substrate is removed.

[0021] According to a specific implementation of the embodiment of the present application, the step of sequentially preparing the first metal electrode and the first waveguide structure in the first SiO2 film includes:

[0022] depositing a SiO2 layer on the first substrate;

[0023] depositing a first metal thin film on the SiO2 layer;

[0024] Processing the first metal film through a patterning process to form the first metal electrode;

[0025] depositing a first SiO2 passivation layer to cover the first metal electrode and the SiO2 layer;

[0026] Depositing a SiNx film on the first SiO2 passivation layer, and processing the SiNx film through a patterning process to form the first waveguide structure;

[0027] A SiO2 waveguide cladding layer is deposited and planarized, wherein the deposited SiO2 waveguide cladding layer covers the first waveguide structure and the first SiO2 passivation layer.

[0028] According to a specific implementation of the embodiment of the present application, the step of preparing the second metal electrode and the thermal adjustment structure above the metal interconnection through-hole includes:

[0029] depositing a second metal film on the SiO2 waveguide cladding;

[0030] processing the second metal film through a patterning process to form the second metal electrode;

[0031] Depositing a thermal adjustment film on the SiO2 waveguide cladding and the second metal electrode;

[0032] Processing the thermal adjustment film through a patterning process to form the thermal adjustment structure;

[0033] Depositing a second SiO2 passivation layer and planarizing it;

[0034] The SiO2 layer, the first SiO2 passivation layer, the SiO2 waveguide cladding layer and the second SiO2 passivation layer constitute the first SiO2 film.

[0035] According to a specific implementation of the embodiment of the present application, the preparing of the second waveguide wafer includes:

[0036] forming a buried oxide layer on the second substrate, and forming an electro-optical material layer on the buried oxide layer;

[0037] etching the electro-optical material layer to form the second waveguide structure;

[0038] Etching the buried oxide layer below the second waveguide structure to form the waveguide boss, and forming the second SiO2 film on the buried oxide layer that has not been etched;

[0039] The second SiO2 film is etched to form the bonding hole, and the position of the bonding hole corresponds to the position of the pad hole.

[0040] According to a specific implementation of the embodiment of the present application, bonding the second waveguide wafer to the first waveguide wafer includes:

[0041] performing cleaning and plasma activation on the first waveguide wafer and the second waveguide wafer in sequence;

[0042] Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device;

[0043] The pre-bonded device is annealed to complete the bonding.

[0044] According to a specific implementation of the embodiment of the present application, removing the second substrate includes:

[0045] The second substrate is removed by grinding or chemical mechanical polishing.

[0046] According to a specific implementation of the embodiment of the present application, the sheet resistance range of the thermal adjustment structure is 10-13Ω.

[0047] Beneficial effects:

[0048] The composite waveguide structure and preparation method thereof in the embodiment of the present application process a boss structure on the second waveguide wafer and a groove structure on the first waveguide wafer, and utilizes a "mortise and tenon" method for W2W bonding, thereby reducing the quality requirements of the traditional W2W method on the overall surface of the wafer, while improving the process structure compatibility between the bonding area and the non-bonding area, making the process structure and device functions richer; in addition, according to the W2W bonding alignment relationship, the structures to be aligned on the SiNx waveguide wafer and the LN waveguide wafer (such as the bonding area, the pad window, etc.) are indirectly aligned through layout design, and the flexibility advantage of independent processing of the SiNx waveguide wafer and the LN waveguide wafer is utilized to make the W2W heterogeneous integration method more compatible with the CMOS process. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 is a schematic diagram of a composite waveguide structure according to an embodiment of the present invention;

[0051] Figure 2 A schematic diagram of a process for preparing a composite waveguide structure according to an embodiment of the present invention;

[0052] Figure 3 Schematic diagram of preparing a SiO2 layer according to one embodiment of the present invention;

[0053] Figure 4 Schematic diagram of preparing a first metal electrode according to one embodiment of the present invention;

[0054] Figure 5 Schematic diagram of preparing a first SiO2 passivation layer according to one embodiment of the present invention;

[0055] Figure 6 A schematic diagram of preparing a first waveguide structure according to an embodiment of the present invention;

[0056] Figure 7 Schematic diagram of preparing SiO2 waveguide cladding according to one embodiment of the present invention;

[0057] Figure 8 A schematic diagram of preparing a metal interconnection through hole according to an embodiment of the present invention;

[0058] Figure 9 Schematic diagram of preparing a second metal electrode and a thermal adjustment structure according to one embodiment of the present invention;

[0059] Figure 10 Schematic diagram of preparing a second SiO2 passivation layer according to one embodiment of the present invention;

[0060] Figure 11 A schematic diagram of preparing a groove according to an embodiment of the present invention;

[0061] Figure 12 A schematic diagram of preparing a pad hole according to an embodiment of the present invention;

[0062] Figure 13 Schematic diagram of preparing a thin film LN substrate wafer according to one embodiment of the present invention;

[0063] Figure 14 A schematic diagram of preparing a second waveguide structure according to an embodiment of the present invention;

[0064] Figure 15 Schematic diagram of preparing a waveguide boss according to one embodiment of the present invention;

[0065] Figure 16 Schematic diagram of preparing bonding holes according to one embodiment of the present invention;

[0066] Figure 17 FIG. 4 is a schematic diagram of bonding a first waveguide wafer and a second waveguide wafer according to an embodiment of the present invention.

[0067] In the figure: 1. first substrate; 2. first SiO2 film; 3. first metal electrode; 4. first waveguide structure; 5. second metal electrode; 6. metal interconnection through hole; 7. thermal adjustment structure; 8. groove; 9. pad hole; 10. electro-optical material layer; 11. sacrificial layer; 12. bonding reserved hole; 13. second substrate; 14. second SiO2 film; 15. second waveguide structure; 16. waveguide boss; 17. buried oxide layer. DETAILED DESCRIPTION

[0068] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0069] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0070] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0071] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0072] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0073] First, refer to Figure 1, an embodiment of the present application provides a composite waveguide structure, including a first waveguide wafer and an electro-optical film bonded to the first waveguide wafer, wherein the first waveguide wafer includes a first substrate 1, a first SiO2 film 2 arranged on the first substrate 1, and a first metal electrode 3, a first waveguide structure 4, a second metal electrode 5 and a groove 8 arranged in the first SiO2 film 2; the first metal electrode 3, the first waveguide structure 4 and the second metal electrode 5 are arranged in the first SiO2 film 2 from low to high, the first metal electrode 3 is located on both sides of the first waveguide structure 4, and the second metal electrode 5 is connected to the first metal electrode 3 through a metal interconnection through-hole 6. The second metal electrode 5 is also connected to the thermal adjustment structure 7, and a pad hole 9 is provided above the second metal electrode 5; the groove 8 is located in the area to be bonded, and the bottom of the groove 8 is located above the first waveguide structure 4 in the area to be bonded; the electro-optical film includes a second SiO2 film 14, a waveguide boss 16 and a second waveguide structure 15 arranged in sequence, the waveguide boss 16 and the second waveguide structure 15 are located in the groove 8, the second waveguide structure 15 is bonded to the bottom of the groove 8, and a bonding pre-hole 12 is provided on the second SiO2 film 14, the position of the bonding pre-hole 12 corresponds to the position of the pad hole 9, and the material of the second waveguide structure 15 is an electro-optical material.

[0074] In this embodiment, a groove 8 structure is provided in the first waveguide wafer. The groove 8 structure is located above the waveguide structure in the area to be bonded. A boss structure is machined on the second waveguide wafer, and W2W bonding is performed using a "mortise and tenon" method. This allows the cladding layer thickness of the waveguide structure in the bonding area to be different from that in the non-bonding area, thereby improving the process structure compatibility of the bonding and non-bonding areas, and facilitating the increase in the diversity of device structures and functions that can be processed on the same wafer. In addition, the pad holes 9 provided on the first waveguide wafer and the bonding holes 12 provided on the second waveguide wafer can be indirectly aligned during fabrication through layout design based on the W2W bonding alignment relationship. This leverages the flexibility of independently processing the two waveguide wafers, making the W2W heterogeneous integration method more compatible with CMOS processes.

[0075] In specific implementation, by bonding the electro-optical film within the groove 8 structure, the electro-optical film and the waveguide structure below the groove 8 structure form a composite waveguide structure, so that the cladding layer thickness of the waveguide structure in the bonding area and the non-bonding area can be different, thereby resolving the processing contradiction caused by the inconsistent structural thickness due to different structural characteristics and requirements in the bonding area and the non-bonding area. Specifically, in the process of preparing a waveguide wafer, after the waveguide structure is completed, it is usually necessary to continue to make other structures upward, such as the thermal adjustment structure 7 or even more layers of metal interconnection. At this time, the structural thickness above the waveguide structure in the bonding area and the non-bonding area increases with the subsequent process. The more processing processes are required later, the thicker the structural thickness above the waveguide structure will become. However, the thickness above the waveguide in the bonding area needs to be thin enough to be fixed below 150nm. This in-groove bonding method can well resolve the above processing contradiction.

[0076] In one embodiment, the deviation between the sum of the heights of the waveguide protrusion 16 and the second waveguide structure 15 and the depth of the groove 8 is less than 50 nm.

[0077] In one embodiment, both the waveguide boss 16 and the second waveguide structure 15 are spaced a predetermined distance from the sidewalls of the groove 8. This spacing between the waveguide boss 16 and the second waveguide structure 15 and the groove 8 prevents the formation of closed pores in the resulting composite waveguide wafer after the first and second waveguide wafers are bonded and the second substrate 13 is removed. Such closed pores can reduce device reliability. Therefore, for the bonded device, maintaining a predetermined spacing and leaving a gap can improve device performance.

[0078] During specific implementation, the bonding reserved hole 12 on the second SiO 2 film 14 also needs to reserve a hole structure corresponding to the interval, so that the second waveguide structure 15 after bonding is in a non-enclosed space.

[0079] In a specific implementation, the material of the first waveguide structure 4 can be SiNx, Si, etc.

[0080] In a specific implementation, the material of the second waveguide structure 15 can be any one of electro-optical materials such as lithium niobate, lithium tantalate, and barium titanate.

[0081] In a second aspect, the present invention also provides a method for preparing a composite waveguide structure, referring to Figure 2 , for preparing the composite waveguide structure according to any embodiment of the first aspect, the method comprising:

[0082] The first SiO2 film 2 is formed on the first substrate 1, and the first metal electrode 3 and the first waveguide structure 4 are sequentially formed in the first SiO2 film 2;

[0083] preparing the metal interconnection through-hole 6 above at least one of the first metal electrodes 3 and filling the metal interconnection through-hole 6 with metal;

[0084] preparing the second metal electrode 5 and the thermal adjustment structure 7 above the metal interconnection through hole 6;

[0085] forming the groove 8 above the first waveguide structure 4 in the area to be bonded of the first SiO2 film 2;

[0086] preparing the pad hole 9 above the second metal electrode 5 to complete the preparation of the first waveguide wafer;

[0087] preparing a second waveguide wafer, wherein the second waveguide wafer includes a second substrate 13 and the electro-optical thin film disposed on the second substrate 13;

[0088] Bonding the second waveguide wafer to the first waveguide wafer, with the second waveguide structure 15 bonded to the bottom of the groove 8, and the bonding reserved hole 12 and the pad hole 9 being arranged opposite to each other;

[0089] The second substrate 13 is removed.

[0090] In this embodiment, the first waveguide wafer can be a SiNx waveguide wafer, and the second waveguide wafer can be an LN waveguide wafer. A groove 8 is fabricated on the SiNx waveguide wafer, and a boss is fabricated on the LN waveguide wafer. When the two wafers are bonded, the "mortise and tenon" W2W bonding between the groove 8 and the boss allows for different cladding thicknesses between the bonding and non-bonding regions. This improves process and structural compatibility between the bonding and non-bonding regions, facilitating greater diversity in device structure and functionality that can be processed on the same wafer. Furthermore, during fabrication, the pad holes 9 on the first waveguide wafer and the pre-bonding holes 12 on the second waveguide wafer are indirectly aligned via layout design based on the W2W bonding alignment relationship. This leverages the flexibility of independently processing the two waveguide wafers, enabling greater compatibility between the W2W heterogeneous integration approach and CMOS processes. This improves process efficiency and flexibility, while reducing the overall surface quality requirements of the wafers placed on the traditional W2W approach.

[0091] In addition, compared with the D2W bonding method, the method of this embodiment reduces the risk of LN chip falling off during the removal of the LN Si substrate, and can directly remove the Si substrate by CMP, avoiding problems such as low processing efficiency and damage to SiNx waveguide devices caused by wet etching, thereby simplifying the process; compared with the D2W bonding method, the LN chip size can be smaller, thereby improving the integration of the optical chip.

[0092] In one embodiment, the step of sequentially preparing the first metal electrode 3 and the first waveguide structure 4 in the first SiO2 film 2 includes:

[0093] A SiO2 layer is deposited on the first substrate 1, such as Figure 3 As shown;

[0094] depositing a first metal film on the SiO2 layer;

[0095] The first metal film is processed by a patterning process to form the first metal electrode 3, such as Figure 4 As shown;

[0096] Deposit a first SiO2 passivation layer to cover the first metal electrode 3 and the SiO2 layer, such as Figure 5 As shown;

[0097] A SiNx film is deposited on the first SiO2 passivation layer, and the SiNx film is processed by a patterning process to form the first waveguide structure 4. Figure 6 As shown;

[0098] Deposit a SiO2 waveguide cladding and flatten it, wherein the deposited SiO2 waveguide cladding covers the first waveguide structure 4 and the first SiO2 passivation layer. Figure 7 shown.

[0099] In specific implementation, a SiO2 layer is deposited on the first substrate 1 by a CVD process or a thermal oxidation growth method, and the thickness of the SiO2 layer is set to 1 to 8 μm; a first metal film (such as Al, Cu, Au, etc.) is deposited by PVD, and the thickness of the first metal film is set to 0.5 to 1.5 μm; then a lead electrode structure is formed by a patterning process such as photolithography and etching; a first SiO2 passivation layer is deposited by CVD, and then it is flattened by CMP until the SiO2 thickness above the first metal electrode 3 is 200 to 500 nm; a Si Nx film with a thickness of 100 to 500 nm and a refractive index of 1.9 to 2.2 is deposited by CVD, and then a SiNx waveguide structure (first waveguide structure 4) is formed by a patterning process such as photolithography and etching; SiO2 is deposited by CVD to form a SiO2 waveguide cladding, and then it is flattened by CMP until the SiO2 thickness above the Si Nx waveguide structure is 1 to 3 μm.

[0100] In one embodiment, the following method is used to prepare the metal interconnection via 6:

[0101] SiO2 dry etching forms interconnection through holes, and then the through holes are filled by tungsten (W) CVD or Cu electroplating, and CMP flattening is performed to form the metal interconnection through holes 6. Figure 8shown.

[0102] In one embodiment, the step of preparing the second metal electrode 5 and the thermal adjustment structure 7 above the metal interconnection through hole 6 includes:

[0103] depositing a second metal film on the SiO2 waveguide cladding;

[0104] The second metal film is processed by a patterning process to form the second metal electrode 5. Figure 9 ;

[0105] Depositing a thermal adjustment film on the SiO2 waveguide cladding and the second metal electrode 5;

[0106] Processing the thermal adjustment film through a patterning process to form the thermal adjustment structure 7;

[0107] Deposit the second SiO2 passivation layer and planarize it, refer to Figure 10 ;

[0108] The SiO 2 layer, the first SiO 2 passivation layer, the SiO 2 waveguide cladding layer and the second SiO 2 passivation layer constitute the first SiO 2 film 2 .

[0109] During specific implementation, the patterning process in the above embodiment may be performed using processes such as photolithography and etching.

[0110] In specific implementation, a 0.5-1.5 μm second metal film is deposited by PVD process and patterned to form a second metal electrode 5, and then a 50-150 nm TiN film is deposited by PVD and patterned to form a thermal adjustment structure 7; then 1-3 μm SiO2 is deposited by CVD and CMP flattened to form a second SiO2 passivation layer.

[0111] In one embodiment, for the preparation of the groove 8, refer to Figure 11 SiO2 is etched by dry etching until the remaining thickness of SiO2 on the SiNx waveguide structure is less than 150 nm and the planar size of the groove 8 is greater than 1 μm×1 μm.

[0112] In specific implementation, in order to ensure that the electro-optical film bonded in the groove 8 structure can form a composite waveguide structure with the first waveguide structure 4, it is proposed that the SiO2 thickness between the bottom surface of the groove 8 and the top surface of the first waveguide structure 4 in the bonding area is less than 150nm.

[0113] In one embodiment, when preparing the pad hole 9, dry etching SiO2 is used to expose the metal pad. Figure 12 .

[0114] In one embodiment, preparing the second waveguide wafer includes:

[0115] A buried oxide layer 17 is formed on the second substrate 13, and an electro-optical material layer 10 is formed on the buried oxide layer 17. Figure 13 ;

[0116] The electro-optical material layer 10 is etched to form the second waveguide structure 15. Figure 14 ;

[0117] The buried oxide layer 17 below the second waveguide structure 15 is etched to form the waveguide boss 16, and the unetched buried oxide layer 17 forms the second SiO2 film 14. Figure 15 ;

[0118] The second SiO2 film 14 is etched to form the bonding hole 12. The position of the bonding hole 12 corresponds to the position of the pad hole 9. Figure 16 .

[0119] In specific implementation, an LNOI substrate wafer (a commercially mature thin film LN substrate) can be used, including a second substrate 13, a buried oxide layer 17 and an electro-optical material layer 10, wherein the electro-optical material layer 10 is an LN thin film with a thickness of 100nm to 500nm (can be prepared using Smart-cut process technology, also called smart shearing technology, a process technology that forms a damage layer by ion implantation of bulk LN and annealing at 200 to 300°C, resulting in splitting and shedding along the damage layer), and the buried oxide layer 17BOX has a thickness of 1 to 8μm (SiO2 thin film prepared by thermal oxidation growth).

[0120] During specific implementation, for the patterning of the second waveguide structure 15, inductively coupled plasma-reactive ion etching (ICP-RIE dry etching) is used to form an LN waveguide structure on the LN film, wherein a sacrificial layer 11 is applied. The sacrificial layer 11 is a photoresist or a hard mask material such as SiNx, Cr, etc. (which needs to be removed later). It should be noted that when designing the patterned photolithography layout in this step, the position of the LN waveguide structure needs to be determined based on the flip alignment relationship of the subsequent W2W bonding with the SiNx waveguide wafer (groove 8 structure) to achieve indirect alignment of the LN waveguide and the SiNx waveguide on the layout.

[0121] In specific implementation, for the preparation of the waveguide boss 16 , it is necessary to continue etching the SiO 2 located below the LN waveguide structure to form the waveguide boss 16 , and then remove the photoresist or hard mask.

[0122] During specific implementation, for the preparation of the bonding reserved hole 12, SiO2 is dry-etched to the Si substrate (second substrate 13). When designing the layout of this graphical process, the alignment hole needs to form an indirect alignment relationship with the metal pad on the SiNx waveguide wafer, the side gap of the bonding groove 8, etc.

[0123] In one embodiment, referring to Figure 17 , bonding the second waveguide wafer to the first waveguide wafer, comprising:

[0124] performing cleaning and plasma activation on the first waveguide wafer and the second waveguide wafer in sequence;

[0125] Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device;

[0126] The pre-bonded device is annealed to complete the bonding.

[0127] In a specific implementation, the bonding strength can be improved by annealing, and the annealing temperature is set to be less than 250°C.

[0128] In one embodiment, removing the second substrate 13 includes:

[0129] The second substrate 13 is removed by grinding or chemical mechanical polishing. The structure after removing the second substrate 13 is shown in FIG. Figure 1 .

[0130] In one embodiment, the sheet resistance of the thermal adjustment structure 7 is in the range of 10-13Ω.

[0131] In a specific implementation, taking the first waveguide wafer being a SiNx waveguide wafer and the second waveguide wafer being an LN waveguide wafer as an example, the method for preparing a composite waveguide structure may include the following steps:

[0132] A: SiNx waveguide wafer processing - CMOS process compatible

[0133] (1) Preparation of SiO2 layer: SiO2 with a thickness of 1 to 8 μm is prepared on a Si substrate by CVD or thermal oxidation growth;

[0134] (2) Preparation of the first metal electrode 3: PVD deposits a first metal film (such as Al, Cu, Au, etc.) with a thickness of 0.5 to 1.5 μm; then a patterning process such as photolithography and etching is used to form a lead electrode structure;

[0135] (3) Preparation and planarization of the first SiO2 passivation layer: CVD deposits SiO2, which is then planarized by CMP to a thickness of 200 to 500 nm on the first metal electrode 3;

[0136] (4) Preparation of SiNx film and waveguide patterning: CVD deposition of SiNx film with a thickness of 100-500 nm and a refractive index of 1.9-2.2, followed by patterning processes such as photolithography and etching to form a SiNx waveguide structure;

[0137] (5) Preparation and planarization of SiO2 waveguide cladding: CVD deposits SiO2 and performs planarization by CMP until the thickness of SiO2 on the SiNx waveguide structure is 1 to 3 μm;

[0138] (6) Etching and filling of metal interconnection through-holes 6: Dry etching of SiO2 forms interconnection through-holes, which are then filled by tungsten (W) CVD or Cu electroplating, and then CMP planarization is performed;

[0139] (7) Preparation of the second metal electrode 5 and the thermal adjustment structure 7: PVD deposits a 0.5-1.5 μm second metal film and performs patterning to form a metal electrode structure, and then PVD deposits a 50-150 nm TiN film and performs patterning to form a thermal adjustment structure 7;

[0140] (8) Preparation and planarization of the second SiO2 passivation layer: CVD deposition of 1-3 μm SiO2 and CMP planarization;

[0141] (9) Etching of the bonding area groove 8: Dry etching of SiO2 until the remaining thickness of SiO2 on the SiNx waveguide is less than 150nm and the planar size of the groove 8 is greater than 1μm×1μm;

[0142] (10) Pad windowing: SiO2 dry etching to expose the metal pad and form a pad hole 9;

[0143] B: LN waveguide wafer processing - external dedicated line processing in CMOS process environment

[0144] (11) Preparation of thin film LN substrate wafer: LN thickness is 100 nm to 500 nm (prepared using Smart-cut process technology, i.e., smart shearing technology, a process technology that forms a damage layer by ion implantation of bulk LN and annealing at 200 to 300°C, followed by splitting and shedding along the damage layer), and buried oxide layer 17 thickness is 1 to 8 μm (SiO2 thin film prepared by thermal oxidation growth);

[0145] (12) LN waveguide patterning: Inductively coupled plasma-reactive ion etching (ICP-RIE dry etching) is used to form an LN waveguide structure on the LN film, where the sacrificial layer 11 is a photoresist or a hard mask material such as SiNx or Cr. It should be noted that when designing the photolithography layout for this patterning step, the position of the LN waveguide structure must be determined based on the flip alignment relationship of the subsequent W2W bonding with the SiNx waveguide wafer (groove 8) to achieve indirect alignment between the LN waveguide structure and the SiNx waveguide structure on the layout;

[0146] (13) LN waveguide boss 16 structure processing: continue etching SiO2 to form LN waveguide boss 16, whose height (the total height of the LN waveguide structure and the waveguide boss 16) is the same as the depth of the SiNx waveguide structure bonding area groove 8 (deviation <50nm), and then remove the photoresist or hard mask;

[0147] (14) Patterning of the bonding hole 12: Dry etching SiO2 to the Si substrate. When designing the layout of this patterning process, the bonding hole 12 needs to form an indirect alignment relationship with the metal pad on the SiNx waveguide wafer, the side gap of the groove 8, etc.

[0148] C: LN-SiNx composite waveguide processing

[0149] (15) LN-SiNx waveguide wafer bonding: First, the wafer surface is cleaned, plasma activated and other surface treatments are performed, and then the LN waveguide wafer and the SiNx waveguide wafer are combined by alignment pre-bonding and annealing (temperature less than 250°C);

[0150] (16) Removal of Si substrate from LN waveguide wafer: The Si substrate is removed by grinding, CMP and other processes.

[0151] In the embodiments provided by the present invention, a boss structure is machined on an LN waveguide wafer, and a groove structure is machined on a SiNx waveguide wafer. This "mortise and tenon" W2W bonding method reduces the quality requirements of the traditional W2W method on the overall surface of the wafer, while improving the process structure compatibility between the bonding area and the non-bonding area, making the process structure and device functions richer. According to the W2W bonding alignment relationship, the structures that need to be aligned on the SiNx waveguide wafer and the LN waveguide wafer (such as the bonding area, pad window, etc.) are indirectly aligned through layout design. By taking advantage of the flexibility of independent processing of the SiNx waveguide wafer and the LN waveguide wafer, the W2W heterogeneous integration method has better compatibility with the CMOS process.

[0152] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A composite waveguide structure, characterized in that: comprising a first waveguide wafer and an electro-optical thin film bonded to the first waveguide wafer, The first waveguide wafer comprises a first substrate (1), a first SiO2 film (2) arranged on the first substrate (1), and a first metal electrode (3), a first waveguide structure (4), a second metal electrode (5), and a groove (8) arranged in the first SiO2 film (2); The first metal electrode (3), the first waveguide structure (4) and the second metal electrode (5) are located in the first SiO2 film (2) at heights from low to high, respectively; the first metal electrode (3) is located on both sides of the first waveguide structure (4); the second metal electrode (5) is connected to the first metal electrode (3) via a metal interconnection through-hole (6); the second metal electrode (5) is also connected to a thermal adjustment structure (7); a pad hole (9) is provided above the second metal electrode (5); the groove (8) is located in the area to be bonded, and the bottom of the groove (8) is located above the first waveguide structure (4) in the area to be bonded; The electro-optical film comprises a second SiO2 film (14), a waveguide boss (16) and a second waveguide structure (15) which are arranged in sequence. The waveguide boss (16) and the second waveguide structure (15) are located in the groove (8). The second waveguide structure (15) is bonded to the bottom of the groove (8). A bonding pre-hole (12) is provided on the second SiO2 film (14). The position of the bonding pre-hole (12) corresponds to the position of the pad hole (9). The material of the second waveguide structure (15) is an electro-optical material.

2. The composite waveguide structure according to claim 1, wherein: The deviation between the sum of the heights of the waveguide protrusion (16) and the second waveguide structure (15) and the depth of the groove (8) is less than 50 nm.

3. The composite waveguide structure according to claim 1, wherein: The waveguide boss (16) and the second waveguide structure (15) are both spaced apart by a preset distance from the side wall of the groove (8).

4. A method for preparing a composite waveguide structure, for preparing the composite waveguide structure according to any one of claims 1 to 3, characterized in that: The method comprises: The first SiO2 film (2) is prepared on the first substrate (1), and the first metal electrode (3) and the first waveguide structure (4) are sequentially prepared in the first SiO2 film (2); Preparing the metal interconnection through-hole (6) above at least one of the first metal electrodes (3), and filling the metal interconnection through-hole (6) with metal; preparing the second metal electrode (5) and the heat regulating structure (7) above the metal interconnection through hole (6); forming the groove (8) above the first waveguide structure (4) in the area to be bonded of the first SiO2 film (2); preparing the pad hole (9) above the second metal electrode (5) to complete the preparation of the first waveguide wafer; preparing a second waveguide wafer, wherein the second waveguide wafer comprises a second substrate (13) and the electro-optical thin film arranged on the second substrate (13); The second waveguide wafer is bonded to the first waveguide wafer, and the second waveguide structure (15) is bonded to the bottom of the groove (8), and the bonding reserved hole (12) is arranged opposite to the pad hole (9); The second substrate (13) is removed.

5. The method for preparing a composite waveguide structure according to claim 4, wherein: The first metal electrode (3) and the first waveguide structure (4) are sequentially prepared in the first SiO2 film (2), comprising: depositing a SiO2 layer on the first substrate (1); depositing a first metal film on the SiO2 layer; Processing the first metal film through a patterning process to form the first metal electrode (3); Depositing a first SiO2 passivation layer to cover the first metal electrode (3) and the SiO2 layer; Depositing a SiNx film on the first SiO2 passivation layer, and processing the SiNx film through a patterning process to form the first waveguide structure (4); A SiO2 waveguide cladding is deposited and planarized, wherein the deposited SiO2 waveguide cladding covers the first waveguide structure (4) and the first SiO2 passivation layer.

6. The method for preparing a composite waveguide structure according to claim 5, wherein: The step of preparing the second metal electrode (5) and the heat regulating structure (7) above the metal interconnection through hole (6) comprises: depositing a second metal film on the SiO2 waveguide cladding; Processing the second metal film through a patterning process to form the second metal electrode (5); Depositing a thermal adjustment film on the SiO2 waveguide cladding and the second metal electrode (5); Processing the thermal adjustment film through a patterning process to form the thermal adjustment structure (7); Depositing a second SiO2 passivation layer and planarizing it; The SiO2 layer, the first SiO2 passivation layer, the SiO2 waveguide cladding layer and the second SiO2 passivation layer constitute the first SiO2 film (2).

7. The method for preparing a composite waveguide structure according to claim 4, wherein: The step of preparing the second waveguide wafer comprises: preparing a buried oxide layer (17) on the second substrate (13), and preparing an electro-optical material layer (10) above the buried oxide layer (17); Etching the electro-optical material layer (10) to form the second waveguide structure (15); Etching the buried oxide layer (17) below the second waveguide structure (15) to form the waveguide boss (16), and forming the second SiO2 film (14) on the buried oxide layer (17) that has not been etched; The second SiO2 film (14) is etched to form the bonding reserved hole (12), and the position of the bonding reserved hole (12) corresponds to the position of the pad hole (9).

8. The method for preparing a composite waveguide structure according to claim 4, wherein: Bonding the second waveguide wafer to the first waveguide wafer includes: performing cleaning and plasma activation on the first waveguide wafer and the second waveguide wafer in sequence; Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device; The pre-bonded device is annealed to complete the bonding.

9. The method for preparing a composite waveguide structure according to claim 4, wherein: The removing of the second substrate (13) comprises: The second substrate (13) is removed by grinding or chemical mechanical polishing.

10. The method for preparing a composite waveguide structure according to any one of claims 4 to 9, characterized in that: The square resistance of the heat regulating structure (7) is in the range of 10-13Ω.

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