Laser projection device and control method thereof

Abstract

The present application discloses a laser projection device and a control method thereof, which belongs to the field of electronic technology. The system-level chip in the laser projection device can control the reset chip to power on in response to the power-on operation, and send a power-on signal to the power control chip. After powering on, the reset chip sends a power-normal signal of valid level to the power control chip and the light valve control chip respectively. Thus, the power control chip can respond to the power-on signal and the power-normal signal, control the power conversion circuit to send multiple valid power signals to the light valve control chip in sequence, and send a power sensing signal of valid level to the light valve control chip to control the light valve control chip to power on. Since the light valve control chip can be powered on by a power control chip and a power conversion circuit, the circuit for controlling the light valve control chip to power on is simplified, the integration of the internal components of the laser projection device is improved, and the cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a laser projection device and a control method thereof. Background Art

[0002] Laser projection equipment can generally include a light valve control chip and a light valve. During the startup process of the laser projection equipment, the light valve control chip can control the light valve to project the projection image onto the projection screen after successful power-on, thereby realizing the display of the projection image.

[0003] However, the circuit for controlling the power-on of the light valve control chip in the related art is relatively complex. Summary of the Invention

[0004] The embodiments of the present disclosure provide a laser projection device that can solve the problem of relatively complex circuits used to control the power-on of light valve control chips in related technologies. The technical solution is as follows:

[0005] In one aspect, a laser projection device is provided, comprising a system-on-chip, a power supply circuit, a power supply control chip, a reset chip, a light valve control chip, and a power conversion circuit;

[0006] The system-level chip is connected to the power circuit and the first input terminal of the power control chip respectively, and the system-level chip is used to control the power circuit to supply power to the reset chip and send a power-on signal to the power control chip in response to a power-on operation;

[0007] The reset chip is also connected to the second input terminal of the power control chip and the first input terminal of the light valve control chip. The reset chip is used to send a power normal signal of a valid level to the power control chip and the light valve control chip respectively after power-on;

[0008] The power control chip is used to respond to the power-on signal and the power normal signal, control the power conversion circuit to send multiple valid power signals to the light valve control chip in sequence, and to send a power sensing signal of a valid level to the light valve control chip to control the light valve control chip to power on.

[0009] On the other hand, a laser projection device is provided, the laser projection device including a system-on-chip, a power supply circuit, a power control chip, a reset chip, a light valve control chip and a power conversion circuit;

[0010] The system-level chip is connected to the power circuit and the first input terminal of the power control chip respectively, and the system-level chip is used to control the power circuit to stop supplying power to the reset chip in response to the standby operation, and send a standby signal to the power control chip;

[0011] The power control chip is used for:

[0012] receiving a power-good signal of an invalid level output by the reset chip through the second input terminal after the reset chip is powered off;

[0013] In response to the standby signal and the power normal signal, sending a power sensing signal of an invalid level to the light valve control chip;

[0014] The power conversion circuit is controlled to sequentially send a plurality of power signals of invalid levels to the light valve control chip, so as to control the light valve control chip to power off.

[0015] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0016] The disclosed embodiments provide a laser projection device and a control method thereof. The system-level chip in the laser projection device can control the reset chip to power on in response to a power-on operation and send a power-on signal to the power control chip. After powering on, the reset chip sends a power-normal signal of a valid level to the power control chip and the light valve control chip, respectively. Thus, the power control chip can respond to the power-on signal and the power-normal signal, control the power conversion circuit to sequentially send multiple valid power signals to the light valve control chip, and send a power sensing signal of a valid level to the light valve control chip to control the light valve control chip to power on. Since the light valve control chip can be powered on by a power control chip and a power conversion circuit, the circuit for controlling the light valve control chip to power on is simplified, the integration of the internal components of the laser projection device is improved, and the cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 is a schematic structural diagram of a laser projection device provided by an embodiment of the present disclosure;

[0019] Figure 2 is a schematic structural diagram of another laser projection device provided by an embodiment of the present disclosure;

[0020] Figure 3 This is a timing diagram of signals received and output by a power control chip provided by an embodiment of the present disclosure;

[0021] Figure 4is a structural diagram of a first conversion circuit provided by an embodiment of the present disclosure;

[0022] Figure 5 is a structural diagram of a second conversion circuit provided by an embodiment of the present disclosure;

[0023] Figure 6 is a structural diagram of a third conversion circuit provided by an embodiment of the present disclosure;

[0024] Figure 7 1 is a schematic structural diagram of another laser projection device provided by an embodiment of the present disclosure;

[0025] Figure 8 is a flow chart of a control method for a laser projection device provided by an embodiment of the present disclosure;

[0026] Figure 9 is a flow chart of a control method for a laser projection device provided by an embodiment of the present disclosure;

[0027] Figure 10 It is a structural diagram of a laser projection device provided by the related art;

[0028] Figure 11 This is a flow chart of a control method for a laser projection device provided by the related art;

[0029] Figure 12 This is a timing diagram of the signals received and output by a first timing control chip provided by the related art;

[0030] Figure 13 is a structural schematic diagram of another laser projection device provided by an embodiment of the present disclosure;

[0031] Figure 14 This is a timing diagram of signals received and output by a power control chip provided by an embodiment of the present disclosure;

[0032] Figure 15 is a schematic diagram of the lens provided by an embodiment of the present disclosure in an open state and a closed state;

[0033] Figure 16 is a schematic diagram of a lens provided by an embodiment of the present disclosure in an initial state;

[0034] Figure 17 is a flow chart of another method for controlling a laser projection device provided by an embodiment of the present disclosure;

[0035] Figure 18 is a flow chart of another method for controlling a laser projection device provided by an embodiment of the present disclosure;

[0036] Figure 19This is a flow chart of another method for controlling a laser projection device provided by the related art;

[0037] Figure 20 This is a timing diagram of the signals received and output by a first timing control chip provided by the related art;

[0038] Figure 21 The present disclosure provides a flowchart of a power-on process of a laser projection device;

[0039] Figure 22 The present invention provides a flowchart of a standby process of a laser projection device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0041] Figure 1 The present disclosure provides a schematic structural diagram of a laser projection device. Figure 1 As shown, the laser projection device includes a system on chip (SOC) 10, a power circuit 20, a power control chip 30, a reset chip 40, a light valve control chip 50 and a power conversion circuit 60. The laser projection device can be a miniaturized laser projection device.

[0042] The power control chip 30 may be a programmable logic chip. Alternatively, the power control chip 30 may be a single-chip microcomputer, a field programmable gate array (FPGA), or a complex programmable logic device (CPLD). The light valve control chip 50 may be a digital light processing chip (DLPC).

[0043] refer to Figure 1 and Figure 2 The system-on-chip 10 is connected to the first input terminal X1 of the power circuit 20 and the power control chip 30, respectively. The power circuit 20 is also connected to the reset chip 40. In response to a power-on operation, the system-on-chip 10 controls the power circuit 20 to supply power to the reset chip 40 and sends a power-on signal to the power control chip 30.

[0044] Optionally, the power-on operation may be a selection operation for a power-on button. The power-on button may be located on the laser projection device or on a remote controller for controlling the laser projection device. The power-on signal may be a high-level signal.

[0045] refer to Figure 2 The reset chip 40 is also connected to the second input terminal X2 of the power control chip 30 and the first input terminal Z1 of the light valve control chip 50. After power is applied, the reset chip 40 is configured to send a valid power good (PWRGOOD) signal to the power control chip 30 and the light valve control chip 50, respectively. The valid power good signal can be a high level signal. For example, the voltage of the high level signal can be 3.3 volts (V).

[0046] In the disclosed embodiment, the system-on-chip 10 controls the power supply circuit 20 to supply power to the reset chip 40, thereby controlling the power-on of the reset chip 40. The reset chip 40 may be provided with a reset pin, which is connected to the second input terminal X2 of the power control chip 30 and the first input terminal Z1 of the light valve control chip 50, respectively. The second input terminal X2 of the power control chip 30 and the first input terminal Z1 of the light valve control chip 50 can both be PWRGOOD pins, i.e., both are used to receive a power-good signal. After the power supply circuit 20 supplies power to the reset chip 40, i.e., after the reset chip 40 is powered on, the reset pin of the reset chip 40 can output a power-good signal of a valid level.

[0047] The power control chip 30 is further connected to the power conversion circuit 60 and the light valve control chip 50, respectively. The power conversion circuit 60 is also connected to the light valve control chip 50. In response to a power-on signal and a valid-level power-good signal, the power control chip 30 controls the power conversion circuit 60 to sequentially send multiple valid power signals to the light valve control chip 50, and to send a valid-level power sensing signal to the light valve control chip 50 to control powering on the light valve control chip 50. The multiple valid power signals can all be high-level power signals, and the voltages of the multiple valid power signals can vary. The valid-level power sensing signal can be a high-level signal, for example, with a voltage of 3.3V. The power sensing signal can be a power-on sense (POSENSE) signal.

[0048] In response to the power-on signal and the power-good signal, the power control chip 30 controls the power conversion circuit 60 to sequentially transmit multiple valid power signals to the light valve control chip 50. After transmitting the multiple valid power signals to the light valve control chip 50, the power control chip 30 transmits a power sensing signal at a valid level to the light valve control chip 50, thereby controlling the light valve control chip 50 to power on. After sequentially receiving the power-good signal at a valid level, the multiple valid power signals, and the power sensing signal at a valid level, the light valve control chip 50 determines that the power supply is normal. After completing internal program initialization, the light valve control chip 50 controls the light valve to flip, thereby displaying the projected image.

[0049] In summary, the embodiments of the present disclosure provide a laser projection device, in which the system-level chip in the laser projection device can control the reset chip to power on in response to a power-on operation, and send a power-on signal to the power control chip. After powering on, the reset chip sends a power-normal signal of a valid level to the power control chip and the light valve control chip, respectively. Thus, the power control chip can respond to the power-on signal and the power-normal signal, control the power conversion circuit to sequentially send multiple valid power signals to the light valve control chip, and send a power sensing signal of a valid level to the light valve control chip to control the light valve control chip to power on. Since the light valve control chip can be powered on by a power control chip and a power conversion circuit, the circuit for controlling the light valve control chip to power on is simplified, the integration of the internal components of the laser projection device is improved, and the cost is reduced.

[0050] refer to Figure 1 , the laser projection device may further include a mainboard 100 and a display panel 200. The system-on-chip 10 is located on the mainboard 100. The power control chip 30, the reset chip 40, the light valve control chip 50 and the power conversion circuit 60 are all located on the display panel 200. In the embodiment of the present disclosure, the power control chip 30 is used to send a valid enable signal to the power conversion circuit 60 in response to a power-on signal and a power normal signal. The power conversion circuit 60 is used to send a plurality of valid power signals to the light valve control chip 50 in sequence in response to the valid enable signal, and to send a valid control signal to the power control chip 30. The power control chip 30 is used to send a power sensing signal to the light valve control chip 50 in response to the valid control signal. The valid enable signal and the valid control signal can both be high-level signals. For example, the power conversion circuit 60 can send four valid power signals to the light valve control chip 50 in sequence.

[0051] refer to Figure 2The power conversion circuit 60 may include a first conversion circuit 61, multiple second conversion circuits 62, and a third conversion circuit 63. For example, the number of the multiple second conversion circuits 62 may be two. The first output terminal Y1 of the power control chip 30 is connected to the input terminal of the first conversion circuit 61, and the output terminal of the first conversion circuit 61 is connected to the second input terminal Z2 of the light valve control chip 50 and the third input terminal X3 of the power control chip 30.

[0052] Table 1 shows the signals to be received and output by the power control chip 30 during the power-on process of the light valve control chip 50. The first effective control signal to the third effective control signal can all be high-level signals, and the multiple effective power signals can include the first effective power signal PWR1 to the third effective power signal PWR3. Figure 2 and Figure 3 The power control chip 30 is configured to send an enable signal EN1 to the first conversion circuit 61 after receiving the power-on signal and the power-normal signal for a first duration t1. In response to the enable signal EN1, the first conversion circuit 61 is configured to send a first enable signal PWR1 to the second input terminal Z2 of the light valve control chip 50 and a first enable control signal PG1 to the third input terminal X3 of the power control chip 30. Both the first enable signal PWR1 and the first enable control signal PG1 can be high-level signals. The first duration t1 can be a fixed duration pre-stored in the power control chip 30. For example, the first duration t1 can be 10 milliseconds (ms). The voltage of the first enable signal PWR1 can be 1.15V.

[0053] Table 1

[0054]

[0055] The first valid power signal PWR1 received at the second input terminal Z2 of the light valve control chip 50 can be used to power a core functional interface within the light valve control chip. For example, the core functional interface may include a V-by-one interface and an interface for outputting a high-speed signal to the light valve. The high-speed signal may be a control signal for controlling the light valve flipping. Optionally, upon receiving a power-on signal at its first input terminal X1 and a power-good signal at its second input terminal X2, the power control chip 30 can start a timer. After the timer reaches a first time duration t1, the timer is reset to 0 and a valid enable signal EN1 is sent to the input terminal of the first conversion circuit 61 via the first output terminal Y1.

[0056] The power control chip 30 may have a second output terminal Y2 and a plurality of fourth input terminals X4, and the light valve control chip 50 may have a plurality of third input terminals Z3. The second output terminal Y2 of the power control chip 30 is connected to the input terminals of the plurality of second conversion circuits 62, and the output terminals of the plurality of second conversion circuits 62 are respectively connected to the plurality of third input terminals Z3 of the light valve control chip 50 and the plurality of fourth input terminals X4 of the power control chip 30 in a one-to-one correspondence. For example, refer to Figure 2 The power control chip 30 may have two fourth input terminals X4 , and the plurality of second conversion circuits 62 may include a first second conversion circuit 62 and a second second conversion circuit 62 .

[0057] The power control chip 30 is configured to send an enable signal EN2 to each second conversion circuit 62 after receiving the first enable control signal PG1 for a second duration t2. In response to the enable signal EN2, each second conversion circuit 62 is configured to send a second enable power signal PWR2 to the corresponding third input terminal Z3 and a second enable control signal PG2 to the corresponding fourth input terminal X4. Each second enable control signal can be a high-level signal. The second duration t2 can be a fixed duration pre-stored in the power control chip 30. For example, the second duration t2 can be 10 ms.

[0058] If the power control chip 30 can have two fourth input terminals X4, the multiple second conversion circuits 62 can include a first second conversion circuit 62 and a second second conversion circuit 62, then the third input terminal X3 of the power control chip 30 can start the timer again after receiving the first valid control signal PG1. After the timing length of the timer reaches the second time length t2, the timer can be cleared to 0 and a valid enable signal EN2 can be sent to the first second conversion circuit 62 and the second second conversion circuit 62 respectively.

[0059] The first second conversion circuit 62 is configured to, in response to the received valid enable signal EN2, send a second valid power signal PWR2 to the corresponding third input terminal Z3, and send a second valid control signal PG2 to a fourth input terminal X4 of the power control chip 30. The second second conversion circuit 62 is configured to, in response to the received valid enable signal EN2, send another second valid power signal PWR2 to the corresponding third input terminal Z3, and send another second valid control signal PG2 to another fourth input terminal X4 of the power control chip 30. For example, the voltage of the first second valid power signal PWR2 may be 1.8V, and the voltage of the other second valid power signal PWR2 may be 3.3V.

[0060] If the light valve control chip 50 has two third input terminals Z3, the second valid power signal PWR2 received at one third input terminal Z2 of the light valve control chip 50 can be used to power the V-by-one interface and the interface that outputs a low-speed signal to the light valve. The low-speed signal can be a signal used to configure the light valve, such as the angle of a lens on the light valve. The second valid power signal PWR2 received at the other third input terminal Z2 of the light valve control chip 50 can be used to power the interface that outputs a low-speed signal to the light valve and the storage interface. The low-speed signal can be a control signal that controls the flipping of the light valve. The storage interface can be an interface for connecting to a program storage component of a laser projection device.

[0061] The third output terminal Y3 of the power control chip 30 is connected to the input terminal of the third conversion circuit 63. The output terminal of the third conversion circuit 63 is respectively connected to the fourth input terminal Z4 of the light valve control chip 50 and the fifth input terminal X5 of the power control chip 30. The fourth output terminal Y4 of the power control chip 30 is connected to the fifth input terminal Z5 of the light valve control chip 50. The power control chip 30 is configured to send an enable signal EN3 to the third conversion circuit 63 after receiving the third duration t3 of the plurality of second valid control signals PG2. In response to the enable signal EN3, the third conversion circuit 63 is configured to send a third valid power signal PWR3 to the light valve control chip 50 and a third valid control signal PG3 to the power control chip 30. The power control chip 30 is configured to send a power sensing signal of an active level to the light valve control chip 50 after receiving the fourth duration t4 of the third valid control signal PG3. The third valid power signal PWR3 received at the fourth input terminal Z4 of the light valve control chip 50 can be used to power the storage interface. The third effective control signal PG3 can be a high-level signal. The third duration t3 and the fourth duration t4 can both be fixed durations pre-stored in the power control chip 30. For example, the third duration t3 can be 10ms, and the fourth duration t4 can be 20ms. The voltage of the third effective power signal PWR3 can be 1.21V.

[0062] The power control chip 30 can restart the timer after receiving multiple second valid control signals PG2 through its multiple third input terminals X3, and clear the timer to 0 after the timing duration of the timer reaches the third duration t3, and send a valid enable signal EN3 to the third conversion circuit 63 through its third output terminal Y3. In addition, the power control chip 30 can restart the timer after receiving the third valid control signal PG3 through its fifth input terminal X5, and clear the timer to 0 after the timing duration of the timer reaches the fourth duration t4, and send a valid level power sensing signal to the fifth input terminal Z5 of the light valve control chip 50 through its fourth output terminal Y4. In the embodiment of the present disclosure, the fifth input terminal Z5 of the light valve control chip 50 can also be called a POSENSE pin, which is used to receive a power sensing signal. The voltage of the above-mentioned first valid control signal PG1 to the third valid control signal PG3 can be 3.3V. Reference Figure 2 The power control chip 30 further has a first power terminal Vc1 and a first ground terminal G1.

[0063] refer to Figure 4 The first conversion circuit 61 may include a first conversion chip D1, a first capacitor c1, a second capacitor c2, a third capacitor c3, a fourth capacitor c4, a first resistor R1, a first inductor L1, a fifth capacitor c5, a sixth capacitor c6, a seventh capacitor c7, a second resistor R2, a third resistor R3, and an eighth capacitor c8. The first conversion chip D1 may be a direct current (DC) / DC converter. The first conversion chip D1 has an enable terminal EN, a power normal terminal PG, a second power terminal Vc2, a boost terminal VBST, a switch control terminal SW, and an output feedback terminal FB.

[0064] The enable terminal EN of the first conversion chip D1 is connected to the first output terminal Y1 of the power control chip 30. That is, the enable terminal EN of the first conversion chip D1 serves as an input terminal of the first conversion circuit 61. The power good terminal PG of the first conversion chip D1 is connected to the third input terminal X3 of the power control chip 30 and one end of the first resistor R1, respectively. That is, the power good terminal PG of the first conversion chip D1 serves as an output terminal of the first conversion circuit 61. The other end of the first resistor R1 is connected to the power supply terminal Vd1. The second power supply terminal Vc2 of the first conversion chip D1 is connected to one end of the first capacitor c1, one end of the second capacitor c2, and one end of the third capacitor c3. The other end of the first capacitor c1 is connected to the second ground terminal G2, the other end of the second capacitor c2 is connected to the third ground terminal G3, and the other end of the third capacitor c3 is connected to the fourth ground terminal G4. The boost terminal VBST of the first conversion chip D1 is connected to one end of the fourth capacitor c4. The switch control terminal SW of the first conversion chip D1 is connected to the other end of the fourth capacitor c4 and one end of the first inductor L1, respectively. The other end of the first inductor L1 is respectively connected to one end of the fifth capacitor c5, one end of the sixth capacitor c6, one end of the seventh capacitor c7, one end of the second resistor R2, one end of the eighth capacitor c8 and the second input terminal Z2 of the light valve control chip 50. That is, the other end of the first inductor L1 is the other output end of the first conversion circuit 61. The other end of the fifth capacitor c5, the other end of the sixth capacitor c6 and the other end of the seventh capacitor c7 are all connected to the fifth ground terminal G5. The output feedback terminal FB of the first conversion chip D1 is connected to the other end of the second resistor R2 and one end of the third resistor R3, and the other end of the third resistor R3 is connected to the sixth ground terminal G6. The other end of the eighth capacitor c8 is connected to the seventh ground terminal G7. Reference Figure 4 The first conversion chip D1 further has an eighth ground terminal G8.

[0065] refer to Figure 5Each second conversion circuit 62 may include a second conversion chip D2, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a fourth resistor R4, a second inductor L2, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a fifth resistor R5, a sixth resistor R6, and a sixteenth capacitor C16. The second conversion chip D2 may be a DC / DC converter having an enable terminal EN, a power-good terminal PG, a third power terminal Vc3, a boost terminal VBST, a switch control terminal SW, and an output feedback terminal FB. The enable terminal EN of the second conversion chip D2 is connected to the second output terminal Y2 of the power control chip 30, i.e., the enable terminal EN of the second conversion chip D2 serves as an input terminal of the second conversion circuit 62. The power-good terminal PG of the second conversion chip D2 is connected to the fourth input terminal X4 of the power control chip 30 and one end of the fourth resistor R4, respectively, i.e., the power-good terminal PG of the second conversion chip D2 serves as an output terminal of the second conversion circuit 62. The other end of the fourth resistor is connected to the power supply terminal Vd2. The third power supply terminal Vc3 is connected to one end of a ninth capacitor C9, one end of a tenth capacitor C10, and one end of an eleventh capacitor C11. The other end of the ninth capacitor C9 is connected to a ninth ground terminal G9, the other end of the tenth capacitor C10 is connected to a tenth ground terminal G10, and the other end of the eleventh capacitor C11 is connected to an eleventh ground terminal G11.

[0066] The boost terminal VBST of the second conversion chip D2 is connected to one end of the twelfth capacitor c12, and the switch control terminal SW of the second conversion chip D2 is respectively connected to the other end of the twelfth capacitor c12 and one end of the second inductor L2. The other end of the second inductor L2 is respectively connected to one end of the thirteenth capacitor c13, one end of the fourteenth capacitor c14, one end of the fifteenth capacitor c15, one end of the fifth resistor R5, one end of the sixteenth capacitor c16 and the third input terminal Z3 of the light valve control chip 50. That is, the other end of the second inductor L2 is the other output end of the second conversion circuit 62. The other end of the thirteenth capacitor c13, the other end of the fourteenth capacitor c14 and the other end of the fifteenth capacitor c15 are all connected to the twelfth ground terminal G12. The output feedback terminal FB of the second conversion chip D2 is connected to the other end of the fifth resistor R5 and one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to the thirteenth ground terminal G13, and the other end of the sixteenth capacitor c16 is connected to the fourteenth ground terminal G14. Reference Figure 5 The second conversion chip D2 further has a fifteenth ground terminal G15.

[0067] refer to Figure 6Each third conversion circuit 63 may include a third conversion chip D3, a seventeenth capacitor C17, an eighteenth capacitor C18, a nineteenth capacitor C19, a twentieth capacitor C20, a seventh resistor R7, a third inductor L3, a twenty-first capacitor C21, a twenty-second capacitor C22, a twenty-third capacitor C23, an eighth resistor R8, a ninth resistor R9, and a twenty-fourth capacitor C24. The third conversion chip D3 may be a DC / DC converter having an enable terminal EN, a power-good terminal PG, a third power terminal Vc3, a boost terminal VBST, a switch control terminal SW, and an output feedback terminal FB. The enable terminal EN of the third conversion chip D3 is connected to the third output terminal Y3 of the power control chip 30. That is, the enable terminal EN of the third conversion chip D3 serves as an input terminal of the third conversion circuit 63. The power-good terminal PG of the third conversion chip D3 is connected to the fifth input terminal X5 of the power control chip 30 and one end of the seventh resistor R7, respectively. That is, the power-good terminal PG of the third conversion chip D3 serves as an output terminal of the third conversion circuit 63. The other end of the seventh resistor is connected to the power supply terminal Vd3. The fourth power supply terminal Vc4 is connected to one end of a seventeenth capacitor C17, one end of an eighteenth capacitor C18, and one end of a nineteenth capacitor C19. The other end of the seventeenth capacitor C17 is connected to the sixteenth ground terminal G16, the other end of the eighteenth capacitor C18 is connected to the seventeenth ground terminal G17, and the other end of the nineteenth capacitor C19 is connected to the eighteenth ground terminal G18.

[0068] The boost terminal VBST of the third conversion chip D3 is connected to one end of the twentieth capacitor c20, and the switch control terminal SW of the third conversion chip D3 is respectively connected to the other end of the twentieth capacitor c20 and one end of the third inductor L3. The other end of the third inductor L3 is respectively connected to one end of the twenty-first capacitor c21, one end of the twenty-second capacitor c22, one end of the twenty-third capacitor c23, one end of the eighth resistor R8, one end of the twenty-fourth capacitor c24 and the fourth input terminal Z4 of the light valve control chip 50. That is, the other end of the third inductor L3 is also the other output end of the third conversion circuit 63. The other end of the twenty-first capacitor c21, the other end of the twenty-second capacitor c22 and the other end of the twenty-third capacitor c23 are all connected to the nineteenth ground terminal G19. The output feedback terminal FB of the third conversion chip D3 is connected to the other end of the eighth resistor R8 and one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the twentieth ground terminal G20, and the other end of the twenty-fourth capacitor c24 is connected to the twenty-first ground terminal G21. Reference Figure 6 The third conversion chip D3 also has a twenty-second ground terminal G22. In the disclosed embodiment, the power supply terminals Vd1 to Vd3 are all VDD power supply terminals. The first power supply terminal Vc1 can be a VDD power supply terminal, and the second power supply terminal Vc2 to the fourth power supply terminal Vc4 are all VCC power supply terminals.

[0069] The power good terminals PG of the first to third conversion chips D1 to D3 may all be PWRGOOD pins.

[0070] In the embodiments of the present disclosure, reference Figure 7 , the power circuit 20 may include a power board 21 and a voltage divider circuit 22. The power board 21 is connected to the input ends of the system-level chip 10 and the voltage divider circuit 22 respectively, and the output end of the voltage divider resistor 22 is connected to the reset chip 40. Optionally, the voltage divider circuit 22 may include a voltage divider resistor. The system-level chip 10 may send a power-on instruction to the power board 21 in response to a power-on operation. The power board 21 may send a first voltage to the voltage divider circuit 22 in response to the power-on instruction. The voltage divider circuit 22 reduces the first voltage to a second voltage and transmits it to the reset chip 40, thereby powering on the reset chip 40. After receiving the second voltage, the reset chip 40 sends a power normal signal of a valid level to the power control chip 30 and the light valve control chip 50. For example, the first voltage may be 12V and the second voltage may be 3.3V.

[0071] refer to Figure 7 The power circuit 20 may further include a first power switch SW1, a control terminal of which is connected to the system-on-chip 10. A first terminal of the first power switch SW1 is connected to the power board 21, and a second terminal of the first power switch SW1 is respectively connected to the second power terminal Vc2 of the first conversion chip D1, the third power terminal Vc3 of each second conversion chip D2, and the fourth power terminal Vc4 of the third conversion chip D3.

[0072] The system-level chip 10 can output a valid enable signal to the control end of the first power switch SW1 in response to the power-on operation, so that the first end and the second end of the first power switch SW1 are conductive, thereby controlling the power supply board 21 to supply power to the first conversion chip D1, each second conversion chip D2 and the third conversion chip D3.

[0073] In the disclosed embodiment, the laser projection device may further include a power converter, which may be a DC / DC converter. The power converter is connected to the second end of the first power switch SW1 and the first power supply terminal Vc1 of the power control chip 30, respectively. The power converter is used to convert the first voltage sent by the power board 21 into a target voltage and transmit it to the power control chip 30. For example, the target voltage may be 3.3V. After the first end and the second end of the first power switch SW1 are conductive, the power board 21 can also supply power to the power control chip 30.

[0074] refer to Figure 2 and Figure 7The laser projection device may further include a light valve 70 connected to the light valve control chip 50. The light valve control chip 50 is further connected to the sixth input terminal X6 of the power control chip 30. The light valve control chip 50 is configured to control the light valve 70 to power on after power is applied, and to send a power-on success signal to the sixth input terminal X6 of the power control chip 30 after the light valve 70 is successfully powered on. The power-on success signal is configured to indicate that the light valve 70 has been successfully powered on. The power-on success signal may be a high-level signal.

[0075] refer to Figure 7 The laser projection device may further include a light valve power supply chip 80 connected to the power supply circuit 20, the light valve control chip 50, and the light valve 70, respectively. The system-on-chip 10 may also control the power supply circuit 20 to supply power to the light valve power supply chip 80 in response to a power-on operation. After powering on, the light valve control chip 50 may send a valid enable signal to the light valve power supply chip 80, which may then supply power to the light valve 70 under the control of the valid enable signal. The second end of the first power switch SW1 is also connected to the light valve power supply chip 80. After the first and second ends of the first power switch SW1 are conductively connected, the power board 21 may also supply power to the light valve power supply chip 80.

[0076] In the disclosed embodiment, the light valve power supply chip 80 can sequentially send multiple valid power signals, a voltage bias (VBIAS) signal, a voltage reset (VRST) signal, and a voltage offset (VOFS) signal to the light valve 70, thereby powering up the light valve. The voltages of the multiple valid power signals, the voltage bias signal, the voltage reset signal, and the voltage offset signal are different. For example, the number of the multiple valid power signals can be two, and the voltages of the two valid power signals can be 1.15V and 1.8V, respectively. The voltage of the voltage bias signal can be 18V, the voltage of the voltage reset signal can be -14V, and the voltage of the voltage offset signal can be 10V.

[0077] refer to Figure 7 The laser projection device may further include a socket Q, which is connected to the light valve power supply chip 80 and the light valve 70, and the socket Q is located on the display panel 200. The light valve power supply chip 80 can sequentially send multiple effective power signals, voltage bias signals, voltage reset signals, and voltage compensation signals to the light valve 70 through the socket Q.

[0078] After sending a valid enable signal to the light valve power supply chip 80 for a preset duration, the light valve control chip 50 can send a communication signal to the light valve 70. If the light valve control chip 50 receives a response signal from the light valve 70, it can determine that the light valve has been successfully powered on. The light valve control chip 50 can then send a power-on success signal to the sixth input terminal X6 of the power control chip 30. If the light valve control chip 50 does not receive a response signal from the light valve 70, it can determine that the light valve 70 has failed to power on. The light valve control chip 50 can then send a power-on failure signal to the sixth input terminal X6 of the power control chip 30. If the power control chip 30 detects the power-on failure signal output by the light valve control chip 50 via the sixth input terminal X6, it can re-execute the power-on process, such as by controlling the power conversion circuit 60 to sequentially send multiple valid power signals to the light valve control chip 50 and a power sensing signal of a valid level to the light valve control chip 50, thereby controlling the light valve control chip 50 to power on again. The power-on failure signal indicates that the light valve 70 has failed to power on. Optionally, the power control chip 30 may again send a valid enable signal to the first conversion circuit 61 in response to the power-on signal and the power-normal signal of the valid level.

[0079] refer to Figure 8 The control method of the laser projection device in the embodiment of the present disclosure may include the following steps:

[0080] Step 801: In response to a power-on operation, the system-level chip controls the power supply circuit to supply power to the reset chip and sends a power-on signal to the power control chip.

[0081] Step 802: After being powered on, the reset chip sends a power-normal signal of a valid level to the power control chip and the light valve control chip respectively.

[0082] Step 803: The power control chip responds to the power-on signal and the power normal signal, controls the power conversion circuit to sequentially send multiple valid power signals to the light valve control chip, and sends a power sensing signal of a valid level to the light valve control chip to control the light valve control chip to power on.

[0083] In summary, the embodiments of the present disclosure provide a control method for a laser projection device. Since the light valve control chip can be powered on by a power control chip and a power conversion circuit, the circuit for controlling the power on of the light valve control chip is simplified, the integration of the internal devices of the laser projection device is improved, and the cost is reduced.

[0084] refer to Figure 9 The control method of the laser projection device in the embodiment of the present disclosure may include the following steps:

[0085] Step 901: In response to a power-on operation, the system-on-chip controls the power supply circuit to supply power to the reset chip and sends a power-on signal to the power control chip.

[0086] Step 902: After receiving the power-on signal and the power-normal signal for a first duration, the power control chip sends a valid enable signal to the first conversion circuit.

[0087] Step 903: In response to the valid enable signal, the first conversion circuit sends a first valid power signal to the light valve control chip and sends a first valid control signal to the power control chip.

[0088] Step 904 : After receiving the second duration of the first valid control signal, the power control chip sends a valid enable signal to each second conversion circuit.

[0089] Step 905 : Each second conversion circuit sends a second valid power signal to the corresponding third input terminal and sends a second valid control signal to the corresponding fourth input terminal in response to the valid enable signal.

[0090] Step 906: After receiving the third duration of the plurality of second valid control signals, the power control chip sends a valid enable signal to the third conversion circuit.

[0091] Step 907 : The third conversion circuit sends a third valid power signal to the light valve control chip and sends a third valid control signal to the power control chip in response to the valid enable signal.

[0092] Step 908 : After receiving the third effective control signal for a fourth duration, the power control chip sends a power sensing signal of an effective level to the light valve control chip.

[0093] Step 909 : After power-on, the light valve control chip controls the light valve to power on, and sends a power-on success signal to the sixth input terminal of the power control chip after the light valve is powered on successfully.

[0094] Step 910: If the power control chip detects a power-on failure signal output by the light valve control chip through the sixth input terminal, the power control chip re-executes the power-on process.

[0095] In the embodiment of the present disclosure, the specific implementation process of the above steps 801 to 803 and steps 901 to 910 can refer to the above device embodiment, and the embodiment of the present disclosure will not be repeated here.

[0096] In summary, the embodiments of the present disclosure provide a control method for a laser projection device. Since the light valve control chip can be powered on by a power control chip and a power conversion circuit, the circuit for controlling the power on of the light valve control chip is simplified, the integration of the internal devices of the laser projection device is improved, and the cost is reduced.

[0097] Laser projection equipment typically includes a system-on-chip (SoC), a reset chip R, a power supply circuit, multiple timing control chips, multiple logic devices, a power conversion circuit, and a light valve control chip. In response to a power-on operation, the SoC controls the power supply circuit to supply power to the reset chip. The reset chip then controls the multiple timing control chips, multiple logic devices, and the power conversion circuit to sequentially transmit a valid power-good signal, multiple valid power signals, and a valid power-sensing signal to the light valve control chip, thereby controlling the light valve control chip to power on. However, the circuitry required to control the light valve control chip's power-on operation through multiple timing control chips, multiple logic devices, and the power conversion circuit results in a relatively complex circuit.

[0098] Among them, reference Figure 10 , the plurality of timing control chips may include a first timing control chip LM1 and a second timing control chip LM2. For example, the first timing control chip LM1 and the second timing control chip LM2 may both be LM3880 chips. In the embodiment of the present disclosure, the power control chip may be integrated with Figure 10 The multiple timing control chips and multiple logic devices shown are shown. The multiple logic devices may include a first logic AND device N1, a second logic AND device N2, a third logic AND device N3, a fourth logic AND device N4, a fifth logic AND device N5, a sixth logic AND device N6, a seventh logic AND device N7, an eighth logic AND device N8, a first logic OR device K1, a second logic OR device K2, a first logic NOT device F1, and a second logic NOT device F2. A system-on-chip (SoC) is connected to the first input terminal of the first logic AND device N1, and a reset chip is connected to the power supply circuit, the second input terminal of the first logic AND device N1, and the light valve control chip. In response to a power-on operation, the SoC controls the power supply circuit to supply power to the reset chip and sends a power-on signal to the first logic AND device. The reset chip R1 is used to send a valid power-good signal to the first logic AND device N1 after power-on.

[0099] The output of the first logic AND device N1 is connected to the first input of the first logic OR device K1, the first input of the second logic AND device N2, and the input of the first logic NOT device F1. The first logic AND device N1 is configured to output high-level signals to the first input of the first logic OR device K1, the first input of the second logic AND device N2, and the first logic NOT device F1. The output of the first logic OR device K1 is connected to the enable terminal of the first timing control chip LM1, which is configured to output a valid enable signal to the enable terminal of the first timing control chip LM1. The first output F11 of the first timing control chip LM1 is connected to the input of the first conversion circuit. The second output F12 of the first timing control chip LM1 is connected to the second input of the second logic AND device N2 and the first input of the third logic AND device N3. The third output F13 of the first timing control chip LM1 is connected to the first input of the fourth logic AND device N4.

[0100] refer to Figure 12 After receiving the valid enable signal En1 for a first target duration T1, the first timing control chip LM1 outputs the valid enable signal En2 to the input of the first conversion circuit 61 via the first output terminal F11. After receiving the valid enable signal En1 for a second target duration T2, the first timing control chip LM1 outputs the high-level signal F1 to the second input of the second logic AND device N2 and the first input of the third logic AND device N3 via the second output terminal F12. After receiving the valid enable signal En1 for a third target duration T3, the first timing control chip LM1 outputs the high-level signal F2 to the first input of the fourth logic AND device N4 via the third output terminal F13. For example, the first target duration can be 10ms, the second target duration can be 20ms, and the third target duration can be 30ms.

[0101] The output of the first conversion circuit 61 is connected to the light valve control chip and the second input of the third logic AND device N3, respectively. The output of the third logic AND device N3 is connected to the input of the first second conversion circuit 62 and the input of the second second conversion circuit. The output of the first second conversion circuit 62 is connected to the first input of the fifth logic AND device N5, and the output of the second second conversion circuit 62 is connected to the second input of the fifth logic AND device N5. In response to a received valid enable signal, the first conversion circuit 61 is configured to output a first valid power signal to the light valve control chip and a first valid control signal PG1 to the first input of the third logic AND device N3.

[0102] The third logic AND device N3 is configured to output valid enable signals to the first and second second conversion circuits 62 and 62, respectively. In response to the received valid enable signal, the first second conversion circuit 62 is configured to output the second valid power supply signal PWR2 to the light valve control chip and the second valid control signal PG2 to the first input terminal of the fifth logic AND device N5. In response to the received valid enable signal, the second second conversion circuit 62 is configured to output the second valid control signal PG2 to the second input terminal of the fifth logic AND device N5. The output terminal of the fifth logic AND device N5 is connected to the second input terminal of the fourth logic AND device N4, which is configured to output a high-level signal to the second input terminal of the fourth logic AND device N4. The output terminal of the fourth logic AND device N4 is connected to the fourth input terminal of the third conversion circuit, which is configured to output the valid enable signal to the third conversion circuit. The output terminal of the third conversion circuit is connected to the first input terminal of the sixth logic AND device N6, which is configured to output the third valid control signal PG3 to the first input terminal of the sixth logic AND device N6 in response to the received valid enable signal.

[0103] The second timing control chip LM2 has an enable terminal EN, a first output terminal F21, a first output terminal F22, and a third output terminal F23. The output terminal of the second logic AND device N2 is connected to the enable terminal EN of the second timing control chip LM2. The second logic AND device N2 is configured to output a high-level signal to the enable terminal EN of the second timing control chip LM2. The first output terminal F21 of the second timing control chip LM2 is connected to the first input terminal of the seventh logic AND device N7, and the third output terminal F23 of the second timing control chip LM2 is connected to the first input terminal of the eighth logic AND device N8. The second timing control chip LM2 is configured to output high-level signals through its first output terminal F21 and second output terminal F22, and to output a high-level signal to the first input terminal of the eighth logic AND device N8 through its third output terminal F23. When the second timing control chip LM2 outputs a high-level signal to the first input terminal of the seventh logic AND device N7, the duration during which the first timing control chip LM1 receives the valid enable signal En1 is equal to the fourth target duration. For example, the fourth target duration can be 30ms. When the second output terminal F22 of the second timing control chip LM2 outputs a high-level signal, the duration during which the first timing control chip LM1 receives the valid enable signal En1 is the fifth target duration. For example, the fifth target duration can be 40ms. When the second timing control chip LM2 outputs a high-level signal to the first input terminal of the eighth logic AND device N8 through its third output terminal F23, the duration during which the first timing control chip LM1 receives the valid enable signal En1 is the sixth target duration. For example, the sixth target duration is 50ms.

[0104] The second input terminal of the seventh logical AND device N7 is connected to the output terminal of the first logical NOT device F1, and the second input terminal of the seventh logical AND device N7 is used to receive the low-level signal output by the first logical NOT device F1. The second input terminal of the eighth logical AND device N8 is connected to the output terminal of the second logical NOT device F2, and the input terminal of the second logical NOT device F2 is connected to the output terminal of the first logical NOT device F1. The second input terminal of the eighth logical AND device N8 is used to receive the high-level signal output by the second logical NOT device F2. The output terminal of the seventh logical AND device N7 is connected to the first input terminal of the second logical OR device K2, and the output terminal of the eighth logical AND device N8 is connected to the second input terminal of the second logical OR device K2. The output terminal of the second logical OR device K2 is connected to the second input terminal of the sixth logical AND device N6, and the output terminal of the sixth logical AND device N6 is connected to the light valve control chip. The seventh logic AND device N7 is used to output a low-level signal to the first input terminal of the second logic OR device K2, the eighth logic AND device N8 is used to output a high-level signal to the second input terminal of the second logic OR device K2, and the second logic OR device K2 is used to output a high-level signal to the second input terminal of the sixth logic AND device N6.

[0105] The sixth logic AND device N6 is used to output a valid level power sensing signal to the light valve control chip after receiving the third valid control signal PG4 output by the fourth conversion circuit at its first input terminal and receiving the high level signal output to the second logic OR device K2 at its second input terminal.

[0106] refer to Figure 11 , Figure 10 The power-on process of the light valve control chip controlled by the circuit shown may include the following steps:

[0107] Step 1001: In response to a power-on operation, the system-level chip controls the power supply circuit to supply power to the reset chip R1 and outputs a power-on signal to the first logic AND device N1, so that the reset chip R1 outputs a valid power-good signal to the first logic AND device N1 after power-on.

[0108] Step 1002: The first logic AND device N1 outputs a high level signal to the first logic OR device K1, the first input terminal of the second logic AND device N2, and the first logic NOT device F1, so that the first logic OR device K1 outputs a valid enable signal to the enable terminal of the first timing control chip LM1.

[0109] Step 1003: After the first target time, the first timing control chip LM1 outputs a valid enable signal to the first conversion circuit to enable the first conversion circuit to output a first valid power signal to the light valve control chip and output a first valid control signal to the third logic AND device N3.

[0110] Step 1004 : The first timing control chip LM1 outputs a high level signal to the second logic AND device N2 and the third logic AND device N3 after the second target time.

[0111] Step 1005: The third logic AND device N3 outputs a valid enable signal to each second conversion circuit to enable each second conversion circuit to output a second valid power signal to the light valve control chip, and enables each second conversion circuit to output a second valid control signal to the fifth logic AND device N5.

[0112] Step 1006: The fifth logic AND device N5 outputs a high level signal to the fourth logic AND device N4.

[0113] Step 1007 : The first timing control chip LM1 outputs a high level signal to the fourth logic AND device N4 after the third target time.

[0114] Step 1008: The fourth logic AND device N4 outputs a valid enable signal to the third conversion circuit, so as to enable the third conversion circuit to output a third valid control signal to the sixth logic AND device N6.

[0115] Step 1009: The second logic AND device N2 outputs a high level signal to the enable terminal of the second timing control chip LM2, so as to enable the second timing control chip LM2 to output a high level signal to the seventh logic AND device N7 and to output a high level signal to the eighth logic AND device N8.

[0116] In step 1010 , the seventh logic AND device N7 and the eighth logic AND device N8 both output high-level signals to the second logic OR device K2 .

[0117] Step 1011: The second logic OR device K2 outputs a high level signal to the sixth logic AND device N6, so that the sixth logic AND device N6 outputs a valid level power sensing signal to the light valve control chip after receiving the third valid control signal and the high level signal.

[0118] The following describes the process of powering off the light valve control chip 50:

[0119] In the disclosed embodiment, the system-on-chip 10 is configured to, in response to a standby operation, control the power supply circuit 20 to stop supplying power to the reset chip 40 and send a standby signal to the power control chip 30. The standby operation may be a selection of a standby button or a power-off button. The standby button and power-off button may be located on the laser projection device or on a remote control for controlling the laser projection device. The standby signal may be a low-level signal.

[0120] In an embodiment of the present disclosure, the system-on-chip 10 can, in response to a standby operation, send a standby command to the power board 21. In response to the standby command, the power board 21 can send a third voltage to the voltage divider circuit 22. The voltage divider circuit 22 reduces the third voltage to a fourth voltage and transmits it to the reset chip 40. The reset chip 40 powers down after receiving the fourth voltage. The third voltage is lower than the first voltage, and the fourth voltage is lower than the second voltage. For example, the third voltage can be 9V.

[0121] The power control chip 30 is configured to receive an invalid-level power-normal signal output by the reset chip 40 through the second input terminal X2 after the reset chip 40 is powered off. In response to the standby signal and the invalid-level power-normal signal, the power control chip 30 sends an invalid-level power sensing signal to the light valve control chip 50, and controls the power conversion circuit 60 to sequentially send multiple invalid-level power signals to the light valve control chip 50 to control the light valve control chip 50 to power off. The invalid level refers to a low level. The invalid-level power-normal signal and the invalid-level power sensing signal can both be low-level signals. The multiple invalid power signals can be low-level power signals. For example, the voltages of the invalid-level power-normal signal, the invalid-level power sensing signal, and the multiple invalid power signals can all be 0V.

[0122] After the SoC 10 controls the power supply circuit 20 to stop supplying power to the reset chip 40, the reset pin of the reset chip 40 is automatically pulled low. At this point, the reset chip 40 outputs a power-good signal at an inactive level to both the second input terminal of the power control chip 30 and the first input terminal Z1 of the light valve control chip 50. In response to the standby signal and the inactive power-good signal, the power control chip 30 transmits a power-sensing signal at an inactive level to the light valve control chip 50. Subsequently, the power control chip 30 controls the power conversion circuit 60 to sequentially transmit multiple power signals at inactive levels to the light valve control chip 50, thereby powering down the light valve control chip 50.

[0123] In summary, the embodiments of the present disclosure provide a laser projection device in which a system-on-chip (SoC) can, in response to a standby operation, control a power supply circuit to stop supplying power to a reset chip and send a standby signal to a power control chip. Furthermore, the power control chip can, in response to the standby signal and an invalid power-normal signal output by the reset chip after powering off, send an invalid power sensing signal to the light valve control chip, and control the power conversion circuit to sequentially send multiple invalid power signals to the light valve control chip to control powering off the light valve control chip. Because powering off the light valve control chip can be controlled by a single power control chip and a single power conversion circuit, compared to related technologies, the circuitry for controlling powering off the light valve control chip is simplified, improving the integration of components within the laser projection device and reducing costs.

[0124] As laser projection devices develop towards miniaturization and lower costs, optical engines must also be designed to be miniaturized. Internal boards and cards, in conjunction with these miniaturized optical engines, are also being designed to be compact and cost-effective. The laser projection device provided by the disclosed embodiments utilizes a single power control chip and a power conversion circuit to power on and off the light valve control chip, resulting in lower costs and a higher degree of integration.

[0125] refer to Figure 13 and Figure 14 The power control chip 30 is configured to send an inactive power sensing signal to the light valve control chip 50 after receiving the standby signal and the power normal signal for a fifth time period t5, and to send an inactive enable signal to the power conversion circuit 60 after receiving the standby signal and the power normal signal for a sixth time period t6. The power conversion circuit 60 is configured to sequentially send multiple inactive power signals to the light valve control chip 50 in response to the inactive enable signal.

[0126] The sixth time duration t6 is greater than the fifth time duration t6, and both the fifth time duration t5 and the sixth time duration t6 can be fixed time durations pre-stored in the power control chip 30. For example, the fifth time duration t5 can be 30ms, and the sixth time duration t6 can be 40ms. The invalid enable signal can be a low level signal.

[0127] Table 2 shows the signals to be received and output by the power control chip 30 during the process of controlling the light valve control chip 50 to power off. The first invalid control signal to the third invalid control signal can all be low level signals, and the multiple invalid power signals can include the first invalid power signal pwr1 to the third invalid power signal pwr3. Figure 13 and Figure 14 After receiving the power-on signal and the power normal signal, the power control chip 30 can start the timer, and after the timer reaches the fifth time period t5, send an invalid level power sensing signal to the fourth input terminal Z4 of the light valve control chip 50 through its fourth output terminal Y4.

[0128] Table 2

[0129]

[0130] In the disclosed embodiment, the power control chip 30 is configured to send an invalid enable signal en1 to the third conversion circuit 63 after receiving the standby signal and the power normal signal for a sixth duration t6. In response to the received invalid enable signal en1, the third conversion circuit 63 is configured to send a first invalid control signal pg1 to the fifth input terminal X5 of the power control chip 30 and a first invalid power signal pwr1 to the light valve control chip 50. Optionally, after receiving the standby signal and the power normal signal at an invalid level, if the timer has reached the sixth duration, the power control chip 30 resets the timer and sends the invalid enable signal en1 to the third conversion circuit 63 via its third output terminal Y3.

[0131] The power control chip 30 is configured to send a disable enable signal en2 to each second conversion circuit 62 after receiving the first disable control signal pg1 at its fifth input terminal X5 for a seventh duration t7. In response to the received disable enable signal en2, each second conversion circuit 62 is configured to send a second disable power signal pwr2 to the corresponding third input terminal Z3 and a second disable control signal pg2 to the corresponding fourth input terminal X4. The seventh duration t7 may be a fixed duration pre-stored in the power control chip 30. For example, the seventh duration may be 10 ms.

[0132] Optionally, after receiving the first invalid control signal pg1, the power control chip 30 may restart the timer, and after the timer reaches the seventh time duration t7, reset the timer to 0, send a second invalid power signal pg2 to the corresponding third input terminal Z3, and send a second invalid control signal pg2 to the corresponding fourth input terminal X4. For example, if the power control chip 30 can have two fourth input terminals X4, the multiple second conversion circuits 62 can include a first second conversion circuit 62 and a second second conversion circuit 62.

[0133] After receiving the first invalid control signal pg1, the fifth input terminal X5 of the power control chip 30 can restart the timer. After the timer reaches the seventh time period t7, the timer can be reset to 0 and an invalid enable signal en2 can be sent to the first second conversion circuit 62 and the second second conversion circuit 62. In response to the received invalid enable signal en2, the first second conversion circuit 62 is configured to send a second invalid power signal pwr2 to a third input terminal Z3 of the light valve control chip 50 and a second invalid control signal pg2 to a fourth input terminal X4 of the power control chip 30.

[0134] The second second conversion circuit 62 is used to send a second invalid power signal pwr2 to another third input terminal Z3 of the light valve control chip 50 and send a second invalid control signal pg2 to another fourth input terminal X4 of the power control chip 30 in response to the received invalid enable signal en2.

[0135] The power control chip 30 is configured to send an invalid enable signal en3 to the first conversion circuit 61 after receiving multiple second invalid control signals pg2 at its fourth input terminal X4 for an eighth time duration t8. In response to the invalid enable signal en3, the first conversion circuit 61 is configured to send a third invalid control signal pg3 to the third input terminal X3 of the power control chip 30 and a third invalid power signal pwr3 to the second input terminal Z2 of the light valve control chip 50, thereby controlling the light valve control chip 50 to power off. The eighth time duration t8 may be a fixed time duration pre-stored in the power control chip 30. For example, the eighth time duration t8 may be 10 ms. Optionally, after receiving multiple second invalid control signals pg2 at its fourth input terminal X4, the power control chip 30 may restart a timer. After the timer reaches the eighth time duration, the power control chip 30 sends the invalid enable signal en3 to the first conversion circuit 61 via its first output terminal Y1. The voltages of the first to third invalid control signals pg1 to pg3 may all be 0V. In the embodiment of the present disclosure, the light valve control chip 50 is configured to control the light valve 70 to power off after receiving a power-good signal of an invalid level.

[0136] Optionally, the light valve 70 may be a digital micromirror device (DMD), which integrates multiple lenses, each lens corresponding to a pixel in the projected image. The states of the lenses in the DMD are different, so that light from different pixels can be projected to different positions, thereby realizing the display of the projected image. Figure 15 Each lens can be in an open or closed state, with each lens having different deflection angles in these two states. In the open state, each lens projects light from the corresponding pixel onto the projection screen. In the closed state, each lens does not project light from the corresponding pixel onto the projection screen. The light valve control chip 50 controls each lens to be in an open or closed state to display the projected image 02 on the projection screen.

[0137] After receiving the power-normal signal of the invalid level, the light valve control chip 50 first controls the multiple lenses on the light valve 70 to be in a static state, that is, stops controlling the multiple lenses to flip (at this time, the projected image displayed on the projection screen will remain unchanged), so that the multiple lenses remain in their current state. This prevents collisions between adjacent lenses and avoids mechanical damage to the mirror surfaces of the two adjacent lenses. Figure 15 Each lens can be in an open or closed state when in a static state. It is understood that before the fifth input terminal Z5 of the light valve control chip 50 receives the power sensing signal of an invalid level, the signal received by the fifth input terminal Z5 of the light valve control chip 50 is a power sensing signal of a valid level.

[0138] The light valve control chip 50 controls the multiple lenses to be in a static state and does not receive an invalid power sensing signal before referring to Figure 16 The light valve control chip 50 can control the multiple lenses to be in an initial state. In this initial state, the light valve 70 no longer projects a projection image onto the projection screen. The light valve control chip 50 then controls the light valve to be powered off. Optionally, the light valve control chip 50 can send an invalid enable signal to the light valve power supply chip 80. Under the control of this invalid enable signal, the light valve power supply chip 80 can stop supplying power to the light valve 70, thereby powering off the light valve 70.

[0139] After receiving the third invalid control signal pg3 from the first conversion circuit 61, the power control chip 30 can determine that the light valve control chip 50 has been successfully powered off if it receives a low-level signal from the light valve control chip 50 through its sixth input terminal X6 after a specified time period. The specified time period can be a fixed time period pre-stored in the power control chip 30.

[0140] After determining that the light valve control chip 50 has been successfully powered off, the power control chip 30 can send an indication signal to the system-on-chip 10, indicating that the light valve control chip 50 has been successfully powered off. In response to this indication signal, the system-on-chip 10 can output a deactivation signal to the control terminal of the first power switch SW1, thereby disconnecting the first terminal from the second terminal of the first power switch SW1. This causes the power board 21 to stop supplying power to the first conversion chip D1, each second conversion chip D2, the third conversion chip D3, the light valve power supply chip 80, and the power control chip 30. It should be understood that when the voltage sent by the power board 21 is 9V, the voltage provided by the power converter to the power control chip can still be 3.3V.

[0141] refer to Figure 17 The control method of the laser projection device in the embodiment of the present disclosure may include the following steps:

[0142] Step 1701 : In response to a standby operation, the system-on-chip controls the power supply circuit to stop supplying power to the reset chip and sends a standby signal to the power control chip.

[0143] Step 1702: After the reset chip is powered off, the power control chip receives the power normal signal of an invalid level output by the reset chip through the second input terminal; in response to the standby signal and the power normal signal, sends the power sensing signal of an invalid level to the light valve control chip; and controls the power conversion circuit to send multiple power signals of invalid levels to the light valve control chip in sequence to control the light valve control chip to power off.

[0144] To sum up, the embodiments of the present disclosure provide a control method for a laser projection device. Since the light valve control chip can be powered off by a power control chip and a power conversion circuit, compared with related technologies, the circuit for controlling the power off of the light valve control chip is simplified, the integration of internal devices of the laser projection device is improved, the cost is reduced, and the flexibility is higher.

[0145] refer to Figure 18 The control method of the laser projection device in the embodiment of the present disclosure may include the following steps:

[0146] Step 1801 : In response to a standby operation, the system-on-chip controls the power supply circuit to stop supplying power to the reset chip and sends a standby signal to the power control chip.

[0147] Step 1802: After the reset chip is powered off, the power control chip sends an invalid power sensing signal to the light valve control chip after receiving the invalid power normal signal and standby signal output by the reset chip for a fifth time period.

[0148] Step 1803: After the reset chip is powered off, the power control chip sends an invalid enable signal to the third conversion circuit after receiving the power normal signal and the standby signal of the invalid level output by the reset chip for a sixth time period.

[0149] Step 1804 : In response to the received invalid enable signal, the third conversion circuit sends a first invalid control signal to the power control chip and sends a first invalid power signal to the light valve control chip.

[0150] Step 1805: After receiving the first invalid control signal for a seventh time period, the power control chip sends an invalid enable signal to each second conversion circuit.

[0151] Step 1806 : Each second conversion circuit sends a second invalid power signal to the corresponding third input terminal and sends a second invalid control signal to the corresponding fourth input terminal in response to the received invalid enable signal.

[0152] Step 1807: After receiving multiple second invalid control signals for an eighth time period, the power control chip sends an invalid enable signal to the first conversion circuit.

[0153] Step 1808 : The first conversion circuit is configured to send a third invalid control signal to the power control chip in response to the invalid enable signal, and send a third invalid power signal to the light valve control chip to control the light valve control chip to power off.

[0154] In the embodiment of the present disclosure, the specific implementation process of the above steps 1701, 1702, and steps 1801 to 1808 can refer to the above device embodiment, and the embodiment of the present disclosure will not be repeated here.

[0155] In summary, the embodiments of the present disclosure provide a control method for a laser projection device. Since the light valve control chip can be powered off by a power control chip and a power conversion circuit, compared with related technologies, the circuit for controlling the power off of the light valve control chip is simplified, the integration of internal devices of the laser projection device is improved, and the cost is reduced.

[0156] refer to Figure 19 , Figure 10 The power-off process of the light valve control chip 50 controlled by the circuit shown may include the following steps:

[0157] Step 1901: In response to the standby operation, the system-level chip controls the power circuit to stop supplying power to the reset chip R1 and sends a standby signal to the first logic AND device N1, so that the reset chip R1 outputs an invalid power normal signal to the first logic AND device N1 after power off.

[0158] The system-level chip can respond to the standby operation by sending a standby signal to the first input terminal of the first logic AND device N1, so that the reset chip R1 outputs an invalid level power good signal to the second input terminal of the first logic AND device N1 after power off.

[0159] Step 1902: The first logic AND device N1 outputs a low-level signal to the first logic OR device K1, the second logic AND device N2, and the first logic NOT device F1, so that the second logic AND device N2 outputs a low-level signal to the enable terminal of the second timing control chip LM2, and the first logic NOT device F1 outputs a high-level signal to the seventh logic AND device N7.

[0160] The first logic AND device N1 outputs a low-level signal to the first input terminal of the first logic OR device K1, the first input terminal of the second logic AND device N2, and the input terminal of the first logic NOT device F1. The second logic AND device N2 outputs a low-level signal to the enable terminal of the second timing control chip LM2, and the first logic NOT device F1 outputs a high-level signal to the second input terminal of the seventh logic AND device N7.

[0161] Step 1903: The second timing control chip LM2 outputs a low level signal to the eighth logic AND device N8 after the seventh target time, and outputs a low level signal to the seventh logic AND device N7 after the ninth target time.

[0162] After the second timing control chip LM2 receives a low-level signal at its enable terminal for a seventh target duration, it outputs a low-level signal to the first input terminal of the eighth logic AND device N8 through its third output terminal F23. After the second timing control chip LM2 receives a low-level signal at its enable terminal for an eighth target duration, it outputs a low-level signal through its second output terminal F22. After the second timing control chip LM2 receives a low-level signal at its enable terminal for a ninth target duration, it outputs a low-level signal to the first input terminal of the seventh logic AND device N7. Furthermore, after receiving a high-level signal from the first logic NOT device F1, the second logic NOT device K2 outputs a low-level signal to the eighth logic AND device N8.

[0163] Step 1904: The seventh logic AND device N7 outputs a low-level signal to the second logic OR device K2.

[0164] After receiving the low-level signal output by the second timing control chip LM2 , the seventh logic AND device N7 outputs a low-level signal to the first input terminal of the second logic OR device K2 .

[0165] Step 1905: The eighth logic AND device N8 outputs a low-level signal to the second logic OR device K2.

[0166] After receiving the low level signal output by the second timing control chip LM2 or the low level signal output by the second logic NOT device K2, the eighth logic AND device N8 outputs a low level signal to the second input terminal of the second logic OR device K2.

[0167] Step 1906: The second logic OR device K2 outputs a low level signal to the sixth logic AND device N6.

[0168] After receiving the low-level signals output by the seventh and eighth logic AND devices N7 and N8 , the second logic OR device K2 outputs a low-level signal to the second input terminal of the sixth logic AND device N6 .

[0169] Step 1907: The sixth logic AND device N6 outputs a power-good signal of an invalid level to the first logic OR device K1 and the light valve control chip respectively.

[0170] After receiving the low level signal, the sixth logic AND device N6 outputs an invalid level power normal signal to the second terminal of the first logic OR device K1 and the light valve control chip 50, so that the first logic OR device K1 outputs a low level signal to the enable terminal EN of the first timing control chip LM1.

[0171] Step 1908: The first logic OR device K1 outputs a low-level signal to the enable terminal EN of the first timing control chip LM1, so as to enable the first timing control chip LM1 to output a low-level signal to the fourth logic AND device N4.

[0172] After receiving the power normal signal of the invalid level output by the sixth logic AND device N6 and the low level signal output by the first logic AND device N1, the first logic OR device K1 outputs a low level signal En3 to the enable end of the first timing control chip LM1 to enable the first timing control chip LM1 to output a low level signal f1 to the fourth logic AND device N4 through its third output end F13.

[0173] It is understandable that when the first timing control chip LM1 outputs a low level signal to the fourth logic AND device N4, the duration for the enable terminal of the second timing control chip LM2 to receive the low level signal is the tenth target duration T10. For example, the tenth target duration may be 40ms. Figure 12 The time from when the enable terminal of the first timing control chip LM1 receives the low level signal En3 to when the enable terminal outputs the low level signal to the fourth logic AND device N4 may be 10ms.

[0174] Step 1909: The fourth logic AND device N4 outputs a first invalid control signal to the third power conversion circuit to enable the first conversion circuit to output a first invalid power signal to the light valve control chip and output a first invalid control signal to the sixth logic AND device N6.

[0175] The fourth logic AND device N4 outputs a first invalid control signal to the input terminal of the third power conversion circuit to enable the first conversion circuit to output a first invalid power signal pwr1 to the light valve control chip and output a first invalid control signal pg1 to the first input terminal of the sixth logic AND device N6.

[0176] Step 1910: The first timing control chip LM1 outputs low-level signals to the third logic AND device N3 and the second logic AND device N2 respectively.

[0177] refer to Figure 20, the first timing control chip LM1 outputs a low-level signal to the first input terminal of the third logic AND device N3 and the second input terminal of the second logic AND device N2, respectively. When the first timing control chip LM1 outputs the low-level signal f2 to the third logic AND device N3 and the second logic AND device N2, respectively, the duration during which the enable terminal EN of the second timing control chip LM2 receives the low-level signal is the eleventh target duration T11. For example, the eleventh target duration can be 50 ms.

[0178] refer to Figure 12 The time length from the first timing control chip LM1 outputting a low-level signal to the fourth logic AND device N4 to the time length from the first timing control chip LM1 outputting a low-level signal f2 to the third logic AND device N3 and the second logic AND device N2 can be 10ms.

[0179] Step 1911: The third logic AND device N3 outputs an invalid enable signal to each second conversion circuit to enable each conversion circuit to output a second invalid control signal to the fifth logic AND device N5 and enable each conversion circuit to output a second invalid power signal to the light valve control chip.

[0180] The third logic AND device N3 outputs an invalid enable signal to the first second conversion circuit. In response to the invalid enable signal, the first second conversion circuit outputs a second invalid control signal to an input terminal of the fifth logic AND device N5 and outputs a second invalid power supply signal to the light valve control chip.

[0181] Step 1912: The first timing control chip LM1 outputs an invalid enable signal to the first conversion circuit to enable the first conversion circuit to output a third invalid power signal to the light valve control chip.

[0182] The first timing control chip LM1 can output a third invalid control signal pg3 to the second input terminal of the fourth logic AND device N4, and output an invalid enable signal En4 to the enable terminal EN of the first conversion circuit, so as to enable the first conversion circuit to output a third invalid power signal pwr3 to the light valve control chip 50. When the first timing control chip LM1 outputs a low-level signal to the first conversion circuit, the duration for which the enable terminal EN of the second timing control chip LM2 receives the low-level signal is the twelfth target duration T12. For example, the twelfth target duration can be 60ms. Figure 12 The time from the first timing control chip LM1 outputting the low level signal f2 to the third logic AND device N3 and the second logic AND device N2 to outputting the low level signal En4 to the enable terminal EN of the first conversion circuit 61 may be 10ms.

[0183] refer to Figure 7, the laser projection device may further include a fan module 90, a switch module 91, a temperature detection module 92, a human eye protection component 93, a light source driving component 94, a light source 95 and a second power switch SW2. If the light source 95 is a three-color laser light source, that is, the light source 95 can emit three different colors of laser beams, then the laser projection device may further include a diffusion wheel 96 connected to the system-level chip 10. Among them, the fan module 90, the temperature detection module 92, the human eye protection component 93 and the diffusion wheel 96 are all located on the periphery of the mainboard 100, and are not located on the display panel 200, and the light source driving component 94 is located on the display panel 200. The system-level chip 10 is respectively connected to the control end of the switch module 91, the temperature detection module 92, the human eye protection component 93, the diffusion wheel 96 and the control end of the second power switch SW2. The power board 21 is also connected to a first end of a second power switch SW2 and a first end of a switch module 91. A second end of the second power switch SW2 is connected to a light source driver assembly, and a second end of the switch module 91 is connected to a fan module 90. The light source driver assembly 94 is also connected to a light source 95.

[0184] refer to Figure 21 The process of starting up a laser projection device may include the following steps:

[0185] Step 2101: Power on the system-on-chip.

[0186] The SoC 10 may include a wake-up circuit and other circuits. When the laser projection device is in standby mode, the power board maintains power to the wake-up circuit. Specifically, when the laser projection device is in standby mode, all other circuits in the SoC, except for the wake-up circuit, are inactive. Therefore, in standby mode, the wake-up circuit in the SoC can detect a power-on operation for the laser projection device and, in response to the power-on operation, wake up other circuits in the SoC and control the power board to supply power to these other circuits, thereby powering up the SoC.

[0187] Step 2102: After the system-level chip is powered on, it supplies power to the temperature detection module, the diffusion wheel, and the human eye protection component, and controls the fan module and the light valve control chip to be powered on.

[0188] After power-on, the system-level chip responds to the power-on operation, directly powers the temperature detection module, the diffusion wheel and the human eye protection component, and controls the power supply circuit to power the fan module and the reset chip, thereby controlling the fan module and the reset chip to power on.

[0189] The SoC 10 can output an enable signal of a valid level to the control end of the switch module 91 in response to a power-on operation, so that the first end and the second end of the switch module 91 are connected, thereby controlling the power supply board 21 to supply power to the fan module 90 .

[0190] If the fan module 90 includes multiple fans, the switch module 91 includes multiple switch circuits connected to the fans. The control terminal of each switch circuit is connected to the SoC 10, the first terminal of each switch circuit is connected to the power board 21, and the second terminal of each switch circuit is connected to a corresponding fan. In response to a power-on operation, the SoC 10 can provide an active enable signal to each switch circuit, connecting the first and second terminals of the switch circuit to conduction, thereby enabling the power board 21 to supply power to the fan connected to the switch circuit.

[0191] Optionally, the SoC 10 may further output a first control signal to the diffusion wheel 96, causing the diffusion wheel 96 to rotate under the control of the first control signal. The rotational speed of the diffusion wheel 96 is positively correlated with the duty cycle of the first control signal. The diffusion wheel 96 is configured to interfere with the three-color laser beams emitted by the light source 95 to adjust the polarization directions of the three-color laser beams. The first control signal may be a pulse width modulation (PWM) signal.

[0192] In the embodiment of the present disclosure, the process of the system-level chip 10 controlling the light valve control chip 50 to power on in response to the power-on operation can refer to the above steps 801 to 810, which will not be repeated in this embodiment of the present disclosure.

[0193] Step 2103: After the light valve control chip is powered on, it outputs a second control signal to the fan module.

[0194] After being powered on, the light valve control chip 50 can output a second control signal to the fan module 90 , and the fan module 90 rotates under the control of the second control signal. The rotation speed of the fan module 90 is positively correlated with the duty cycle of the second control signal.

[0195] refer to Figure 7 The laser projection device may include a program storage component 97 connected to the light valve control chip 50. After power is turned on, the light valve control chip 50 can read the program from the external program storage component 97 for initialization and output a second control signal to the fan module 90 after the initialization is completed.

[0196] Step 2104 : After determining that the fan module and the temperature detection module are in normal working state, the system-level chip instructs the light valve control chip to control the light valve to power on.

[0197] The SoC 10 detects whether the fan module 90 and the temperature detection module 92 are in normal operation. If the fan module 90 and / or the temperature detection module 92 are in normal operation, the SoC 10 may send a power supply instruction to the light valve control chip 50, instructing the light valve control chip 50 to power on the light valve 70.

[0198] Optionally, the fan module 90 may include at least one fan, and the temperature detection module may include at least one temperature sensor. The SoC 10 may obtain the rotational speed of each fan in the fan module 90 and the temperature detected by each temperature detector in the temperature detection module 92. If the SoC 10 detects that the rotational speed of each fan in the fan module 90 is within a rotational speed threshold range, the SoC 10 may determine that the fan module 90 is operating normally. If the SoC 10 detects that the rotational speed of any fan in the fan module 90 is not within the rotational speed threshold range, the SoC 10 may determine that the fan module 90 is not operating normally. The rotational speed threshold range may be pre-stored in the SoC 10. If the SoC 10 detects that the temperature detected by each temperature detector in the temperature detection module 92 is within the temperature threshold range, the SoC 10 may determine that the temperature detection module 92 is operating normally. If the SoC 10 detects that the temperature detected by any temperature detector in the temperature detection module 92 is not within the temperature threshold range, the SoC 10 may determine that the temperature detection module 92 is not operating normally. The SoC 10 may pre-store the temperature threshold range.

[0199] Optionally, after controlling the light valve power supply chip 80 to power the light valve 70, the light valve control chip 50 may send a confirmation signal to the system-on-chip 10. After receiving the confirmation signal, the system-on-chip 10 may determine that the light valve 70 is powered on successfully. Figure 6 The light valve control chip 50 can send a confirmation signal to the system-on-chip 10 via the I2C (inter integrated circuit) bus. After powering the eye protection component 93, the system-on-chip 10 can also determine whether to enable the eye protection function based on a signal fed back by a target object detected by the eye protection component 93. The signal fed back by the target object can be an infrared signal radiated by the target object.

[0200] Step 2105 : After determining that the light valve is powered on, the system-level chip controls the light source driving component to be powered on, so as to drive the light source to emit a light beam.

[0201] After determining that the light valve 70 is successfully powered on, the SoC 10 controls the power supply board 21 to supply power to the light source driver assembly 94, thereby driving the light source 95 to emit a light beam. Optionally, the SoC 10 can respond to a power-on command by outputting an enable signal of a valid level to the control terminal of the second power switch SW2, thereby conducting the first terminal and the second terminal of the second power switch SW2, thereby controlling the power supply board 21 to supply power to the light source driver assembly 94.

[0202] Step 2106: The light valve control chip outputs a third control signal to the light source driving component.

[0203] In the disclosed embodiment, after determining that the light valve 70 is successfully powered on, the system-on-chip 10 may further send a projected image to the light valve control chip 50. Furthermore, after receiving the projected image, the light valve control chip 10 may send a third control signal to the light source driver assembly 94. After powering on, the light source driver assembly 94 drives the light source 95 to emit a light beam under the control of the third control signal. The third control signal may include an enable signal and a current control signal, and the current control signal may be a PWM signal.

[0204] Optionally, the system-level chip 10 can send each frame of the projection image to the light valve control chip 50 in the form of a VX1 signal at a frequency of 60 Hz. The resolution of the projection image can be 4K. If the light source is a three-color laser light source, the third control signal can include an enable signal corresponding to the three primary colors of the projection image, and a current control signal corresponding to the three primary colors of the projection image. The light source driving component 94 can drive the light source to emit the primary color light beam based on the enable signal and current control signal of each primary color. Figure 7 The laser projection device may further include a galvanometer 98 connected to the light valve control chip 50. When the resolution of the projected image is greater than the resolution of the light valve 70, the galvanometer 98 may shift multiple sub-images to different positions on the projection screen to achieve superimposed display of the multiple sub-images, thereby achieving display of the projected image and thus extending the resolution of the light valve.

[0205] After receiving the projection image from the system-on-chip 10, the light valve control chip 50 can divide the projection image into multiple sub-images if the resolution of the projection image is greater than the resolution of the light valve. For each sub-image, the light valve control chip 50 can control the light source driver 94 to drive the light source 95 to emit a light beam. As the light beam emitted by the light source 95 irradiates the light valve 70, the light valve 70 is controlled to modulate the illumination beam irradiating its surface according to the sub-image, and the light valve 70 is controlled to transmit the modulated image beam to the galvanometer 98. The galvanometer 98 is used to transmit the image beam transmitted by the light valve to the projection lens. The projection lens is used to project the image beam transmitted by the galvanometer onto the projection screen, thereby projecting multiple sub-images onto the projection screen in sequence, thereby achieving the display of a high-resolution projection image through the low-resolution light valve projection.

[0206] During the projection and display of each sub-image frame, the light valve control chip 50 can control and transmit the galvanometer mirror drive current corresponding to each sub-image frame to the galvanometer mirror 98 to drive the polarization of the galvanometer mirror 98. The galvanometer mirror drive current corresponding to different sub-image frames has different directions, thereby enabling the projection of multiple sub-image frames to different positions on the projection screen, thereby achieving the superposition display of these multiple sub-image frames. Furthermore, during the projection and display of multiple sub-image frames, the current direction of the galvanometer mirror drive current can alternate, and the waveform of the changing galvanometer mirror drive current can be a sine wave.

[0207] refer to Figure 7 The laser projection device may include a digital to analog converter (DAC) D, which is connected to the light valve control chip 50 and the galvanometer 98 respectively. The DAC D is used to convert the galvanometer drive current transmitted by the light valve control chip 50 from a digital signal to an analog signal, and transmit the converted analog signal to the galvanometer 98. The light valve control chip 50 can also send a control instruction to the galvanometer through the I2C bus based on the detected temperature of the galvanometer 98. The control instruction can be used to adjust the angle of the galvanometer, etc. Figure 7The system-on-chip 10 can also send correction data to the light valve control chip 50 via a universal serial bus (USB). The laser projection device may include a memory R, ​​which may be an electrically erasable programmable read-only memory (EEPROM). The light valve control chip 50 can send the correction data to the memory R via the I2C bus, so that the memory R stores the correction data. The correction data can be used to correct the projection position or projection shape of the projected image. The light valve control chip 50 can correct the projection position or projection shape of the projected image based on the correction data.

[0208] In the embodiments of the present disclosure, reference Figure 22 , the standby process of the laser projection device may include the following steps:

[0209] Step 2201: In response to the standby operation, the system-on-chip controls the light valve control chip and the light valve to power off.

[0210] The process of controlling the light valve control chip to power off can refer to the above steps 1601 to 1608, and the process of controlling the light valve to power off can also refer to the above content, which will not be repeated in this embodiment of the present disclosure.

[0211] Step 2202: The system-level chip controls the light source driving component to power off to turn off the light source.

[0212] refer to Figure 7 The system-level chip 10 can respond to the standby operation by outputting an enable signal of an invalid level to the control end of the second power switch SW2, so that the first end and the second end of the second power switch SW2 are disconnected, thereby controlling the power supply board 21 to stop supplying power to the light source driving component 94, so that the light source 95 stops emitting a light beam, that is, turning off the light source 95.

[0213] Step 2203: After determining that the light valve is powered off successfully, the system-level chip controls the fan, the temperature detection module, the human eye protection component, and the diffusion wheel to power off.

[0214] refer to Figure 7After determining that the light valve has been successfully powered off, the SoC 10 can output an enable signal of an inactive level to the control terminal of the switch module 91, disconnecting the first terminal from the second terminal of the switch module 91, thereby controlling the power supply board 21 to stop supplying power to the fan module 90. If the fan module 90 includes multiple fans, the SoC 10 can also send an enable signal of an inactive level to each switch circuit after determining that the light valve has been successfully powered off, disconnecting the first terminal from the second terminal of the switch circuit, thereby causing the power supply board 21 to stop supplying power to the fan connected to the switch circuit.

[0215] Step 2204: The system-on-chip enters a standby state.

[0216] The wake-up circuit in the SoC can control the power board to stop supplying power to other circuits, thereby putting the SoC into a standby state. In the embodiment of the present disclosure, the voltage of the valid enable signal can be 3.3V, and the voltage of the invalid enable signal can be 0V.

[0217] In the embodiments of the present disclosure, the terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth", "ninth", "tenth", "eleventh", "twelfth", "thirteenth", "fourteenth", "fifteenth", "sixteenth", "seventeenth", "eighteenth", "nineteenth", "twentieth", "twenty-first" and "twenty-second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. In the embodiments of the present disclosure, the term "multiple" means two or more. The above is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A laser projection device, characterized in that: The laser projection device includes a system-level chip, a power circuit, a power control chip, a reset chip, a light valve control chip and a power conversion circuit; The system-level chip is connected to the power circuit and the first input terminal of the power control chip respectively, and the system-level chip is used to control the power circuit to supply power to the reset chip and send a power-on signal to the power control chip in response to a power-on operation; The reset chip is also connected to the second input terminal of the power control chip and the first input terminal of the light valve control chip. The reset chip is used to send a power normal signal of a valid level to the power control chip and the light valve control chip respectively after power-on; The power control chip is used to respond to the power-on signal and the power normal signal, control the power conversion circuit to send multiple valid power signals to the light valve control chip in sequence, and to send a power sensing signal of a valid level to the light valve control chip to control the light valve control chip to power on.

2. The laser projection device according to claim 1, characterized in that: The power control chip is used to send a valid enable signal to the power conversion circuit in response to the power-on signal and the power normal signal; The power conversion circuit is used for sending a plurality of valid power signals to the light valve control chip in response to the valid enable signal, and sending a valid control signal to the power control chip; The power control chip is used to send the power sensing signal to the light valve control chip in response to the effective control signal.

3. The laser projection device according to claim 2, characterized in that: The power conversion circuit includes: a first conversion circuit, a plurality of second conversion circuits and a third conversion circuit; The first output terminal of the power control chip is connected to the input terminal of the first conversion circuit, and the output terminal of the first conversion circuit is connected to the second input terminal of the light valve control chip and the third input terminal of the power control chip respectively; The power control chip is configured to send the valid enable signal to the first conversion circuit after receiving the power-on signal and the power normal signal for a first duration; The first conversion circuit is used for sending a first valid power signal to the light valve control chip and sending a first valid control signal to the power control chip in response to the valid enable signal; The power control chip further has a second output terminal and a plurality of fourth input terminals, and the light valve control chip has a plurality of third input terminals. The second output terminal of the power control chip is connected to the input terminals of the plurality of second conversion circuits, and the output terminals of the plurality of second conversion circuits are respectively connected to the plurality of third input terminals of the light valve control chip and the plurality of fourth input terminals of the power control chip in a one-to-one correspondence. The power control chip is configured to send the valid enable signal to each of the second conversion circuits after receiving the first valid control signal for a second time period; Each of the second conversion circuits is configured to send a second valid power signal to the corresponding third input terminal and a second valid control signal to the corresponding fourth input terminal in response to the valid enable signal; The third input terminal of the power control chip is connected to the input terminal of the third conversion circuit, the output terminal of the third conversion circuit is connected to the fourth input terminal of the light valve control chip and the fifth input terminal of the power control chip respectively, and the fourth output terminal of the power control chip is connected to the fifth input terminal of the light valve control chip; The power control chip is configured to send the valid enable signal to the third conversion circuit after receiving the plurality of second valid control signals for a third time period; The third conversion circuit is used for sending a third valid power signal to the light valve control chip and sending a third valid control signal to the power control chip in response to the valid enable signal; The power control chip is configured to send the power sensing signal to the light valve control chip after receiving the third valid control signal for a fourth time period.

4. The laser projection device according to any one of claims 1 to 3, characterized in that: The laser projection device further includes: a light valve connected to the light valve control chip; The light valve control chip is also connected to the sixth input terminal of the power control chip. The light valve control chip is used to control the light valve to power on after power-on, and send a power-on success signal to the sixth input terminal of the power control chip after the light valve is powered on successfully. The power-on success signal is used to indicate that the light valve is powered on successfully.

5. The laser projection device according to any one of claims 1 to 3, characterized in that: The power control chip is a programmable logic chip.

6. A laser projection device, characterized in that: The laser projection device includes a system-level chip, a power circuit, a power control chip, a reset chip, a light valve control chip and a power conversion circuit; The system-level chip is connected to the power circuit and the first input terminal of the power control chip respectively, and the system-level chip is used to control the power circuit to stop supplying power to the reset chip in response to the standby operation, and send a standby signal to the power control chip; The reset chip is also connected to the second input terminal of the power control chip and the first input terminal of the light valve control chip. The power control chip is used to: receiving a power-good signal of an invalid level output by the reset chip through the second input terminal after the reset chip is powered off; In response to the standby signal and the power normal signal, sending a power sensing signal of an invalid level to the light valve control chip; The power conversion circuit is controlled to sequentially send a plurality of power signals of invalid levels to the light valve control chip, so as to control the light valve control chip to power off.

7. The laser projection device according to claim 6, characterized in that: The power control chip is configured to send a power sensing signal of an invalid level to the light valve control chip after receiving the standby signal and the power normal signal for a fifth time period, and send an invalid enable signal to the power conversion circuit after receiving the standby signal and the power normal signal for a sixth time period, wherein the sixth time period is greater than the fifth time period; The power conversion circuit is used for sending a plurality of invalid power signals to the light valve control chip in sequence in response to the invalid enable signal.

8. The laser projection device according to claim 7, characterized in that: The power conversion circuit includes: a first conversion circuit, a plurality of second conversion circuits and a third conversion circuit; The third input terminal of the power control chip is connected to the input terminal of the third conversion circuit, the output terminal of the third conversion circuit is connected to the fourth input terminal of the light valve control chip and the fifth input terminal of the power control chip respectively, and the fourth output terminal of the power control chip is connected to the fifth input terminal of the light valve control chip; the power control chip is configured to send the invalid enable signal to the third conversion circuit after receiving the standby signal and the power normal signal for a sixth time period; the third conversion circuit is configured to send a first invalid control signal to the power control chip and a first invalid power signal to the light valve control chip in response to the invalid enable signal; The power control chip further has a second output terminal and a plurality of fourth input terminals, and the light valve control chip has a plurality of third input terminals. The second output terminal of the power control chip is connected to the input terminals of the plurality of second conversion circuits, and the output terminals of the plurality of second conversion circuits are respectively connected to the plurality of third input terminals of the light valve control chip and the plurality of fourth input terminals of the power control chip in a one-to-one correspondence. The power control chip is configured to send the invalid enable signal to each of the second conversion circuits after receiving the first invalid control signal for a seventh time period; each of the second conversion circuits is configured to send a second invalid power signal to the corresponding third input terminal and a second invalid control signal to the corresponding fourth input terminal in response to the invalid enable signal; The first output end of the power control chip is connected to the input end of the first conversion circuit, and the output end of the first conversion circuit is respectively connected to the second input end of the light valve control chip and the third input end of the power control chip; the power control chip is used to send the invalid enable signal to the first conversion circuit after receiving multiple second invalid control signals for an eighth time period; the first conversion circuit is used to send a third invalid control signal to the power control chip in response to the invalid enable signal, and send a third invalid power signal to the light valve control chip to control the light valve control chip to power off.

9. A method for controlling a laser projection device, characterized in that: The laser projection device includes a system-level chip, a power circuit, a power control chip, a reset chip, a light valve control chip, and a power conversion circuit; the system-level chip is connected to the power circuit and the first input terminal of the power control chip respectively, and the reset chip is also connected to the second input terminal of the power control chip and the first input terminal of the light valve control chip. The method includes: In response to a power-on operation, the system-on-chip controls the power supply circuit to supply power to the reset chip and sends a power-on signal to the power control chip; After power-on, the reset chip sends a power normal signal of a valid level to the power control chip and the light valve control chip respectively; In response to the power-on signal and the power-normal signal, the power control chip controls the power conversion circuit to sequentially send multiple valid power signals to the light valve control chip, and sends a power sensing signal of a valid level to the light valve control chip to control the light valve control chip to power on.

10. A method for controlling a laser projection device, characterized in that: The laser projection device includes a system-level chip, a power circuit, a power control chip, a reset chip, a light valve control chip, and a power conversion circuit; the system-level chip is connected to the power circuit and the first input terminal of the power control chip respectively, and the reset chip is also connected to the second input terminal of the power control chip and the first input terminal of the light valve control chip. The method includes: In response to the standby operation, the system-level chip controls the power supply circuit to stop supplying power to the reset chip and sends a standby signal to the power control chip; The power control chip receives an invalid level power normal signal output by the reset chip through the second input terminal after the reset chip is powered off; in response to the standby signal and the power normal signal, sends an invalid level power sensing signal to the light valve control chip; and controls the power conversion circuit to send multiple invalid level power signals to the light valve control chip in sequence to control the light valve control chip to power off.

Images