Electrostatic discharge protection circuit and input and output circuit

Abstract

The present invention discloses an input-output circuit and an electrostatic discharge protection circuit. The electrostatic discharge protection circuit is suitable for a component charging model. The electrostatic discharge protection circuit includes a bipolar junction transistor. The bipolar junction transistor has a first end coupled to an input end of an input buffer and an output end of an output buffer. The second end of the bipolar junction transistor is coupled to a first ground rail. The control end of the bipolar junction transistor is coupled to one of a first power rail, a second power rail, a first ground rail, and a second ground rail.

Description

Technical Field

[0001] The present invention relates to an input-output circuit and an electrostatic discharge protection circuit, and more particularly to an input-output circuit and an electrostatic discharge protection circuit capable of reducing voltage stress during an electrostatic discharge test operation. Background Art

[0002] In the electrostatic discharge protection action of the component charging model for the input and output circuit, the conventional technology often provides a discharge path for the electrostatic discharge current through a metal oxide semiconductor field effect transistor with a grounded gate. However, during the electrostatic discharge test, especially under the test of the negative voltage mode, the drain and source ends of the metal oxide semiconductor field effect transistor with a grounded gate are often subjected to excessive voltage stress, resulting in damage to the metal oxide semiconductor field effect transistor with a grounded gate. As a result, the internal circuit of the integrated circuit cannot be well protected, reducing the reliability of the circuit. Summary of the invention

[0003] The invention provides an electrostatic discharge protection circuit, which can prevent a transistor that performs a current discharge action from being damaged due to being subjected to an excessive voltage.

[0004] The electrostatic discharge protection circuit of the present invention is suitable for a component charging model. The electrostatic discharge protection circuit includes a bipolar junction transistor. The bipolar junction transistor has a first end coupled to an input end of an input buffer and an output end of an output buffer. The second end of the bipolar junction transistor is coupled to a first ground rail. The control end of the bipolar junction transistor is coupled to one of a first power rail, a second power rail, a first ground rail, and a second ground rail. The input buffer receives a first operating power supply and a first ground voltage respectively through the first power rail and the first ground rail. The output buffer receives a second operating power supply and a second ground voltage respectively through the second power rail and the second ground rail.

[0005] The input-output circuit of the present invention includes an input buffer, an output buffer and the electrostatic discharge protection circuit as described above.

[0006] Based on the above, the present invention connects a bipolar junction transistor between the output buffer and the input buffer, and according to the type of the bipolar junction transistor (PNP or NPN), the control terminal (base) of the bipolar junction transistor is coupled to the first power rail, the second power rail, the first ground rail or the second ground rail. Through the characteristics of the bipolar junction transistor, in the electrostatic discharge state of the device charging model, the voltage difference between the first terminal and the second terminal (collector and emitter) of the bipolar junction transistor can be reduced, thereby reducing the voltage stress borne by the bipolar junction transistor and reducing the risk of damage to the bipolar junction transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of an input-output circuit according to an embodiment of the present invention is shown.

[0008] Figure 2 A schematic diagram of an input-output circuit according to another embodiment of the present invention is shown.

[0009] Figure 3 A schematic diagram of an input-output circuit according to another embodiment of the present invention is shown.

[0010] Figure 4 A schematic diagram of an input-output circuit according to another embodiment of the present invention is shown.

[0011] Figure 5 A schematic diagram of an input-output circuit according to another embodiment of the present invention is shown.

[0012] Figure 6 A schematic diagram of an input-output circuit according to another embodiment of the present invention is shown.

[0013] Fig. 7A as well as Figure 7B Schematic diagrams are respectively shown showing implementations of the voltage clamping circuit in the electrostatic discharge protection circuit according to the embodiments of the present invention.

[0014]

Explanation of symbols

[0015] 100, 200, 300, 400, 500, 600: Input and output circuits

[0016] 110, 210, 310, 410, 510, 610: Electrostatic discharge protection circuit

[0017] 111, 211, 311, 411, 511, 611: Voltage clamping circuit

[0018] 120, 220, 320, 420, 520, 620: Input buffer

[0019] 130, 230, 330, 430, 530, 630: Output buffer

[0020] D1, D711~D71N, D721~D72M: diode

[0021] ESD_R: Resistance

[0022] GL1: First ground rail

[0023] GL2: Second ground rail

[0024] IE: Input

[0025] MP1, MN1, MP2, MN2: Transistors

[0026] OE: Output

[0027] PAD: solder pad

[0028] PD, PU: control signal

[0029] PL1: First power rail

[0030] PL2: Second power rail

[0031] T1: Bipolar Junction Transistor

[0032] VCC: Operation power supply

[0033] VCCQ: Operation power supply

[0034] VSS: Ground voltage

[0035] VSSQ: Ground voltage

[0036] WL: Transmission wire DETAILED DESCRIPTION

[0037] Please refer to Figure 1 , Figure 1 A schematic diagram of an input-output circuit according to an embodiment of the present invention is shown. The input-output circuit 100 includes an electrostatic discharge protection circuit 110, an input buffer 120, and an output buffer 130. In the present embodiment, the input buffer 120 is coupled to a first power rail PL1 and a first ground rail GL1, and receives an operating power supply VCC and a ground voltage VSS through the first power rail PL1 and the first ground rail GL1, respectively. The output buffer 130 is coupled to a second power rail PL2 and a second ground rail GL2, and receives an operating power supply VCCQ and a ground voltage VSSQ through the second power rail PL2 and the second ground rail GL2, respectively. In the present embodiment, the output buffer 130 can also serve as a part of the electrostatic discharge protection circuit when an electrostatic discharge phenomenon occurs.

[0038] The input buffer 120 includes transistors MP1 and MN1. The first end of the transistor MP1 is coupled to the first power rail PL1; the second end of the transistor MP1 is coupled to the first end of the transistor MN1. The control end of the transistor MP1 forms the input end IE of the input buffer 120 and is coupled to the control end of the transistor MN1. The second end of the transistor MN1 is coupled to the first ground rail GL1. The output buffer 130 includes transistors MP2 and MN2. The first end of the transistor MP2 is coupled to the second power rail PL2; the second end of the transistor MP2 is coupled to the first end of the transistor MN1 and forms the output end OE of the output buffer 130, wherein the output end OE of the output buffer 130 is connected to the pad PAD; the control end of the transistor MP2 receives the control signal PU. The control end of the transistor MN2 receives the control signal PD, and the second end of the transistor MN2 is coupled to the ground rail GL2.

[0039] The electrostatic discharge protection circuit 110 includes a bipolar junction transistor (BJT) T1. In this embodiment, the first end (collector) of the BJT T1 is coupled to the input end IE of the input buffer 120, the second end (emitter) of the BJT T1 is coupled to the first ground rail GL1, and the control end (base) of the BJT T1 is coupled to the second ground rail GL2. Please note that the BJT T1 in this embodiment is an NPN transistor.

[0040] The electrostatic discharge protection circuit 110 further includes a resistor ESD_R and a voltage clamp circuit 111. The resistor ESD_R is coupled between the input terminal IE of the input buffer 120 and the output terminal OE of the output buffer 130. In addition, the voltage clamp circuit 111 is coupled between the first ground rail GL1 and the second ground rail GL2.

[0041] When the electrostatic discharge test action of the device charging model is performed on the input-output circuit 100, the bipolar junction transistor T1 can be turned on and used to clamp the voltage on the input terminal IE of the input buffer 120 to protect the input buffer 120 from being damaged. In addition, in this embodiment, the positive voltage test mode of the human body model (HBM) and the negative voltage test mode of the device charging model (CDM) have the same current flow direction. In addition, the negative voltage test mode of the human body model and the positive voltage test mode of the device charging model also have the same current flow direction. Therefore, in the embodiment of the present invention, the positive voltage test mode and the negative voltage test mode of the device charging model can also be applied to the negative voltage test mode and the positive voltage test mode of the human body model, respectively.

[0042] Further explanation of this embodiment, in the negative voltage test mode of the device charging model, the transistor MN2 can be turned on, and a current discharge path can be formed from the pad PAD, the transistor MN2, the second ground rail GL2, the voltage clamp circuit 111 to the first ground rail GL1. In addition, the bipolar junction transistor T1 is also turned on, and another current discharge path can be formed from the pad PAD, the resistor ESD_R, the bipolar junction transistor T1 to the first ground rail GL1. It is worth noting that since the electrostatic discharge current can flow from the second ground rail GL2 to the first ground rail GL1 through the voltage clamp circuit 111, the ground voltage VSSQ on the second ground rail GL2 can be greater than the ground voltage VSS on the first ground rail GL1. At this time, the PN junction between the control terminal (base) and the second terminal (emitter) of the bipolar junction transistor T1 can limit the voltage difference between the ground voltage VSSQ and the ground voltage VSS from being too large, which can effectively reduce the voltage stress between the first terminal and the second terminal of the bipolar junction transistor T1 and reduce the possibility of damage to the bipolar junction transistor T1.

[0043] On the other hand, in the positive voltage test mode, the transistor MN2 can be turned on, and a current discharge path can be formed from the first ground rail GL1, the voltage clamping circuit 111, the second ground rail GL2, the transistor MN2 to the pad PAD. In addition, the bipolar junction transistor T1 is also turned on, and another current discharge path can be formed from the first ground rail GL1, the bipolar junction transistor T1, the resistor ESD_R to the pad PAD to achieve the effect of electrostatic discharge protection.

[0044] Incidentally, in this embodiment, transistors MP1 and MP2 are P-type MOSFETs, and transistors MN1 and MN2 are N-type MOSFETs. In addition, the bulk of transistor MN2 in the output buffer 130 is coupled to the first ground rail GL1 to receive the ground voltage VSS.

[0045] On the other hand, in this embodiment, the control terminal of the bipolar junction transistor T1 can also be coupled to the first ground rail GL1 , and is not limited to being coupled to the second ground rail GL2 .

[0046] Please refer to the following Figure 2 , Figure 2A schematic diagram of an input-output circuit according to another embodiment of the present invention is shown. The input-output circuit 200 includes an electrostatic discharge protection circuit 210, an input buffer 220, and an output buffer 230. In this embodiment, the input buffer 220 is coupled to the first power rail PL1 and the first ground rail GL1, and receives the operating power VCC and the ground voltage VSS through the first power rail PL1 and the first ground rail GL1, respectively. The output buffer 130 is coupled to the second power rail PL2 and the second ground rail GL2, and receives the operating power VCCQ and the ground voltage VSSQ through the second power rail PL2 and the second ground rail GL2, respectively. The input buffer 220 is composed of transistors MP1 and MN1, and the output buffer 230 is composed of transistors MP2 and MN2.

[0047] The electrostatic discharge protection circuit 210 includes a bipolar junction transistor T1, a resistor ESD_R and a voltage clamp circuit 211. The circuit coupling relationship is similar to Figure 1 The embodiments are similar and will not be described in detail here.

[0048] and Figure 1 In a different embodiment, in an embodiment of the present invention, a diode D1 may be formed between the first end and the second end of the bipolar junction transistor T1. The anode of the diode D1 is coupled to the first ground rail GL1, and the cathode of the diode D1 is coupled to the input terminal IE of the input buffer 220. The diode D1 may be used to enhance the reverse current discharge capability and improve the electrostatic discharge protection capability in the positive voltage test mode during the electrostatic discharge test action of the device charging model.

[0049] Please refer to Figure 3 , Figure 3 FIG. 2 is a schematic diagram of an input-output circuit according to another embodiment of the present invention. The input-output circuit 300 includes an electrostatic discharge protection circuit 310, an input buffer 320, and an output buffer 330. The input buffer 320 and the output buffer 330 are connected to the Figure 1 , 2 The implementation methods of the input buffers 120 and 220 and the output buffers 130 and 230 of the embodiments are the same and will not be described in detail herein.

[0050] The electrostatic discharge protection circuit 310 includes a resistor ESD_R, a bipolar junction transistor T1 and a voltage clamping circuit 311. Figure 1 , 2The embodiment is different, and the bipolar junction transistor T1 of this embodiment is a PNP transistor. The first end (emitter) of the bipolar junction transistor T1 is coupled to the input end IE of the input buffer 320, the second end (collector) of the bipolar junction transistor T1 is coupled to the first ground rail GL1, and the control end (base) of the bipolar junction transistor T1 is coupled to the second power rail PL2.

[0051] In the electrostatic discharge test action, the voltage on the second power rail PL2 can be close to the ground voltage VSSQ. Therefore, in the negative voltage test mode under the device charging model, the bipolar junction transistor T1 can be turned on according to the voltage on the pad PAD higher than the ground voltage VSSQ, and generate an electrostatic discharge current discharge path.

[0052] Similarly, in the positive voltage test mode under the device charging model, the bipolar junction transistor T1 can also be turned on to generate another current discharge path for electrostatic discharge.

[0053] Please refer to Figure 4 , Figure 4 FIG. 4 is a schematic diagram of an input-output circuit according to another embodiment of the present invention. The input-output circuit 400 includes an electrostatic discharge protection circuit 410, an input buffer 420, and an output buffer 430. The input buffer 420 and the output buffer 430 are connected to the Figure 3 The implementation of the input buffer 320 and the output buffer 330 of the embodiment is the same, and will not be described in detail here. Figure 3 The embodiment is different. In this embodiment, a diode D1 can be further provided at both ends of the bipolar junction transistor T1. The anode of the diode D1 is coupled to the first ground rail GL1, and the cathode of the diode D1 is coupled to the input terminal IE of the input buffer 420. The diode D1 can be used to enhance the reverse current discharge capability and improve the electrostatic discharge protection capability in the positive voltage test mode during the electrostatic discharge test action of the device charging model.

[0054] Please refer to Figure 5 , Figure 5 FIG. 5 is a schematic diagram of an input-output circuit according to another embodiment of the present invention. The input-output circuit 500 includes an electrostatic discharge protection circuit 510, an input buffer 520, and an output buffer 530. Figure 3 An embodiment of Figure 3In a different embodiment, the control terminal of the bipolar junction transistor T1 in the electrostatic discharge protection circuit 510 of this embodiment is coupled to the first power rail PL1. Based on the electrostatic discharge test action, the voltage on the first power rail PL1 can be close to the ground voltage VSS. In such a configuration, in the negative voltage test mode under the device charging model, the bipolar junction transistor T1 can still be turned on according to the voltage on the pad PAD that is higher than the ground voltage VSSQ, and a current discharge path for electrostatic discharge is generated.

[0055] Please refer to the following Figure 6 , Figure 6 FIG. 6 is a schematic diagram of an input-output circuit according to another embodiment of the present invention. The input-output circuit 600 includes an electrostatic discharge protection circuit 610, an input buffer 620, and an output buffer 630. Figure 5 An embodiment of Figure 5 In a different embodiment, in the electrostatic discharge protection circuit 610 of this embodiment, a diode D1 may be further provided at both ends of the bipolar junction transistor T1. The anode of the diode D1 is connected to the first ground rail GL1, and the cathode of the diode D1 is connected to the input terminal IE of the input buffer 620. The diode D1 can be used to enhance the reverse current discharge capability and improve the electrostatic discharge protection capability in the positive voltage test mode during the electrostatic discharge test action of the device charging model.

[0056] Please refer to the following Fig. 7A as well as Figure 7B , Fig. 7A as well as Figure 7B Schematic diagrams showing implementations of the voltage clamping circuit in the electrostatic discharge protection circuit according to the embodiments of the present invention are shown respectively. Fig. 7A In the embodiment, the voltage clamping circuit 710 includes a plurality of diodes D711-D71N and D721-D72M. The diodes D711-D71N are connected in series with each other according to the same polarity direction, and are connected between the first ground rail GL1 and the second ground rail GL2. The anode of the diode D711 can be directly connected to the second ground rail GL2, and the cathode of the diode D71N can be directly connected to the first ground rail GL1. In addition, the diodes D721-D72M are connected in series with each other according to the same polarity direction, and are connected between the first ground rail GL1 and the second ground rail GL2. The anode of the diode D721 can be directly connected to the first ground rail GL1, and the cathode of the diode D72M can be directly connected to the second ground rail GL2.

[0057] In this embodiment, the number of diodes D711-D71N and the number of diodes D721-D72M may be the same or different. In other embodiments, the number of diodes D711-D71N may be one, and the number of diodes D721-D72M may be one, without any other limitation.

[0058] exist Figure 7B In the embodiment, the voltage clamping circuit 720 includes a transmission wire WL. The transmission wire WL can provide an impedance, and the voltage clamping effect is generated by using the provided impedance.

[0059] In summary, the present invention achieves the effect of electrostatic discharge protection by arranging a bipolar junction transistor in an electrostatic discharge protection circuit and providing a discharge path for electrostatic discharge current by turning on the bipolar junction transistor during the electrostatic discharge test action. In addition, when the bipolar junction transistor of the present invention is turned on, the voltage difference between the collector and the emitter of the bipolar junction transistor can be clamped through the PN interface between the base and the emitter, effectively preventing the bipolar junction transistor from being subjected to excessive voltage stress and reducing the risk of being damaged.

[0060] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An electrostatic discharge protection circuit, wherein: include: a bipolar junction transistor having a first terminal coupled to an input terminal of an input buffer and an output terminal of an output buffer, a second terminal of the bipolar junction transistor coupled to a first ground rail, a control terminal of the bipolar junction transistor coupled to a first power rail, a second power rail, the first ground rail, and one of a second ground rail, The input buffer receives a first operating power supply and a first ground voltage through the first power rail and the first ground rail, respectively, and the output buffer receives a second operating power supply and a second ground voltage through the second power rail and the second ground rail, respectively. A forward biased diode is formed between the second end and the first end of the bipolar junction transistor to provide a reverse current discharge path.

2. The electrostatic discharge protection circuit according to claim 1, wherein: Also includes: a resistor coupled between a pad and the input terminal of the input buffer, The pad is coupled to the output end of the output buffer.

3. The electrostatic discharge protection circuit according to claim 1, wherein: The bipolar junction transistor is a PNP transistor, and the control terminal of the bipolar junction transistor is coupled to the first power rail or the second power rail. The bipolar junction transistor is an NPN transistor, and the control terminal of the bipolar junction transistor is coupled to the first ground rail or the second ground rail.

4. The electrostatic discharge protection circuit according to claim 1, wherein: Also includes: A voltage clamping circuit is coupled between the first ground rail and the second ground rail.

5. The electrostatic discharge protection circuit according to claim 4, wherein: The voltage clamping circuit includes at least one first diode and at least one second diode, the anode of the at least one first diode is coupled to the first ground rail, the cathode of the at least one first diode is coupled to the second ground rail, the anode of the at least one second diode is coupled to the second ground rail, and the cathode of the at least one second diode is coupled to the first ground rail.

6. The electrostatic discharge protection circuit according to claim 1, wherein: The voltage clamping circuit is a transmission conductor.

7. An input-output circuit, wherein: include: An input buffer receives a first operating power supply and a first ground voltage through a first power rail and a first ground rail respectively; an output buffer receiving a second operating power supply and a second ground voltage through a second power rail and a second ground rail respectively; as well as An electrostatic discharge protection circuit, comprising: a bipolar junction transistor having a first terminal coupled to the input terminal of the input buffer and the output terminal of the output buffer, a second terminal of the bipolar junction transistor coupled to the first ground rail, and a control terminal of the bipolar junction transistor coupled to one of the first power rail, the second power rail, the first ground rail, and the second ground rail, A forward biased diode is formed between the second end and the first end of the bipolar junction transistor to provide a reverse current discharge path.

8. The input-output circuit according to claim 7, wherein: The electrostatic discharge protection circuit further includes a resistor, wherein the resistor is coupled between a pad and the input end of the input buffer, and the pad is coupled to the output end of the output buffer.

9. The input-output circuit according to claim 7, wherein: The bipolar junction transistor is a PNP transistor, and the control terminal of the bipolar junction transistor is coupled to the first power rail or the second power rail. The bipolar junction transistor is an NPN transistor, and the control terminal of the bipolar junction transistor is coupled to the first ground rail or the second ground rail.

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